WO2022110820A1 - 动态随机存取存储器电容器及其制备方法 - Google Patents

动态随机存取存储器电容器及其制备方法 Download PDF

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WO2022110820A1
WO2022110820A1 PCT/CN2021/105504 CN2021105504W WO2022110820A1 WO 2022110820 A1 WO2022110820 A1 WO 2022110820A1 CN 2021105504 W CN2021105504 W CN 2021105504W WO 2022110820 A1 WO2022110820 A1 WO 2022110820A1
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dielectric
layer
material layer
random access
access memory
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French (fr)
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陈卓
王盈智
王士欣
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/471,243 priority Critical patent/US11930630B2/en
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/10—Metal-oxide dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/601—Capacitive arrangements

Definitions

  • the present disclosure belongs to the field of semiconductor elements, and in particular relates to a dynamic random access memory capacitor and a preparation method thereof.
  • the dielectric material layer is getting thinner and thinner, which not only becomes more and more difficult to achieve in the process, but also leads to higher and higher dielectric losses.
  • embodiments of the present disclosure provide a dynamic random access memory capacitor, including a dielectric layer, the dielectric layer including: a high dielectric material layer; and a low dielectric loss material layer disposed on the high dielectric material layer on both sides.
  • Another aspect of an embodiment of the present disclosure provides a method for fabricating a dynamic random access memory capacitor, including: S1, forming a low dielectric loss material layer; S2, forming a high dielectric material layer on the low dielectric loss material layer ; S3, forming a low dielectric loss material layer on the high dielectric material layer.
  • the dielectric layer of the DRAM capacitor provided by the embodiments of the present disclosure includes a high dielectric material layer and a low dielectric loss material layer disposed on both sides of the high dielectric material layer.
  • the high dielectric material layer can improve the dielectric properties of the dielectric layer. constant, so that it has better dielectric properties; the low dielectric loss material layers arranged on both sides can effectively solve the dielectric loss of the high dielectric material layer, so as to realize the high dielectric constant and low dielectric of the dielectric layer. purpose of loss.
  • the DRAM capacitor provided by the embodiment of the present disclosure has a simple manufacturing process and is convenient for industrialized production.
  • FIG. 1A is a schematic partial cross-sectional view of a DRAM capacitor according to an embodiment of the present disclosure.
  • FIG. 1B is a partially enlarged schematic view of the dielectric layer of the DRAM capacitor in FIG. 1A .
  • FIG. 2A is a schematic partial cross-sectional view of a DRAM capacitor according to another embodiment of the present disclosure.
  • FIG. 2B is a partially enlarged schematic view of the dielectric layer of the DRAM capacitor in FIG. 2A .
  • Example embodiments will now be described more fully with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the thickness of regions and layers are exaggerated for clarity.
  • the same reference numerals in the drawings denote the same or similar structures, and thus their detailed descriptions will be omitted.
  • high dielectric constant material herein refers to a material with a dielectric constant higher than 4; the term “low dielectric loss material” refers to a material with a dielectric loss below 0.2.
  • the dynamic random access memory capacitor of the present disclosure includes a dielectric layer, wherein the dielectric layer includes a high dielectric material layer and a low dielectric loss material layer disposed on both sides of the high dielectric material layer.
  • High-k materials can increase the dielectric constant of the dielectric layer and make it have better dielectric properties.
  • the low dielectric loss material layers disposed on the surfaces of both sides can effectively solve the dielectric loss of the high dielectric material layer, so as to achieve the purpose of high dielectric constant and low dielectric loss of the dielectric layer.
  • the dielectric layer 2 includes a layer of high dielectric material 22 and a first low dielectric loss disposed on the inner side and on the surface of the first capacitor electrode 1 of the DRAM capacitor The material layer 21 and the second low dielectric loss material layer 23 arranged on the outside.
  • the dielectric layer 2 includes two high dielectric material layers 22 , ie, high dielectric material layers 22 a and 22 b. That is, the high dielectric material layers 22a, 22b and the low dielectric loss material layers 21a, 21b, 23 are alternately arranged.
  • the dielectric layer can also be a stack of more layers, for example, a stack including 3 layers of high-dielectric material layers and 4 layers of low-dielectric loss material layers, or a stack of 4 layers of high-dielectric material layers and stacking of 5 low dielectric loss material layers and so on.
  • the dielectric layer 2 includes two high dielectric material layers, as shown in FIG.
  • the total thickness d of the dielectric layer 2 is the thickness d of the high dielectric layers 22a, 22b and the low dielectric loss material layers 21a, 21a,
  • the sum of the thicknesses d3 of 21b, 23 (ie, d 2d4+ 3d3 ), the thickness d4 of the high dielectric material layers 22a, 22b and the thickness d3 of the low dielectric loss material layers 21a, 21b, 23
  • the ratio is 200-100:1. According to the relevant formula of capacitor series connection, it can be known that the greater the ratio of the thickness of the high dielectric material layer to the thickness of the low dielectric loss material layer, the closer the dielectric constant of the dielectric layer is to the dielectric constant of the high dielectric material layer.
  • the thickness ratio of the high dielectric material layer to the low dielectric loss material layer is 200-100:1.
  • Those skilled in the art can choose any value according to specific needs, such as 190:1, 180:1, 170:1, 160:1, 150:1, 140:1, 130:1, 120:1, 110:1 1 and so on.
  • the thickness of the low dielectric loss material layer may be 0.34nm-10nm.
  • the low dielectric loss material layer is a graphene oxide layer
  • a single layer of graphene oxide can be used as the low dielectric loss material layer, and the thickness of the single layer graphene oxide layer is 0.34 nm.
  • an appropriate thickness of the low dielectric loss material layer such as but not limited to 1nm, 2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 8nm , 9nm, 10nm, etc.
  • the high dielectric material layer may be, but is not limited to, formed of a doped dielectric ceramic material.
  • the doped dielectric ceramic material may be one or more of Ag, In, Sb, Bi, Ta, La, Nd, Ce, one or more metals doped HfO 2 , TiO 2 , ZrO 2 , CeO 2 A dielectric ceramic material. Based on the total weight of the doped dielectric ceramic material layer, the maximum dielectric constant can be achieved when the doping amount is between 1.5% and 3.5%. Therefore, those skilled in the art can select an appropriate value between 1.5% and 3.5% according to actual needs, such as but not limited to 1.8%, 2%, 2.3%, 2.5%, 2.8%, 3% and so on.
  • the low dielectric loss material layer may be formed of a low dielectric loss insulating material, such as polymer, graphene oxide, and the like.
  • the polymer may be formed from one or more selected from polyimide, polyvinylidene fluoride, epoxy resin, and polystyrene.
  • the inventive concept of the present disclosure will be explained below by taking the doped dielectric ceramic material as a high dielectric material layer as an example with reference to the accompanying drawings.
  • the high dielectric material is not intended to be limited to only doped dielectric ceramic materials.
  • the high dielectric material layer 22 contains dopant particles 222 in the dielectric ceramic material 221 , and since the dopant element replaces the metal in the dielectric ceramic material, more induced dipole moments are generated and the dopant ions enter The interior of the crystal will distort the lattice in favor of polarization, so it has a higher dielectric constant. However, due to the electron displacement of the doping particles, higher dielectric losses are caused.
  • the first low dielectric loss material layer 21 and the second low dielectric loss material layer 22 disposed on both sides of the high dielectric material layer 22 can effectively solve the problem of ion doping by covering the outer surface of the high dielectric material layer 22. Dielectric loss caused by impurities to achieve the purpose of low loss.
  • the first low dielectric loss material layer 21 and the second low dielectric loss material layer 22 may be polymer layers or graphene oxide layers.
  • first low dielectric loss material layers 21 a and 21 b and second low dielectric loss material layers 21 a and 21 b are respectively stacked on both sides of the two high dielectric material layers 22 a and 22 b Electrically lossy material layer 23 .
  • the high dielectric material layers 22a and 22b include dielectric ceramic materials 221a, 221b and doped particles 222a, 222b, respectively. Based on the same principle as the previous embodiment, the high dielectric material layers 22a and 22b can increase the dielectric constant of the material, and the first low dielectric loss material layers 21a and 21b and The second low dielectric loss material layer 23 achieves the purpose of low loss.
  • the dynamic random access memory capacitor of the present disclosure can be prepared by the following method. S1, forming a high dielectric material layer; S2, forming a low dielectric loss material layer on the high dielectric material layer; S3, forming a low dielectric loss material layer on the high dielectric material layer.
  • the steps S1, S2 and S3 only represent the context of the steps, and are not intended to limit the close connection between the steps, but other auxiliary steps, such as cleaning and drying, may also be included between the steps.
  • the dielectric ceramic material layer containing multiple layers of doping it can be achieved by repeating the steps S2 and S3 at least once.
  • the layer of doped dielectric ceramic material is formed by atomic layer deposition in step S2.
  • Monolayer graphene oxide (GO) was prepared by Hummers method. That is, graphite powder/NaNO 3 /KMnO 4 is mixed with a small amount of concentrated sulfuric acid/H 2 O 2 in a mass ratio of 10:5:12 as a reaction precursor, and the redox reaction is fully carried out in an ice bath (the reaction temperature is controlled not to exceed 10 °C). Derivatives were removed with H2SO4 / H2O2 /HCl to give graphene oxide .
  • Single-layer graphene oxide is obtained by ultrasonic or mechanical exfoliation. The single-layer graphene oxide is spin-coated on the surface of the first capacitor electrode (TiN) by an in-situ spin coating method to form a graphene oxide layer.
  • Tetradiethylamino hafnium (TDEAH), Sb(CH) and water were used as reaction precursors, and 99.99% high-purity nitrogen was used as carrier and flushing gas.
  • the temperature of the precursor was 100 degrees, and the temperature of the reaction chamber was 300 degrees.
  • Sb- doped HfO layer was
  • Another layer of GO was spin-coated on the surface of Sb-doped HfO2 , enabling GO to coat the Sb-doped HfO2 layer.
  • a second capacitor electrode (TiN) is formed on the surface of the outer graphene oxide layer, thereby completing the preparation of the DRAM capacitor.
  • Cyclotetradimethylamino titanium, CH 3 COOAg and water were used as reaction precursors, and 99.99% high-purity Ar was used as carrier and flushing gas.
  • the precursor temperature was 100 degrees
  • the reaction chamber temperature was 300 degrees
  • the Ag-doped TiO2 layer was deposited.
  • Table 1 shows the test results of the capacitor prepared in this example, the composition and thickness parameters of each layer in the dielectric layer.
  • Cyclotetradimethylamino titanium, InSb and water were used as reaction precursors, and high-purity Ar of 99.99 was used as carrier and flushing gas.
  • the precursor temperature was 100 degrees
  • the reaction chamber temperature was 300 degrees
  • the In and Sb doped TiO2 layers were deposited.
  • Table 1 shows the test results of the capacitor prepared in this example, the composition and thickness parameters of each layer in the dielectric layer.
  • Tetradimethylamino zirconium, C 6 H 9 BiO 6 and water were used as reaction precursors, and high-purity Ar of 99.99 was used as carrier and flushing gas.
  • the precursor temperature was 100 degrees
  • the reaction chamber temperature was 300 degrees
  • the Bi-doped ZrO 2 layer was deposited.
  • Table 1 shows the test results of the capacitor prepared in this example, the composition and thickness parameters of each layer in the dielectric layer.
  • Tetradimethylamino zirconium, TaH and water were used as reaction precursors, and high-purity Ar of 99.99 was used as carrier and flushing gas.
  • the precursor temperature was 100 degrees, and the reaction chamber temperature was 300 degrees, and a Ta-doped ZrO 2 layer was deposited.
  • Polyvinylidene fluoride, N,N-dimethylformamide and acetone were prepared into a precursor solution with a concentration percentage of 25%, heated to dissolve, and electrospinning was used to form a Tyler cone under the high pressure of 10KV. It is deposited on the TIN electrode in a filamentary shape, and then annealed at 200 degrees to obtain a 2nm polyvinylidene fluoride fiber film layer.
  • Table 1 shows the test results of the capacitor prepared in this example, the composition and thickness parameters of each layer in the dielectric layer.
  • Tetradiethylamino hafnium (TDEAH), LaH and water were used as reaction precursors, 99.99% high-purity nitrogen was used as carrier and flushing gas, the precursor temperature was 100°C, and the reaction chamber temperature was 300°C. HfO 2 layer.
  • Table 1 shows the test results of the capacitor prepared in this example, the composition and thickness parameters of each layer in the dielectric layer.
  • Tetradiethylamino hafnium (TDEAH), Ce(AC)3 and water were used as reaction precursors, 99.99% high-purity nitrogen was used as carrier and flushing gas, the precursor temperature was 100 degrees, the reaction chamber temperature was 300 degrees, and the deposition A Ce-doped HfO 2 layer is obtained.
  • Table 1 shows the test results of the capacitor prepared in this example, the composition and thickness parameters of each layer in the dielectric layer.
  • Example 2 After the 3-layer structure was prepared in the same manner as in Example 1, the Sb-doped HfO 2 layer and the GO layer were repeatedly formed once each, and finally the second capacitor electrode was formed, thereby completing the preparation of the DRAM capacitor. The capacitors were tested for dielectric constant and dielectric loss in the same manner as in Example 1.
  • Table 1 shows the test results of the capacitor prepared in this example, the composition and thickness parameters of each layer in the dielectric layer.
  • Tetradiethylamino hafnium ( TDEAH ) water was used as the reaction precursor, and 99.99% high-purity nitrogen was used as the carrier and flushing gas.
  • the formation methods and testing methods of other layers are the same as those in Example 1.
  • Table 1 shows the test results of the capacitors prepared in this comparative example, as well as the composition and thickness parameters of the dielectric layer.
  • Tetradiethylamino hafnium (TDEAH), SbCl 3 /Sb(CH) and water were used as reaction precursors, 99.99% high-purity nitrogen was used as carrier and flushing gas, the precursor temperature was 100 degrees, and the reaction chamber temperature was 300 degrees Celsius , and deposited the Sb-doped HfO2 layer.
  • Table 1 shows the test results of the capacitors prepared in this comparative example, as well as the composition and thickness parameters of the dielectric layer.
  • the dielectric layer of the present disclosure can indeed achieve the purpose of taking into account the high dielectric constant and low dielectric loss of the capacitor.

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Abstract

一种动态随机存取存储器电容器及其制备方法。其中，DRAM电容器包括介电层（2），所述介电层（2）包括：高介电材料层（22）；和低介电损耗材料层（21，23），设置在所述高介电材料层（22）两侧表面。高介电材料层（22）可以提高介电层（2）的介电常数，使其具有更好的介电性能；两侧表面设置的低介电损耗材料层（21，23）可以有效解决高介电材料层（22）的介电损耗，从而实现介电层（2）的高介电常数和低介电损耗的目的。所述DRAM电容器制程简单，便于工业化生产。

Description

动态随机存取存储器电容器及其制备方法
相关申请的交叉引用
本公开要求在2020年11月26日提交的中国专利申请号202011349123.8的优先权，以上专利通过引用被全部合并至本公开。
技术领域
本公开属于半导体元件领域，具体涉及一种动态随机存取存储器电容器及其制备方法。
背景技术
随着电子工业向多功能化发展，电子器件的集成化、小型化和高性能化已经成为一种趋势。对于DRAM电容器来说，其中的介电材料层也越来越薄，不仅工艺制程越来越难达到，还会导致介电损耗也越来越高。
提供一种具有高介电常数和低介电损耗的DRAM电容器介电层成为亟待解决的问题。
发明内容
本公开实施例一方面提供一种动态随机存取存储器电容器，包括介电层，所述介电层包括：高介电材料层；和低介电损耗材料层，设置在所述高介电材料层两侧表面。
本公开实施例另一方面提供一种动态随机存取存储器电容器的制备方法，包括：S1，形成低介电损耗材料层；S2，在所述低介电损耗材料层上形成高介电材料层；S3，在所述高介电材料层上形成低介电损耗材料层。
本公开实施例提供的DRAM电容器的介电层包括高介电材料层和设置在高介电材料层两侧表面的低介电损耗材料层，高介电材料层可以提高介电层的介电常数，使其具有更好的介电性能；两侧表面设置的低介电损耗材料层可以有效解决高介电材料层的介电损耗，从而实现介电层的高介电常数和低介电损耗的目的。本公开实施例提供的DRAM电容器制程简单，便于工业化生产。
附图说明
通过参照附图详细描述其示例实施方式，本公开的上述和其它特征及优点将变得更加明显。
图1A是本公开一实施方式的DRAM电容器的局部剖面示意图。
图1B是图1A中DRAM电容器的介电层的局部放大示意图。
图2A本公开另一实施方式的DRAM电容器的局部剖面示意图。
图2B是图2A中DRAM电容器的介电层的局部放大示意图。
其中，附图标记说明如下：
1：第一电容器电极
2：介电层
21，21a，21b：第一低介电损耗材料层
22：高介电材料层
221，221a，221b：介电陶瓷材料粒子
222，222a，222b：掺杂粒子
23：第二低介电损耗材料层
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。在图中，为了清晰，夸大了区域和层的厚度。在图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
本文中术语“高介电常数材料是指介电常数高于4的材料；术语“低介电损耗材料”是指介电损耗低于0.2的材料。
本公开的动态随机存取存储器电容器，包括介电层，其中介电层包括高介电材料层和设置在高介电材料层两侧表面的低介电损耗材料层。高介电材料可以提高介电层的介电常数，使其具有更好的介电性能。两侧表面设置的低介电损耗材料层可以有效解决高介电材料层的介电损耗，从而实现介电层的高介电常数和低介电损耗的目的。
在可选的实施方式中，如图1A所示，介电层2包括一层高介电材料层22和设置在内侧的、与DRAM电容器的第一电容器电极1表面的第一低介电损耗材料层21和设置在外侧的第二低介电损耗材料层23。
在可选的实施方式中，如图2A所示，介电层2包括两层高介电材料层22，即高介电材料层22a和22b。也就是说，高介电材料层22a、22b与低介电损耗材料层21a、21b、23交替排列。
以上两种方式仅是列举，介电层还可以是更多层的堆叠，例如包含3层高介电材料层和4层低介电损耗材料层的堆叠、或者包含4层高介电材料层和5层低介电损耗材料层的堆叠等等。
在可选的实施方式中，高介电材料层与低介电损耗材料层的厚度比为200-100：1。即，如图1B所示，介电层2的总厚度d为高介电层22的厚度d 1和低介电损耗材料层21和23的厚度d 2的和(即，d＝d 1+2d 2)，高介电材料层22的厚度d 1与低介电损耗材料层21、23 的厚度d 2的比为200-100：1。当介电层2包括两层高介电材料层时，如图2B所示，介电层2的总厚度d为高介电层22a、22b的厚度d 4和低介电损耗材料层21a、21b、23的厚度d 3的和(即，d＝2d 4+3d 3)，高介电材料层22a、22b的厚度d 4与低介电损耗材料层21a、21b、23的厚度d 3的比为200-100：1。根据电容串联的相关公式，可知高介电材料层的厚度与低介电损耗材料层的厚度比越大，介电层的介电常数越接近高介电材料层的介电常数，因此为了发挥高介电材料层的高介电常数性能，趋向于选择更大的厚度比。但同时考虑工艺可行性和介电层的总体厚度，在一些实施例中，高介电材料层与低介电损耗材料层的厚度比为200-100：1。本领域技术人员可以根据具体的需要选择其中的任何数值，例如190：1、180：1、170：1、160：1、150：1、140：1、130：1、120：1、110：1等等。低介电损耗材料层的厚度可以是0.34nm-10nm。当低介电损耗材料层为氧化石墨烯层时，可以采用单层氧化石墨烯作为低介电损耗材料层，单层氧化石墨烯层的厚度为0.34nm。综合考虑电容器的性能、工艺可行性、材料的种类和成本等因素，选择适当的低介电损耗材料层的厚度，例如但不限于为1nm、2nm、3nm、4nm、5nm、6nm、7nm、8nm、9nm、10nm等等。
在可选的实施方式中，高介电材料层可以但不限于，由掺杂的介电陶瓷材料形成。掺杂的介电陶瓷材料可以是Ag、In、Sb、Bi、Ta、La、Nd、Ce中一种或多种金属掺杂的HfO 2、TiO 2、ZrO 2、CeO 2中一种或多种介电陶瓷材料。以掺杂的介电陶瓷材料层的总重量计，掺杂量在1.5％-3.5％之间时，介电常数可以达到最大。因此，本领域技术人员可以根据实际的需要，在1.5％-3.5％之间选择适当的数值，例如但不限于1.8％、2％、2.3％、2.5％、2.8％、3％等等。
低介电损耗材料层可以是由低介电损耗绝缘材料形成，例如聚合物、氧化石墨烯等。聚合物可以选自聚酰亚胺、聚偏氟乙烯、环氧树脂、聚苯乙烯中的一种或多种形成。
以下结合附图，以掺杂的介电陶瓷材料为高介电材料层为例解释本公开的发明构思。但本领域技术人员应当理解，高介电材料不并意在仅限定为掺杂的介电陶瓷材料。
参照图1B，高介电材料层22由于介电陶瓷材料221中包含掺杂粒子222，由于掺杂元素取代介电陶瓷材料中的金属，从而产生更多的感应偶极矩以及掺杂离子进入晶体内部后会使晶格畸变有利于极化，所以拥有更高的介电常数。但是，由于掺杂粒子会产生电子位移，从而导致较高的介电损耗。设置在高介电材料层22两侧的第一低介电损耗材料层21和第二低介电损耗材料层22，通过包覆在高介电材料层22外表面，可以有效解决因离子掺杂导致的介电损耗，实现低损耗的目的。同时掺杂后可以增加介电陶瓷材料的粘结与低介电损耗材料层之间的粘结强度。第一低介电损耗材料层21和第二低介电损耗材料层22可以是聚合物层或氧化石墨烯层。
参照图2B，当介电层包含两层高介电材料层时，两层高介电材料层22a和22b的两侧分别层叠有第一低介电损耗材料层21a和21b和第二低介电损耗材料层23。高介电材料层22a和22b分别包括介电陶瓷材料221a，221b和掺杂粒子222a,222b。基于前述实施方 式相同的原理，高介电材料层22a和22b可以提高材料的介电常数，包覆在介电陶瓷材料层22a和22b两侧的第一低介电损耗材料层21a和21b和第二低介电损耗材料层23实现低损耗的目的。
本公开的动态随机存取存储器电容器可以通过如下方法制备。S1，形成高介电材料层；S2，在高介电材料层上形成低介电损耗材料层；S3，在高介电材料层上形成低介电损耗材料层。其中步骤S1、S2和S3仅表示步骤地前后关系，并不意在限定各步骤之间紧密连接，而是各步骤之间还可以包含其它辅助步骤，例如清洗、干燥等步骤。当制备包含多层掺杂的介电陶瓷材料层时，重复S2、S3步骤至少一次即可实现。在一些实施例中，S2步骤中通过原子层沉积形成掺杂的介电陶瓷材料层。
以下通过具体实例进一步描述本公开。不过这些实例仅仅是范例性的，并不对本公开的保护范围构成任何限制。
在下述实施例和对比例中，所使用到的试剂、材料以及仪器如没有特殊的说明，均可商购获得。
实施例1
采用Hummers法制备单层氧化石墨烯(GO)。即将石墨粉/NaNO 3/KMnO 4以质量比10：5：12混合少量浓硫酸/H 2O 2作为反应前驱体，在冰浴条件充分进行氧化还原反应(控制反应温度不超过10℃)。用H 2SO 4/H 2O 2/HCl去除衍生物，得到氧化石墨烯。通过超声或者机械剥离，得到单层氧化石墨烯。将单层氧化石墨烯通过原位旋涂法，旋涂在第一电容器电极(TiN)表面，形成氧化石墨烯层。
采用四二乙基氨基铪(TDEAH)、Sb(CH)和水作为反应前驱体，采用99.99的高纯氮气作为载体和冲洗气体，前驱体温度为100度，反应腔室温度300℃，沉积得到Sb掺杂的HfO 2层。
在Sb掺杂的HfO 2表面再旋涂一层GO，使GO能够包覆Sb掺杂的HfO 2层。
在外侧的氧化石墨烯层表面形成第二电容器电极(TiN)，从而完成DRAM电容器的制备。
通过上海爱义电子设备有限公司AS2855高频介电常数介质损耗测试系统对电容器进行介电常数和介电损耗测试AS2855高频介电常数介质损耗测试系统由S916测试装置(夹具)、QBG-3E/QBG-3F/AS2853A型高频Q表、数据采集和tanδ自动测量控件(装入QBG-3E/QBG-3F或AS2853A的软件模块)、及LKI-1型电感器组成。使用QBG-3E/3F或AS2853A数字Q表具有自动计算介电常数(ε)和介质损耗(tanδ)。电容器的测试结果及介电层中各层的组成、厚度参数如表1所示。
实施例2
采用环四二甲氨基钛、CH 3COOAg和水作为反应前驱体，采用99.99的高纯Ar作为载体和冲洗气体。前驱体温度100度，反应腔室温度300度，沉积得到Ag掺杂的TiO 2层。
其它各层的形成方式及测试方法与实施例1相同。
该实施例制备的电容器的测试结果及介电层中各层的组成、厚度参数如表1所示。
实施例3
采用环四二甲氨基钛、InSb和水作为反应前驱体，采用99.99的高纯Ar作为载体和冲洗气体。前驱体温度100度，反应腔室温度300度，沉积得到In和Sb掺杂的TiO 2层。
选择一定质量的聚酰亚胺固体颗粒与万能溶剂N,N-二甲基甲酰胺配出浓度百分比为25％的聚酰亚胺前驱液，然后采用高速旋涂的方法在TiN上面旋涂前驱液(转速5000)，然后放进炉管用200度退火，得到2nm的聚酰亚胺膜层。
其它各层的形成方式及测试方法与实施例1相同。
该实施例制备的电容器的测试结果及介电层中各层的组成、厚度参数如表1所示。
实施例4
采用四二甲氨基锆、C 6H 9BiO 6和水作为反应前驱体，采用99.99的高纯Ar作为载体和冲洗气体。前驱体温度100度，反应腔室温度300度，沉积得到Bi掺杂的ZrO 2层。
其它各层的形成方式及测试方法与实施例3相同。
该实施例制备的电容器的测试结果及介电层中各层的组成、厚度参数如表1所示。
实施例5
采用四二甲氨基锆、TaH和水作为反应前驱体，采用99.99的高纯Ar作为载体和冲洗气体。前驱体温度100度，反应腔室温度300度，沉积得到Ta掺杂的ZrO 2层。
将聚偏氟乙烯、N,N-二甲基甲酰胺、丙酮配出浓度百分比为25％的前驱液，加热溶解，采用静电纺丝法，在10KV的高压下，使前驱液形成Tyler锥并成拉丝状沉积在TIN电极上，然后200度退火得到2nm的聚偏氟乙烯纤维膜层。
其它各层的形成方式及测试方法与实施例1相同。
该实施例制备的电容器的测试结果及介电层中各层的组成、厚度参数如表1所示。
实施例6
采用四二乙基氨基铪(TDEAH)、LaH和水作为反应前驱体，采用99.99的高纯氮气作为载体和冲洗气体，前驱体温度为100度，反应腔室温度300℃，沉积得到La掺杂的HfO 2层。
其它各层的形成方式及测试方法与实施例5相同。
该实施例制备的电容器的测试结果及介电层中各层的组成、厚度参数如表1所示。
实施例7
采用四二乙基氨基铪(TDEAH)、Ce(AC)3和水作为反应前驱体，采用99.99的高纯氮气作为载体和冲洗气体，前驱体温度为100度，反应腔室温度300℃，沉积得到Ce掺杂的HfO 2层。
其它各层的形成方式及测试方法与实施例1相同。
该实施例制备的电容器的测试结果及介电层中各层的组成、厚度参数如表1所示。
实施例8
以实施例1相同的方式制备3层结构后，再重复形成Sb掺杂的HfO 2层和GO层各一次，最后形成第二电容器电极，从而完成DRAM电容器的制备。对电容器进行介电常数和介电损耗测试，方法与实施例1相同。
该实施例制备的电容器的测试结果及介电层中各层的组成、厚度参数如表1所示。
对比例1
采用四二乙基氨基铪(TDEAH)水作为反应前驱体，采用99.99的高纯氮气作为载体和冲洗气体，前驱体温度为100度，反应腔室温度300℃，沉积得到HfO 2层。其它各层的形成方式及测试方法与实施例1相同。
该对比例制备的电容器的测试结果及介电层的组成、厚度参数如表1所示。
对比例2
采用四二乙基氨基铪(TDEAH)、SbCl 3/Sb(CH)和水作为反应前驱体，采用99.99的高纯氮气作为载体和冲洗气体，前驱体温度为100度，反应腔室温度300℃，沉积得到Sb掺杂的HfO 2层。
该对比例制备的电容器的测试结果及介电层的组成、厚度参数如表1所示。
表1
Figure PCTCN2021105504-appb-000001
Figure PCTCN2021105504-appb-000002
如表1所示，结合实施例1-8和对比例1-2的数据可以看出，本公开的介电层确实可以实现兼顾电容器的高介电常数和低介电损耗的目的。
以上公开的本公开实施例只是用于帮助阐述本公开。部分实施例并没有详尽叙述所有的细节，也不限制该发明仅为所述的具体实施方式。显然，根据本说明书的内容，可作很多的修改和变化。本说明书选取并具体描述这些实施例，是为了更好地解释本公开的原理和实际应用，从而使所属技术领域技术人员能很好地理解和利用本公开。本公开仅受权利要求书及其全部范围和等效物的限制。

Claims (13)

  1. 一种动态随机存取存储器电容器，包括介电层，其中，所述介电层包括：
    高介电材料层；和
    低介电损耗材料层，设置在所述高介电材料层两侧表面。
  2. 根据权利要求1所述的动态随机存取存储器电容器，其中，所述介电层包括一层以上的所述高介电材料层。
  3. 根据权利要求2所述的动态随机存取存储器电容器，其中，所述介电层包括2层所述高介电材料层。
  4. 根据权利要求1所述的动态随机存取存储器电容器，其中，所述高介电材料层与所述低介电损耗材料层的厚度比为200-100：1，所述低介电损耗材料层的厚度为0.34nm-10nm。
  5. 根据权利要求4所述的动态随机存取存储器电容器，其中，所述高介电材料层与所述低介电损耗材料层的厚度比为200-150：1。
  6. 根据权利要求4所述的动态随机存取存储器电容器，其中，所述低介电损耗材料层的厚度为1nm-5nm。
  7. 根据权利要求1所述的动态随机存取存储器电容器，其中，所述高介电材料层包括掺杂的介电陶瓷材料，所述掺杂的介电陶瓷材料为Ag、In、Sb、Bi、Ta、La、Nd、Ce中一种或多种金属掺杂的HfO 2、TiO 2、ZrO 2、CeO 2中一种或多种介电陶瓷材料。
  8. 根据权利要求7所述的动态随机存取存储器电容器，其中，以所述掺杂的介电陶瓷材料的总重量计，所述Ag、In、Sb、Bi、Ta、La、Nd、Ce中一种或多种金属掺杂的掺杂重量含量为1.5％-3.5％。
  9. 根据权利要求1所述的动态随机存取存储器电容器，其中，所述低介电损耗材料层包括聚酰亚胺、聚偏氟乙烯、环氧树脂、聚苯乙烯、氧化石墨烯中的一种或多种。
  10. 一种动态随机存取存储器电容器的制备方法，其中，包括：
    S1，形成低介电损耗材料层；
    S2，在所述低介电损耗材料层上形成高介电材料层；
    S3，在所述高介电材料层上形成低介电损耗材料层。
  11. 根据权利要求10所述的制备方法，其中，依次重复所述S2、S3步骤至少一次。
  12. 根据权利要求10所述的制备方法，其中，所述高介电材料层包括掺杂的介电陶瓷材料，通过原子层沉积所述掺杂的介电陶瓷材料形成所述高介电材料层。
  13. 根据权利要求12所述的制备方法，其中，所述掺杂的介电陶瓷材料为Ag、In、Sb、Bi、Ta、La、Ce、Nd中一种或多种金属掺杂的HfO 2、TiO 2、ZrO 2、CeO 2中一种或多种介电陶瓷材料。
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