WO2022110594A1 - 发光二极管芯片及其制作方法、显示装置 - Google Patents

发光二极管芯片及其制作方法、显示装置 Download PDF

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Publication number
WO2022110594A1
WO2022110594A1 PCT/CN2021/083586 CN2021083586W WO2022110594A1 WO 2022110594 A1 WO2022110594 A1 WO 2022110594A1 CN 2021083586 W CN2021083586 W CN 2021083586W WO 2022110594 A1 WO2022110594 A1 WO 2022110594A1
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Prior art keywords
layer
light
semiconductor layer
accommodating groove
electrode
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PCT/CN2021/083586
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English (en)
French (fr)
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王涛
沈佳辉
伍凯义
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重庆康佳光电技术研究院有限公司
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Priority to US17/704,003 priority Critical patent/US20220216374A1/en
Publication of WO2022110594A1 publication Critical patent/WO2022110594A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes

Definitions

  • the present application relates to the field of semiconductor devices, and in particular, to a light-emitting diode chip, a manufacturing method thereof, and a display device.
  • LED Light Emitting Diode
  • the basic structure includes an n-type semiconductor layer and a p-type semiconductor layer and a light-emitting layer disposed between them.
  • the light-emitting layer is connected to another semiconductor layer, and in order to prevent the metal of the electrode from breaking, it is necessary to connect the semiconductor layer, the light-emitting layer to another semiconductor layer in turn by setting a chute, and the chute set in this way is difficult and the process time. It is long, and the area of the light-emitting layer is seriously lost, resulting in low light-emitting efficiency.
  • the purpose of the present application is to provide a light-emitting diode chip, a manufacturing method thereof, and a display device, aiming to solve the problems in the related art that the area of the light-emitting layer of the light-emitting diode chip is large and difficult to process.
  • a light-emitting diode chip comprising a light-transmitting substrate, an epitaxial layer, a first electrode and a second electrode;
  • the epitaxial layer includes a first semiconductor layer, a second semiconductor layer and a light-emitting layer, and the light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer;
  • An accommodating groove is arranged on the first semiconductor layer, and the bottom of the accommodating groove is not in contact with the light-emitting layer; a metal layer is arranged in the accommodating groove, and the metal layer and the first semiconductor layer are ohmic touch;
  • the second semiconductor layer is provided with an oblique groove at a position corresponding to the accommodating groove, and the oblique groove passes through the second semiconductor layer, the light-emitting layer and the first semiconductor layer in sequence, and makes the metal layer the surface is at least partially exposed;
  • the light-transmitting substrate is combined with the side of the first semiconductor layer on which the accommodating groove is formed;
  • the first electrode is disposed in the chute, and the second electrode is disposed on the second semiconductor layer.
  • the present application also provides a display device, wherein the display device includes several of the above-mentioned light-emitting diode chips.
  • the present application also provides a method for manufacturing a light-emitting diode chip, including:
  • the epitaxial layer comprising a first semiconductor layer, a second semiconductor layer and a light emitting layer, the light emitting layer being disposed between the first semiconductor layer and the second semiconductor layer;
  • an accommodating groove is provided on the first semiconductor layer, and the bottom of the accommodating groove does not contact the light-emitting layer;
  • a metal layer is arranged in the accommodating groove, and the metal layer is in ohmic contact with the first semiconductor layer;
  • a sloping groove is arranged at the position of the second semiconductor layer corresponding to the accommodating groove; wherein, the sloping groove passes through the second semiconductor layer, the light-emitting layer and the first semiconductor layer in sequence, and makes the metal layer the surface is at least partially exposed;
  • a first electrode is formed through the chute, and a second electrode is formed on the second semiconductor layer.
  • the length of the first electrode is greatly shortened, and the position of the inclined groove can be shallower, thereby The process difficulty is greatly reduced, and the area loss of the light-emitting layer is reduced, so that the light-emitting efficiency of the light-emitting diode is improved.
  • the display device in the present application is composed of several above-mentioned light-emitting diode chips, the display device has higher luminous efficiency.
  • the manufacturing method of the light-emitting diode chip in the present application by arranging an accommodating groove on the first semiconductor layer, and arranging a metal layer in the accommodating groove, the length of the first electrode is greatly shortened, and the arranging position of the chute can be more Therefore, the difficulty of manufacturing the light-emitting diode chip is greatly reduced, and the area loss of the light-emitting layer is reduced, so that the light-emitting efficiency of the light-emitting diode is improved.
  • FIG. 1 is a schematic structural diagram of a light-emitting diode chip in the prior art
  • FIG. 2 is a flowchart of a chip manufacturing method provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of a light-emitting diode chip provided with an accommodating groove according to an embodiment of the present application
  • FIG. 4 is a schematic structural diagram of a light-emitting diode chip provided with a metal layer in an accommodating groove according to an embodiment of the present application;
  • FIG. 5 is a schematic structural diagram of a light-emitting diode chip provided with an epitaxial layer disposed on a light-transmitting substrate according to an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram of a light-emitting diode chip provided with a chute provided by an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of a light-emitting diode chip provided with an insulating layer provided by an embodiment of the present application;
  • FIG. 8 is a schematic structural diagram of a light-emitting diode chip provided with electrodes according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another light-emitting diode chip according to an embodiment of the present application.
  • FIG. 10 is a flowchart of a chip manufacturing method provided by an embodiment of the present application.
  • 10-epitaxial layer 101-first semiconductor layer; 102-light emitting layer; 103-second semiconductor layer; 104-substrate; 105-light-transmitting substrate; 106-transparent bonding layer; 107-transparent current conducting layer; 108 - insulating layer; 109 - second electrode; 110 - first electrode; 20 - receiving groove; 30 - metal layer; 40 - chute; 1081 - first through hole; 1082 - second through hole.
  • the light-emitting diode chip structure generally includes a light-transmitting substrate 105 , a transparent bonding layer 106 connecting the light-transmitting substrate 105 and the epitaxial layer 10 , and a transparent current disposed at the bottom of the epitaxial layer 10 .
  • the two electrodes include the first electrode 110 and the second electrode 109, which need to be electrically connected to the two semiconductor layers respectively.
  • the first electrode 110 needs to penetrate the insulating layer 108 and the second electrode in sequence.
  • the first semiconductor layer 101 is provided with an accommodating groove 20 , and the metal layer 30 is disposed in the accommodating groove 20 , which is equivalent to a conductive connection position on the first semiconductor layer 101 Raised, so that the penetration depth of the inclined groove 40 is reduced when the electrodes are arranged, and on the premise that the angle of the inclined groove 40 remains unchanged, the loss of the area of the light emitting layer 102 by the inclined groove 40 can be greatly reduced, and because the accommodating groove 20 Only in the first semiconductor layer 101, the depth of the inclined groove 40 is also reduced, thereby reducing the process difficulty of the entire chip fabrication.
  • this embodiment takes the chip manufacturing method shown in FIG. 2 as an example below for easy-to-understand descriptions:
  • the chip fabrication method includes but is not limited to:
  • the epitaxial layer 10 includes a first semiconductor layer 101, a second semiconductor layer 103 and a light-emitting layer 102; the light-emitting layer 102 is disposed between the first semiconductor layer 101 and the second semiconductor layer 103;
  • a chute 40 is arranged at the position of the second semiconductor layer 103 corresponding to the accommodating groove 20; at least partially exposed;
  • the first electrode 110 is formed through the inclined groove 40
  • the second electrode 109 is formed on the second semiconductor layer 103 .
  • the chip fabrication method provided in the embodiment of the present application is applied to the fabrication of light emitting diode chips, including blue light diode chips, red light diode chips, and green light diode chips, and the like.
  • the light emitting diode chip can be made of compounds containing gallium (Ga), arsenic (As), phosphorus (P), nitrogen (N), etc., such as red aluminum gallium indium phosphide (AlGaInP ) LED chips, Gallium Nitride (GaN) LED chips, etc.
  • the light-emitting principle of light-emitting diodes is: like ordinary diodes, light-emitting diodes are composed of PN junctions and have unidirectional conductivity. When a forward voltage in line with its unidirectional conduction direction is applied to the light-emitting diode, the holes from the p-region to the n-region and the electrons injected from the n-region to the p-region are connected with the electrons of the n-region and the p-region near the PN junction, respectively. The holes in the region recombine, resulting in spontaneous emission of fluorescence. The energy states of electrons and holes in different semiconductor materials are different. When electrons and holes recombine, the energy released is somewhat different, the more energy released, the shorter the wavelength of the light emitted. Commonly used are diodes that emit red, green or yellow light.
  • the light emitting diode chip needs to be provided with a positive electrode and a negative electrode on the p-type semiconductor layer and the n-type semiconductor layer, respectively, and emit light by the above-mentioned separation after energization.
  • a light-emitting diode with a top-bottom stacked design one of the two electrodes can be directly disposed on the surface of a semiconductor layer, and the other electrode must pass through the semiconductor layer and the light-emitting layer 102 to another semiconductor layer to Connectivity to another semiconductor layer is achieved.
  • the epitaxial layer 10 includes two semiconductor layers and a light-emitting layer 102 located between the semiconductor layers, wherein the semiconductor layers include a first semiconductor layer 101 and a second semiconductor layer 103 respectively, wherein the first semiconductor layer 101 and the second semiconductor layer 103 are in the p Choose one of the n-type semiconductor and the n-type semiconductor, that is, if the first semiconductor layer 101 is a p-type semiconductor, then the second semiconductor layer 103 is an n-type semiconductor; if the first semiconductor layer 101 is an n-type semiconductor, then the second semiconductor layer 101 is an n-type semiconductor.
  • Layer 103 is a p-type semiconductor. In this embodiment, although there are differences between the first semiconductor layer 101 and the second semiconductor layer 103, their respective semiconductor types are not limited.
  • an accommodating groove 20 is provided on the first semiconductor layer 101 .
  • the opening of the accommodating groove 20 extends from the surface of the first semiconductor to the inside of the first semiconductor, and does not contact the light-emitting layer 102 .
  • the accommodating groove 20 is a space structure having a bottom and side walls, and the bottom of the accommodating groove 20 refers to the bottom surface opposite to the opening direction of the accommodating groove 20 , which is the same as the bottom surface of the accommodating groove 20 .
  • the placement direction of the epitaxial layer 10 and the first semiconductor layer 101 is irrelevant.
  • the placement mode of the epitaxial layer 10 may be the first semiconductor layer 101, the light emitting layer 102 and the second semiconductor layer 103 in order from top to bottom.
  • the opening direction of the accommodating groove 20 is upward; or the second semiconductor layer 103 , the light emitting layer 102 and the first semiconductor layer 101 are sequentially from top to bottom, in this case, the opening direction of the accommodating groove 20 is downward.
  • the accommodating groove 20 in the embodiment of the present application only defines that the accommodating groove 20 is opened from the outer surface of the first semiconductor layer 101 inward, and does not limit its specific spatial direction.
  • the embodiment of the present application does not limit the opening shape of the accommodating groove 20, and the opening shape of the accommodating groove 20 may be a rectangle, a circle, an ellipse, a semicircle, a triangle, and the like.
  • a metal layer 30 is disposed, and the metal layer 30 can form an ohmic contact with the first semiconductor layer 101 , please refer to FIG. 4 .
  • the so-called ohmic contact means that when the semiconductor is in contact with the metal, a potential barrier layer is often formed, but when the semiconductor doping concentration is high, electrons can pass through the potential barrier by the tunnel effect, thereby forming a low-resistance ohmic contact.
  • Ohmic contact is very important for semiconductor devices, and forming a good ohmic contact is beneficial to the input and output of current.
  • alloys with different formulations are often selected as ohmic contact materials.
  • the metal layer 30 can be an alloy material that matches the work function such as gold germanium alloy AuGe, gold tin alloy AuSn, gold zinc alloy AuZn, gold beryllium alloy AuBe, etc., and can form ohmic contact with P type.
  • the specific setting process of the metal layer 30 may be setting by means of evaporation.
  • the metal layer 30 is generally arranged at the bottom of the accommodating groove 20. Based on the different depths of the accommodating groove 20, the distance between the metal layer 30 and the light-emitting layer 102 and the second semiconductor layer 103 can be adjusted.
  • the epitaxial layer 10 and the light-transmitting substrate 105 are fixedly connected, that is, the first semiconductor layer 101 and the light-transmitting substrate 105 are combined.
  • the light-transmitting substrate 105 is combined.
  • the first semiconductor layer 101 is close to the light-transmitting substrate 105
  • the second semiconductor layer 103 is far away from the light-transmitting substrate 105
  • the corresponding light-emitting layer 102 is located therebetween. Since the first semiconductor layer 101 is provided with the accommodating groove 20 , it is equivalent to the position where the opening of the accommodating groove 20 is sealed by the light-transmitting substrate 105 .
  • connection between the light-transmitting substrate 105 and the epitaxial layer 10 can be realized by arranging a transparent bonding layer 106 therebetween;
  • Combining a light-transmitting substrate 105 may include: opening a side of the first semiconductor layer 101 with the accommodating groove 20 through a transparent bonding layer 106 to combine with the light-transmitting substrate 105 .
  • the so-called transparent bonding layer 106 generally refers to a transparent glue, which can transmit light while realizing a fixed connection, please refer to FIG. 5 .
  • the method may further include: providing a substrate 104 and growing the epitaxial layer 10 on the substrate 104 .
  • the epitaxial layer 10 may be fabricated on the substrate 104 in advance, and the substrate 104 only temporarily accommodates the epitaxial layer 10 , wherein the material of the substrate 104 may be gallium arsenide (GaAs).
  • GaAs gallium arsenide
  • combining the side of the first semiconductor layer 101 with the accommodating groove 20 with a light-transmitting substrate 105 may specifically include: opening the first semiconductor layer 101 with accommodating grooves 20 .
  • the substrate 104 After one side of the groove 20 is fixedly connected to the light-transmitting substrate 105, the substrate 104 is peeled off.
  • disposing the accommodating groove 20 on the first semiconductor layer 101 may be performed when the epitaxial layer 10 is placed on the substrate 104; for the epitaxial layer 10 disposed on the substrate 104, the outermost semiconductor layer is the It can be used as the first semiconductor layer 101 , which can facilitate the setting of the accommodating groove 20 , please refer to FIGS. 3 and 4 .
  • the electrodes of the light emitting diode chip include two, respectively, a first electrode 110 connected to the first semiconductor layer 101 and a second electrode 109 connected to the second semiconductor layer 103 .
  • the first electrode 110 and the second electrode 109 are insulated from each other. After the first electrode 110 and the second electrode 109 are connected to a positive voltage according to the unidirectional conduction direction of the light emitting diode, light can be emitted.
  • the second semiconductor layer 103 is far from the light-transmitting substrate 105 and is located on the outside, the first semiconductor layer 101 is close to the light-transmitting substrate 105 and is located on the inside, and the second electrode 109 is easier to set, and it is only necessary to set the second electrode 109 on the outermost side of the second semiconductor layer 103 to provide ohmic contact with the second semiconductor layer 103 .
  • the first electrode 110 needs to pass through the second semiconductor layer 103 and the light-emitting layer 102 to the bottom of the accommodating groove 20 provided on the first semiconductor layer 101 , and communicate with the metal layer 30 at the bottom of the accommodating groove 20 , and must maintain and Insulation between the first electrodes 110 .
  • the insulation between the first electrode 110 and the second electrode 109 is not only that there is no direct contact between the first electrode 110 and the second electrode 109 , but also does not directly pass through the first semiconductor layer 101 to achieve communication. Due to the arrangement of the accommodating groove 20 , the distance between the metal layer 30 and the light-emitting layer 102 and the second semiconductor layer 103 is small, the depth of the inclined groove 40 required for opening the second electrode 109 is shallower, and the area of the light-emitting layer 102 is lost. smaller.
  • the chute 40 in the embodiment of the present application means that the side of the chute 40 is inclined and funnel-shaped, which can facilitate the subsequent installation of the first electrode 110 and reduce the possibility of fracture of the first electrode 110, because if the If the groove is straight, the continuity requirement of the first electrode 110 is very high, and it is easy to break.
  • the specific shape of the inclined groove 40 in this embodiment may be a circular truncated shape, that is, a cavity of a rotating trapezoidal body.
  • the inclined plane angle of the chute 40 may be between 30 and 90 degrees and less than 90 degrees, and the optimum angle is generally 60 to 70 degrees, please refer to FIG. 6 .
  • the chute 40 may further include:
  • An insulating layer 108 is covered on the outer surface of the epitaxial layer 10 , please refer to FIG. 7 .
  • the outer surface of the epitaxial layer 10 represents the exposed surface of the epitaxial layer 10 after being connected to the light-transmitting substrate 105 , excluding the surface where the epitaxial layer 10 is connected to the light-transmitting substrate 105 .
  • the insulating layer 108 is disposed after the inclined groove 40 is disposed, so the insulating layer 108 will be disposed along the surface of the inclined groove 40 to cover the surface of the inclined groove 40 and thus cover the second semiconductor layer on the side of the inclined groove 40 103 , part of the light-emitting layer 102 and the first semiconductor layer 101 .
  • the electrodes are further provided, that is, the first electrode 110 is formed through the chute 40, and the second electrode 109 is formed on the second semiconductor layer 102, which may include:
  • a first through hole 1081 is opened on the insulating layer 108 at a position corresponding to the chute 40, and the first through hole 1081 communicates with the metal layer 30; a first electrode 110 is provided on the chute 40, and the first electrode 110 passes through the first through hole 1081 is connected to the metal layer 30;
  • a second through hole 1082 is formed on the insulating layer 108 at a position away from the inclined groove 40, and the second through hole 1082 communicates with the second semiconductor layer 103; a second electrode 109 is arranged on the through hole, and the second electrode 109 passes through the second through hole 1082 is in ohmic contact with the second semiconductor layer 103, please refer to FIG. 8 .
  • the first electrode 110 is connected to the metal layer 30 through a first through hole 1081 opened on the insulating layer 108 at a position corresponding to the chute 40, and the second electrode 109 is connected to the first through hole 1082 opened on the insulating layer 108.
  • the two semiconductor layers 103 are in ohmic contact. For better insulation effect, the position between the first through hole 1081 and the second through hole 1082 is relatively far.
  • the first semiconductor layer 101 may be a p-type semiconductor, and the second semiconductor layer 103 is correspondingly an n-type semiconductor.
  • the first electrode 110 is a positive electrode
  • the second electrode 109 is a negative electrode.
  • the setting process of the accommodating grooves 20 and the inclined grooves 40 may be realized by etching, that is, on the first semiconductor layer 101 , the setting of the accommodating grooves 20 may include: on the first semiconductor layer A photoresist layer is coated on 101;
  • the first semiconductor layer 101 is etched to form the accommodating groove 20 .
  • And setting the chute 40 may include:
  • the inclined groove 40 is etched inward from the outer surface of the second semiconductor layer 103 , and the bottom surface of the inclined groove 40 is communicated with the metal layer 30 .
  • the etching may be dry etching or wet etching.
  • the metal layer 30 may cover the entire space of the accommodating groove 20 , please refer to FIG. 9 .
  • the location of the metal layer 30 may be arranged only on the bottom surface of the accommodating groove 20, or may fill the entire accommodating groove 20, which basically does not affect the luminous efficiency of the light-emitting diode chip.
  • the length of the first electrode 110 is greatly shortened,
  • the position of the inclined groove 40 can be shallower, thereby greatly reducing the difficulty of the process and reducing the area loss of the light-emitting layer 102, so that the light-emitting efficiency of the light-emitting diode is improved.
  • the embodiments of the present application further provide a light-emitting diode chip, and the light-emitting diode chip is manufactured by the chip manufacturing method in the embodiments of the present application.
  • the light-emitting diode chip in the embodiment of the present application includes a light-transmitting substrate, an epitaxial layer, a first electrode and a second electrode; wherein,
  • the epitaxial layer includes a first semiconductor layer, a second semiconductor layer and a light-emitting layer, and the light-emitting layer is arranged between the first semiconductor layer and the second semiconductor layer;
  • the first semiconductor layer is provided with an accommodating groove, and the bottom of the accommodating groove is not in contact with the light-emitting layer; a metal layer is arranged in the accommodating groove, and the metal layer is in ohmic contact with the first semiconductor layer;
  • the second semiconductor layer is provided with an oblique groove at a position corresponding to the accommodating groove, and the oblique groove passes through the second semiconductor layer, the light-emitting layer and the first semiconductor layer in sequence, and at least partially exposes the surface of the metal layer;
  • the light-transmitting substrate is combined with the side of the first semiconductor layer where the accommodating groove is formed;
  • the first electrode is arranged in the inclined groove, and the second electrode is arranged on the second semiconductor layer.
  • the light emitting diode chips in the embodiments of the present application may include blue light diode chips, red light diode chips, green light diode chips, and the like.
  • the light emitting diode chip can be made of compounds containing gallium (Ga), arsenic (As), phosphorus (P), nitrogen (N), etc., such as red aluminum gallium indium phosphide (AlGaInP ) LED chips, Gallium Nitride (GaN) LED chips, etc.
  • the light-emitting principle of light-emitting diodes is: like ordinary diodes, light-emitting diodes are composed of PN junctions and have unidirectional conductivity.
  • the holes from the p-region to the n-region and the electrons injected from the n-region to the p-region are connected with the electrons of the n-region and the p-region near the PN junction, respectively.
  • the holes in the region recombine, resulting in spontaneous emission of fluorescence.
  • the energy states of electrons and holes in different semiconductor materials are different. When electrons and holes recombine, the energy released is somewhat different, the more energy released, the shorter the wavelength of the light emitted. Commonly used are diodes that emit red, green or yellow light.
  • the epitaxial layer 10 includes two semiconductor layers and a light-emitting layer 102 located between the semiconductor layers, wherein the semiconductor layers respectively include a first semiconductor layer 101 and a second semiconductor layer 103, wherein the first semiconductor layer 101 and the second semiconductor layer 103 are each selected from a p-type semiconductor and an n-type semiconductor, that is, if the first semiconductor layer 101 is a p-type semiconductor, then the second semiconductor layer 103 is an n-type semiconductor; if the first semiconductor layer 101 is an n-type semiconductor n-type semiconductor, then the second semiconductor layer 103 is a p-type semiconductor.
  • their respective semiconductor types are not limited.
  • an accommodating groove 20 is provided on the first semiconductor layer 101 .
  • the opening of the accommodating groove 20 extends from the surface of the first semiconductor to the inside of the first semiconductor, and does not contact the light-emitting layer 102 .
  • the embodiment of the present application does not limit the opening shape of the accommodating groove 20, and the opening shape of the accommodating groove 20 may be a rectangle, a circle, an ellipse, a semicircle, a triangle, and the like.
  • a metal layer 30 is provided, and an ohmic contact can be formed between the metal layer 30 and the first semiconductor layer 101 .
  • the metal layer 30 is generally arranged at the bottom of the accommodating groove 20. Based on the different depths of the accommodating groove 20, the distance between the metal layer 30 and the light-emitting layer 102 and the second semiconductor layer 103 can be adjusted. The smaller the distance between the layer 30 and the light-emitting layer 102 and the second semiconductor layer 103; and the smaller the distance between the metal layer 30 and the light-emitting layer 102 and the second semiconductor layer 103, the smaller the distance between the metal layer 30 and the light-emitting layer 102 and the second semiconductor layer 103, the smaller the distance between the The required depth of the groove 40 is also smaller.
  • the surface of the metal layer 30 is at least partially exposed because after the inclined groove 40 is provided, the inclined groove 40 penetrates through the metal layer 30 so that the metal layer 30 can be exposed through the inclined groove 40 .
  • the metal layer 30 may partially fill the receiving groove 20 ; alternatively, the metal layer may fill the receiving groove 20 . Partial filling means that the metal layer 30 only occupies a part of the space of the accommodating groove 20 , and filling means that the metal layer 30 fills the entire space of the accommodating groove 20 .
  • the first semiconductor layer 101 is combined with the light-transmitting substrate 105 . Specifically, a layer of the first semiconductor layer 101 on which the accommodating groove 20 is formed is combined with the light-transmitting substrate 105 . The first semiconductor layer 101 is close to the light-transmitting substrate 105 , the second semiconductor layer 103 is far away from the light-transmitting substrate 105 , and the corresponding light-emitting layer 102 is located therebetween. Since the first semiconductor layer 101 is provided with the accommodating groove 20 , it is equivalent to the position where the opening of the accommodating groove 20 is sealed by the light-transmitting substrate 105 .
  • it may further include: a transparent bonding layer 106;
  • the transparent bonding layer 106 is configured to bond the side of the first semiconductor layer 101 with the accommodating groove 20 to the light-transmitting substrate 105 .
  • the so-called transparent bonding layer 106 generally refers to a transparent glue, which can transmit light while realizing a fixed connection.
  • an insulating layer 108 may also be included;
  • the insulating layer 108 is disposed on the second semiconductor layer 102 , and the first electrode 110 and the second electrode 109 pass through the first through hole 1081 and the second through hole 1082 through the insulating layer 108 , the metal layer 30 and the second semiconductor layer 102 respectively. connect.
  • the insulating layer 108 is provided to better realize the insulation between the first electrode 110 and the second electrode 109; on the premise that the insulating layer 108 is provided, an electrode is further provided, that is, the first electrode 110 is made through the chute 40.
  • forming the second electrode 109 on the second semiconductor layer 102 is as follows:
  • a first through hole 1081 is opened on the insulating layer 108 at a position corresponding to the chute 40, and the first through hole 1081 communicates with the metal layer 30; a first electrode 110 is provided on the chute 40, and the first electrode 110 passes through the first through hole 1081 is connected to the metal layer 30;
  • a second through hole 1082 is formed on the insulating layer 108 at a position away from the inclined groove 40, and the second through hole 1082 communicates with the second semiconductor layer 103; a second electrode 109 is arranged on the through hole, and the second electrode 109 passes through the second through hole 1082 is in ohmic contact with the second semiconductor layer 103 .
  • the first electrode 110 is connected to the metal layer 30 through a first through hole 1081 opened on the insulating layer 108 at a position corresponding to the chute 40, and the second electrode 109 is connected to the first through hole 1082 opened on the insulating layer 108.
  • the two semiconductor layers 103 are in ohmic contact. For better insulation effect, the position between the first through hole 1081 and the second through hole 1082 is relatively far.
  • the accommodating groove 20 is provided on the first semiconductor layer 101, and the metal layer 30 is provided in the accommodating groove 20, so that the first electrode 110 is
  • the setting length is greatly shortened, and the setting position of the chute 40 can be shallower, thereby greatly reducing the difficulty of the process, reducing the area loss of the light-emitting layer 102, and improving the light-emitting efficiency of the light-emitting diode chip.
  • Embodiments of the present application further provide a display device, which includes several of the above-mentioned light-emitting diode chips.
  • the display device in the embodiment of the present application is composed of the same type of light-emitting diode chip obtained by the chip manufacturing method in the embodiment of the present application, so the manufacturing process of the display device is simpler and the luminous efficiency is higher.
  • the epitaxial layer 10 is formed on the substrate 104;
  • the epitaxial layer 10 includes two semiconductor layers and a light-emitting layer 102, the semiconductor layers are the first semiconductor layer 101 and the second semiconductor layer 103, the first semiconductor layer 101 and the second semiconductor layer respectively
  • the layers 103 are different, and the first semiconductor layer 101 and the second semiconductor layer 103 are respectively selected from a p-type semiconductor and an n-type semiconductor; the light-emitting layer 102 is arranged between the p-type semiconductor and the n-type semiconductor;
  • the second semiconductor layer 103 of the epitaxial layer 10 on the substrate 104 is connected to the substrate 104, and the first semiconductor layer 101 is far away from the substrate 104;
  • an accommodating groove 20 is provided, and the bottom of the accommodating groove 20 does not contact the light-emitting layer 102 , please refer to FIG. 3 ;
  • a metal layer 30 is disposed at the bottom of the accommodating groove 20 , and the metal layer 30 is in ohmic contact with the first semiconductor layer 101 , please refer to FIG. 4 ;
  • the substrate 104 is removed, and the epitaxial layer 10 is transferred to the transparent substrate 105, and is fixedly connected to the transparent substrate 105 through the transparent bonding layer 106; wherein, the first semiconductor layer 101 in the epitaxial layer 10 is connected to the transparent substrate 105.
  • the transparent substrates 105 please refer to FIG. 5;
  • an insulating layer 108 is provided on the exposed surface of the epitaxial layer 10; wherein, the insulating layer 108 covers the current surface of the epitaxial layer 10, and also covers the inclined surface of the chute 40, please refer to FIG. 7;
  • the embodiment of the present application also provides a chip manufacturing device, which includes a processor, a memory and a communication bus, wherein:
  • the communication bus is used to realize the connection communication between the processor and the memory
  • the processor is configured to execute one or more computer programs stored in the memory, so as to implement the steps of the chip manufacturing method in the embodiments of the present application.
  • Embodiments of the present application also provide a computer-readable storage medium included in any method or technology for storing information, such as computer-readable instructions, data structures, computer program modules, or other data Implemented volatile or nonvolatile, removable or non-removable media.
  • Computer-readable storage media include but are not limited to RAM (Random Access Memory, random access memory), ROM (Read-Only Memory, read-only memory), EEPROM (Electrically Erasable Programmable read only memory, electrically erasable programmable read-only memory), flash memory or other memory technology, CD-ROM (Compact Disc Read-Only Memory), digital versatile disk (DVD) or other optical disk storage, magnetic cartridges , magnetic tape, magnetic disk storage, or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer.
  • RAM Random Access Memory
  • ROM Read-Only Memory
  • EEPROM Electrically Erasable Programmable read only memory
  • flash memory or other memory technology
  • CD-ROM Compact Disc Read-Only Memory
  • DVD digital versatile disk
  • magnetic cartridges magnetic tape
  • magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and that can be accessed by a computer.
  • the computer-readable storage medium in the embodiments of the present application may be used to store one or more computer programs, and the one or more computer programs stored therein may be executed by a processor to implement at least one step performed by the above-mentioned chip manufacturing apparatus.
  • Embodiments of the present application also provide a computer program (or computer software), which can be distributed on a computer-readable medium and executed by a computable device, so as to implement at least one step performed by the above-mentioned chip manufacturing device; And in some cases, at least one of the steps shown or described may be performed in an order different from that described in the above embodiments.
  • a computer program or computer software
  • Embodiments of the present application further provide a computer program product, including a computer-readable device, on which the computer program shown above is stored.
  • the computer-readable device may include the computer-readable storage medium as shown above.
  • the functional modules/units in the system and the device can be implemented as software (which can be implemented by computer program codes executable by a computing device). ), firmware, hardware, and their appropriate combination.
  • the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be composed of several physical components Components execute cooperatively.
  • Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit .
  • communication media typically embodies computer readable instructions, data structures, computer program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and can include any information delivery, as is well known to those of ordinary skill in the art medium. Therefore, the present application is not limited to any particular combination of hardware and software.

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Abstract

本申请涉及一种发光二极管芯片及其制作方法、显示装置。发光二极管芯片包括透光基板（105）、外延层（10）、第一电极（110）以及第二电极（109）；外延层（10）包括第一半导体层（101）、第二半导体层（103）以及发光层（102）；第一半导体层（101）上设有一容置槽（20），容置槽（20）中设有一金属层（30），金属层（30）与第一半导体层（101）欧姆接触；第二半导体层（103）设有一斜槽（40），透光基板（105）与第一半导体层（101）结合，第一电极（110）设置于斜槽（40）中，第二电极（109）设置于第二半导体层（103）上。

Description

发光二极管芯片及其制作方法、显示装置
相关申请案交叉申请
本申请要求于2020年11月25日递交的发明名称为“发光二极管芯片及其制作方法、显示装置”的中国专利申请202011337564.6的优先权，上述申请作为参考全部结合到本申请中。
技术领域
本申请涉及半导体器件领域，尤其涉及一种发光二极管芯片及其制作方法、显示装置。
 背景技术
发光二极管（Light Emitting Diode， LED）是新一代的显示技术，与相关技术中的液晶显示相比具有更高的光电效率，更高的亮度，更高的对比度以及更低的功耗，且能结合柔性面板实现柔性显示，在相关领域中有着广泛的应用。在现有的发光二极管的制作工艺中，基本结构是包括n型半导体层和p型半导体层和设置在两者之间的发光层，在设置电极时，其中一个电极需要依次穿过半导体层、发光层到另一半导体层，而为了防止该电极的金属断裂，需要通过设置斜槽的方式依次连通半导体层、发光层到另一半导体层，而这种方式设置的斜槽难度大，工艺时间长，而且的发光层面积损失严重，导致发光效率低下。
因此，如何降低对发光层面积损耗，降低工艺难度，是亟需解决的问题。
 技术问题
鉴于上述相关技术的不足，本申请的目的在于提供一种发光二极管芯片及其制作方法、显示装置，旨在解决相关技术中，发光二极管芯片的发光层面积损耗大，工艺难度高的问题。
 技术解决方案
一种发光二极管芯片，所述发光二极管芯片包括透光基板、外延层、第一电极和第二电极；
所述外延层包括第一半导体层、第二半导体层和发光层，所述发光层设置于所述第一半导体层和第二半导体层之间；
所述第一半导体层上设有一容置槽，所述容置槽的底部未接触所述发光层；所述容置槽中设有一金属层，所述金属层与所述第一半导体层欧姆接触；
所述第二半导体层对应所述所述容置槽的位置设有一斜槽，所述斜槽依次穿过所述第二半导体层、发光层和第一半导体层，并使所述金属层的表面至少部分露出；
所述透光基板与所述第一半导体层开设有所述容置槽的一侧结合；以及，
所述第一电极设置于所述斜槽中，所述第二电极设置于所述第二半导体层上。
基于同样的发明构思，本申请还提供一种显示装置，所述显示装置中包括若干上述的发光二极管芯片。
基于同样的发明构思，本申请还提供一种发光二极管芯片的制作方法，包括：
提供外延层，所述外延层包括第一半导体层、第二半导体层和发光层，所述发光层设置于所述第一半导体层和第二半导体层之间；
在所述第一半导体层上，设置一容置槽，所述容置槽的底部未接触所述发光层；
在所述容置槽中设置一金属层，所述金属层与所述第一半导体层欧姆接触；
将所述第一半导体层开设有所述容置槽的一侧与一透光基板结合；
于所述第二半导体层对应所述容置槽的位置设置一斜槽；其中，所述斜槽依次穿过所述第二半导体层、发光层和第一半导体层，并使所述金属层的表面至少部分露出；
透过所述斜槽制作第一电极，并在所述第二半导体层上制作第二电极。
 有益效果
本申请中的发光二极管芯片，通过在第一半导体层上设置容置槽，并在容置槽中设置金属层，使得第一电极的设置长度大大缩短，斜槽的设置位置可以更浅，从而大大降低了工艺难度，而且降低了对发光层的面积损耗，使得提升了发光二极管的发光效率。
本申请中的显示装置由于由若干上述发光二极管芯片组成，因此该显示装置具有更高的发光效率。
本申请中的发光二极管芯片的制作方法，通过在第一半导体层上设置容置槽，并在容置槽中设置金属层，使得第一电极的设置长度大大缩短，斜槽的设置位置可以更浅，从而大大降低了制得发光二极管芯片的工艺难度，而且降低了对发光层的面积损耗，使得提升了发光二极管的发光效率。
 附图说明
图1为现有技术中的发光二极管芯片结构示意图；
图2为本申请实施例提供的芯片制造方法流程图；
图3为本申请实施例提供的设置容置槽的发光二极管芯片结构示意图；
图4为本申请实施例提供的在容置槽中设置金属层的发光二极管芯片结构示意图；
图5为本申请实施例提供的将外延层设置于透光基板上的发光二极管芯片结构示意图；
图6为本申请实施例提供的设置斜槽的发光二极管芯片结构示意图；
图7为本申请实施例提供的设置绝缘层的发光二极管芯片结构示意图；
图8为本申请实施例提供的设置电极的发光二极管芯片结构示意图；
图9为本申请实施例提供的另一发光二极管芯片结构示意图；
图10为本申请实施例提供的芯片制作方法流程图。
附图标记说明：
10-外延层；101-第一半导体层；102-发光层；103-第二半导体层；104-衬底；105-透光基板；106-透明键合层；107-透明电流传导层；108-绝缘层；109-第二电极；110-第一电极；20-容置槽；30-金属层；40-斜槽；1081-第一通孔；1082-第二通孔。
 本发明的实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的较佳实施方式。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施方式。相反地，提供这些实施方式的目的是使对本申请的公开内容理解的更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施方式的目的，不是旨在于限制本申请。
现有方案中，请参考图1，发光二极管芯片结构一般是依次包括透光基板105、连接透光基板105和外延层10之间的透明键合层106、设置在外延层10底部的透明电流传导层107、外延层10、绝缘层108以及两个电极；其中，外延层10从靠近到远离透光基板105依次包括第一半导体层101、发光层102和第二半导体层103。两个电极包括第一电极110和第二电极109，需要分别与两个半导体层电性连接，由于两个半导体层是层叠设置的，其中第一电极110就需要依次贯穿绝缘层108、第二半导体层103、发光层102和第一半导体层101，直至第一半导体层101底部的透明电流传导层107，而这么长的电极是很容易断裂的，因此需要设置斜槽40来提升电极的连接一体稳定性；这样就会导致，斜槽40非常深，贯穿了整个外延层10，且对发光层102的面积损失极大，大大影响了发光效率。
基于此，本申请希望提供一种能够解决上述技术问题的方案，其详细内容将在后续实施例中得以阐述。
本实施例所示例的发光二极管芯片，通过在第一半导体层101上，设置容置槽20，将金属层30设置在容置槽20中，相当于将第一半导体层101上的导电连接位置抬高，使得在设置电极时，降低了斜槽40的贯穿深度，在斜槽40的角度不变的前提下，可以大大降低斜槽40对发光层102面积的损失，且由于容置槽20只开设在第一半导体层101，斜槽40的深度也降低了，从而降低了整个芯片制作的工艺难度。为了便于理解，本实施例下面以图2所示的芯片制作方法为示例，进行便于理解性的说明：
请参见图2-9所示，该芯片制作方法包括但不限于：
S101、提供外延层10，外延层10包括第一半导体层101、第二半导体层103和发光层102；发光层102设置于第一半导体层101和第二半导体层103之间；
S102、在第一半导体层101上，设置一容置槽20，容置槽20的底部未接触发光层102；
S103、在容置槽中设置金属层30，金属层30与第一半导体层101欧姆接触；
S104、将第一半导体层101开设有容置槽20的一侧与一透光基板105结合；
S105、于第二半导体层103对应容置槽20的位置设置一斜槽40；斜槽40依次穿过第二半导体层103、发光层102和第一半导体层103，并使金属层30的表面至少部分露出；
S106、透过斜槽40制作第一电极110，并在第二半导体层103上制作第二电极109。
本申请实施例所提供的芯片制作方法是应用于发光二极管芯片的制作中，包括蓝光二极管芯片、红光二极管芯片以及绿光二极管芯片等等。按照其发光的颜色等等区分，发光二极管芯片可以由含镓（Ga）、砷（As）、磷（P）、氮（N）等的化合物制成，如红光磷化铝镓铟（AlGaInP）发光二极管芯片，氮化镓（GaN）发光二极管芯片等等。发光二极管的发光原理为：与普通二极管一样，发光二极管一样是由PN结组成，具有单向导电性。当给发光二极管加上符合其单向导电方向的正向电压时，从p区到n区的空穴和由n区注入到p区的电子，在PN结附近分别与n区的电子和p区的空穴复合，产生自发辐射的荧光。不同的半导体材料中电子和空穴所处的能量状态不同。当电子和空穴复合时释放出的能量多少不同，释放出的能量越多，则发出的光的波长越短。常用的是发红光、绿光或黄光的二极管。
有基于此，发光二极管芯片，需要在p型半导体层和n型半导体层上，分别设置正电极和负电极，在通电之后通过上述远离进行发光。而对于上下层叠式设计的发光二极管，其两个电极中，其中一个电极可以直接设置在某一半导体层的表面，另一电极则必须穿过半导体层、发光层102到另一半导体层，来实现和另一半导体层之间的连通。
外延层10包括两个半导体层和位于半导体层之间的发光层102，其中半导体层分别包括第一半导体层101和第二半导体层103，其中第一半导体层101和第二半导体层103在p型半导体和n型半导体中各自择一，也就是如果第一半导体层101是p型半导体，那么第二半导体层103就是n型半导体；如果第一半导体层101是n型半导体，那么第二半导体层103就是p型半导体。本实施例中，虽然有第一半导体层101和第二半导体层103的差别，并未限定其各自的半导体类型。
为了便于电极的设置，在第一半导体层101上，设置有容置槽20。容置槽20的开设是从第一半导体的表面向第一半导体的内部延伸，且不接触到发光层102。请参考图3，本领域技术人员均知晓，容置槽20是一种具有底部和侧壁的空间结构，且容置槽20的底部指的是容置槽20的开口方向相对的底面，与外延层10以及第一半导体层101的放置方向无关，外延层10的放置方式可以是从上到下依次是第一半导体层101、发光层102和第二半导体层103，在这种情况下容置槽20的开口方向朝上；或者是从上到下依次是第二半导体层103、发光层102和第一半导体层101，在这种情况下容置槽20的开口方向朝下。换言之，本申请实施例中的容置槽20，只是限定了其开设是从第一半导体层101的外表面向内，并不限定其具体的空间方向。此外，本申请实施例并不限定容置槽20的开口形状，容置槽20开口形状可以是矩形、圆形、椭圆形、半圆形、三角形等等。
在容置槽20中，设置有金属层30，金属层30可以和第一半导体层101之间形成欧姆接触，请参考图4。所谓欧姆接触，是指半导体与金属接触时，多会形成势垒层，但当半导体掺杂浓度很高时，电子可借隧道效应穿过势垒，从而形成低阻值的欧姆接触。欧姆接触对半导体器件非常重要，形成良好的欧姆接触有利于电流的输入和输出，对不同半导体材料常选择不同配方的合金作欧姆接触材料。为了形成欧姆接触，金属层30可以是金锗合金AuGe、金锡合金AuSn、金锌合金AuZn、金铍合金AuBe等功函数匹配，可以与P型形成欧姆接触的合金材料。金属层30的具体设置工艺可以是通过蒸镀方式设置。金属层30一般设置在容置槽20的底部，基于容置槽20的深度不同，可以调整金属层30和发光层102、第二半导体层103之间的距离，容置槽20越深，金属层30和发光层102、第二半导体层103之间的距离越小；而金属层30和发光层102、第二半导体层103之间的距离越小，在后续设置斜槽40的时候，斜槽40所需的深度也越小。值得一提的是，本实施例中通过设置容置槽20和金属层30，可以无需像现有技术一般在第一半导体层101表面设置透明电流传导层，从而降低了工艺难度和流程，节约了成本。其中，金属层30表面至少部分露出，是因为设置斜槽40后，斜槽40贯穿至金属层30使得金属层30可以通过斜槽40露出。
为了正常出光，外延层10与透光基板105之间固定连接，也就是将第一半导体层101与透光基板105结合，具体的，第一半导体层101开设有容置槽20的一层与透光基板105结合。第一半导体层101靠近透光基板105，第二半导体层103远离透光基板105，相应的发光层102距离位于两者之间。由于第一半导体层101上，设置有容置槽20，相当于透光基板105封住了容置槽20的开口所在的位置。
透光基板105和外延层10之间的连接，可以通过在两者之间设置透明键合层106实现；也就是说，将第一半导体层101开设有所述容置槽20的一侧与一透光基板105结合可以包括：通过一透明键合层106，将第一半导体层101开设有容置槽20的一侧，与透光基板105结合。所谓透明键合层106，一般指的是透明的胶水，在实现固定连接的同时可以透光，请参考图5。
在一些实施例中，在提供外延层10之前，还可以包括：提供一衬底104，并于衬底104上生长外延层10。外延层10可以预先在衬底104上制作得到，衬底104只是暂时的容置外延层10，其中衬底104的材质可以是砷化镓GaAs。相应的，在外延层10在衬底104上生长时，将第一半导体层101开设有容置槽20的一侧与一透光基板105结合具体可以包括：将第一半导体层101开设有容置槽20的一侧与透光基板105固定连接之后，将衬底104剥离。换言之，在第一半导体层101上设置容置槽20，可以是在外延层10置于衬底104上时进行；对于设置在衬底104上的外延层10而言，最外侧的半导体层即可作为第一半导体层101，可以便于容置槽20的设置，请参考图3、4。
发光二极管芯片的电极包括两个，分别是与第一半导体层101连接的第一电极110，和与第二半导体层103连接的第二电极109。第一电极110和第二电极109之间是相互绝缘的，在将第一电极110和第二电极109按照发光二极管的单向导通方向，接入正电压之后，就可以发光了。由于第二半导体层103和第一半导体层101的层状结构，第二半导体层103距离透光基板105远，位于外侧，第一半导体层101距离透光基板105近，位于内侧，第二电极109更容易设置，只需要将第二电极109在第二半导体层103最外侧上，设置与第二半导体层103之间欧姆接触即可。而第一电极110，需要穿过第二半导体层103、发光层102至第一半导体层101上设置的容置槽20的底部，与容置槽20底部的金属层30连通，且要保持和第一电极110之间的绝缘。第一电极110和第二电极109之间的绝缘，不仅是第一电极110和第二电极109之间没有直接接触，而且也不会直接通过第一半导体层101，实现连通。由于容置槽20的设置，金属层30和发光层102、第二半导体层103之间的间距小，开设第二电极109所需的斜槽40的深度更浅，对发光层102的面积损失更小。本申请实施例中的斜槽40，表示的是斜槽40的侧面是倾斜的，呈漏斗状，可以便于后续第一电极110的设置，降低第一电极110的断裂可能，因为如果设置的是直槽，那么第一电极110的连续性要求就会很高，很容易发生断裂。本实施例中的斜槽40，其具体的形状可以为圆台形，也就是旋转梯形体的空腔。斜槽40的斜面角度可以是在30~90度之间不到90度，最佳角度一般是60~70度，请参考图6。
为了更好的实现第一电极110和第二电极109之间的绝缘，在一些实施例中，在设置斜槽40之后，还可以包括：
在外延层10的外表面上覆盖绝缘层108，请参考图7。其中，外延层10的外表面，表示的是外延层10在连接到透光基板105之后所外露的表面，是排除了外延层10与透光基板105连接的表面的。绝缘层108是在设置了斜槽40之后所设置，因此绝缘层108会沿着斜槽40的表面设置，包覆斜槽40的表面，因此会覆盖住位于斜槽40侧面的第二半导体层103、发光层102和第一半导体层101的部分。
在设置了绝缘层108的前提下，进一步设置电极，也就是透过斜槽40制作第一电极110，并在第二半导体层102上制作第二电极109可以包括：
在绝缘层108上与斜槽40对应的位置开设第一通孔1081，第一通孔1081与金属层30相通；在斜槽40上设置第一电极110，第一电极110通过第一通孔1081与金属层30相连；
在绝缘层108上远离斜槽40的位置开设第二通孔1082，第二通孔1082与第二半导体层103相通；在通孔上设置第二电极109，第二电极109通过第二通孔1082与第二半导体层103欧姆接触，请参考图8。第一电极110通过绝缘层108上与斜槽40对应的位置所开设的第一通孔1081，与金属层30连接，第二电极109通过绝缘层108上开设的第二通孔1082，与第二半导体层103欧姆接触。为了更好的绝缘效果，第一通孔1081和第二通孔1082之间的位置较远。
在一些实施例中，第一半导体层101可以为p型半导体，第二半导体层103相应的为n型半导体。对应的，第一电极110是正电极，第二电极109是负电极。
在一些实施例中，容置槽20、斜槽40的设置工艺可以是通过蚀刻的方式实现，也就是说，在第一半导体层101上，设置容置槽20可以包括：于第一半导体层101上涂布一光阻层；
对光阻层进行图案化处理；
以图案化处理后的光阻层为掩膜，对第一半导体层101进行蚀刻以形成容置槽20。
而设置斜槽40可以包括：
通过蚀刻工艺，从第二半导体层103的外表面向内蚀刻出斜槽40，斜槽40的底面与金属层30连通。其中，蚀刻可以是干法蚀刻或者是湿法蚀刻。
在一些实施例中，金属层30可以覆盖整个容置槽20的空间，请参考图9。金属层30的设置位置可以仅仅设置在容置槽20的底面，或者是填充整个容置槽20均可，基本上不会对发光二极管芯片的发光效率造成影响。
可见，通过本申请实施例提供的芯片制作方法，通过在第一半导体层101上设置容置槽20，并在容置槽20中设置金属层30，使得第一电极110的设置长度大大缩短，斜槽40的设置位置可以更浅，从而大大降低了工艺难度，而且降低了对发光层102的面积损耗，使得提升了发光二极管的发光效率。
本申请实施例还提供了一种发光二极管芯片，该发光二极管芯片通过本申请实施例中的芯片制作方法制得。具体的，请参考图8和图9，本申请实施例中的发光二极管芯片，包括透光基板、外延层、第一电极和第二电极；其中，
外延层包括第一半导体层、第二半导体层和发光层，发光层设置于第一半导体层和第二半导体层之间；
第一半导体层上设有一容置槽，容置槽的底部未接触发光层；容置槽中设有一金属层，金属层与第一半导体层欧姆接触；
第二半导体层对应容置槽的位置设有一斜槽，斜槽依次穿过第二半导体层、发光层和第一半导体层，并使金属层的表面至少部分露出；
透光基板与第一半导体层开设有容置槽的一侧结合；
第一电极设置于斜槽中，第二电极设置于第二半导体层上。
本申请实施例中的发光二极管芯片，可以包括蓝光二极管芯片、红光二极管芯片以及绿光二极管芯片等等。按照其发光的颜色等等区分，发光二极管芯片可以由含镓（Ga）、砷（As）、磷（P）、氮（N）等的化合物制成，如红光磷化铝镓铟（AlGaInP）发光二极管芯片，氮化镓（GaN）发光二极管芯片等等。发光二极管的发光原理为：与普通二极管一样，发光二极管一样是由PN结组成，具有单向导电性。当给发光二极管加上符合其单向导电方向的正向电压时，从p区到n区的空穴和由n区注入到p区的电子，在PN结附近分别与n区的电子和p区的空穴复合，产生自发辐射的荧光。不同的半导体材料中电子和空穴所处的能量状态不同。当电子和空穴复合时释放出的能量多少不同，释放出的能量越多，则发出的光的波长越短。常用的是发红光、绿光或黄光的二极管。
该发光二极管芯片的结构中，外延层10包括两个半导体层和位于半导体层之间的发光层102，其中半导体层分别包括第一半导体层101和第二半导体层103，其中第一半导体层101和第二半导体层103在p型半导体和n型半导体中各自择一，也就是如果第一半导体层101是p型半导体，那么第二半导体层103就是n型半导体；如果第一半导体层101是n型半导体，那么第二半导体层103就是p型半导体。本实施例中，虽然有第一半导体层101和第二半导体层103的差别，并未限定其各自的半导体类型。
为了便于电极的设置，在第一半导体层101上，设置有容置槽20。容置槽20的开设是从第一半导体的表面向第一半导体的内部延伸，且不接触到发光层102。本申请实施例并不限定容置槽20的开口形状，容置槽20开口形状可以是矩形、圆形、椭圆形、半圆形、三角形等等。
在容置槽20中，设置有金属层30，金属层30可以和第一半导体层101之间形成欧姆接触。金属层30一般设置在容置槽20的底部，基于容置槽20的深度不同，可以调整金属层30和发光层102、第二半导体层103之间的距离，容置槽20越深，金属层30和发光层102、第二半导体层103之间的距离越小；而金属层30和发光层102、第二半导体层103之间的距离越小，在后续设置斜槽40的时候，斜槽40所需的深度也越小。其中，金属层30表面至少部分露出，是因为设置斜槽40后，斜槽40贯穿至金属层30使得金属层30可以通过斜槽40露出。
在一些实施例中，金属层30可以部分填充容置槽20；或者，金属层可以填满容置槽20。部分填充表示金属层30只占据容置槽20空间的一部分，而填满表示金属层30充满了整个容置槽20的空间。
第一半导体层101与透光基板105之间结合，具体的，第一半导体层101开设有容置槽20的一层与透光基板105结合。第一半导体层101靠近透光基板105，第二半导体层103远离透光基板105，相应的发光层102距离位于两者之间。由于第一半导体层101上，设置有容置槽20，相当于透光基板105封住了容置槽20的开口所在的位置。
在一些实施例中，还可以包括：透明键合层106；
透明键合层106被配置为将第一半导体层101开设有容置槽20的一侧与透光基板105结合。所谓透明键合层106，一般指的是透明的胶水，在实现固定连接的同时可以透光。
在一些实施例中，还可以包括绝缘层108；
绝缘层108设置于第二半导体层102上，第一电极110、第二电极109分别透过贯穿绝缘层108的第一通孔1081、第二通孔1082与金属层30、第二半导体层102连接。设置绝缘层108是为了更好的实现第一电极110和第二电极109之间的绝缘；在设置了绝缘层108的前提下，进一步设置电极，也就是透过斜槽40制作第一电极110，并在第二半导体层102上制作第二电极109具体为：
在绝缘层108上与斜槽40对应的位置开设第一通孔1081，第一通孔1081与金属层30相通；在斜槽40上设置第一电极110，第一电极110通过第一通孔1081与金属层30相连；
在绝缘层108上远离斜槽40的位置开设第二通孔1082，第二通孔1082与第二半导体层103相通；在通孔上设置第二电极109，第二电极109通过第二通孔1082与第二半导体层103欧姆接触。第一电极110通过绝缘层108上与斜槽40对应的位置所开设的第一通孔1081，与金属层30连接，第二电极109通过绝缘层108上开设的第二通孔1082，与第二半导体层103欧姆接触。为了更好的绝缘效果，第一通孔1081和第二通孔1082之间的位置较远。
本申请实施例中的发光二极管芯片由于由上述芯片制作方法制得，通过在第一半导体层101上设置容置槽20，并在容置槽20中设置金属层30，使得第一电极110的设置长度大大缩短，斜槽40的设置位置可以更浅，从而大大降低了工艺难度，降低了对发光层102的面积损耗，提升了发光二极管芯片的发光效率。
本申请实施例还提供了一种显示装置，该显示装置中包括若干上述的发光二极管芯片。
本申请实施例中的显示装置，由于其由本申请实施例中的芯片制作方法，制得的同类发光二极管芯片组成，因此该显示装置的制作工艺更简单，且发光效率更高。
针对本申请实施例中的芯片制作方法，下面结合附图10进行具体的说明。
S201、在衬底104上生成外延层10；外延层10包括两层半导体层和发光层102，半导体层分别为第一半导体层101和第二半导体层103，第一半导体层101和第二半导体层103不同，且第一半导体层101和第二半导体层103分别在p型半导体和n型半导体中择一；发光层102设置于p型半导体和n型半导体之间；
其中，在衬底104上的外延层10，其第二半导体层103与衬底104连接，第一半导体层101远离衬底104；
S202、在第一半导体层101上，设置容置槽20，容置槽20的底部未接触发光层102，请参考图3；
S203、在容置槽20的槽底，设置金属层30，金属层30与第一半导体层101欧姆接触，请参考图4；
S204、将衬底104去除，并将外延层10转移到透光基板105上，通过透明键合层106与透光基板105固定连接；其中，通过外延层10中的第一半导体层101，与透光基板105之间固定连接，请参考图5；
S205、设置斜槽40，斜槽40与容置槽20的位置相对，斜槽40从第二半导体层103的外表面依次穿过第二半导体层103、发光层102和第二半导体层103，并连通金属层30，请参考图6；
S206、在外延层10外露的表面上，设置绝缘层108；其中，绝缘层108沿外延层10当前的表面覆盖，在斜槽40的斜面上同样有覆盖，请参考图7；
S207、在绝缘层108上设置第一通孔1081和第二通孔1082；其中，第一通孔1081设置在与斜槽40对应的位置，其位于斜槽40的底部，与第一半导体层101中的金属层30连通；第二通孔1082远离第一通孔1081设置，与第二半导体层103连通；
S208、设置第一电极110和第二电极109；其中，第一电极110通过蒸镀的方式，沿斜槽40表面的绝缘层108，穿过第一通孔1081与金属层30连接；第二电极109同样通过蒸镀的方式，沿绝缘层108上设置的第二通孔1082，与第二半导体层103欧姆接触。由于绝缘层108的设置，第一电极110和第二电极109之间的相互绝缘的，请参考图8。
本申请实施例还提供了一种芯片制作设备，其包括处理器、存储器及通信总线，其中：
通信总线用于实现处理器和存储器之间的连接通信；
处理器用于执行存储器中存储的一个或者多个计算机程序，以实现本申请实施例中的芯片制作方法的步骤。
本申请实施例还提供了一种计算机可读存储介质，该计算机可读存储介质包括在用于存储信息(诸如计算机可读指令、数据结构、计算机程序模块或其他数据)的任何方法或技术中实施的易失性或非易失性、可移除或不可移除的介质。计算机可读存储介质包括但不限于RAM（Random Access Memory，随机存取存储器）, ROM（Read-Only Memory，只读存储器）, EEPROM（Electrically Erasable Programmable read only memory，带电可擦可编程只读存储器）、闪存或其他存储器技术、CD-ROM（Compact Disc Read-Only Memory，光盘只读存储器），数字多功能盘(DVD)或其他光盘存储、磁盒、磁带、磁盘存储或其他磁存储装置、或者可以用于存储期望的信息并且可以被计算机访问的任何其他的介质。
本申请实施例中的计算机可读存储介质可用于存储一个或者多个计算机程序，其存储的一个或者多个计算机程序可被处理器执行，以实现上述芯片制作设备所执行的至少一个步骤。
本申请实施例还提供了一种计算机程序（或称计算机软件），该计算机程序可以分布在计算机可读介质上，由可计算装置来执行，以实现上述芯片制作设备所执行的至少一个步骤；并且在某些情况下，可以采用不同于上述实施例所描述的顺序执行所示出或描述的至少一个步骤。
本申请实施例还提供了一种计算机程序产品，包括计算机可读装置，该计算机可读装置上存储有如上所示的计算机程序。本申请实施例中该计算机可读装置可包括如上所示的计算机可读存储介质。
可见，本领域的技术人员应该明白，上文中所公开方法中的全部或某些步骤、系统、装置中的功能模块/单元可以被实施为软件（可以用计算装置可执行的计算机程序代码来实现）、固件、硬件及其适当的组合。在硬件实施方式中，在以上描述中提及的功能模块/单元之间的划分不一定对应于物理组件的划分；例如，一个物理组件可以具有多个功能，或者一个功能或步骤可以由若干物理组件合作执行。某些物理组件或所有物理组件可以被实施为由处理器，如中央处理器、数字信号处理器或微处理器执行的软件，或者被实施为硬件，或者被实施为集成电路，如专用集成电路。
此外，本领域普通技术人员公知的是，通信介质通常包含计算机可读指令、数据结构、计算机程序模块或者诸如载波或其他传输机制之类的调制数据信号中的其他数据，并且可包括任何信息递送介质。所以，本申请不限制于任何特定的硬件和软件结合。
应当理解的是，本申请的应用不限于上述的举例，对本领域普通技术人员来说，可以根据上述说明加以改进或变换，所有这些改进和变换都应属于本申请所附权利要求的保护范围。

Claims (15)

  1. 一种发光二极管芯片，所述发光二极管芯片包括透光基板、外延层、第一电极以及第二电极；
    所述外延层包括第一半导体层、第二半导体层以及发光层，所述发光层设置于所述第一半导体层和第二半导体层之间；
    所述第一半导体层上设有一容置槽，所述容置槽的底部未接触所述发光层；所述容置槽中设有一金属层，所述金属层与所述第一半导体层欧姆接触；
    所述第二半导体层对应所述所述容置槽的位置设有一斜槽，所述斜槽依次穿过所述第二半导体层、发光层和第一半导体层，并使所述金属层的表面至少部分露出；
    所述透光基板与所述第一半导体层开设有所述容置槽的一侧结合；以及，
    所述第一电极设置于所述斜槽中，所述第二电极设置于所述第二半导体层上。
  2. 如权利要求1所述的发光二极管芯片，其中，所述金属层部分填充所述容置槽。
  3. 如权利要求1所述的发光二极管芯片，其中，所述金属层部分填充所述容置槽。
  4. 如权利要求1所述的发光二极管芯片，其中，还包括透明键合层；
    所述透明键合层被配置为将所述第一半导体层开设有所述容置槽的一侧与所述透光基板结合。
  5. 如权利要求1-4任一项所述的发光二极管芯片，其中，还包括绝缘层；
    所述绝缘层设置于所述第二半导体层上，所述第一电极、所述第二电极分别透过贯穿所述绝缘层的第一通孔、第二通孔与所述金属层、所述第二半导体层连接。
  6. 一种显示装置，所述显示装置中包括若干如权利要求1-5任一项所述的发光二极管芯片。
  7. 一种发光二极管芯片的制作方法，包括：
    提供外延层，所述外延层包括第一半导体层、第二半导体层和发光层，所述发光层设置于所述第一半导体层和第二半导体层之间；
    在所述第一半导体层上，设置一容置槽，所述容置槽的底部未接触所述发光层；
    在所述容置槽中设置一金属层，所述金属层与所述第一半导体层欧姆接触；
    将所述第一半导体层开设有所述容置槽的一侧与一透光基板结合；
    于所述第二半导体层对应所述容置槽的位置设置一斜槽；其中，所述斜槽依次穿过所述第二半导体层、发光层和第一半导体层，并使所述金属层的表面至少部分露出；以及，
    透过所述斜槽制作第一电极，并在所述第二半导体层上制作第二电极。
  8. 如权利要求7所述的发光二极管芯片的制作方法，其中，在所述提供外延层之前，还包括：
    提供一衬底，并于所述衬底上生长所述外延层。
  9. 如权利要求8所述的发光二极管芯片的制作方法，其中，所述将所述第一半导体层开设有所述容置槽的一侧与一透光基板结合包括：
    将所述第一半导体层开设有所述容置槽的一侧与所述透光基板固定连接之后，将所述衬底剥离。
  10. 如权利要求7所述的发光二极管芯片的制作方法，其中，所述将所述第一半导体层开设有所述容置槽的一侧与一透光基板结合包括：
    通过一透明键合层，将所述第一半导体层开设有所述容置槽的一侧，与所述透光基板结合。
  11. 如权利要求7-10任一项所述的发光二极管芯片的制作方法，其中，在所述设置斜槽之后，还包括：
    在所述外延层的外表面上覆盖绝缘层。
  12. 如权利要求11所述的发光二极管芯片的制作方法，其中，
    所述透过所述斜槽制作第一电极，并在所述第二半导体层上制作第二电极包括：
    在所述绝缘层上与所述斜槽对应的位置开设第一通孔，所述第一通孔与所述金属层相通；在所述斜槽上设置第一电极，所述第一电极通过所述第一通孔与所述金属层相连；
    在所述绝缘层上远离所述斜槽的位置开设第二通孔，所述第二通孔与所述第二半导体层相通；在所述通孔上设置第二电极，所述第二电极通过所述第二通孔与所述第二半导体层欧姆接触。
  13. 如权利要求7-10任一项所述的发光二极管芯片的制作方法，其中，所述在所述第一半导体层上，设置一容置槽包括：
    于所述第一半导体层上涂布一光阻层；
    对所述光阻层进行图案化处理；
    以图案化处理后的所述光阻层为掩膜，对所述第一半导体层进行蚀刻以形成所述容置槽。
  14. 如权利要求7-10任一项所述的发光二极管芯片的制作方法，其中，所述于所述第二半导体层对应所述容置槽的位置设置一斜槽包括：
    通过蚀刻工艺，从所述第二半导体层的外表面向内蚀刻出所述斜槽，所述斜槽的底面与金属层连通。
  15. 如权利要求7-10所述的发光二极管芯片的制作方法，其中，所述金属层部分填充或填满所述容置槽。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070131958A1 (en) * 2005-12-14 2007-06-14 Advanced Optoelectronic Technology Inc. Single chip with multi-LED
CN101515621A (zh) * 2009-02-19 2009-08-26 旭丽电子(广州)有限公司 发光二极管芯片、制法及封装方法
US20110114978A1 (en) * 2009-11-19 2011-05-19 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing same
CN104362236A (zh) * 2014-11-11 2015-02-18 杭州士兰明芯科技有限公司 一种led结构及其制作方法
CN107331679A (zh) * 2017-07-05 2017-11-07 广东工业大学 一种csp封装的高压led芯片结构及制作方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20110008550A (ko) * 2009-07-20 2011-01-27 삼성전자주식회사 발광 소자 및 그 제조 방법
CN104377291B (zh) * 2013-08-16 2017-09-01 比亚迪股份有限公司 Led芯片及其制备方法
CN104638086A (zh) * 2015-03-09 2015-05-20 武汉大学 一种含高电流密度三维电极结构的led芯片
TWI569471B (zh) * 2015-05-25 2017-02-01 隆達電子股份有限公司 半導體發光結構及其製造方法
US10312414B1 (en) * 2017-12-01 2019-06-04 Innolux Corporation Light emitting unit and display device
CN111564543B (zh) * 2020-05-12 2021-03-23 厦门乾照光电股份有限公司 一种垂直高压发光二极管芯片及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070131958A1 (en) * 2005-12-14 2007-06-14 Advanced Optoelectronic Technology Inc. Single chip with multi-LED
CN101515621A (zh) * 2009-02-19 2009-08-26 旭丽电子(广州)有限公司 发光二极管芯片、制法及封装方法
US20110114978A1 (en) * 2009-11-19 2011-05-19 Kabushiki Kaisha Toshiba Semiconductor light-emitting device and method for manufacturing same
CN104362236A (zh) * 2014-11-11 2015-02-18 杭州士兰明芯科技有限公司 一种led结构及其制作方法
CN107331679A (zh) * 2017-07-05 2017-11-07 广东工业大学 一种csp封装的高压led芯片结构及制作方法

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