WO2022110230A1 - 一种射频电路、信号反馈电路和通信系统 - Google Patents

一种射频电路、信号反馈电路和通信系统 Download PDF

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Publication number
WO2022110230A1
WO2022110230A1 PCT/CN2020/132959 CN2020132959W WO2022110230A1 WO 2022110230 A1 WO2022110230 A1 WO 2022110230A1 CN 2020132959 W CN2020132959 W CN 2020132959W WO 2022110230 A1 WO2022110230 A1 WO 2022110230A1
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Prior art keywords
circuit
signal
output
feedback circuit
radio frequency
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PCT/CN2020/132959
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English (en)
French (fr)
Inventor
郭衍
李晓然
李伟男
李峰
李鹏
史坡
Original Assignee
华为技术有限公司
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Priority to CN202080015922.3A priority Critical patent/CN115176426A/zh
Priority to PCT/CN2020/132959 priority patent/WO2022110230A1/zh
Publication of WO2022110230A1 publication Critical patent/WO2022110230A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B17/00—Monitoring; Testing
    • H04B17/10—Monitoring; Testing of transmitters
    • H04B17/11—Monitoring; Testing of transmitters for calibration
    • H04B17/13—Monitoring; Testing of transmitters for calibration of power amplifiers, e.g. gain or non-linearity
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems

Definitions

  • the present application relates to the field of wireless communication technologies, and in particular, to a radio frequency circuit, a signal feedback circuit and a communication system.
  • PA Power amplifier
  • the front-end circuit As a radio frequency power amplifier, is one of the most important key components in the transmission chain of modern communication systems. Its main function is to amplify the low-power signal processed by the front-end circuit to the rated power level specified by the communication system standard, and then feed it into the back-end devices, such as duplexers, antennas, etc. for wireless transmission.
  • the gain curve of the PA will be nonlinear, and the nonlinearity of the PA gain curve will directly reduce the signal transmission quality and affect the adjacent frequency band system.
  • DPD digital pre-distortion
  • the working principle of DPD is very simple. It is to fit the gain nonlinearity of the PA through the DPD core (core), and then obtain the inverse function of the PA distortion characteristics, and configure the DPD core according to the inverse function. Perform signal compensation, so that the low-power signal output by the front-end circuit will pass through two nonlinear devices with opposite characteristics, the DPD core and the PA, and the distortion characteristics of each other will cancel each other out, so as to obtain the final linear PA transmission characteristics.
  • ET-PA envelope-tracking
  • the existing ET designs are designed for the long term evolution (LTE) technology of 3G and general mobile communication technologies. Due to the limited signal transmission bandwidth of 3G and LTE, when PA is applied to the large broadband application scenario of 5G , nonlinearity will also appear in the ET, which directly affects the signal transmission quality of the PA.
  • LTE long term evolution
  • the present application provides a radio frequency circuit, a signal feedback circuit and a communication system, which are used to configure a signal feedback path for the communication system to improve the signal transmission quality of the communication system.
  • the communication system may be a wireless communication device, or may be a part of a device in the wireless communication device, such as an integrated circuit product such as a system chip or a communication chip.
  • the wireless communication device may be a computer device that supports wireless communication functionality.
  • the wireless communication device may be a terminal such as a smart phone, or may be a wireless access network device such as a base station.
  • a system-on-chip may also be referred to as a system on chip (system on chip, SoC), or simply referred to as a SoC chip.
  • the communication chip may include a baseband processing chip and a radio frequency processing chip. Baseband processing chips are also sometimes referred to as modems or baseband chips.
  • the radio frequency processing chip is also sometimes referred to as a radio frequency transceiver (transceiver) or radio frequency chip.
  • some or all of the communication chips may be integrated inside the SoC chip.
  • the baseband processing chip is integrated in the SoC chip, and the radio frequency processing chip is not integrated with the SoC chip.
  • an embodiment of the present application provides a radio frequency circuit, where the radio frequency circuit includes at least one radio frequency transmission channel and a signal feedback circuit.
  • At least one radio frequency transmission channel is connected with at least one PA, and at least one PA is connected with at least one envelope tracking ET circuit for supplying power to at least one PA; the first input end of the signal feedback circuit is used for connecting with at least one PA The output end of the signal feedback circuit is connected to the output end of the signal feedback circuit, and the second input end of the signal feedback circuit is used for connecting with the output end of at least one ET circuit. output terminal output.
  • the signal transmitted in at least one radio frequency transmission channel is transmitted through at least one PA.
  • the output signal of the at least one PA that causes the nonlinear distortion of the output signal and the The output signal of the at least one ET circuit is fed back to the front-end device, and the front-end device can perform signal adjustment based on the feedback signal, so as to reduce the nonlinear distortion of the signal output by the at least one radio frequency transmission channel and ensure the quality of the output signal of the at least one PA.
  • the signal feedback circuit includes: a feedback circuit and an analog-to-digital conversion circuit.
  • the first input end of the feedback circuit is used for connecting with the output end of at least one PA
  • the second input end of the feedback circuit is used for connecting with the output end of at least one ET circuit
  • the output end of the feedback circuit is connected with the analog-to-digital conversion circuit
  • the analog-to-digital conversion circuit is used to perform analog-to-digital conversion processing on the signal output by the feedback circuit and output it through the output end of the analog-to-digital converter.
  • the analog signal output by at least one PA and the analog signal output by at least one ET circuit can be fed back, and the feedback analog signal can be converted into a digital signal that can be directly processed by the back-end device through the analog-to-digital conversion circuit.
  • the signal feedback circuit includes: a first coupler in a one-to-one correspondence with the at least one PA and a second coupler in a one-to-one correspondence with the at least one ET circuit.
  • each first coupler is connected to the output end of the corresponding PA, and each first coupler is used to feed back the output signal of the connected PA; each second coupler is connected to the output end of the corresponding power supply circuit, and each second coupler is connected to the output end of the corresponding power supply circuit. A second coupler is used to feed back the output signal of the connected ET circuit.
  • the first coupler and the second coupler are used to feed back the output signal of each PA connected to the radio frequency circuit and the output signal of each ET circuit.
  • the first input terminal of the feedback circuit is connected to the output terminal of at least one PA through at least one third coupler, and the second input terminal of the feedback circuit is connected to at least one ET circuit through at least one fourth coupler output connection.
  • at least the third coupler is in one-to-one correspondence with at least one PA
  • at least one fourth coupler is in one-to-one correspondence with at least one ET circuit.
  • the radio frequency circuit includes multiple radio frequency transmission channels, and at least one PA is connected to the multiple radio frequency transmission channels in a one-to-one correspondence, and the signal feedback circuit further includes: a selection circuit.
  • the feedback circuit is connected to the analog-to-digital conversion circuit through a selection circuit, and the selection circuit is used for sequentially outputting the signals output by the feedback circuit according to a preset output sequence.
  • the radio frequency channel is connected to multiple PAs and multiple PAs are connected to multiple ET circuits, there are multiple signals fed back by the feedback circuit.
  • a circuit can be selected to feed back the The signals are sequentially output to the analog-to-digital conversion circuit for analog-to-digital conversion, thereby reducing the area of the radio frequency circuit occupied by multiple analog-to-digital conversion circuits.
  • the analog-to-digital conversion circuit includes: a filter corresponding to each PA one-to-one and an analog-to-digital converter corresponding to each filter one-to-one.
  • each filter is connected to the selection circuit, and each filter is used to receive the output signal of the corresponding PA and the output signal of the ET circuit connected to the corresponding PA, and filter the received signal and output it To the connected analog-to-digital converter; each analog-to-digital converter is used to receive the signal output by the connected filter, and perform analog-to-digital conversion processing on the received signal.
  • the feedback circuit further includes: a combiner in a one-to-one correspondence with each PA.
  • each combiner is connected to the output end of the first coupler connected to the corresponding PA, and the second input end of each combiner is connected to the ET circuit for supplying power to the corresponding PA
  • the output end of the second coupler is connected, the output end of each combiner is connected to the analog-to-digital conversion circuit, and each combiner is used to combine the signals output by the connected first coupler and the second coupler into one signal output to the converter.
  • the two feedback signals can be combined into one signal through the combiner, which reduces the number of ports of the selection circuit, and helps to reduce the volume of the signal feedback circuit under the condition of ensuring the transmission of a complete feedback signal.
  • the signal feedback circuit further includes: a processor.
  • the processor is connected to the analog-to-digital conversion circuit, and the processor is used for receiving a signal output by the analog-to-digital conversion circuit, and outputting a signal for adjusting the signal received by the radio frequency circuit and the output signal of at least one ET circuit.
  • the processor processes the signal output by the analog-to-digital converter, determines the nonlinear distortion of the PA output signal according to the signal output by the analog-to-digital converter, and adjusts the RF circuit to receive the signal according to the nonlinear distortion of the PA output signal.
  • the signal and the signal of the at least one ET circuit output signal are subjected to nonlinear distortion compensation.
  • each radio frequency transmit channel is connected to the first digital predistortion DPD core, and the ET circuit for powering the PA connected to each radio frequency transmit channel includes a second DPD core.
  • an embodiment of the present application provides a signal feedback circuit.
  • the signal feedback circuit is applied in a communication system.
  • the communication system includes a radio frequency circuit, at least one power amplifier connected to the radio frequency circuit, and a power amplifier connected to at least one PA. Envelope tracking ET circuit for powering the connected PA.
  • the first input end of the signal feedback circuit is used for connecting with the output end of at least one PA
  • the second input end of the signal feedback circuit is used for connecting with the output end of at least one ET circuit
  • the signal feedback circuit is used for feeding back at least one
  • the output signal of the PA and the signal output by the at least one ET circuit are output through the output terminal of the signal feedback circuit.
  • the signal transmitted in the radio frequency circuit is transmitted through at least one PA.
  • the output signal of at least one PA and the output of at least one power supply circuit that cause nonlinear distortion of the output signal can be The signal is fed back to the front-end device, and the front-end device can adjust the signal based on the feedback signal, so as to reduce the nonlinear distortion of the signal output by at least one radio frequency transmission channel and ensure the quality of the output signal of at least one PA.
  • the signal feedback circuit includes: a feedback circuit and an analog-to-digital conversion circuit.
  • the first input end of the feedback circuit is used for connecting with the output end of at least one PA
  • the second input end of the feedback circuit is used for connecting with the output end of at least one ET circuit
  • the output end of the feedback circuit is connected with the analog-to-digital conversion circuit
  • the analog-to-digital conversion circuit is used to perform analog-to-digital conversion processing on the signal output by the feedback circuit and output it through the output end of the analog-to-digital converter.
  • each feedback module includes: the signal feedback circuit includes: a first coupler corresponding to the at least one PA and a second coupler corresponding to the at least one ET circuit.
  • each first coupler is connected to the output end of the corresponding PA, and each first coupler is used to feed back the output signal of the connected PA; each second coupler is connected to the output end of the corresponding ET circuit, and each second coupler is connected to the output end of the corresponding ET circuit. A second coupler is used to feed back the output signal of the connected ET circuit.
  • the radio frequency circuit includes multiple radio frequency transmission channels, and at least one PA is connected to the multiple radio frequency transmission channels in a one-to-one correspondence, and the signal feedback circuit further includes: a selection circuit.
  • the feedback circuit is connected to the analog-to-digital conversion circuit through a selection circuit, and the selection circuit is used for sequentially outputting the signals output by the feedback circuit according to a preset output sequence.
  • the analog-to-digital conversion circuit includes: a filter corresponding to each PA one-to-one and an analog-to-digital converter corresponding to each filter one-to-one.
  • each filter is connected to the selection circuit, and each filter is used to receive the output signal of the corresponding PA and the output signal of the ET circuit connected to the corresponding PA, and filter the received signal and output it To the connected analog-to-digital converter; each analog-to-digital converter is used to receive the signal output by the connected filter, and perform analog-to-digital conversion processing on the received signal.
  • the feedback circuit further includes: a combiner in a one-to-one correspondence with each PA.
  • each combiner is connected to the output end of the first coupler connected to the corresponding PA, and the second input end of each combiner is connected to the ET circuit for supplying power to the corresponding PA
  • the output end of the second coupler is connected, the output end of each combiner is connected to the analog-to-digital conversion circuit, and each combiner is used to combine the signals output by the connected first coupler and the second coupler into one signal output to the converter.
  • the first input terminal of the feedback circuit is connected to the output terminal of at least one PA through at least one third coupler, and the second input terminal of the feedback circuit is connected to at least one ET circuit through at least one fourth coupler output connection.
  • at least the third coupler is in one-to-one correspondence with at least one PA
  • at least one fourth coupler is in one-to-one correspondence with at least one ET circuit.
  • the signal feedback circuit further includes: a processor.
  • the processor is connected to the analog-to-digital conversion circuit, and the processor is used for receiving a signal output by the analog-to-digital conversion circuit, and outputting a signal for adjusting the signal received by the radio frequency circuit and the output signal of at least one ET circuit.
  • At least one first digital predistortion DPD core is connected to the radio frequency circuit connected to at least one PA, and each ET circuit connected to the signal feedback circuit includes a second DPD core.
  • an embodiment of the present application provides a communication system, which may include a baseband subsystem, a radio frequency circuit connected to the baseband subsystem, at least one PA connected to the radio frequency circuit; at least one PA connected to the at least one PA ET circuits; each ET for powering the connected PAs; antennas connected in a one-to-one correspondence with at least one PA; and provided in the second aspect of the present application and any possible design in connection with at least one PA and at least one ET circuit signal feedback circuit.
  • the signal feedback circuit provided in the second aspect and any possible design can be used to configure a signal feedback circuit in a communication system with dual DPD cores, and output the radio frequency signal to the PA through the signal feedback circuit
  • the nonlinear distortion of the signal is used for signal compensation, so as to ensure the quality of the signal transmitted by the communication system.
  • the signal feedback circuit is fixedly connected with a plurality of radio frequency signal transmission circuits.
  • FIG. 1 is a schematic structural diagram of a wireless communication system according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram 1 of a communication system provided by an embodiment of the present application.
  • FIG. 3 is a second schematic structural diagram of a communication system according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a signal feedback circuit provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram 1 of a circuit structure of a signal feedback circuit provided by an embodiment of the present application.
  • FIG. 6 is a second schematic diagram of the circuit structure of a signal feedback circuit according to an embodiment of the present application.
  • FIG. 7 is a third schematic diagram of the circuit structure of a signal feedback circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a voltage waveform of an output signal of a feedback module provided by an embodiment of the present application.
  • FIG. 9 is a schematic diagram of another feedback circuit output signal voltage waveform according to an embodiment of the present application.
  • FIG. 10 is a fourth schematic diagram of the circuit structure of a signal feedback circuit provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of a radio frequency circuit provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of a communication system provided by an embodiment of the present application.
  • LTE Long Term Evolution
  • FDD Frequency Division Duplex
  • TDD Time Division Duplex
  • 5th Generation 5th Generation
  • New Radio New Radio
  • devices can be divided into devices that provide wireless network services and devices that use wireless network services.
  • the devices that provide wireless network services refer to those devices that make up a wireless communication network, which can be referred to as network equipment or network elements for short.
  • Network equipment is usually owned by operators or infrastructure providers, who are responsible for operation or maintenance.
  • Network devices can be further classified into radio access network (RAN) devices and core network (core network, CN) devices.
  • RAN radio access network
  • core network core network
  • a typical RAN device includes a base station (BS).
  • the base station may also sometimes be referred to as a wireless access point (access point, AP), or a transmission reception point (transmission reception point, TRP).
  • the base station may be a general node B (generation Node B, gNB) in a 5G new radio (new radio, NR) system, or an evolutional Node B (evolutional Node B, eNB) in a 4G long term evolution (long term evolution, LTE) system. ).
  • Base stations can be classified into macro base stations or micro base stations according to their physical form or transmit power. Micro base stations are also sometimes referred to as small base stations or small cells.
  • a device using a wireless network service may be referred to as a terminal for short.
  • the terminal can establish a connection with the network device, and provide the user with specific wireless communication services based on the service of the network device.
  • user equipment user equipment
  • subscriber unit subscriber unit
  • SU subscriber unit
  • terminals tend to move with users and are sometimes referred to as mobile stations (mobile stations, MSs).
  • some network devices such as relay nodes (relay nodes, RNs) or wireless routers, can sometimes be regarded as terminals because they have UE identity or belong to users.
  • the terminal may be a mobile phone, a tablet computer, a laptop computer, a wearable device (such as a smart watch, smart bracelet, smart helmet, smart glasses), and other Devices with wireless access capabilities, such as smart cars, various Internet of things (IOT) devices, including various smart home devices (such as smart meters and smart home appliances) and smart city devices (such as security or monitoring equipment, intelligent road transport facilities), etc.
  • IOT Internet of things
  • smart home devices such as smart meters and smart home appliances
  • smart city devices such as security or monitoring equipment, intelligent road transport facilities
  • FIG. 1 is a schematic structural diagram of a communication system according to an embodiment of the present application.
  • the communication system may be a terminal or a base station in an embodiment of the present application.
  • the communication system may include multiple components, for example: an application Subsystem, memory (memory), mass storage (massive storage), baseband subsystem, radio frequency integrated circuit (RFIC), radio frequency front end (radio frequency front end, RFFE) device, and antenna (antenna, ANT) ). These components may be coupled by various interconnecting buses or other electrical connections.
  • RFIC radio frequency integrated circuit
  • RFFE radio frequency front end
  • antenna antenna
  • ANT_1 represents the first antenna
  • ANT_N represents the Nth antenna
  • N is a positive integer greater than 1.
  • Tx represents the transmit path
  • Rx represents the receive path
  • different numbers represent different paths.
  • Each path can represent a signal processing channel.
  • FBRx represents the feedback receiving path
  • PRx represents the primary receiving path
  • DRx represents the diversity receiving path.
  • HB means high frequency
  • LB means low frequency, both refer to the relative high and low frequency.
  • BB stands for baseband. It should be understood that the marks and components in FIG. 3 are for illustrative purposes only, and are only used as a possible implementation manner, and the embodiments of the present application also include other implementation manners.
  • a communication system may include more or fewer paths, including more or fewer components.
  • the application subsystem can be used as the main control system or main computing system of the communication system to run the main operating system and application programs, manage the hardware and software resources of the entire communication system, and provide users with a user interface.
  • the application subsystem may also include driver software related to other subsystems (eg, baseband subsystem).
  • the application subsystem may include one or more processors.
  • the multiple processors may be multiple of the same type of processors, or may include a combination of multiple types of processors.
  • the processor may be a general-purpose processor or a processor designed for a specific field.
  • the processor may be a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller (MCU).
  • the processor may also be a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processing, ISP), an audio signal processor (audio signal processor, ASP), and an artificial intelligence (artificial intelligence, AI) Apply a specially designed AI processor.
  • AI processors include, but are not limited to, neural network processing units (NPUs), tensor processing units (TPUs), and processors called AI engines.
  • the radio frequency integrated circuit including the RFIC 1, and one or more optional RFICs 2) and the radio frequency front-end device may together form the radio frequency subsystem.
  • the radio frequency subsystem can also be divided into the radio frequency receive path (RF receive path) and the radio frequency transmit path (RF transmit path).
  • the radio frequency transmit channel can transmit radio frequency signals through the antenna, and the radio frequency receive channel can receive radio frequency signals through the antenna, process the radio frequency signals (such as amplifying, filtering and down-converting) to obtain baseband signals, and transmit them to the baseband subsystem.
  • the RF transmit channel can receive the baseband signal from the baseband subsystem, process the baseband signal (such as upconverting, amplifying and filtering) to obtain the RF signal, and finally radiate the RF signal into space through the antenna.
  • a radio frequency integrated circuit may be referred to as a radio frequency processing chip or a radio frequency chip.
  • the radio frequency subsystem may include an antenna switch, an antenna tuner, a low noise amplifier (LNA), a power amplifier (PA), a mixer (mixer), a local oscillator (LOO) ), filters and other electronic devices, which can be integrated into one or more chips as required.
  • a radio frequency integrated circuit may be referred to as a radio frequency processing chip or a radio frequency chip.
  • the RF front-end device can also be an independent chip.
  • a radio frequency chip is also sometimes referred to as a receiver, transmitter, or transceiver.
  • the antenna can sometimes be considered part of the RF subsystem and can be integrated into the chip of the RF subsystem. Antennas, RF front-end devices, and RF chips can all be manufactured and sold separately.
  • the RF subsystem can also use different devices or different integration methods based on power consumption and performance requirements.
  • some devices belonging to the radio frequency front-end are integrated into the radio frequency chip, and even the antenna and the radio frequency front-end device are integrated into the radio frequency chip, and the radio frequency chip can also be called a radio frequency antenna module or an antenna module.
  • the radio frequency signal is usually an analog signal
  • the signal processed by the baseband subsystem is mainly a digital signal
  • an analog-to-digital conversion device is also required in the communication system.
  • the analog-to-digital conversion device may be disposed in the baseband subsystem, or may be disposed in the radio frequency subsystem.
  • the analog-to-digital conversion device includes an analog-to-digital converter (ADC) that converts an analog signal to a digital signal, and a digital-to-analog converter (DAC) that converts a digital signal to an analog signal.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • the baseband subsystem may also include one or more processors.
  • the baseband subsystem may also include one or more hardware accelerators (HACs).
  • HACs hardware accelerators
  • Hardware accelerators can be used to specifically complete some sub-functions with high processing overhead, such as data packet assembly and parsing, data packet encryption and decryption, etc. These sub-functions can also be implemented using general-purpose processors, but hardware accelerators may be more appropriate due to performance or cost considerations.
  • the hardware accelerator is mainly implemented by an application-specific integrated circuit (application specified intergated circuit, ASIC).
  • ASIC application specified intergated circuit
  • the hardware accelerator may also include one or more relatively simple processors, such as MCU.
  • the baseband subsystem and the radio frequency subsystem together form a communication subsystem, which provides a wireless communication function for the communication system.
  • the baseband subsystem is responsible for managing the software and hardware resources of the communication subsystem, and can configure the working parameters of the radio frequency subsystem.
  • the processor of the baseband subsystem can run a sub-operating system of the communication subsystem, and the sub-operating system is often an embedded operating system or a real-time operating system, such as the VxWorks operating system or the QuRT system of Qualcomm.
  • the baseband subsystem may be integrated into one or more chips, which may be referred to as baseband processing chips or baseband chips.
  • the baseband subsystem can be used as a separate chip, which can be called a modem or a modem chip.
  • Baseband subsystems can be manufactured and sold in units of modem chips. Modem chips are also sometimes called baseband processors or mobile processors.
  • the baseband subsystem can also be further integrated in a larger chip, manufactured and sold in a larger chip unit. This larger chip may be called a system-on-a-chip, system-on-a-chip, or system on a chip (SoC), or simply a SoC chip.
  • SoC system on a chip
  • the software components of the baseband subsystem can be built into the hardware components of the chip before the chip leaves the factory, or can be imported into the hardware components of the chip from other non-volatile memory after the chip leaves the factory, or can also be downloaded online through the network. and update these software components.
  • the communication system also includes memory, such as the memory and mass storage in FIG. 1 .
  • memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory, NVM).
  • Volatile memory refers to memory in which data stored inside is lost when the power supply is interrupted.
  • volatile memory is mainly random access memory (random access memory, RAM), including static random access memory (static RAM, SRAM) and dynamic random access memory (dynamic RAM, DRAM).
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • Non-volatile memory refers to memory whose internal data will not be lost even if the power supply is interrupted.
  • Non-volatile memories include read only memory (ROM), optical disks, magnetic disks, and various memories based on flash memory technology.
  • volatile memory can be selected for memory and cache, and non-volatile memory such as flash memory can be selected for mass storage.
  • FIG. 2 is a schematic structural diagram of another communication system provided by an embodiment of the present application.
  • Figure 2 shows some common devices used for RF signal processing in a communication system.
  • the communication system in the embodiment of the present application is not limited to this, and the communication system may include one or more radio frequency receiving channels and one or more radio frequency emission channel.
  • each radio frequency transmission channel may include devices such as a DAC and a mixer. Before the output signal of each radio frequency transmission channel is transmitted through the antenna, power adjustment processing is also performed on the output signal of the radio frequency signal transmission channel through the PA.
  • the RF receiving channel may include devices such as mixers, filters, and ADCs, and the antenna received by the RF receiving channel from the antenna may also be processed by devices such as a low noise amplifier (LNA).
  • LNA low noise amplifier
  • FIG. 2 is only an example, and the devices included in the radio frequency receiving channel and the radio frequency transmitting channel are not listed one by one in this embodiment of the present application.
  • the communication system further includes an ET circuit for supplying power to the PA, where the ET circuit supplies power for connecting the PA.
  • the ET circuit may include a power supply and an ET device, and the ET device can adjust the voltage value output by the power supply to the PA according to the transmission signal of the PA.
  • the ET device is set based on a single frequency point.
  • the design of the existing ET device will not meet the requirements of the radio frequency subsystem. And it will cause signal distortion to the power supply signal sent to the PA.
  • the concept of setting a DPD core in the ET circuit is proposed.
  • FIG. 3 it is a possible structure of the communication system according to the embodiment of the present application.
  • the communication system may include a radio frequency circuit including at least one radio frequency transmit channel and at least one radio frequency receive channel (not shown).
  • each radio frequency transmit channel includes devices such as a mixer, a DAC, and a low-pass filter (Low-pass filter, LPF), and each radio frequency receiving channel includes devices such as a mixer, a DAC, and an LPF.
  • LPF low-pass filter
  • the communication system shown in FIG. 3 may further include other devices to realize the transmission of radio frequency signals.
  • the output end of each RF transmit channel is connected to a PA.
  • each RF transmission channel can also be connected to the first DPD core, which can be used for nonlinear distortion of the signal caused by the connected PA. signal compensation.
  • the first DPD core may be located in the radio frequency transmission channel, or may be independent of the radio frequency transmission channel.
  • each PA needs an external power supply to work when amplifying the radio frequency signal. Therefore, the voltage input terminal of the PA can also be connected to the ET circuit, that is, the ET circuit can supply power to the PA.
  • the ET circuit may include a second DPD core, a power supply and an ET device, the ET device can adjust the voltage value output by the power supply to the PA according to the transmission signal of the PA, and the second DPD core can be used for nonlinearity according to the signal output by the power supply Signal compensation for distortion.
  • the communication system may also include other devices, which will not be listed one by one here.
  • the power supply can usually only receive digital control signals, and adjust the voltage value output to the PA according to the digital control signals, while the signal of the second DPD core is usually an analog signal.
  • DAC between DPD core and power supply.
  • an embodiment of the present application provides a signal feedback circuit for use in a communication system.
  • the communication system may be the communication system structure provided above, and is used to configure a signal feedback path for the communication system.
  • the signal fed back by the feedback circuit adjusts the signal input to the PA, so as to improve the working efficiency of the communication system and the quality of signal transmission.
  • the first input terminal of the signal feedback circuit 400 provided in the embodiment of the present application is used for connecting with the output terminal of at least one PA, and the second input terminal of the signal feedback circuit 400 is used for connecting with the output terminal of at least one ET circuit.
  • the output terminal is connected, and the signal feedback circuit 400 is used for feeding back the output signal of at least one PA and the signal output by at least one ET circuit and outputting the signal through the output terminal of the signal feedback circuit.
  • the signal feedback circuit 400 may include a feedback circuit 401 and an analog-to-digital conversion circuit 402 .
  • the first input terminal of the feedback circuit 401 is used to connect to the output terminal of at least one PA
  • the second input terminal of the feedback circuit 401 is used to connect to the output terminal of the at least one ET circuit
  • the output terminal of the feedback circuit 401 is connected to the analog output terminal.
  • the input terminal of the digital conversion circuit is connected; the analog-to-digital conversion circuit is used to perform analog-to-digital conversion processing on the signal output by the feedback circuit and output it through the output terminal of the analog-to-digital converter.
  • the communication system further includes a baseband subsystem, and the signal feedback circuit 400 provided in this embodiment of the present application may be connected to the baseband subsystem.
  • the baseband subsystem receives the signal output by the signal feedback circuit 400
  • the The received signal outputs a signal used to condition the received signal of the radio frequency circuit and the output signal of the at least one ET circuit.
  • the signal feedback circuit 400 provided in this embodiment of the present application further includes a processor 403 (not shown).
  • the processor 403 is connected to the analog-to-digital conversion circuit 402, and the processor 403 can be used for receiving the signal output by the analog-to-digital conversion circuit 402, and outputting a signal for adjusting the received signal of the radio frequency circuit and the output signal of at least one ET circuit.
  • the signal feedback circuit 400 provided in this embodiment of the present application may be located in the radio frequency circuit, and may be independent of the radio frequency circuit.
  • the signal feedback circuit 400 and at least one PA and at least one ET circuit can be connected through a data transmission line and an interface provided on the signal feedback circuit 400 .
  • the first input terminal of the feedback circuit 401 is used to connect with the output terminal of at least one PA, the second input terminal of the feedback circuit 401 is used to connect to the output terminal of at least one ET circuit, and the output terminal of the feedback circuit 401 is connected to the analog-to-digital conversion circuit. 402 input terminal connection.
  • the feedback circuit 401 includes a first coupler corresponding to at least one PA and a second coupler corresponding to at least one ET circuit.
  • each first coupler is connected to the output end of the corresponding PA, and each first coupler is used to feed back the output signal of the connected PA; the input end of each second coupler is connected to the corresponding ET circuit The output terminals are connected, and each second coupler is used to feed back the output signal of the connected ET circuit.
  • the feedback circuit 401 may further include a combiner in a one-to-one correspondence with each PA.
  • the first input end of each combiner is connected to the output end of the first coupler connected to the corresponding PA, and the second input end of each combiner is connected to the ET circuit used to supply power to the corresponding PA.
  • the output end of the second coupler is connected, the output end of each combiner is connected to the analog-to-digital conversion circuit 402, and each combiner is used to combine the signals output by the connected first coupler and the second coupler into one signal Then output to the analog-to-digital conversion circuit 402 .
  • the first input terminal of the feedback circuit 401 is connected to the output terminal of at least one PA through at least one third coupler, and the second input terminal of the feedback circuit 401 is connected to at least one PA through at least one fourth coupler.
  • the output of the ET circuit is connected.
  • at least the third coupler is in one-to-one correspondence with at least one PA
  • at least one fourth coupler is in one-to-one correspondence with at least one ET circuit.
  • the feedback circuit 401 is connected to the output end of the PA through the third coupler, and is connected to the output end of the ET circuit through the fourth coupler.
  • the area of the two couplers reduces the cost and volume of the signal feedback circuit 400 .
  • the analog-to-digital conversion circuit 402 is connected to the output terminal of the feedback circuit 401, and the analog-to-digital conversion circuit 402 can be used to perform analog-to-digital conversion processing on the signal output by the feedback circuit 401 and output it through the output terminal of the analog-to-digital converter.
  • the filter may be LPF.
  • each LPF is connected to the feedback circuit 401, and each LPF is used to receive the output signal of the corresponding PA and the output signal of the ET circuit connected to the corresponding PA, and filter the received signal and output it To the connected ADC; each ADC is used to receive the signal output by the connected filter and perform analog-to-digital conversion processing on the received signal.
  • the analog-to-digital conversion circuit 402 may include one LPF and one ADC.
  • the communication system includes multiple PAs and ET circuits connected to the multiple PAs in one-to-one correspondence. Therefore, the feedback circuit 401 outputs the output signals of the multiple PAs and the output signals of the multiple ET circuits. Only one signal can be processed at the same time. Therefore, the signal feedback circuit 400 provided in this embodiment of the present application further includes a selection circuit 404 (not shown).
  • the feedback circuit 401 can be connected to the analog-to-digital conversion circuit 402 through the selection circuit 404 , the selection circuit 404 is configured to sequentially output the signals output by the feedback circuit 401 according to the preset output sequence, and then process the received signals after the LPF and the ADC receive the signal output by the selection circuit 404 .
  • the processor 403 is connected to the analog-to-digital conversion circuit 402, and the processor 403 is configured to receive the analog-to-digital converted signal output by the analog-to-digital conversion circuit 402, and output a signal for adjusting the received signal of the radio frequency circuit and the output signal of at least one ET circuit.
  • the processor 403 may store the correspondence between the feedback signal and the predistortion parameter. After receiving the analog-to-digital converted feedback signal output by the ADC, the processor 403 determines the target radio frequency corresponding to the received feedback signal at this time.
  • the transmit channel can determine the pre-distortion parameter corresponding to the feedback signal according to the stored correspondence between the feedback signal and the pre-distortion parameter, and output the pre-distortion parameter to the first DPD core connected to the target transmit channel and used for transmitting with the target.
  • the second DPD core in the ET circuit powered by the PA connected by the channel after the first DPD core and the second DPD core receive the predistortion parameter, adjust the signal output by the ET circuit and the signal output to the radio frequency circuit to realize the Signal compensation is performed for the nonlinear distortion generated by the PA and the nonlinear distortion generated by the ET circuit, so as to adjust the signal received by the radio frequency circuit and the output signal of at least one ET circuit, and improve the signal quality transmitted by the communication system.
  • the ADC outputs the output signals of multiple PAs and the output signals of multiple ET circuits in the communication system according to the preset sequence, and determines the signal received by the processor 403 as the source of the signal according to the sequence of the ADC output signals, and Determine the target transmission channel according to the signal source.
  • the processor when the signal output by the ADC is the output signal of the PA connected to the target radio frequency transmit channel, after determining the predistortion parameter, the processor outputs the predistortion parameter to the first DPD core connected to the target radio frequency transmit channel.
  • the feedback signal at least includes frequency and amplitude
  • the corresponding relationship between the feedback signal and the predistortion parameter is shown in Table 1 below:
  • the processor 403 when receiving the feedback signal output by the ADC, uses the amplitude and frequency included in the feedback signal output by the ADC to find the corresponding predistortion parameter, and outputs the predistortion parameter to the corresponding DPD in the nucleus.
  • the feedback circuit feeds back the signals output by the multiple PAs connected to the radio frequency circuit of the communication system and the multiple ET circuits used to supply power to the multiple PAs, and outputs the signals to the processing after ADC processing.
  • the processor 403, the processor 403 can configure the preset true parameters according to the stored correspondence between the feedback signal and the predistortion parameters, and output the configured predistortion parameters to the first DPD core and the second DPD core.
  • a signal feedback circuit can be configured for a communication system with dual DPD cores through a signal feedback circuit, and appropriate predistortion parameters can be configured for the dual DPD cores through a processor, thereby ensuring the signal quality of the transmission signal of the communication system.
  • the processor 403 may be a CPU, DSP, or MCU.
  • the signal feedback circuit 400 in the embodiment of the present application can be divided into four specific circuit structures. The following four options can be included:
  • FIG. 5 it is a schematic structural diagram of a signal feedback circuit 400 according to an embodiment of the present application.
  • the signal feedback circuit 400 includes a feedback circuit 401 , an analog-to-digital conversion circuit 402 , a selection circuit 404 and a processor 403 .
  • the feedback circuit 401 includes a first coupler corresponding to at least one PA and a second coupler corresponding to at least one ET circuit.
  • the selection circuit 404 includes a plurality of selection switches K.
  • the analog-to-digital conversion circuit 402 includes an LPF and an ADC.
  • the first coupler may include a first attenuator A1, the input end of A1 is connected to the output end of the corresponding PA, and A1 may be used to attenuate and output the amplitude of the output signal of the connected PA;
  • the second coupling The device can include a second attenuator A2, the input end of A2 is connected to the output end of the corresponding ET circuit, and A2 can be used to attenuate and output the amplitude of the output signal of the connected ET circuit;
  • the output end of an A1 and the output end of each A2 are connected, and K can be used to receive the feedback signal output by the connected A1 and A2, and output the received signals in turn according to the preset output sequence;
  • the input end of the LPF is connected to the K
  • the output end of the LPF is connected to the ADC, and is used to filter the output signal of K and output it to the ADC;
  • the ADC is connected to the processor 403 to perform analog-to-digital conversion processing on the output signal of the
  • K may include multiple first input ports, multiple second input ports, and first output ports. Wherein, each first input port is connected to the output end of each A1 in one-to-one correspondence, each second input port is connected to the output end of each A2 in a one-to-one correspondence, and the output port is connected to the analog-to-digital conversion circuit 402 .
  • the feedback circuit can output multiple signals. Therefore, when configuring K, you can choose one of four K, one of eight K, one of sixteen K or Other types of multiplexers. It should be noted that the structure of the selection circuit in the embodiment of the present application is only for illustration, and other chips or devices may be selected in actual use.
  • the communication system may also include a baseband subsystem, and the radio frequency circuit can receive the baseband signal from the baseband subsystem, and perform up-conversion and filtering processing on the baseband signal through the LPF and the mixer in the radio frequency transmission channel to obtain the radio frequency signal.
  • the PA performs power adjustment processing on the radio frequency signal. Therefore, the frequency of the output signal of the PA is much higher than the frequency of the baseband signal. Therefore, the feedback signal output by A1 cannot be directly processed.
  • the ADC processes the output signal of the PA output by A2
  • the ADC needs to down-convert the signal output by A2, and then output it to the back-end connection device.
  • the working frequency of the ADC can be switched between the first frequency and the second frequency.
  • the working frequency of the ADC is the first frequency.
  • the ADC processes the feedback signal output by A2 During processing, the working frequency of the ADC is switched from the first frequency to the second frequency.
  • the first frequency is not equal to the second frequency, for example, the first frequency may be smaller than the second frequency.
  • the first frequency may be 2.1 GHz; the second frequency may be 3.5 GHz.
  • the above is only an example, and the specific values of the first frequency and the second frequency can be determined according to the actual situation, and will not be listed one by one here.
  • the ADC may receive a control instruction for frequency switching output by a processor or an external processor, and perform frequency switching when receiving the above control instruction.
  • a control instruction for frequency switching output by a processor or an external processor may perform frequency switching when receiving the above control instruction.
  • how to receive the control instruction and the specific format of the control instruction are not limited in this embodiment of the present application.
  • FIG. 6 it is a schematic structural diagram of a signal feedback circuit provided by an embodiment of the present application.
  • the signal feedback circuit 400 includes a feedback circuit 401 , an analog-to-digital conversion circuit 402 , a selection circuit 404 and a processor 403 .
  • the feedback circuit 401 includes a first coupler corresponding to at least one PA and a second coupler corresponding to at least one ET circuit.
  • the selection circuit 404 includes a plurality of selection switches K.
  • the analog-to-digital conversion circuit 402 includes an LPF and an ADC.
  • the first coupler may include A1 and a mixer, the input end of A1 is connected to the output end of the corresponding PA, the output end of A2 is connected to the first input end of the mixer, and A1 can be used for pairing The amplitude of the output signal of the connected PA is attenuated and output to the mixer.
  • the second input end of the mixer is connected to the input end of the PA.
  • the mixer can be used to mix the signal output by A1, and mix The signal output after mixing processing;
  • the second coupler can include A2 and a mixer, the input end of A2 is connected with the output end of the corresponding ET circuit, and A2 can be used for the amplitude of the output signal of the connected ET circuit.
  • the input end of K is connected to the output end of each mixer in the feedback circuit and the output end of A2, K can be used to receive the signal output from the connected mixer and A2, and follow the preset output sequence , and output the received signal in turn;
  • the input end of LPF is connected to the output end of K, and the output end of LPF is connected to the ADC for filtering the K output signal and outputting it to the ADC;
  • the ADC is connected to the processor 403 for The analog-to-digital conversion processing is performed on the output signal of the LPF and output to the processor 403;
  • the processor 406 can generate a predistortion parameter according to the received signal, and output the predistortion parameter to the corresponding DPD core.
  • the frequency of the feedback signal output by A1 is too high, and the processor 403 cannot directly process it. Before the signal output by A1 is output to the ADC, the mixer needs to down-convert the feedback signal output by A1, and then output it to the ADC. Back-end connection device. Therefore, the ADC does not need to switch between the first frequency and the second frequency, which reduces the problems of low conversion efficiency and low conversion accuracy caused by delays in the switching timing of the ADC frequency.
  • the processor 403 may store the corresponding relationship between the feedback signal and the predistortion parameter. After receiving the analog-to-digital converted feedback signal output by the ADC, the processor 403 may store the corresponding relationship between the feedback signal and the predistortion parameter according to the stored feedback signal. Corresponding relationship, determine the predistortion parameter corresponding to the feedback signal, and output the predistortion parameter to the DPD module corresponding to the feedback signal.
  • FIG. 7 it is a schematic structural diagram of a signal feedback circuit provided by an embodiment of the present application.
  • the signal feedback circuit 400 includes a feedback circuit 401 , an analog-to-digital conversion circuit 402 , a selection circuit 404 and a processor 403 .
  • the feedback circuit 401 includes a first coupler corresponding to at least one PA one-to-one, a second coupling corresponding to at least one ET circuit one-to-one, and a combiner corresponding to each PA one-to-one.
  • the selection circuit 404 includes a plurality of selection switches K.
  • the analog-to-digital conversion circuit 402 includes an LPF and an ADC.
  • the first coupler may include A1, the input end of A1 is connected to the output end of the corresponding PA, and A1 may be used to attenuate and output the amplitude of the output signal of the connected PA;
  • the second coupler may Including A2, the input end of A2 is connected with the output end of the corresponding ET circuit, and A2 can be used to attenuate and output the amplitude of the output signal of the connected ET circuit;
  • the first input end of the combiner is connected to the corresponding PA
  • the output end of A1 is connected, and the second input end of the combiner is connected to the output end of A2 which is used to connect the ET circuit for supplying power to the corresponding PA.
  • the combiner can be used to receive the output signal of A1 and the output of A2.
  • the signals are combined into one signal and then output to K; the input end of K is connected to the output end of each combiner in the feedback circuit, and K can be used to receive the signal output by each combiner, and follow the preset output sequence. , and output the received signal in turn; the input end of LPF is connected with the output end of K, and the output end of LPF is connected with ADC, which is used for filtering the output signal of K and outputting it to ADC; ADC is connected with processor 403, using Perform analog-to-digital conversion processing on the output signal of the LPF and output it to the processor 403; the processor 403 can be used to generate a predistortion parameter according to the received signal, and output the predistortion parameter to the corresponding DPD core.
  • the frequency of the output signal of the PA is much higher than that of the baseband signal. Therefore, the frequency difference of the combined feedback signal output by the combiner is relatively large, and the ADC can only process signals in a fixed frequency range at the same time.
  • the working frequency of the ADC can be changed to perform down-frequency processing on the high-frequency signal in the output signal of the combiner, so that the output signal of the combiner is within a certain frequency range.
  • the combined signal output by the combiner includes the output signal u1 of the ET circuit after the amplitude reduction and the output signal u2 of the PA after the amplitude reduction respectively.
  • the frequency of u2 is the baseband frequency
  • u1 is the high frequency signal.
  • the ADC After receiving the combined signal and the control signal output by the processor or the baseband subsystem, the ADC performs down-frequency processing on the high-frequency signal u2 to obtain a signal with a similar baseband frequency, such as u2 in Figure 9. At this time, u1 and u2 The frequency of u2 is similar, and the frequency of the combined signal is within a certain range, the ADC can process the signal in the combined signal at the same time, and output the processed signal to the processor.
  • K may include multiple input ports and a first output port. Wherein, each input port is connected with each feedback module 401 in a one-to-one correspondence, and the output port is connected with the analog-to-digital conversion module 403 .
  • the combiner in each feedback module 401 outputs one feedback signal. Therefore, when configuring the selection module 402, one of four types K and one of eight can be selected according to the number of RF signal transmission circuits in the communication system. Type K, one of sixteen type K or other types of multiplexers. It should be noted that the structure of the selection module 402 in the embodiment of the present application is only for illustration, and other chips or devices may be selected in actual use.
  • each combiner in the feedback circuit 401 can combine two signals into one signal, and the ADC and the LPF can process the two signals at the same time, which shortens the time for the ADC and the LPF to process the output signal of the feedback circuit 401 , the working efficiency of the signal feedback circuit 400 is improved.
  • the signal output by the ADC is the combined signal of the two signals
  • the processor receives the signal
  • the received signal is split by the line pair, and the predistortion parameter is generated according to the split signal, and the predistortion The parameters are output to the corresponding DPD core.
  • FIG. 10 it is a schematic structural diagram of a signal feedback circuit provided by an embodiment of the present application.
  • the signal feedback circuit 400 includes a feedback circuit 401 , an analog-to-digital conversion circuit 402 , a selection circuit 404 and a processor 403 .
  • the feedback circuit 401 includes a first coupler corresponding to at least one PA one-to-one, a second coupling corresponding to at least one ET circuit one-to-one, and a combiner corresponding to each PA one-to-one.
  • the selection circuit 404 includes a plurality of selection switches K.
  • the analog-to-digital conversion circuit 402 includes an LPF and an ADC.
  • the first coupler may include A1 and a mixer, the input end of A1 is connected to the output end of the corresponding PA, the output end of A1 is connected to the first input end of the mixer, and A1 can be used for pairing The amplitude of the output signal of the connected PA is attenuated and output to the mixer.
  • the second input end of the mixer is connected to the input end of the PA.
  • the mixer can be used to mix the signal output by A1, and mix The signal output after mixing processing;
  • the second coupler may include A2, the input end of A2 is connected with the output end of the corresponding ET circuit, and A2 can be used to attenuate the amplitude of the output signal of the connected ET circuit and output
  • the first input end of the combiner is connected with the output end of the mixer in the first coupler connected to the corresponding PA, and the second input end of the combiner is connected with the first input end of the ET circuit used for supplying power to the corresponding PA.
  • the output end of A2 in the two couplers is connected, and the combiner can be used to combine the output signal of the connected mixer and the output signal of A2 into one signal and output it to K; the input end of K is connected to each combiner
  • the output terminal of LPF is connected to the output terminal of K, and K can be used to receive the signal output by the combiner, and output the received signal in turn according to the preset output sequence; the input terminal of LPF is connected to the input terminal of K, and the output terminal of LPF is connected to ADC.
  • the ADC is connected to the processor 403 for performing analog-to-digital conversion processing on the output signal of the LPF and outputting it to the processing module 403; the processor 403 can be used for Generate predistortion parameters according to the received signal, and output the predistortion parameters to the corresponding DPD core.
  • each combiner in the feedback circuit 401 can combine two signals into one signal, and the ADC and the LPF can process the two signals at the same time, which shortens the time for the ADC and the LPF to process the output signal of the feedback circuit 401 , the working efficiency of the signal feedback circuit 400 is improved.
  • the frequency of the output signal of the PA is much higher than that of the baseband signal. Since A1 is directly connected to the mixer, the mixer performs down-frequency processing on the PA output signal of the attenuation amplitude output by A1, and the frequency of the output signal is at Near the baseband signal, when the combiner combines the output signal of A2 and the output signal of the mixer, the frequency of the combined signal is within a certain range. Therefore, the ADC does not need to switch between the first frequency and the second frequency, which reduces the problems of low conversion efficiency and low conversion accuracy caused by the delay of the ADC frequency switching time.
  • analog-to-digital conversion circuit in the signal feedback circuit provided in the previous embodiments of the present application only includes one ADC and one box of LPFs.
  • the number and structure of devices in the analog-to-digital conversion circuit provided by the previous embodiments also has several other structures, and the other circuit structures have the same principles, and are not described in detail in this application.
  • an embodiment of the present application further provides a radio frequency circuit.
  • the radio frequency circuit 1100 provided in this embodiment of the present application may include at least one radio frequency transmission channel 1101 and a signal feedback circuit 1102 .
  • At least one radio frequency transmission channel is connected with at least one power amplifier PA, and at least one PA is connected with at least one envelope tracking ET circuit for supplying power to at least one PA.
  • the first input terminal of the signal feedback circuit 1102 is used for connecting with the output terminal of at least one PA
  • the second input terminal of the signal feedback circuit 1102 is used for connecting with the output terminal of at least one ET circuit
  • the signal feedback circuit 1102 is used for feeding back at least one
  • the output signal of the PA and the signal output by the at least one ET circuit are output through the output terminal of the signal feedback circuit.
  • FIG. 11 only shows one radio frequency transmission channel, the radio frequency circuit 1100 in the embodiment of the present application is not limited to this.
  • each radio frequency transmission channel is connected to the first digital predistortion DPD core, and the ET circuit for powering the PA connected to each radio frequency transmission channel includes a second DPD core.
  • an embodiment of the present application also provides a communication system.
  • the communication system 1200 provided by the embodiment of the present application may include a baseband subsystem 1201 and be connected to the baseband subsystem 1201 .
  • the signal feedback circuit 400 provided in the foregoing embodiments of the present application.
  • each ET circuit is used to supply power to the connected PA, and the ET circuit includes an ET device, a power supply, a second DPD core and a DAC.
  • the communication system 1200 further includes at least one first DPD core (not shown), and the baseband subsystem is connected to the radio frequency circuit 1202 through the at least one first DPD core.
  • the baseband subsystem 1201 can be used to provide baseband signals for the radio frequency circuit 1202; the radio frequency circuit 1202 can be used to convert the baseband signals sent by the baseband subsystem 1201 into radio frequency signals, and output the radio frequency signals to the corresponding antenna; the signal feedback circuit 400 may be used to configure a signal feedback path for communication system 1200; each antenna is used to transmit received radio frequency signals.
  • the signal feedback circuit 400 may be fixedly connected with the radio frequency circuit 1202 .
  • the communication system 1200 also includes an antenna switch 1206 connected between the antenna 1205 and the at least one PA 1203.
  • the antenna switch 1206 can receive a control command sent by the baseband subsystem 1201 for controlling the state of the antenna switch 1206. After receiving the control command, the antenna switch 1206 adjusts the state of the switch to control the antenna 1206 and at least one PA1203 Connection.
  • connection involved in this application describes the connection relationship between two objects, and can represent two connection relationships.
  • the connection between A and B can represent: A is directly connected with B, and A is connected through C and B.
  • system structure and service scenarios provided in the embodiments of the present application are mainly to explain some possible implementations of the technical solutions of the present application, and should not be construed as unique limitations on the technical solutions of the present application.
  • Those of ordinary skill in the art can know that with the evolution of the system and the emergence of newer service scenarios, the technical solutions provided in this application are still applicable to the same or similar technical problems.

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Abstract

一种射频电路、信号反馈电路和通信系统，用于为通信系统配置信号反馈路径。该射频电路包括：至少一条射频发射通道和射频电路；至少一条射频发射通道与至少一个PA连接，且至少一个PA与用于为至少一个PA供电的至少一个包络跟踪ET电路连接；该信号反馈电路的第一输入端用于与至少一个PA的输出端连接，信号反馈电路的第二输入端用于与至少一个ET电路的输出端连接，信号反馈电路用于反馈至少一个PA的输出信号以及至少一个ET电路输出的信号并通过信号反馈电路的输出端输出。

Description

一种射频电路、信号反馈电路和通信系统 技术领域
本申请涉及无线通信技术领域，尤其涉及一种射频电路、信号反馈电路和通信系统。
背景技术
功率放大器(power amplifier，PA)作为射频功率放大器是现代通信系统发送链路当中最为重要的一个关键器件。其主要功能是将前端电路处理完毕后的小功率信号放大至通信系统标准所规定的额定功率档位，然后馈入后端器件，如双工器，天线等进行无线发射。
PA工作期间，为了保证了PA的放大效率，要求其工作在信号饱和区间。实际应用中，由于PA器件的生产制造问题，PA的增益曲线会呈现非线性，PA增益曲线的非线性会直接降低信号传输质量并影响相邻频带系统。
为了对抗PA的非线性，数字预失真(digital pre-distortion，DPD)技术在上世纪90年代被提出并被广泛的应用在多种无线通信系统中，包括接入网基站及用户终端。DPD的工作原理非常简单，就是通过DPD核(core)对PA的增益非线性进行拟合，然后获得PA失真特性的逆函数，并根据该逆函数为DPD核配置合适的预失真参数对传输信号进行信号补偿，这样前端电路输出的小功率信号会经过DPD核及PA两个特性相反的非线性器件，彼此的失真特性相互抵消，从而获得最终线性的PA传输特性。
随了无线通信系统的发展，为了减少PA的放大损耗，包络跟踪(envelope-tracking，ET)技术被提出，ET技术是一种根据PA输入信号的幅值对PA的供电端口或者是偏置端口进行调制来实现减少PA放大损耗的技术，提升了PA工作能量转换效率的射频PA架构。因此其功耗在理论上可以大幅度降低，显著提升射频前端的能量转换效率。ET-PA同时也是业界认为的5G终端侧不可或缺的重要特性之一。
目前，现有的ET设计都是针对3G和通用移动通信技术的长期演进(long term evolution，LTE)技术设计，由于3G和LTE的信号传输带宽有限，当PA应用5G所处的大宽带应用场景时，ET中也会出现非线性，直接影响PA的信号传输质量。
发明内容
本申请提供一种射频电路、信号反馈电路和通信系统，用于为通信系统配置信号反馈路径，以提升通信系统的信号传输质量。
应理解，本申请实施例提供的方案中，通信系统可以是无线通信设备，也可以是无线通信设备中的部分器件，如系统芯片或通信芯片等集成电路产品。无线通信设备可以是支持无线通信功能的计算机设备。
具体地，无线通信设备可以是诸如智能手机这样的终端，也可以是诸如基站这样的无线接入网设备。系统芯片也可称为片上系统(system on chip，SoC)，或简称为SoC芯片。通信芯片可包括基带处理芯片和射频处理芯片。基带处理芯片有时也被称为调制解调器(modem)或基带芯片。射频处理芯片有时也被称为射频收发机(transceiver)或射频芯片。在物理实现中，通信芯片中的部分芯片或者全部芯片可集成在SoC芯片内部。例如，基带处理芯片集成在SoC芯片中，射频处理芯片不与SoC芯片集成。
第一方面，本申请实施例提供了一种射频电路，该射频电路中包括至少一条射频发射 通道和信号反馈电路。
具体地，至少一条射频发射通道与至少一个PA连接，且至少一个PA与用于为至少一个PA供电的至少一个包络跟踪ET电路连接；信号反馈电路的第一输入端用于与至少一个PA的输出端连接，信号反馈电路的第二输入端用于与至少一个ET电路的输出端连接，信号反馈电路用于反馈至少一个PA的输出信号以及至少一个供电电路输出的信号并通过信号反馈电路的输出端输出。
采用上述方案，至少一条射频发送通道内传输的信号通过至少一个PA进行传输，为了能够降低至少一个PA输出的信号的非线性失真，可以对引起输出信号非线性失真的至少一个PA的输出信号以及至少一个ET电路的输出信号反馈给前端设备，前端设备可以基于反馈的信号进行信号调整，以实现降低至少一条射频发射通道输出的信号的非线性失真，保证至少一个PA输出信号的质量。
在一种可能的设计中，信号反馈电路包括：反馈电路和模数转换电路。
具体地，反馈电路的第一输入端用于与至少一个PA的输出端连接，反馈电路的第二输入端用于与至少一个ET电路的输出端连接，反馈电路的输出端与模数转换电路的输入端连接；模数转换电路用于对反馈电路输出的信号进行模数转换处理并通过模数转换器的输出端输出。
采用上述方案，可以将至少一个PA输出的模拟信号以及至少一个ET电路输出的模拟信号进行反馈，并通过模数转换电路将反馈的模拟信号转换为后端设备可以直接处理的数字信号。
在一种可能的设计中，信号反馈电路包括：与至少一个PA一一对应的第一耦合器以及与至少一个ET电路一一对应的第二耦合器。
具体地，每一个第一耦合器与对应的PA的输出端连接，每一个第一耦合器用于反馈连接的PA的输出信号；每一个第二耦合器与对应的供电电路的输出端连接，每一个第二耦合器用于反馈连接的ET电路的输出信号。
采用上述方案，为了保证每一个PA输出的信号质量，采用第一耦合器和第二耦合器将与射频电路连接的每一个PA的输出信号以及与每一个ET电路的输出信号进行反馈。
在一种可能的设计中，反馈电路的第一输入端通过至少一个第三耦合器与至少一个PA的输出端连接，反馈电路的第二输入端通过至少一个第四耦合器与至少一个ET电路的输出端连接。其中，至少第三耦合器与至少一个PA一一对应，且至少一个第四耦合器与至少一个ET电路一一对应。
在一种可能的设计中，射频电路中包括多条射频发射通道，且至少一个PA与多条射频发射通道一一对应连接，信号反馈电路还包括：选择电路。
具体地，反馈电路通过选择电路与模数转换电路连接，选择电路用于按照预先设置的输出顺序，依次输出反馈电路输出的信号。
采用上述方案，由于射频通道与多个PA连接、且多个PA与多个ET电路连接，因此，反馈电路反馈的信号有多个，为了减少射频电路的面积，可以选择电路将反馈电路反馈的信号依次输出给模数转换电路进行模数转换，从而减小了设置多个模数转换电路占用的射频电路的面积。
在一种可能的设计中，模数转换电路包括：与每一个PA一一对应的滤波器以及与每一个滤波器一一对应的模数转换器。
具体地，每一个滤波器的输入端与选择电路连接，每一个滤波器用于接收对应的PA的输出信号以及与对应的PA连接的ET电路的输出信号，并对接收的信号进行滤波处理后输出给连接的模数转换器；每一个模数转换器用于接收连接的滤波器输出的信号，并对接收的信号进行模数转换处理。
在一种可能的设计中，反馈电路还包括：与每一个PA一一对应合路器。
具体地，每一个合路器的第一输入端与对应的PA连接的第一耦合器的输出端连接，每一个合路器的第二输入端与用于为对应的PA供电的ET电路连接的第二耦合器的输出端连接，每一个合路器的输出端与模数转换电路连接，每一个合路器用于将连接的第一耦合器和第二耦合器输出的信号合并为一个信号后输出给转换器。
采用上述方案，可以通过合路器将两路反馈信号合并为一路信号，减少了选择电路的端口数量，在保证传输完整的反馈信号的情况下，有利于减少信号反馈电路的体积。
在一种可能的设计中，信号反馈电路还包括：处理器。
具体地，处理器与模数转换电路连接，处理器用于接收模数转换电路输出的信号，并输出用于调整射频电路接收信号以及至少一个ET电路输出信号的信号。
采用上述方案，处理器对模数转换器输出的信号进行处理，并根据模数转换器输出的信号确定PA输出信号的非线性失真情况，并根据PA输出信号的非线性失真情况调整射频电路接收信号以及至少一个ET电路输出信号的信号进行非线性失真补偿。
在一种可能的设计中，每一条射频发射通道的输入端与第一数字预失真DPD核连接，且用于为每一个射频发射通道连接的PA供电的ET电路中包括第二DPD核。
第二方面，本申请实施例提供了一种信号反馈电路，该信号反馈电路应用于通信系统中，该通信系统包括射频电路、与射频电路连接的至少一个功率放大器以及与至少一个PA连接的用于为连接的PA供电的包络跟踪ET电路。
具体地，信号反馈电路的第一输入端用于与至少一个PA的输出端连接，信号反馈电路的第二输入端用于与至少一个ET电路的输出端连接，信号反馈电路用于反馈至少一个PA的输出信号以及至少一个ET电路输出的信号并通过信号反馈电路的输出端输出。
采用上述方案，射频电路内传输的信号通过至少一个PA进行传输，为了能够降低PA输出信号的非线性失真，可以对引起输出信号非线性失真的至少一个PA的输出信号以及至少一个供电电路的输出信号反馈给前端设备，前端设备可以基于反馈的信号进行信号调整，以实现降低至少一条射频发射通道输出的信号的非线性失真，保证至少一个PA输出信号的质量。
在一种可能的设计中，信号反馈电路包括：反馈电路和模数转换电路。
具体地，反馈电路的第一输入端用于与至少一个PA的输出端连接，反馈电路的第二输入端用于与至少一个ET电路的输出端连接，反馈电路的输出端与模数转换电路的输入端连接；模数转换电路用于对反馈电路输出的信号进行模数转换处理并通过模数转换器的输出端输出。
在一种可能的设计中，每一个反馈模组包括：信号反馈电路包括：与至少一个PA一一对应的第一耦合器以及与至少一个ET电路一一对应的第二耦合器。
具体地，每一个第一耦合器与对应的PA的输出端连接，每一个第一耦合器用于反馈连接的PA的输出信号；每一个第二耦合器与对应的ET电路的输出端连接，每一个第二耦合器用于反馈连接的ET电路的输出信号。
在一种可能的设计中，射频电路中包括多条射频发射通道，且至少一个PA与多条射频发射通道一一对应连接，信号反馈电路还包括：选择电路。
具体地，反馈电路通过选择电路与模数转换电路连接，选择电路用于按照预先设置的输出顺序，依次输出反馈电路输出的信号。
在一种可能的设计中，模数转换电路包括：与每一个PA一一对应的滤波器以及与每一个滤波器一一对应的模数转换器。
具体地，每一个滤波器的输入端与选择电路连接，每一个滤波器用于接收对应的PA的输出信号以及与对应的PA连接的ET电路的输出信号，并对接收的信号进行滤波处理后输出给连接的模数转换器；每一个模数转换器用于接收连接的滤波器输出的信号，并对接收的信号进行模数转换处理。
在一种可能的设计中，反馈电路还包括：与每一个PA一一对应合路器。
具体地，每一个合路器的第一输入端与对应的PA连接的第一耦合器的输出端连接，每一个合路器的第二输入端与用于为对应的PA供电的ET电路连接的第二耦合器的输出端连接，每一个合路器的输出端与模数转换电路连接，每一个合路器用于将连接的第一耦合器和第二耦合器输出的信号合并为一个信号后输出给转换器。
在一种可能的设计中，反馈电路的第一输入端通过至少一个第三耦合器与至少一个PA的输出端连接，反馈电路的第二输入端通过至少一个第四耦合器与至少一个ET电路的输出端连接。其中，至少第三耦合器与至少一个PA一一对应，且至少一个第四耦合器与至少一个ET电路一一对应。
在一种可能的设计中，信号反馈电路还包括：处理器。
具体地，处理器与模数转换电路连接，处理器用于接收模数转换电路输出的信号，并输出用于调整射频电路接收信号以及至少一个ET电路输出信号的信号。
在一种可能的设计中，与至少一个PA连接的射频电路连接至少一个第一数字预失真DPD核，信号反馈电路连接的每一个ET电路中包括第二DPD核。
第三方面，本申请实施例提供了一种通信系统，该通信系统可以包括基带子系统、与基带子系统连接的射频电路、与射频电路连接的至少一个PA；与至少一个PA连接的至少一个ET电路；每一个ET用于为连接的PA供电；与至少一个PA一一对应连接的天线；以及与至少一个PA以及至少一个ET电路连接的本申请第二方面以及任一可能的设计中提供的信号反馈电路。
采用上述通信系统架构，可以利用第二方面以及任一可能的设计中提供的信号反馈电路，为具有双DPD核的通信系统中配置信号反馈电路，并通过该信号反馈电路为射频信号对PA输出信号的非线性失真进行信号补偿，从而保证通信系统传输的信号质量。
在一种可能的设计中，信号反馈电路与多个射频信号发送电路固定连接。
附图说明
图1为本申请实施例提供的一种无线通信系统的结构示意图；
图2为本申请实施例提供的一种通信系统结构示意图一；
图3为本申请实施例提供的一种通信系统结构示意图二；
图4为本申请实施例提供的一种信号反馈电路的结构示意图；
图5为本申请实施例提供的一种信号反馈电路的电路结构示意图一；
图6为本申请实施例提供的一种信号反馈电路的电路结构示意图二；
图7为本申请实施例提供的一种信号反馈电路的电路结构示意图三；
图8为本申请实施例提供的一种反馈模组输出信号电压波形示意图；
图9为本申请实施例提供的另一种反馈电路输出信号电压波形示意图；
图10为本申请实施例提供的一种信号反馈电路的电路结构示意图四；
图11为本申请实施例提供的一种射频电路的结构示意图；
图12为本申请实施例提供的一种通信系统的结构示意图。
具体实施方式
下面将结合附图对本申请实施例作进一步地详细描述。
本申请实施例的技术方案可以应用于各种通信系统，例如：长期演进(Long Term Evolution，LTE)系统、LTE频分双工(Frequency Division Duplex，FDD)系统、LTE时分双工(Time Division Duplex，TDD)、第五代(5th Generation，5G)系统或新无线(New Radio，NR)等，在此不做限制。
下面结合附图并举实施例，对本申请提供的技术方案作进一步说明。应理解，本申请实施例中提供的系统结构和业务场景主要是为了解释本申请的技术方案的一些可能的实施方式，不应被解读为对本申请的技术方案的唯一性限定。本领域普通技术人员可以知晓，随着系统的演进，以及更新的业务场景的出现，本申请提供的技术方案对于相同或类似的技术问题仍然可以适用。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
无线通信系统中，设备可分为提供无线网络服务的设备和使用无线网络服务的设备。提供无线网络服务的设备是指那些组成无线通信网络的设备，可简称为网络设备(network equipment)，或网络单元(network element)。网络设备通常归属于运营商或基础设施提供商，并由这些厂商负责运营或维护。网络设备还可进一步分为无线接入网(radio access network，RAN)设备以及核心网(core network，CN)设备。典型的RAN设备包括基站(base station，BS)。
应理解，基站有时也可以被称为无线接入点(access point，AP)，或发送接收点(transmission reception point，TRP)。具体地，基站可以是5G新无线(new radio，NR)系统中的通用节点B(generation Node B，gNB)，4G长期演进(long term evolution，LTE)系统的演进节点B(evolutional Node B，eNB)。根据基站的物理形态或发射功率的不同，基站可被分为宏基站(macro base station)或微基站(micro base station)。微基站有时也被称为小基站或小小区(small cell)。
使用无线网络服务的设备，可简称为终端(terminal)。终端能够与网络设备建立连接，并基于网络设备的服务为用户提供具体的无线通信业务。应理解，由于终端与用户的关系更加紧密，有时也被称为用户设备(user equipment，UE)，或订户单元(subscriber unit，SU)。此外，相对于通常在固定地点放置的基站，终端往往随着用户一起移动，有时也被称为移动台(mobile station，MS)。此外，有些网络设备，例如中继节点(relay node，RN)或者无线路由器等，由于具备UE身份，或者归属于用户，有时也可被认为是终端。
具体地，终端可以是移动电话(mobile phone)，平板电脑(tablet computer)，膝上型 电脑(laptop computer)，可穿戴设备(比如智能手表，智能手环，智能头盔，智能眼镜)，以及其他具备无线接入能力的设备，如智能汽车，各种物联网(internet of thing，IOT)设备，包括各种智能家居设备(比如智能电表和智能家电)以及智能城市设备(比如安防或监控设备，智能道路交通设施)等。
图1为本申请实施例提供的一种通信系统的结构示意图，该通信系统可以是本申请实施例中的终端或者基站，如图1所示，该通信系统可以包括多个组件，例如：应用子系统，内存(memory)，大容量存储器(massive storge)，基带子系统，射频集成电路(radio frequency intergreted circuit，RFIC)，射频前端(radio frequency front end，RFFE)器件，以及天线(antenna，ANT)。这些组件可以通过各种互联总线或其他电连接方式耦合。
图1中，ANT_1表示第一天线，ANT_N表示第N天线，N为大于1的正整数。Tx表示发送路径，Rx表示接收路径，不同的数字表示不同的路径。每条路径均可以表示一个信号处理通道。其中，FBRx表示反馈接收路径，PRx表示主接收路径，DRx表示分集接收路径。HB表示高频，LB表示低频，两者是指频率的相对高低。BB表示基带。应理解，图3中的标记和组件仅为示意目的，仅作为一种可能的实现方式，本申请实施例还包括其他的实现方式。例如，通信系统可以包括更多或更少的路径，包括更多或更少的组件。
其中，应用子系统可作为通信系统的主控制系统或主计算系统，用于运行主操作系统和应用程序，管理整个通信系统的软硬件资源，并可为用户提供用户操作界面。此外，应用子系统中也可包括与其他子系统(例如基带子系统)相关的驱动软件。
应用子系统可包括一个或多个处理器。多个处理器可以多个相同类型的处理器，也可以包括多种类型的处理器组合。本申请中，处理器可以是通用用途的处理器，也可以是为特定领域设计的处理器。例如，处理器可以是中央处理单元(center processing unit，CPU)，数字信号处理器(digital signal processor，DSP)，或微控制器(micro control unit，MCU)。处理器也可以是图形处理器(graphics processing unit，GPU)、图像信号处理器(image signal processing，ISP)，音频信号处理器(audio signal processor，ASP)，以及为人工智能(artificial intelligence，AI)应用专门设计的AI处理器。AI处理器包括但不限于神经网络处理器(neural network processing unit，NPU)，张量处理器(tensor processing unit，TPU)以及被称为AI引擎的处理器。
图1中，射频集成电路(包括RFIC 1，以及一个或多个可选的RFIC 2)和射频前端器件可以共同组成射频子系统。根据信号的接收或发送电路的不同，射频子系统也可以分为射频接收通道(RF receive path)和射频发射通道(RF transmit path)。其中，射频发射通道可通过天线发射射频信号，射频接收通道可通过天线接收射频信号，对该射频信号进行处理(如放大、滤波和下变频)以得到基带信号，并传递给基带子系统。射频发送通道可接收来自基带子系统的基带信号，对基带信号进行处理(如上变频、放大和滤波)以得到射频信号，并最终通过天线将该射频信号辐射到空间中。射频集成电路可以被称为射频处理芯片或射频芯片。
具体地，射频子系统可包括天线开关，天线调谐器，低噪声放大器(low noise amplifier，LNA)，功率放大器(power amplifier，PA)，混频器(mixer)，本地振荡器(local oscillator，LO)、滤波器(filter)等电子器件，这些电子器件可以根据需要集成到一个或多个芯片中。射频集成电路可以被称为射频处理芯片或射频芯片。射频前端器件也可以是独立的芯片。 射频芯片有时也被称为接收机(receiver)、发射机(transmitter)或收发机(transceiver)。随着技术的演进，天线有时也可以认为是射频子系统的一部分，并可集成到射频子系统的芯片中。天线、射频前端器件和射频芯片都可以单独制造和销售。当然，射频子系统也可以基于功耗和性能的需求，采用不同的器件或者不同的集成方式。例如，将属于射频前端的部分器件集成在射频芯片中，甚至将天线和射频前端器件都集成射频芯片中，该射频芯片也可以称为射频天线模组或天线模组。
此外，由于射频信号通常是模拟信号，基带子系统处理的信号主要是数字信号，通信系统中还需要有模数转换器件。本申请实施例中，模数转换器件可以设置在基带子系统中，也可以设置在射频子系统中。模数转换器件包括将模拟信号转换为数字信号的模数转换器(analog to digital converter，ADC)，以及将数字信号转换为模拟信号的数模转换器(digital to analog converter，DAC)。
与应用子系统类似，基带子系统也可包括一个或多个处理器。此外，基带子系统还可以包括一种或多种硬件加速器(hardware accelerator，HAC)。硬件加速器可用于专门完成一些处理开销较大的子功能，如数据包(data packet)的组装和解析，数据包的加解密等。这些子功能采用通用功能的处理器也可以实现，但是因为性能或成本的考量，采用硬件加速器可能更加合适。在具体的实现中，硬件加速器主要是用专用集成电路(application specified intergated circuit，ASIC)来实现。当然，硬件加速器中也可以包括一个或多个相对简单的处理器，如MCU。
本申请实施例中，基带子系统和射频子系统共同组成通信子系统，为通信系统提供无线通信功能。通常，基带子系统负责管理通信子系统的软硬件资源，并且可配置射频子系统的工作参数。基带子系统的处理器中可以运行通信子系统的子操作系统，该子操作系统往往是嵌入式操作系统或实时操作系统(real time operating system)，例如VxWorks操作系统或高通公司的QuRT系统。
基带子系统可以集成为一个或多个芯片，该芯片可称为基带处理芯片或基带芯片。基带子系统可以作为独立的芯片，该芯片可被称调制解调器(modem)或modem芯片。基带子系统可以按照modem芯片为单位来制造和销售。modem芯片有时也被称为基带处理器或移动处理器。此外，基带子系统也可以进一步集成在更大的芯片中，以更大的芯片为单位来制造和销售。这个更大的芯片可以称为系统芯片，芯片系统或片上系统(system on a chip，SoC)，或简称为SoC芯片。基带子系统的软件组件可以在芯片出厂前内置在芯片的硬件组件中，也可以在芯片出厂后从其他非易失性存储器中导入到芯片的硬件组件中，或者还可以通过网络以在线方式下载和更新这些软件组件。
此外，该通信系统中还包括存储器，例如图1中的内存和大容量存储器。此外，在应用子系统和基带子系统中，还可以分别包括一个或多个缓存。具体实现中，存储器可分为易失性存储器(volatile memory)和非易失性存储器(non-volatile memory，NVM)。易失性存储器是指当电源供应中断后，内部存放的数据便会丢失的存储器。目前，易失性存储器主要是随机存取存储器(random access memory，RAM)，包括静态随机存取存储器(static RAM，SRAM)和动态随机存取存储器(dynamic RAM，DRAM)。非易失性存储器是指即使电源供应中断，内部存放的数据也不会因此丢失的存储器。常见的非易失性存储器包括只读存储器(read only memory，ROM)、光盘、磁盘以及基于闪存(flash memory)技术的各种存储器等。通常来说，内存和缓存可以选用易失性存储器，大容量存储器可以选 用非易失性存储器，例如闪存。
图2为本申请实施例提供的另一种通信系统的结构示意图。图2示出了通信系统中用于射频信号处理的一些常见器件。应理解，图2中虽然只示出了一条射频接收通道和一条射频发射通道，本申请实施例中的通信系统不限于此，通信系统可以包括一条或多条射频接收通道以及一条或多条射频发射通道。其中，每一条射频发射通道可以包括DAC以及混频器等器件，每一条射频发射通道的输出信号在通过天线发射之前，还通过PA对射频信号发送通道的输出信号进行功率调整处理。射频接收通道可以包括混频器、滤波器以及ADC等器件，射频接收通道从天线接收的天线还可以经过低噪声放大器(low noise amplifier，LNA)等器件进行处理。图2仅为示例，本申请实施例在此不再一一列举射频接收通道和射频发射通道中所包括的器件。
本申请实施例中，通信系统还包括用于对PA供电的ET电路，该ET电路为连接PA供电。其中，ET电路中可以包括供电电源和ET器，ET器可以根据PA的传输信号调整供电电源输出给PA的电压数值。
需要说明的是，ET器是基于单频点设置的，当本申请实施例中通信系统应用在5G等大带宽的应用场景时，现有的ET器的设计将无法满足射频子系统的需求，且会对发送给PA的供电信号造成信号失真，为了解决这一方案，提出了为ET电路中也设置DPD核这一概念。
结合前面的描述，如图3所示，为本申请实施例通信系统的一种可能的结构。
参见图3，该通信系统可以包括射频电路，该射频电路中包括至少一条射频发射通道和至少一条射频接收通道(未示出)。其中，每一条射频发射通道中包括混频器、DAC和低通滤波器(Low-pass filter，LPF)等器件，每一条射频接收通道中包括混频器、DAC和LPF等器件。需要说明的是，图3虽然只示出了两条射频发射通道，本申请实施例中的通信系统不限于此。
在实际应用中，图3中所示的通信系统中还可以包括其它器件，以实现射频信号的发送。例如，图3中，每一条射频发射通道的输出端与一个PA连接。
实际使用中，为了避免PA生产制造原因造成的输出信号失真，每一条射频发射通道的输入端还可以与第一DPD核连接，第一DPD核可以用于根据连接的PA造成的信号非线性失真情况进行信号补偿。其中，第一DPD核可以位于射频发射通道中，也可以独立于射频发射通道。
本申请实施例中，每一个PA在对射频信号放大时，需要外部电源供电才能工作，因此，PA的电压输入端还可以与ET电路连接，即ET电路可以为PA供电。其中，ET电路可以包括第二DPD核、供电电源和ET器，ET器可以根据PA的传输信号调整供电电源输出给PA的电压数值，第二DPD核可以用于根据供电电源输出的信号非线性失真情况进行信号补偿。实际使用时，通信系统还可以包括其它器件，在此不再一一列举。
实际使用中，供电电源通常只可以接收数字控制信号，并根据数字控制信号调整输出给PA的电压数值的大小，而第二DPD核的信号通常是模拟信号，ET电路中还包括连接在第二DPD核和供电电源之间的DAC。
目前，现有技术中只设计了用于为第一DPD核进行信号补偿的信号反馈路径，对于通信系统中同时存在第一DPD核和第二DPD核的结构，还未提供如何配置信号反馈电路的方案。
基于此，本申请实施例提供了一种信号反馈电路，用于与通信系统中，该通信系统可以是前述提供的通信系统结构，用于为通信系统配置信号反馈路径，后端器件可以根据信号反馈电路反馈的信号对输入给PA的信号进行调整，以提升通信系统的工作效率以及信号传输质量。
参见图4所示，本申请实施例中提供的信号反馈电路400的第一输入端用于与至少一个PA的输出端连接，信号反馈电路400的第二输入端用于与至少一个ET电路的输出端连接，信号反馈电路400用于反馈至少一个PA的输出信号以及至少一个ET电路输出的信号并通过信号反馈电路的输出端输出。
其中，信号反馈电路400中可以包括反馈电路401和模数转换电路402。
具体地，反馈电路401的第一输入端用于与至少一个PA的输出端连接，反馈电路401的第二输入端用于与至少一个ET电路的输出端连接，反馈电路401的输出端与模数转换电路的输入端连接；模数转换电路用于对反馈电路输出的信号进行模数转换处理并通过模数转换器的输出端输出。
在一种可选的方式中，通信系统中还包括基带子系统，本申请实施例提供的信号反馈电路400可以与基带子系统连接，基带子系统接收到信号反馈电路400输出的信号后，根据接收的信号输出用于调整射频电路接收信号以及至少一个ET电路输出信号的信号。
在另一种可选的方式中，本申请实施例提供的信号反馈电路400还包括处理器403(未示出)。
具体地，处理器403与模数转换电路402连接，处理器403可以用于接收模数转换电路402输出的信号，并输出用于调整射频电路接收信号以及至少一个ET电路输出信号的信号。
实际使用时，本申请实施例提供的信号反馈电路400可以位于射频电路中，可以独立于射频电路。在信号反馈电路400独立于射频电路时，信号反馈电路400和至少一个PA以及至少一个ET电路可以通过数据传输线以及设置在信号反馈电路400上的接口实现连接。
下面对信号反馈电路400中的反馈电路401、模数转换电路202和处理器203的具体结构进行介绍。
一、反馈电路401
反馈电路401的第一输入端用于与至少一个PA的输出端连接，反馈电路401的第二输入端用于与至少一个ET电路的输出端连接，反馈电路401的输出端与模数转换电路402的输入端连接。
其中，反馈电路401包括与至少一个PA一一对应的第一耦合器以及与至少一个ET电路一一对应的第二耦合器。
具体地，每一个第一耦合器的输入端与对应的PA的输出端连接，每一个第一耦合器用于反馈连接的PA的输出信号；每一个第二耦合器的输入端与对应的ET电路的输出端连接，每一个第二耦合器用于反馈连接的ET电路的输出信号。
可选地，反馈电路401还可以包括与每一个PA一一对应合路器。其中，每一个合路器的第一输入端与对应的PA连接的第一耦合器的输出端连接，每一个合路器的第二输入端与用于为对应的PA供电的ET电路连接的第二耦合器的输出端连接，每一个合路器的输出端与模数转换电路402连接，每一个合路器用于将连接的第一耦合器和第二耦合器输出 的信号合并为一个信号后输出给模数转换电路402。
在一种可实现方式中，反馈电路401的第一输入端通过至少一个第三耦合器与至少一个PA的输出端连接，反馈电路401的第二输入端通过至少一个第四耦合器与至少一个ET电路的输出端连接。其中，至少第三耦合器与至少一个PA一一对应，且至少一个第四耦合器与至少一个ET电路一一对应。
需要说明的是，反馈电路401通过第三耦合器与PA的输出端连接，以及通过第四耦合器与ET电路的输出端连接，因此，反馈电路中减少了用于设置第一耦合器和第二耦合器的面积，减少了信号反馈电路400的成本以及体积。
二、模数转换电路402
模数转换电路402与反馈电路401的输出端连接，模数转换电路402可以用于对反馈电路401输出的信号进行模数转换处理并通过模数转换器的输出端输出。其中，与每一个PA一一对应的滤波器以及与每一个滤波器一一对应的ADC。其中，该滤波器可以是LPF。
具体地，每一个LPF的输入端与反馈电路401连接，每一个LPF用于接收对应的PA的输出信号以及与对应的PA连接的ET电路的输出信号，并对接收的信号进行滤波处理后输出给连接的ADC；每一个ADC用于接收连接的滤波器输出的信号，并对接收的信号进行模数转换处理。
在一示例中，为了减小信号反馈电路400的体积，模数转换电路402中可以包括一个LPF和一个ADC。
实际使用时，通信系统中包括多个PA以及与多个PA一一对应连接的ET电路，因此，反馈电路401输出了多个PA的输出信号以及多个ET电路的输出信号，由于ADC和LPF在同一时间内只能对一个信号进行处理，因此，本申请实施例提供的信号反馈电路400还包括选择电路404(未示出)，反馈电路401可以通过选择电路404与模数转换电路402连接，选择电路404用于按照预先设置的输出顺序，依次输出反馈电路401输出的信号，LPF和ADC接收的选择电路404输出的信号之后对接收的信号进行处理。
三、处理器403
处理器403与模数转换电路402连接，处理器403用于接收模数转换电路402输出经过模数转换后的信号，并输出用于调整射频电路接收信号以及至少一个ET电路输出信号的信号。
具体实现时，处理器403中可以存储有反馈信号与预失真参数的对应关系，处理器403在接收到ADC输出的模数转换后的反馈信号后，确定此时接收的反馈信号对应的目标射频发射通道，可以根据存储的反馈信号与预失真参数的对应关系，确定该反馈信号对应的预失真参数，并将预失真参数输出给与目标发射通道连接的第一DPD核以及用于与目标发射通道连接的PA供电的ET电路中的第二DPD核，第一DPD核和第二DPD核接收到预失真参数之后，对ET电路输出的信号以及输出给射频电路的信号进行调整，以实现对PA产生的非线性失真以及ET电路产生的非线性失真进行信号补偿，从而实现调整射频电路接收信号以及至少一个ET电路输出信号的信号，提升通信系统传输的信号质量。
具体实现时，ADC按照预先设置的顺序输出通信系统中的多个PA的输出信号以及多个ET电路的输出信号，根据ADC输出信号顺序，确定处理器403接收的信号为该信号的来源，并根据信号来源确定目标发射通道。
在一示例中，当ADC输出的信号为与目标射频发射通道连接的PA输出信号时，处理 器在确定预失真参数后，将预失真参数输出给与目标射频发射通道连接的第一DPD核。
示例性的，反馈信号至少包括频率和幅值，反馈信号和预失真参数之间的对应关系如下表一所示：
表一
频率 幅值 预失真参数
X1 Y1 Z1
X2 Y2 Z2
X3 Y3 Z3
X4 Y4 Z4
如表一所示，处理器403在接收到ADC输出的反馈信号时，利用ADC输出的反馈信号中包括的幅值和频率找到对应的预失真参数，并将该预失真参数输出给对应的DPD核中。
采用上述信号反馈电路400的结构，反馈电路反馈通信系统与射频电路连接的多个PA以及用于为多个PA供电的多个ET电路输出的信号，并将该信号经过ADC处理后输出给处理器403，处理器403可以根据存储的反馈信号与预失真参数的对应关系，配置预设真参数，并将配置好的预失真参数输出给第一DPD核和第二DPD核中。上述方案中，可以通过信号反馈电路为具有双DPD核的通信系统配置信号反馈电路，并且可以通过处理器为双DPD核配置合适的预失真参数，保证了通信系统传输信号的信号质量。
处理器403可以是CPU，DSP，或MCU。
需要说明的是，以上对反馈电路401、模数转换电路402和处理器403结构的介绍仅为示例，实际应用中，反馈电路401、模数转换电路402和处理器403也可以采用其它结构，本申请实施例对此不作限制。
具体实现时，根据信号反馈电路401包括的器件的不同，本申请实施例信号反馈电路400可以分为四种具体电路结构，下面结合实施例对本申请提供的信号反馈电路400的结构进行说明，具体可以包括如下四种方案：
下面，结合实施例对本申请提供的信号反馈电路400的具体结构进行详细介绍。
实施例一
如图5所示，为本申请实施例提供的信号反馈电路400的一种结构示意图。
信号反馈电路400包括反馈电路401、模数转换电路402、选择电路404和处理器403。
其中，反馈电路401包括与至少一个PA一一对应的第一耦合器以及与至少一个ET电路一一对应的第二耦合器。选择电路404包括多个选择开关K。模数转换电路402包括LPF和ADC。
具体地，第一耦合器可以包括第一衰减器A1，A1的输入端与对应的PA的输出端连接，A1可以用于对连接的PA的输出信号的幅值进行衰减并输出；第二耦合器中可以包括第二衰减器A2，A2的输入端与对应的ET电路的输出端连接，A2可以用于对连接的ET电路的输出信号的幅值进行衰减并输出；K与反馈电路中每一个A1的输出端以及每一个A2的输出端连接，K可以用于接收连接的A1和A2输出的反馈信号，并按照预先设置的输出顺序，依次将接收的信号输出；LPF的输入端与K的输出端连接，LPF的输出端和ADC连接，用于对K的输出信号进行滤波处理并输出给ADC；ADC与处理器403连接，用于对LPF的输出信号进行模数转换处理并输出给处理器403；处理器403根据接收的信 号生成预失真参数，并输出给对应DPD核中。
具体实现时，K可以包括多个第一输入端口、多个第二输入端口和第一输出端口。其中，每一个第一输入端口与每一个A1的输出端一一对应连接，每一个第二输入端口与每一个A2的输出端一一对应连接，输出端口与模数转换电路402连接。
实际使用时，反馈电路可以输出多路信号，因此，在配置K时，可以根据通信系统中PA以及ET电路的数量选择四选一型K、八选一型K、十六选一型K或者其它类型的多路选择器。需要说明的是，本申请实施例中选择电路的结构仅为示意，实际使用时，可以选择其它芯片或者器件。
需要说明的是，通信系统还可以包括基带子系统，射频电路可接收来自基带子系统的基带信号，并通过射频发射通道中LPF以及混频器对基带信号进行上变频和滤波处理以得到射频信号，PA对该射频信号进行功率调整处理，因此，PA的输出信号的频率远高于基带信号的频率，因此，A1输出的反馈信号无法直接处理。在ADC处理A2输出的PA的输出信号时，ADC需要对A2输出的信号进行降频处理，再输出给后端连接器件。
具体实现的，ADC工作频率可以在第一频率和第二频率之间进行切换，当ADC对A1输出的反馈信号进行处理时，ADC的工作频率为第一频率，当ADC对A2输出的反馈信号进行处理时，ADC的工作频率由第一频率切换为第二频率。其中，第一频率不等于第二频率，例如第一频率可以小于第二频率。
例如，第一频率可以为2.1GHz；第二频率可以为3.5GHz。当然以上仅为示例，第一频率与第二频率的具体取值，可以根据实际情况确定，在此不再逐一举例。
具体实现时，ADC可以接收处理器或者外部处理器输出的进行频率切换的控制指令，并在接收上述控制指令时，进行频率切换。具体如何接收控制指令，控制指令的具体格式，本申请实施例对次不做限定。实施例二
如图6所示，为本申请实施例提供的信号反馈电路的一种结构示意图。
信号反馈电路400包括反馈电路401、模数转换电路402、选择电路404和处理器403。
其中，反馈电路401包括与至少一个PA一一对应的第一耦合器以及与至少一个ET电路一一对应的第二耦合器。选择电路404包括多个选择开关K。模数转换电路402包括LPF和ADC。
具体实现时，第一耦合器中可以包括A1和混频器，A1的输入端与对应的PA的输出端连接，A2的输出端与混频器的第一输入端连接，A1可以用于对连接的PA的输出信号的幅值进行衰减并输出给混频器，混频器的第二输入端与PA的输入端连接，混频器可以用于A1输出的信号进行混频处理，并将混频处理后的信号输出；第二耦合器可以包括A2以及混频器，A2的输入端与对应的ET电路的输出端连接，A2可以用于对连接的ET电路的输出信号的幅值进行衰减并输出；K的输入端与反馈电路中每一个混频器的输出端以及A2的输出端连接，K可以用于接收连接的混频器和A2输出的信号，并按照预先设置的输出顺序，依次将接收的信号输出；LPF的输入端与K的输出端连接，LPF的输出端和ADC连接，用于对K输出信号进行滤波处理并输出给ADC；ADC与处理器403连接，用于对LPF的输出信号进行模数转换处理并输出给处理器403；处理器406可以根据接收的信号生成预失真参数，并将预失真参数输出给对应的DPD核中。
需要说明的是，A1输出的反馈信号的频率过高，处理器403无法直接处理，在A1输出的信号输出给ADC之前，需要混频器对A1输出的反馈信号进行降频处理，再输出给后 端连接器件。因此，ADC可以无需在第一频率和第二频率之间切换，降低了由于ADC频率切换时刻延时等原因造成的转换效率低以及转换准确率低的问题。
具体实现时，处理器403中可以存储有反馈信号与预失真参数的对应关系，处理器403在接收到ADC输出的模数转换后的反馈信号后，可以根据存储的反馈信号与预失真参数的对应关系，确定该反馈信号对应的预失真参数，并将预失真参数输出给该反馈信号对应的DPD模块。
需要说明的是，反馈信号与预失真参数的对应关系可详见实施例中表一，本申请这里不做重复介绍。
实施例三
如图7所示，为本申请实施例提供的信号反馈电路的一种结构示意图。
信号反馈电路400包括反馈电路401、模数转换电路402、选择电路404和处理器403。
其中，反馈电路401包括与至少一个PA一一对应的第一耦合器、与至少一个ET电路一一对应的第二耦合以及与每一个PA一一对应合路器。选择电路404包括多个选择开关K。模数转换电路402包括LPF和ADC。
具体地，第一耦合器中可以包括A1，A1的输入端与对应的PA的输出端连接，A1可以用于对连接的PA的输出信号的幅值进行衰减并输出；第二耦合器中可以包括A2，A2的输入端与对应的ET电路的输出端连接，A2可以用于对连接的ET电路的输出信号的幅值进行衰减并输出；合路器的第一输入端与对应的PA连接的A1的输出端连接，合路器的第二输入端与用于为对应的PA供电的ET电路连接的A2的输出端连接，合路器可以用于将接收A1的输出信号以及A2的输出信号进行合并为一路信号后输出给K；K的输入端与反馈电路中每一个合路器的输出端连接，K可以用于接收每一个合路器输出的信号，并按照预先设置的输出顺序，依次将接收的信号输出；LPF的输入端与K的输出端连接，LPF的输出端和ADC连接，用于对K的输出信号进行滤波处理并输出给ADC；ADC与处理器403连接，用于对LPF的输出信号进行模数转换处理并输出给处理器403；处理器403可以用于根据接收的信号生成预失真参数，并将预失真参数输出给对应的DPD核中。
需要说明的是，PA的输出信号的频率远高于基带信号，因此，合路器输出的合并后的反馈信号的频率差较大，而ADC同一时间内只能对固定频率范围的信号进行处理，为了保证ADC的工作效率以及反馈信号的质量，可以改变ADC的工作频率对合路器输出信号中的高频信号进行降频处理，使合路器的输出信号处于一定频率范围内。
举例来说，例如图8所示，合路器输出的合并信号分别包括降幅后的ET电路的输出信号u1和降幅后的PA输出信号u2。其中，u2的频率为基带频率，u1为高频信号。
ADC在接收该合并信号、且接收处理器或者基带子系统输出的控制信号后，对高频信号u2进行降频处理，得到基带频率相近的信号，如图9中的u2，此时，u1和u2的频率相近，且合并信号的频率处于一定范围内，ADC可以对该合并信号中的信号同时进行处理，并将处理后的信号输出给处理器。
具体实现时，K可以包括多个输入端口和第一输出端口。其中，每一个输入端口与每一个反馈模组401一一对应连接，输出端口与模数转换模组403连接。
实际使用时，每一个反馈模组401中合路器输出一路反馈信号，因此，在配置选择模组402时，可以根据通信系统中射频信号发送电路的数量选择四选一型K、八选一型K、 十六选一型K或者其它类型的多路选择器。需要说明的是，本申请实施例中选择模组402的结构仅为示意，实际使用时，可以选择其它芯片或者器件。
需要说明的是，反馈电路401中的每一个合路器可以将两路信号合并为一路信号，ADC和LPF可以同时对两路信号进行处理，缩短了ADC和LPF处理反馈电路401输出信号的时间，提升了信号反馈电路400的工作效率。
具体实现时，由于ADC输出的信号为两路信号的合并信号，处理器收到该信号后，线对接收的信号进行拆分，并根据拆分后的信号生成预失真参数，并将预失真参数输出给对应的DPD核中。
实施例四
如图10所示，为本申请实施例提供的信号反馈电路的一种结构示意图。
信号反馈电路400包括反馈电路401、模数转换电路402、选择电路404和处理器403。
其中，反馈电路401包括与至少一个PA一一对应的第一耦合器、与至少一个ET电路一一对应的第二耦合以及与每一个PA一一对应合路器。选择电路404包括多个选择开关K。模数转换电路402包括LPF和ADC。
具体实现时，第一耦合器中可以包括A1和混频器，A1的输入端与对应的PA的输出端连接，A1的输出端与混频器的第一输入端连接，A1可以用于对连接的PA的输出信号的幅值进行衰减并输出给混频器，混频器的第二输入端与PA的输入端连接，混频器可以用于A1输出的信号进行混频处理，并将混频处理后的信号输出；第二耦合器中可以包括A2，A2的输入端与对应的ET电路的输出端连接，A2可以用于对连接的ET电路的输出信号的幅值进行衰减并输出；合路器的第一输入端与对应的PA连接的第一耦合器中混频器的输出端连接，合路器的第二输入端与用于为对应的PA供电的ET电路连接的第二耦合器中的A2的输出端连接，合路器可以用于将连接的混频器输出的信号以及A2的输出信号合并为一路信号后输出给K；K的输入端与每一个合路器的输出端连接，K可以用于接收合路器输出的信号，并按照预先设置的输出顺序，依次将接收的信号输出；LPF的输入端与K的输入端连接，LPF的输出端和ADC连接，用于对K的输出的信号进行滤波处理并输出给ADC；ADC与处理器403连接，用于对LPF的输出信号进行模数转换处理并输出给处理模器403；处理器403可以用于根据接收的信号生成预失真参数，并将预失真参数输出给对应的DPD核中。
需要说明的是，反馈电路401中的每一个合路器可以将两路信号合并为一路信号，ADC和LPF可以同时对两路信号进行处理，缩短了ADC和LPF处理反馈电路401输出信号的时间，提升了信号反馈电路400的工作效率。
需要说明的是，PA的输出信号的频率远高于基带信号，由于A1与混频器直接连接，混频器对A1输出的衰减幅值的PA输出信号进行降频处理，输出信号的频率处于基带信号的附近，合路器在将A2的输出信号以及混频器的输出信号进行合并时，其合并信号的频率处于一定范围区间内，ADC在接收合路器输出的信号后可以直接对该信号进行处理，因此，ADC可以无需在第一频率和第二频率之间切换，降低了由于ADC频率切换时刻延时等原因造成的转换效率低以及转换准确率低的问题。
需要说明的是，本申请前面实施例提供的信号反馈电路中的模数转换电路只包括一个一个ADC和一盒LPF，实际使用时，根据前述实施例提供的模数转换电路中器件数量和 结构的不同，以及反馈电路结构的不同，本申请实施例提供的信号反馈电路还具有其它几种结构，其它电路结构原理相同，本申请不一一详细介绍。
基于同一发明构思，本申请实施例还提供一种射频电路。示例性的，如图11所示，本申请实施例所提供的射频电路1100可以包括至少一条射频发射通道1101和信号反馈电路1102。
其中，至少一条射频发射通道与至少一个功率放大器PA连接，且至少一个PA与用于为至少一个PA供电的至少一个包络跟踪ET电路连接。信号反馈电路1102的第一输入端用于与至少一个PA的输出端连接，信号反馈电路1102的第二输入端用于与至少一个ET电路的输出端连接，信号反馈电路1102用于反馈至少一个PA的输出信号以及至少一个ET电路输出的信号并通过信号反馈电路的输出端输出。需要说明的是，图11虽然只示出了一条射频发射通道，本申请实施例中的射频电路1100不限于此。
其中，每一条射频发射通道的输入端与第一数字预失真DPD核连接，且用于为每一个射频发射通道连接的PA供电的ET电路中包括第二DPD核。
可以理解的是，上述射频电路中的信号反馈电路1102的电路结构设计可以参考图4至图10的相关设计，此处不再重复赘述。
基于相同的技术构思，本申请实施例还提供一种通信系统，示例性的，如图12所示，本申请实施例所提供的通信系统1200可以包括基带子系统1201、与基带子系统1201连接的射频电路1202、与射频电路连接的至少一个PA1203、与至少一个PA连接的至少一个ET电路1204、与至少一个PA1203一一对应连接的天线1205；以及与至少一个PA1203以及至少一个ET电路1204连接的本申请实施例前述提供的信号反馈电路400。其中，每一个ET电路用于为连接的PA供电，ET电路包括ET器、供电电源、第二DPD核和DAC。
可选地，该通信系统1200还包括至少一个第一DPD核(未示出)，基带子系统通过该至少一个第一DPD核与射频电路1202连接。
其中，基带子系统1201可以用于为射频电路1202提供基带信号；射频电路1202可以用于将基带子系统1201发送的基带信号转换为射频信号，并将射频信号输出给对应的天线；信号反馈电路400可以用于为通信系统1200配置信号反馈路径；每一个天线用于发射接收的射频信号。
在一种可选的方式中，信号反馈电路400可以与射频电路1202固定连接。
在一示例中，该通信系统1200还包括连接在天线1205和至少一个PA1203之间的天线开关1206。
具体实现时，天线开关1206可以接收基带子系统1201发送的用于控制天线开关1206状态的控制指令，天线开关1206在接收到该控制指令后，调整开关的状态，实现控制天线1206与至少一个PA1203的连接。
需要说明的是，本申请中所涉及的多个，是指两个或两个以上。
本申请中所涉及的连接，描述两个对象的连接关系，可以表示两种连接关系，例如，A和B连接，可以表示：A与B直接连接，A通过C和B连接这两种情况。
另外，需要理解的是，在本申请的描述中，“第一”、“第二”等词汇，仅用于区分描述的目的，而不能理解为指示或暗示相对重要性，也不能理解为指示或暗示顺序。
此外，本申请实施例中提供的系统结构和业务场景主要是为了解释本申请的技术方案的一些可能的实施方式，不应被解读为对本申请的技术方案的唯一性限定。本领域普通技术人员可以知晓，随着系统的演进，以及更新的业务场景的出现，本申请提供的技术方案对于相同或类似的技术问题仍然可以适用。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (18)

  1. 一种射频电路，其特征在于，所述射频电路包括至少一条射频发射通道和信号反馈电路；
    所述至少一条射频发射通道与至少一个功率放大器PA连接，且所述至少一个PA与用于为所述至少一个PA供电的至少一个包络跟踪ET电路连接；
    所述信号反馈电路的第一输入端用于与所述至少一个PA的输出端连接，所述信号反馈电路的第二输入端用于与所述至少一个ET电路的输出端连接，所述信号反馈电路用于反馈所述至少一个PA的输出信号以及所述至少一个ET电路输出的信号并通过所述信号反馈电路的输出端输出。
  2. 如权利要求1所述的射频电路，其特征在于，所述信号反馈电路包括：反馈电路和模数转换电路；
    所述反馈电路的第一输入端用于与所述至少一个PA的输出端连接，所述反馈电路的第二输入端用于与所述至少一个ET电路的输出端连接，所述反馈电路的输出端与所述模数转换电路的输入端连接；
    所述模数转换电路用于对所述反馈电路输出的信号进行模数转换处理并通过所述模数转换器的输出端输出。
  3. 如权利要求2所述的射频电路，其特征在于，所述信号反馈电路包括：与所述至少一个PA一一对应的第一耦合器以及与所述至少一个ET电路一一对应的第二耦合器；
    每一个所述第一耦合器与对应的PA的输出端连接，每一个所述第一耦合器用于反馈连接的PA的输出信号；
    每一个所述第二耦合器与对应的供电电路的输出端连接，每一个所述第二耦合器用于反馈连接的ET电路的输出信号。
  4. 如权利要求2或3所述的射频电路，其特征在于，所述射频电路中包括多条射频发射通道，且所述至少一个PA与所述多条射频发射通道一一对应连接，所述信号反馈电路还包括：选择电路；
    所述反馈电路通过所述选择电路与所述模数转换电路连接，所述选择电路用于按照预先设置的输出顺序，依次输出所述反馈电路输出的信号。
  5. 如权利要求2-3所述的射频电路，其特征在于，所述模数转换电路包括：与每一个PA一一对应的滤波器以及与每一个所述滤波器一一对应的模数转换器；
    每一个滤波器的输入端与所述反馈电路连接，每一个滤波器用于接收对应的PA的输出信号以及与对应的PA连接的ET电路的输出信号，并对接收的信号进行滤波处理后输出给连接的模数转换器；
    每一个所述模数转换器用于接收连接的滤波器输出的信号，并对接收的信号进行模数转换处理。
  6. 如权利要求3所述的射频电路，其特征在于，所述反馈电路还包括：与每一个PA一一对应合路器；
    每一个所述合路器的第一输入端与对应的PA连接的第一耦合器的输出端连接，每一个所述合路器的第二输入端与用于为对应的PA供电的ET电路连接的第二耦合器的输出端连接，每一个所述合路器的输出端与所述模数转换电路连接，每一个合路器用于将连接的 第一耦合器和第二耦合器输出的信号合并为一个信号后输出给所述转换器。
  7. 如权利要求2-6中任一项所述的射频电路，其特征在于，所述信号反馈电路还包括：处理器；
    所述处理器与所述模数转换电路连接，所述处理器用于接收所述模数转换电路输出的信号，并输出用于调整所述射频电路接收信号以及所述至少一个ET电路输出信号的信号。
  8. 如权利要求1-7中任一项所述的射频电路，其特征在于，每一条射频发射通道的输入端与第一数字预失真DPD核连接，且用于为每一个射频发射通道连接的PA供电的ET电路中包括第二DPD核。
  9. 一种信号反馈电路，应用于通信系统中，所述通信系统包括射频电路、与所述射频电路连接的至少一个功率放大器PA以及与所述至少一个PA连接的用于为连接的PA供电的包络跟踪ET电路，其特征在于，
    所述信号反馈电路的第一输入端用于与所述至少一个PA的输出端连接，所述信号反馈电路的第二输入端用于与所述至少一个ET电路的输出端连接，所述信号反馈电路用于反馈所述至少一个PA的输出信号以及所述至少一个ET电路输出的信号并通过所述信号反馈电路的输出端输出。
  10. 如权利要求9所述的信号反馈电路，其特征在于，所述信号反馈电路包括：反馈电路和模数转换电路；
    所述反馈电路的第一输入端用于与所述至少一个PA的输出端连接，所述反馈电路的第二输入端用于与所述至少一个ET电路的输出端连接，所述反馈电路的输出端与所述模数转换电路的输入端连接；
    所述模数转换电路用于对所述反馈电路输出的信号进行模数转换处理并通过所述模数转换器的输出端输出。
  11. 如权利要求10所述的信号反馈电路，其特征在于，所述信号反馈电路包括：与所述至少一个PA一一对应的第一耦合器以及与所述至少一个ET电路一一对应的第二耦合器；
    每一个所述第一耦合器与对应的PA的输出端连接，每一个所述第一耦合器用于反馈连接的PA的输出信号；
    每一个所述第二耦合器与对应的ET电路的输出端连接，每一个所述第二耦合器用于反馈连接的ET电路的输出信号。
  12. 如权利要求10或11所述的信号反馈电路，其特征在于，所述射频电路中包括多条射频发射通道，且所述至少一个PA与所述多条射频发射通道一一对应连接，所述信号反馈电路还包括：选择电路；
    所述反馈电路通过所述选择电路与所述模数转换电路连接，所述选择电路用于按照预先设置的输出顺序，依次输出所述反馈电路输出的信号。
  13. 如权利要求12所述的信号反馈电路，其特征在于，所述模数转换电路包括：与每一个PA一一对应的滤波器以及与每一个所述滤波器一一对应的模数转换器；
    每一个滤波器的输入端与所述选择电路连接，每一个滤波器用于接收对应的PA的输出信号以及与对应的PA连接的ET电路的输出信号，并对接收的信号进行滤波处理后输出给连接的模数转换器；
    每一个所述模数转换器用于接收连接的滤波器输出的信号，并对接收的信号进行模数转换处理。
  14. 如权利要求11所述的信号反馈电路，其特征在于，所述反馈电路还包括：与每一个PA一一对应合路器；
    每一个所述合路器的第一输入端与对应的PA连接的第一耦合器连接，每一个所述合路器的第二输入端与用于为对应的PA供电的ET模块连接的第二耦合器连接，每一个所述合路器的输出端与所述模数转换电路连接，每一个合路器用于将连接的第一耦合器和第二耦合器输出的信号合并为一个信号后输出给所述转换器。
  15. 如权利要求10-14中任一项所述信号反馈电路，其特征在于，所述信号反馈电路还包括：处理器；
    所述处理器与所述模数转换电路连接，所述处理器用于接收所述模数转换电路输出的信号，并输出用于调整所述射频电路接收信号以及所述至少一个ET电路输出信号的信号。
  16. 如权利要求9-15中任一项所述的信号反馈电路，其特征在于，与所述至少一个PA连接的射频电路连接至少一个第一数字预失真DPD核，所述信号反馈电路连接的每一个ET电路中包括第二DPD核。
  17. 一种通信系统，其特征在于，包括：
    基带子系统；
    与所述基带子系统连接的射频电路；
    与所述射频电路连接的至少一个功率放大器PA；
    与所述至少一个PA连接的至少一个包络跟踪ET电路；每一个ET电路用于为连接的PA供电；
    与所述至少一个PA一一对应连接的天线；以及
    与所述至少一个PA以及所述至少一个ET电路连接的如权利要求9-16中任一项所述的信号反馈电路。
  18. 如权利要求17所述的通信系统，其特征在于，所述信号反馈电路与所述射频电路固定连接。
PCT/CN2020/132959 2020-11-30 2020-11-30 一种射频电路、信号反馈电路和通信系统 WO2022110230A1 (zh)

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