WO2022110109A1 - 纹路识别模组和显示装置 - Google Patents

纹路识别模组和显示装置 Download PDF

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Publication number
WO2022110109A1
WO2022110109A1 PCT/CN2020/132663 CN2020132663W WO2022110109A1 WO 2022110109 A1 WO2022110109 A1 WO 2022110109A1 CN 2020132663 W CN2020132663 W CN 2020132663W WO 2022110109 A1 WO2022110109 A1 WO 2022110109A1
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WIPO (PCT)
Prior art keywords
electrode
layer
pattern recognition
recognition module
substrate
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PCT/CN2020/132663
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English (en)
French (fr)
Inventor
王奎元
李成
耿越
祁朝阳
代翼
李泽飞
李小贯
丰亚洁
王迎姿
Original Assignee
京东方科技集团股份有限公司
北京京东方传感技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方传感技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080003085.2A priority Critical patent/CN115066753A/zh
Priority to US17/610,203 priority patent/US20230178578A1/en
Priority to PCT/CN2020/132663 priority patent/WO2022110109A1/zh
Publication of WO2022110109A1 publication Critical patent/WO2022110109A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition
    • G06V10/12—Details of acquisition arrangements; Constructional details thereof
    • G06V10/14—Optical characteristics of the device performing the acquisition or on the illumination arrangements
    • G06V10/147—Details of sensors, e.g. sensor lenses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14678—Contact-type imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H01L27/14616—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor characterised by the channel of the transistor, e.g. channel having a doping gradient
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14649—Infrared imagers

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pattern recognition module and a display device.
  • the recognition is generally carried out in the form of a pixel array.
  • the pixel array includes a plurality of pixel units for pattern recognition arranged in an array.
  • the pixel unit includes: a thin film transistor and a photoelectric sensor.
  • the thin film transistor can be used to provide a driving signal to the photoelectric sensor to control the photoelectric sensor to work.
  • the photoelectric sensor uses a In order to receive the detection light and output the corresponding electrical signal, the electrical signal is transmitted to the signal sensing line (sense line) through the thin film transistor for processing by the external chip to obtain the valley ridge information of the corresponding position.
  • Embodiments of the present disclosure provide a pattern recognition module, a preparation method thereof, and a display device.
  • an embodiment of the present disclosure provides a pattern recognition module, including:
  • a substrate including a texture identification area and a peripheral area located around the texture identification area;
  • a photoelectric sensing structure located on the substrate and in the pattern recognition area, includes: a plurality of grid lines, a plurality of signal sensing lines, and a plurality of grid lines and a plurality of signal sensing lines intersecting and defined by the plurality of grid lines A plurality of pixel units; wherein, the pixel units include: thin film transistors, the gates of the thin film transistors are electrically connected to the corresponding gate lines, and the first electrodes of the thin film transistors are electrically connected to the corresponding signal sensing lines;
  • the pattern recognition area includes: a photosensitive area
  • the pixel unit located in the photosensitive area further includes: a photoelectric sensor
  • the photoelectric sensor includes a third electrode, a photosensitive pattern, and a third electrode, a photosensitive pattern, and a third electrode, a photosensitive pattern, and a third electrode, which are sequentially stacked along a direction away from the substrate.
  • the third electrode is connected to the second electrode of the thin film transistor located in the same pixel unit;
  • the area ratio of the photoelectric sensor to the corresponding pixel unit is 40% to 90%.
  • the channel region of the thin film transistor has an inverted L shape or an arc shape.
  • the orthographic projection of the photosensor on the substrate does not overlap the orthographic projection of the active layer of the thin film transistor on the substrate.
  • the gate line extends in a first direction
  • the signal sensing line extends in a second direction
  • the first direction is perpendicular to the second direction
  • the thin film transistor includes: a gate electrode, an active layer, a first electrode and a second electrode, the shape of the cross section of the first electrode parallel to the plane where the substrate is located is a rectangle, and the first electrode has a The first side and the second side oppositely arranged in the first direction and the third side and the fourth side oppositely arranged in the second direction, the first electrode and the first the signal sensing line closest to the side is electrically connected, and the gate is electrically connected to the gate line located closest to the third side of the first electrode;
  • the second electrode includes: a first conductive part and a second conductive part, the first conductive part extends along the first direction and is opposite to the second side of the first electrode, the second conductive part is along the The second direction extends and is disposed opposite to the fourth side of the first electrode, and the first conductive portion is electrically connected to the second conductive portion.
  • the second electrode further includes: a third conductive part, the first conductive part, the second conductive part and the third conductive part are arranged in the same layer, and the third conductive part is The extending direction intersects both the first direction and the second direction, and two ends of the third conductive portion are respectively connected to the first conductive portion and the second conductive portion.
  • the texture identification area further includes: a dummy area located at the periphery of the photosensitive area, and the pixel units located in the dummy area are configured to output reference noise signals to the corresponding signal sensing lines.
  • a planarization layer and a passivation layer are sequentially disposed on the side of the photosensitive pattern facing away from the substrate, and the fourth electrode is located on the side of the passivation layer facing away from the substrate and passes through
  • the via holes on the planarization layer and the passivation layer are electrically connected with the corresponding photosensitive patterns;
  • the pixel unit located in the dummy area further includes a fifth electrode and a sixth electrode, the fifth electrode is electrically connected to the second electrode of the thin film transistor located in the dummy area, and the fifth electrode is connected to the sixth electrode.
  • the planarization layer and the passivation layer are included between the six electrodes.
  • a first insulating layer is formed on a side of the thin film transistor away from the substrate, and a photo sensor located in the photosensitive region is connected to the first insulating layer of the thin film transistor through a via hole on the first insulating layer.
  • a planarization layer and a passivation layer are sequentially arranged on the side of the photosensitive pattern facing away from the substrate, and the fourth electrode is located on the side of the passivation layer facing away from the substrate and passes through the planarization layer and the passivation layer.
  • the via hole on the passivation layer is electrically connected with the corresponding photosensitive pattern;
  • the pixel unit located in the dummy area further includes a fifth electrode and a sixth electrode, the fifth electrode is electrically connected to the second electrode of the thin film transistor located in the dummy area, and the fifth electrode is connected to the sixth electrode.
  • the three electrodes are provided in the same layer and the same material, the sixth electrode and the fourth electrode are provided in the same layer and the same material, and the first insulating layer and the planarization layer are included between the fifth electrode and the sixth electrode. layer and the passivation layer.
  • the pixel unit located in the dummy area further includes: a sensor contrast structure
  • the sensor contrast structure includes: a fifth electrode, a contrast pattern and a sixth electrode that are stacked in sequence along a direction away from the substrate,
  • the fifth electrode is electrically connected to the second electrode of the thin film transistor located in the dummy region, the fifth electrode and the third electrode are provided in the same layer and the same material, and the sixth electrode is the same as the fourth electrode Layer same material setting;
  • the material of the control pattern is a non-photoelectric material and the dielectric constant is approximately the same as that of the photosensitive pattern.
  • the method further includes: a first shading pattern located on a side of the photosensor away from the substrate, the orthographic projection of the first shading pattern on the substrate completely covers the dummy area and does not cover it the photosensitive area.
  • the dummy area is located on one side of the photosensitive area.
  • the dummy regions are located on opposite sides or intersecting sides of the photosensitive region.
  • the dummy area is located on four sides of the photosensitive area.
  • the thin film transistor included in the pixel unit located in the photosensitive area and the thin film transistor included in the pixel unit located in the dummy area have the same structure, shape and size .
  • the texture recognition module further includes:
  • a collimation structure located on the side of the photoelectric sensing structure away from the substrate, covering at least the photosensitive area
  • the collimation structure includes: an aperture layer, and the aperture layer includes a plurality of light-transmitting holes arranged in an array.
  • the collimation structure further includes: a dielectric light-transmitting layer, a lens layer and a flat light-transmitting layer, which are located on the side of the aperture layer away from the substrate and are sequentially stacked along a direction away from the substrate;
  • the lens layer includes a plurality of convex lenses corresponding to the light-transmitting holes one-to-one, and the optical axes of the convex lenses pass through the corresponding light-transmitting holes.
  • the convex lens is a plano-convex lens
  • the plane surface of the plano-convex lens faces the medium light-transmitting layer and is attached to the surface of the medium light-transmitting layer
  • the convex surface of the plano-convex lens faces the medium light-transmitting layer.
  • the flat light-transmitting layer is attached to the surface of the flat light-transmitting layer.
  • one of the photosensors corresponds to a plurality of the light-transmitting holes, and one of the light-transmitting holes corresponds to one of the photosensors.
  • the number of the light-transmitting holes corresponding to each of the photosensors is the same;
  • the number of light-transmitting holes corresponding to one photoelectric sensor includes: 4-100.
  • the texture recognition module further includes:
  • the non-visible light filter layer located on the side of the photoelectric sensor away from the substrate, is configured to filter out the non-visible light in the transmitted light.
  • the non-visible light filter layer includes an infrared filter layer configured to filter out infrared light from the transmitted light.
  • the infrared filter layer includes: an infrared absorption layer with an infrared absorption function or an infrared reflection layer with an infrared reflection function.
  • the non-visible light filter layer is located between the collimating structure and the photosensor.
  • the non-visible light filter layer is integrated within the collimating structure.
  • the non-visible light filter layer is filled in the light-transmitting hole.
  • the collimating structure includes: the aperture layer, a medium light-transmitting layer, a lens layer, and a flat light-transmitting layer that are sequentially stacked along a direction away from the substrate, the lens layer including a plurality of convex lenses corresponding to the light holes one-to-one, and the optical axis of the convex lenses passes through the corresponding light-transmitting holes;
  • At least one of the medium light-transmitting layer and the flat light-transmitting layer is reused as the invisible light filter layer.
  • the photoelectric sensing structure comprises: a gate electrode, a gate insulating layer, an active layer, a first conductive electrode layer, a first insulating layer, a photosensitive pattern, a gate insulating layer, an active layer, a first conductive electrode layer, a first insulating layer, a photosensitive pattern, a planarization layer, a passivation layer and a second conductive electrode layer, the first light-shielding pattern is located on the side of the second conductive electrode layer away from the substrate;
  • the first conductive electrode layer includes the first electrode, the second electrode and the third electrode, and the second conductive electrode layer includes the fourth electrode.
  • a second insulating layer is provided on a side of the fourth electrode away from the substrate, and a bias electrode is provided on a side of the second insulating layer away from the substrate and located in the peripheral region.
  • the fourth electrode extends to the peripheral region and is electrically connected to the bias trace through a via hole on the second insulating layer.
  • the material of the bias trace includes a metal material, and the first light-shielding pattern is provided in the same layer as the bias trace.
  • the pattern recognition module further includes: a second shading pattern, the second shading pattern and the offset wiring are arranged on the same layer;
  • the orthographic projection of the second shading pattern on the substrate completely covers the orthographic projection of the portion of the channel region of the active layer in the thin film transistor on the substrate.
  • the pattern recognition module further includes: a barrier layer located on a side of the second shading pattern away from the substrate, and a ground shield layer located on a side of the barrier layer away from the substrate, the ground shield The orthographic projection of the layer on the substrate completely covers the texture recognition area.
  • the ground shielding layer is electrically connected to the first light shielding pattern and the second light shielding pattern through via holes on the blocking layer.
  • the substrate is a flexible substrate, and a third insulating layer is disposed between the substrate and the photoelectric sensing structure.
  • an embodiment of the present disclosure further provides a display device, which includes: the pattern recognition module provided in the first aspect, and a display panel located on a side of the first shading pattern away from the substrate.
  • the display panel and the pattern recognition module are fixed by optical glue
  • the display panel and the pattern recognition module are arranged at intervals.
  • the display panel is an OLED display panel
  • the OLED display panel includes an OLED display backplane, a polarizer, and a protective cover plate, which are sequentially stacked along a direction away from the pattern recognition module.
  • the material of the cover plate includes polyimide.
  • the display device further includes:
  • the middle frame includes a bottom plate and a side wall formed by bending the edge of the bottom plate toward the front side, the bottom plate and the side wall form a receiving groove, and the pattern recognition module and the display panel are fixed on the In the accommodating groove, the display panel is located on the side of the pattern recognition module away from the bottom plate.
  • the pattern recognition module is fixed on the bottom plate.
  • a stepped support structure is formed on the side wall, and the display panel is fixed on the stepped support structure.
  • through holes are formed on the bottom plate, and the display device further includes: a flexible circuit board for texture identification and a chip for texture identification;
  • the flexible circuit board for texture recognition passes through the through hole, and one end of the flexible circuit board is electrically connected to the binding electrode for texture identification located in the peripheral area in the texture identification module, and the other end is electrically connected to the chip for texture identification located on the back of the bottom plate.
  • the display device further includes: a flexible circuit board for texture identification and a chip for texture identification, one end of the flexible circuit board for texture identification is electrically connected to a binding electrode for texture identification located in a peripheral area in the texture identification module connection, the other end of the flexible circuit board for texture identification is electrically connected with the chip for texture identification;
  • Both the flexible circuit board for texture identification and the chip for texture identification are located in the accommodating groove.
  • an embodiment of the present disclosure further provides a method for preparing a pattern recognition module as described in the first aspect, including:
  • a substrate including a texture identification area and a peripheral area located around the texture identification area;
  • a photoelectric sensing structure is formed on the substrate, the photoelectric sensing structure is located on the substrate and in the pattern recognition area, and includes: a plurality of grid lines, a plurality of signal sensing lines, and a plurality of grid lines. Lines and a plurality of signal sensing lines define a plurality of pixel units; wherein, the pixel units include: thin film transistors, the gates of the thin film transistors are electrically connected to the corresponding gate lines, and the first electrodes of the thin film transistors is electrically connected with the corresponding signal sensing line; the pattern recognition area includes: a photosensitive area, and the pixel unit located in the photosensitive area further includes: a photoelectric sensor, and the photoelectric sensor includes a series of layers arranged in a direction away from the substrate. A third electrode, a photosensitive pattern and a fourth electrode, the third electrode is connected to the second electrode of the thin film transistor located in the same pixel unit; the area ratio of the photoelectric sensor to the corresponding pixel unit is 40% ⁇ 90%.
  • FIG. 1 is a schematic top view of a pattern recognition module provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of a pattern recognition module provided in an embodiment of the present disclosure in a pattern recognition area;
  • FIG. 3 is a schematic top view of a pixel unit and a corresponding gate line and a signal sensing line in an embodiment of the disclosure
  • FIG. 4a is another schematic top view of a pattern recognition module provided by an embodiment of the present disclosure.
  • 4b is another schematic top view of the pattern recognition module provided by the embodiment of the disclosure.
  • FIG. 4c is still another schematic top view of the pattern recognition module provided by the embodiment of the present disclosure.
  • FIG 5 is another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the present disclosure in the pattern recognition area;
  • FIG. 6 is another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the present disclosure in the pattern recognition area;
  • FIG. 7 is another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the present disclosure in the pattern recognition area;
  • FIG 8 is still another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the present disclosure in the pattern recognition area;
  • FIG. 9a is still another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the disclosure in the pattern recognition area;
  • Fig. 9b is a schematic cross-sectional view of the collimation structure in Fig. 9a;
  • 9c is a schematic top view of a photoelectric sensor corresponding to a plurality of light-transmitting holes in an embodiment of the disclosure.
  • FIG. 9d is another top schematic view of a photoelectric sensor corresponding to a plurality of transparent holes in an embodiment of the disclosure.
  • FIG. 10 is still another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the present disclosure in the pattern recognition area;
  • FIG. 11 is a schematic diagram of filling an infrared filter layer in a light-transmitting hole in an embodiment of the disclosure
  • FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 13 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 14 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 15 is a schematic structural diagram of still another display device according to an embodiment of the present disclosure.
  • Figure 16 is a schematic top view of the back of the bottom plate in Figures 13 to 15;
  • FIG. 17 is still another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 18 is a flowchart of a method for manufacturing a pattern recognition module provided by an embodiment of the present disclosure.
  • a display device with a pattern recognition function generally includes a display panel and a photoelectric sensing structure.
  • the fingerprint is in contact with the surface of the display panel, and the detection light emitted by the display panel is reflected on the surface of the fingerprint and then directed to the photoelectric sensing structure.
  • Each photoelectric sensor in the photoelectric sensing structure will generate a corresponding electrical signal based on the received light (detection light reflected by the fingerprint surface), and the electrical signal is transmitted to the external chip through electrical structures such as driving transistors and signal sensing lines. According to the received electrical signal, the valley ridge of the grain at the corresponding position is identified.
  • FIG. 1 is a schematic top view of a pattern recognition module provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic cross-sectional view of the pattern recognition module provided by an embodiment of the present disclosure in a pattern recognition area, as shown in FIGS. 1 and 2 .
  • the pattern recognition module includes: a substrate 1 and a photoelectric sensing structure 2 .
  • the substrate 1 includes a texture identification area 101 and a peripheral area 102 located around the texture identification area 101 .
  • the substrate 1 may be a glass substrate 1 or a PI flexible substrate 1 .
  • the photoelectric sensing structure 2 is located on the substrate 1 and in the pattern recognition area, and includes: a plurality of grid lines 11a, a plurality of signal sensing lines 15, and a plurality of grid lines 11a and a plurality of signal sensing lines 15.
  • the pixel unit includes: a thin film transistor 16, the gate 11 of the thin film transistor 16 is electrically connected to the corresponding gate line, and the first electrode 13 of the thin film transistor 16 is electrically connected to the corresponding signal sensing line 15.
  • the texture recognition area 101 includes a photosensitive area A1 , and the pixel unit located in the photosensitive area further includes: a photoelectric sensor 20 .
  • the orthographic projection of the photosensor on the substrate does not overlap with the orthographic projection of the active layer of the thin film transistor on the substrate.
  • a first insulating layer 5 is formed on the side of the thin film transistor 16 away from the substrate 1 , and the photosensor 20 located in the photosensitive area A1 communicates with the corresponding second thin film transistor 16 through a via hole on the first insulating layer 5 Electrode 14 is connected.
  • the pixel units located in the photosensitive area and located in the photosensitive area A1 are configured to generate a corresponding electrical signal (implemented by the photoelectric sensor 20 ) according to the received light and output the electrical signal (by the thin film transistor 16 ) to the corresponding signal sensing line. implementation) for texture recognition.
  • the area ratio of the photoelectric sensor to the corresponding pixel unit is 40% to 90%.
  • the photosensor 20 may be a PIN photodiode or a PN photodiode.
  • the photoelectric sensor 20 includes: a third electrode 17 , a photosensitive pattern 18 and a fourth electrode 19 that are stacked in sequence along the direction away from the substrate 1 , the third electrode 17 and the second electrode 14 of the thin film transistor 16 located in the same pixel unit Electrically connected, the voltage applied to the third electrode 17 can be controlled through the thin film transistor 16 , thereby controlling the working state of the photoelectric sensor 20 .
  • the photosensitive pattern 18 includes a stacked P-type semiconductor layer and an N-type semiconductor layer (such as an N-type Si layer), or includes a stacked P-type semiconductor layer (such as a P-type Si layer), an intrinsic semiconductor layer (such as this A Si layer) and an N-type semiconductor layer (eg, an N-type Si layer).
  • the I layer is a-Si material
  • the P layer is a-Si doped B ion material
  • the N layer is a-Si doped P ion material.
  • the fourth electrode 19 is a transparent electrode, which can be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and gallium zinc oxide (GZO).
  • an ohmic contact layer 21 is provided between the fourth electrode 19 and the photosensitive pattern 18 to reduce the contact resistance between the fourth electrode 19 and the photosensitive pattern 18, and the material of the ohmic contact layer 21 is metal material and the ohmic contact layer 21 as a whole has better light transmittance.
  • the third electrode 17 is a metal electrode, and is made of metal materials or alloy materials such as copper (Cu), aluminum (Al), and titanium (Ti).
  • “transparent” of a structure in the embodiments of the present disclosure means that the structure can transmit light, rather than that the light transmittance of the structure is 100%.
  • the pixel unit located in the photosensitive area A1 outputs an electrical signal corresponding to the received light to the corresponding signal sensing line 15 for processing by an external chip to obtain the valley ridge information of the corresponding position, So as to realize texture recognition.
  • the peripheral area 102 of the pattern recognition module generally includes a binding area, and binding electrodes are arranged in the binding area.
  • the bonding area generally includes a gate driving chip bonding area C1 and a data driving chip bonding area C2, and the bonding electrode located in the gate driving chip bonding area C1 is the bonding electrode for the gate driving chip.
  • the binding electrode located in the binding area C2 of the data driving chip is the binding electrode for the data driving chip.
  • the setting of the binding region and the binding electrode belongs to the conventional technology in the art, and will not be described in detail in this disclosure.
  • FIG. 3 is a schematic top view of a pixel unit and a corresponding gate line and signal sensing line in the embodiment of the disclosure.
  • the thin film transistor 16 includes: a gate 11 , an active layer 12 , The first electrode 13 and the second electrode 14 , the first electrode 13 specifically refers to the source electrode of the thin film transistor 16 , and the second electrode 14 specifically refers to the drain electrode of the thin film transistor 16 .
  • the region on the active layer 12 between the first electrode 13 and the second electrode 14 is a channel region, and the channel region of the thin film transistor is in an inverted L shape or an arc shape.
  • the gate line 11a extends along the first direction X
  • the signal sensing line 15 extends along the second direction Y
  • the first direction X is perpendicular to the second direction Y; in FIG. 5, the first direction X is horizontal
  • the second direction Y is the vertical direction.
  • the shape of the cross section of the first electrode 13 parallel to the plane where the substrate 1 is located is a rectangle, and the first electrode 13 has a first side and a second side oppositely arranged in the first direction and oppositely arranged in the second direction.
  • the third side and the fourth side of the first electrode 13 are electrically connected to the signal sensing line 15 located on the nearest first side of the first electrode 13 , and the gate 11 is connected to the gate located on the nearest third side of the first electrode 13
  • the line 11a is electrically connected;
  • the second electrode 14 includes: a first conductive part 14a and a second conductive part 14b, the first conductive part 14a extends along the first direction and is opposite to the second side of the first electrode 13, the second conductive part 14a
  • the portion 14b extends along the second direction and is disposed opposite to the fourth side of the first electrode 13, and the first conductive portion 14a is electrically connected to the second conductive portion 14b.
  • the source is a rectangle, and the drain and the two sides (the second side and the fourth side) on the source are different. side) are disposed opposite to each other, and the width of the channel region on the active layer 12 is increased at this time.
  • the size of the source electrode can be correspondingly reduced (the overall length of the drain electrode is basically equal to the length of the strip-shaped drain electrode in the traditional thin film transistor 16).
  • the overlapping capacitance formed between the electrode and other structures eg, the capacitance between the source electrode and the gate electrode 11 ) can be reduced, which is beneficial to reduce the self-noise of the thin film transistor 16 and improve the accuracy of pattern recognition.
  • the second electrode 14 further includes: a third conductive portion 14c, the first conductive portion 14a, the second conductive portion 14b and the third conductive portion 14c are disposed in the same layer, and the extension direction of the third conductive portion 14c Crossing both the first direction and the second direction, both ends of the third conductive portion 14c are connected to the first conductive portion 14a and the second conductive portion 14b, respectively.
  • the channel region on the active layer 12 is in an inverted "L" shape.
  • the above-mentioned thin film transistor 16 with an inverted "L"-shaped channel region is an optional embodiment solution in the embodiments of the present disclosure, which will not limit the technical solutions of the present disclosure.
  • noise reduction processing may be performed on the output electrical signals of the pixel units in the photosensitive area A1 received by the external chip before imaging based on the electrical signals.
  • a dummy area A2 located at the periphery of the photosensitive area A1 is also provided in the texture recognition area 101,
  • the pixel units located in the dummy area A2 are configured to output reference noise signals to the corresponding signal sensing lines, and the reference noise signals can be used for noise reduction of the electrical signals received by the external chip and output from the pixel units in the photosensitive area A1
  • the processing is beneficial to improve the recognition accuracy of the texture information in the photosensitive area A1.
  • the number of pixel units in the virtual area A2 is multiple, and the noise signals output by all the pixel units in the virtual area A2 may be pre-processed to obtain a reference noise signal (for example, for all noise signals)
  • the signal is averaged to obtain the reference noise signal, or the noise signal with the largest current value is selected as the reference noise signal, or the noise signal with the smallest current value is selected as the reference noise signal, etc.);
  • the electrical signal output by the pixel unit is subjected to noise reduction processing.
  • the current (or voltage) magnitude of the electrical signal output by the pixel unit in the photosensitive area A1 may be directly subtracted from the current (voltage) magnitude of the reference noise signal.
  • the specific algorithm for performing noise reduction processing on the signal to be noise reduction based on the noise signal is not limited by the technical solution of the present disclosure.
  • FIG. 4a is another schematic top view of the texture recognition module provided by the embodiment of the disclosure
  • FIG. 4b is another schematic top view of the texture recognition module provided by the embodiment of the disclosure
  • FIG. 4c is the texture provided by the embodiment of the disclosure
  • Fig. 1 shows the situation where the virtual area A2 is located on one side of the photosensitive area A1
  • Fig. 4a shows a virtual area A2.
  • FIG. 4b shows a situation where the dummy area A2 is located at the photosensitive area A1
  • FIG. the four sides of the situation is shown in FIG. the four sides of the situation.
  • the dummy area A2 may also be located on three different sides of the photosensitive area A1, and the corresponding drawings are not shown in this case.
  • the thin film transistors 16 included in the pixel units located in the photosensitive area A1 and the thin film transistors 16 included in the pixel units located in the dummy area A2 have the same structure, shape and size.
  • the self-noise of the thin film transistors 16 included in the pixel units located in the photosensitive area A1 and the thin film transistors 16 included in the pixel units located in the dummy area A2 is the same or approximately the same; at this time, based on the pixel units in the dummy area A2
  • the noise signal output by the thin film transistor 16 is used to perform noise reduction processing on the electrical signal output by the pixel unit (thin film transistor 16 ) in the photosensitive area A1.
  • the noise reduction effect is better, which is beneficial to improve the accuracy of texture recognition.
  • the side of the photosensitive pattern 18 facing away from the substrate 1 is sequentially provided with a planarization layer 6 and a passivation layer 7 , and the planarization layer 6 and the passivation layer 7 are formed with a photosensitive pattern 18 one-to-one via holes, so that the surface of the photosensitive pattern 18 on the side facing away from the substrate 1 is at least partially exposed, and the fourth electrode 19 is located on the side of the passivation layer 7 facing away from the substrate 1 and is passed through the planarization layer 6 and the passivation
  • the via holes on the layer 7 are electrically connected to the corresponding photosensitive patterns 18;
  • the pixel unit located in the dummy area A2 also includes: a fifth electrode 17a and a sixth electrode 19a, the fifth electrode 17a and the thin film transistors in the dummy area
  • the second electrode 14 is connected to the fifth electrode 17a and the sixth electrode 19a includes a planarization layer 6 and a passivation layer 7.
  • the side of the photosensitive pattern 18 facing away from the substrate 1 is sequentially provided with a planarization layer 6 and a passivation layer 7 , and the planarization layer 6 and the passivation layer 7 are formed with a photosensitive pattern 18 one-to-one via holes, so that the surface of the photosensitive pattern 18 on the side facing away from the substrate 1 is at least partially exposed, and the fourth electrode 19 is located on the side of the passivation layer 7 facing away from the substrate 1 and is passed through the planarization layer 6 and the passivation
  • the via holes on the layer 7 are electrically connected to the corresponding photosensitive patterns 18;
  • the pixel unit located in the dummy area A2 also includes: a fifth electrode 17a and a sixth electrode 19a, the fifth electrode 17a and the thin film transistors in the dummy area
  • the second electrode 14 is connected to the second electrode, the fifth electrode 17a and the third electrode are arranged in the same layer and the same material, the sixth electrode 19a and the fourth electrode are arranged in
  • the photosensitive pattern 18 (filled by the flattening layer) is not set in the pixel unit located in the dummy area A2, that is, the pixel unit located in the dummy area A2 will not produce photoelectric effect, and at this time the pixel unit located in the dummy area
  • the electrical signal output by the pixel unit in A2 can be used as a reference noise signal.
  • FIG. 5 is another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the present disclosure in the pattern recognition area. As shown in FIG. 5 , it is different from the pixel unit located in the virtual area A2 in FIG.
  • the pixel unit in the area A2 not only includes the thin film transistor 16, but also includes a sensor contrast structure 25.
  • the sensor contrast structure 25 includes: a fifth electrode 17a, a contrast pattern 24, and a sixth electrode 19a, which are sequentially stacked along the direction away from the substrate 1.
  • the electrode 17a is electrically connected to the second electrode 14 of the corresponding thin film transistor, the dielectric constant of the control pattern 24 is approximately the same as that of the photosensitive pattern 18, and the control pattern 25 is made of non-photoelectric material.
  • the connection method between the sixth electrode 19a in the sensor comparison structure 25 and the comparison pattern 24 is the same as the connection method between the fourth electrode 19 and the photoelectric pattern 18 in the photoelectric sensing structure 2 .
  • the structure of the sensor control structure 25 is similar to that of the photoelectric sensing structure 2, and the dielectric constant of the control pattern 24 is the same as that of the photosensitive pattern 18, so that the pixel units located in the dummy area A2 and the pixel units located in the dummy area A2 are
  • the self-noise of the pixel units in the photosensitive area A1 is the same or approximately the same.
  • noise reduction processing is performed on the electrical signals output by the pixel units in the photosensitive area A1 to reduce noise.
  • the noise effect is better, which is conducive to improving the accuracy of texture recognition.
  • the contrast pattern even if there is light in the virtual area A2, since the contrast pattern adopts non-photoelectric material, the contrast pattern will not generate current due to the light, so as to avoid the noise signal output by the light to the pixel units located in the virtual area A2. influences.
  • FIG. 6 is another schematic cross-sectional view of the pattern recognition module provided by the embodiment of the present disclosure in the pattern recognition area
  • FIG. 7 is another schematic cross-sectional view of the pattern recognition module provided by the embodiment of the present disclosure in the pattern recognition area, as shown in FIG. 6 and FIG. 7, different from the situation shown in FIG. 2 and FIG. 5, in the situation shown in FIG. 6, the pattern recognition module also includes: a first shading pattern 3, the first shading pattern 3 is located at the sixth electrode 19a away from On one side of the substrate 1, the orthographic projection of the first shading pattern 3 on the substrate 1 completely covers the dummy area A2 and does not cover the photosensitive area A1.
  • FIG. 5-FIG. 7 the third electrode 17, the fifth electrode 17a and the second electrode 14 are arranged in the same layer, that is, each of the third electrode 17, the fifth electrode 17a corresponds to the corresponding second electrode 14 are directly connected.
  • the photoelectric sensing structure 2 includes: gates 11 (generally made of a metal material with a thickness of ), gate insulating layer 4 (generally using inorganic insulating layer material, including: SiNx or SiO2), active layer 12 (material is a-Si or monocrystalline silicon), first conductive electrode layer (generally using metal material, the thickness is Specifically, it includes: the first electrode 13, the second electrode 14, the third electrode 17, the fifth electrode 17a, the signal sensing line 15), the first insulating layer 5 (generally using an inorganic insulating layer material, including: SiNx or SiO2), Photosensitive pattern 18 (thickness is the photoelectric conversion material), the planarization layer 6 (thickness is organic material), passivation layer 7 (thickness is of SiNx or SiO2 to ensure the adhesion between the subsequent film layer and the upper surface of the planarization layer 6), the second conductive electrode layer (thickness is The transparent conductive material specifically includes: the fourth electrode 19 and the sixth electrode 19a).
  • the process of making masks for each film layer in the texture identification area 101 includes: gate 11 ⁇ gate insulating layer 4 ⁇ active layer 12 ⁇ first conductive electrode layer ⁇ first insulating layer 5 ⁇ third electrode 17 ⁇ Photosensitive pattern 18 ⁇ planarization layer 6 ⁇ passivation layer 7 ⁇ second conductive electrode layer.
  • the fourth electrode 19 is electrically connected to the photosensitive pattern 18 through the passivation layer 7 and the via holes on the planarization layer 6, wherein the planarization layer 6 and the passivation layer 7 can be patterned respectively, so the sizes of the via holes on the two are different. ;
  • the size of the via hole on the passivation layer 7 is smaller than the size of the via hole on the planarization layer 6 .
  • the radius of the via hole on the passivation layer 7 is 3.5 ⁇ m ⁇ 4 ⁇ m smaller than the radius of the corresponding via hole on the planarization layer 6 .
  • the process of preparing the third electrode 17/fifth electrode 17a and the planarization layer 6 not only includes The process of preparing the photosensitive pattern 18 also includes the process of preparing the control pattern 24 .
  • FIG. 8 is another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the present disclosure in the pattern recognition area.
  • the third electrode and the second electrode shown in FIGS. 2 and 5 to 7 are the same The layers are arranged differently.
  • the third electrodes 17 and the second electrodes 14 are arranged in different layers, and each third electrode 17 and the corresponding second electrode 14 are connected through the via holes on the first insulating layer 5; The situation should also belong to the protection scope of the present disclosure.
  • connection via hole is preferably set at the edge position of the control pattern 24. It is beneficial to reduce the leakage current of the photoelectric sensor.
  • the second insulating layer 8 is provided on the side of the fourth electrode 19 away from the substrate 1 , and the second insulating layer 8 is provided on the side of the second insulating layer 8 away from the substrate 1 and is located in the peripheral area There are bias traces 22 , and the fourth electrode 19 extends to the peripheral region 102 and is electrically connected to the bias traces 22 through via holes on the second insulating layer 8 .
  • the material of the bias trace 22 includes a metal material, and the first shading pattern 3 and the bias trace 22 are provided in the same layer. That is, the first light-shielding pattern 3 can be simultaneously prepared based on the existing production process of the bias wiring 22 , so the production cycle of the product can be effectively shortened and the production cost can be reduced.
  • the bias traces 22 are disposed on the same layer as the bonding electrodes located in the peripheral region 102 .
  • the pattern recognition module further includes: a second light-shielding pattern 23, the second light-shielding pattern 23 and the bias wiring 22 are arranged in the same layer, and the orthographic projection of the second light-shielding pattern 23 on the substrate 1 completely covers the thin film transistor The orthographic projection of the channel region portion of the active layer 12 in 16 on the substrate 1 .
  • the second light shielding pattern 23 is used to prevent external light from irradiating the channel region of the active layer 12, so as to prevent the electrical characteristics of the thin film transistor 16 from being shifted due to light.
  • the pattern recognition module further includes: a barrier layer 9 and a ground shield layer 10 , the barrier layer 9 is located on the side of the second shading pattern 23 away from the substrate 1 , and the ground shield layer 10 is located on the side of the barrier layer 9 away from the substrate 1 , the orthographic projection of the ground shielding layer 10 on the substrate 1 completely covers the pattern recognition area 101 .
  • the ground shielding layer 10 by disposing the ground shielding layer 10, the influence of noise caused by the electromagnetic coupling of the display panel 28 to the photoelectric sensor 20 can be effectively shielded, which is beneficial to improve the accuracy of pattern recognition.
  • the ground shielding layer 10 is electrically connected to the second shading pattern 23 through the via hole on the blocking layer 9 , which can effectively prevent the problem of charge accumulation and discharge on the second shading pattern 23 .
  • the ground shielding layer 10 is electrically connected to the first shading pattern 3 through the via hole on the blocking layer 9, which can effectively prevent the occurrence of charges on the first shading pattern 3 The problem of accumulation discharge.
  • FIG. 9a is another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the disclosure in the pattern recognition area
  • FIG. 9b is a cross-sectional schematic diagram of the alignment structure in FIG. 9a
  • FIG. 9c is a photoelectric sensor in the embodiment of the present disclosure
  • FIG. 9d is another schematic top view of a photoelectric sensor corresponding to a plurality of transparent holes in an embodiment of the disclosure, as shown in FIGS.
  • the pattern recognition module further includes: a collimation structure 26, the collimation structure 26 is located on the side of the photoelectric sensing structure 2 away from the substrate 1, and the collimation structure 26 at least covers the photosensitive area A2; the collimation structure 26 includes: an aperture The layer 261, the aperture layer 261 includes: a plurality of light-transmitting holes 261a arranged in an array. The light-transmitting hole 261a can play a role of collimating light.
  • one photoelectric sensor 20 corresponds to a plurality of light-transmitting holes 261 a
  • one light-transmitting hole 261 a corresponds to one photoelectric sensor 20
  • the number of light-transmitting holes 261a corresponding to each photoelectric sensor 20 is the same; the number of light-transmitting holes 261a corresponding to one photoelectric sensor 20 includes: 4-100.
  • the number of the light-transmitting holes 261 a corresponding to the photoelectric sensor 20 specifically refers to the number of the light-transmitting holes 261 a located in the area where the photosensitive pattern 18 is located in the photoelectric sensor 20 .
  • the intensity of the light signal received by the photoelectric sensor 20 is related to the number of light-transmitting holes 261 a corresponding to the photoelectric sensor 20 .
  • the greater the number of corresponding light-transmitting holes 261a the stronger the intensity of the light signal received by the photoelectric sensor 20 and the greater the current magnitude of the electrical signal output by the photoelectric sensor 20, which is more conducive to electrical signal detection.
  • the number of light-transmitting holes 261a is too large, the spacing between adjacent light-transmitting holes 261a is reduced, and the risk of light crosstalk is greater.
  • the number of the middle light-transmitting holes 261a is 4-100; in principle, each photoelectric sensor 20 may correspond to at least one light-transmitting hole 261a.
  • the plurality of light-transmitting holes 261 a corresponding to the same photoelectric sensor 20 are uniformly distributed in the area where the photosensitive pattern 18 is located in the photoelectric sensor 20 .
  • the plurality of light-transmitting holes 261a corresponding to the same photosensor 20 are arranged in a matrix in the row direction and the column direction, and are adjacent in the row direction or two adjacent in the column direction The distances between the light-transmitting holes 261a are equal.
  • the plurality of light-transmitting holes 261a corresponding to the same photosensor 20 are arranged in a hexagonal manner, and the distance between any two adjacent light-transmitting holes 261a is arranged.
  • the light-transmitting holes 261a in the embodiment of the present disclosure may also adopt other arrangement manners, which will not be described one by one in the present disclosure.
  • the collimation structure 26 further includes: a dielectric light-transmitting layer 262 , a lens layer 263 and a flat transparent layer 262 , a lens layer 263 and a flat transparent layer, which are located on the side of the aperture layer 261 away from the substrate 1 and are sequentially stacked along the direction away from the substrate 1 .
  • the optical layer 264; the lens layer 263 includes a plurality of convex lenses 263a corresponding to the light-transmitting holes 261a one-to-one, and the optical axes of the convex lenses 263a pass through the corresponding light-transmitting holes 261a.
  • the convex lens is a 263a plano-convex lens.
  • the plane surface of the plano-convex lens 263a faces the medium light-transmitting layer 262 and is attached to the surface of the medium light-transmitting layer 262.
  • the surfaces of layer 264 are in contact with each other.
  • the convex lens 263a can modulate the propagation direction of the light reflected by the texture, so as to reduce the inclination angle of part of the light, so that the propagation direction of the formed convergent light beam is concentrated.
  • the aperture layer 261 only allows the condensed light beams of a specific angle to pass through, and performs collimation processing on the condensed light beams output by the convex lens to improve the direction consistency of the condensed light beams received by the sensor.
  • the light-transmitting holes 261a of the aperture layer 261 are in one-to-one correspondence with the convex lenses 263a, ensuring that the light converged by each convex lens 263a passes through the same size holes for the same collimation, thereby reducing the difference between the signals.
  • the collimation structure 26 can be fixed by bonding with the photoelectric sensing structure 2 through optical OCA glue, or can be directly prepared on the photoelectric sensing structure 2 by processes such as thin film deposition and thin film patterning. belong to the protection scope of the present disclosure.
  • FIG. 10 is another schematic cross-sectional view of the pattern recognition module provided in the embodiment of the present disclosure in the pattern recognition area.
  • the pattern recognition module further includes: a non-visible light filter layer 27 .
  • the non-visible light filter layer 27 is located on the side of the photoelectric sensor 20 away from the substrate 1, and is configured to filter out the non-visible light in the transmitted light.
  • the non-visible light filter layer 27 is an infrared filter layer configured to filter out infrared light from the transmitted light. Under strong ambient light, most of the light passing through the finger is infrared light (with a wavelength range of 760 nm to 1 mm), and the detection light emitted by the display panel 28 after being reflected by the fingerprint surface is visible light (with a wavelength range of 400 nm to 700 nm). .
  • the infrared filter layer is configured to block infrared light and transmit visible light, so that the detection light reflected by the finger can pass but the infrared light transmitted through the finger cannot pass, thereby reducing the ambient light signal
  • the impact on the photoelectric sensor 20 improves the anti-glare performance of the product.
  • the infrared filter layer includes: an infrared absorption layer with an infrared absorption function or an infrared reflection layer with an infrared reflection function.
  • the infrared filter layer when the infrared filter layer is an infrared absorption layer with an infrared absorption function, the infrared filter layer can be composed of a material with an infrared filter function; when the infrared filter layer is an infrared reflection layer with an infrared reflection function, the infrared reflection The layers may be composed of materials with infrared reflecting functions or stacks of materials with different dielectric constants.
  • the invisible light filter layer 27 is located between the collimation structure 26 and the photosensor 20 or the invisible light filter layer 27 is integrated in the collimation structure 26 .
  • the non-visible light filter layer 27 is disposed between the collimation structure 26 and the photosensor 20 as an independent structure.
  • the non-visible light filter layer 27 can be attached on the photoelectric sensing structure 2 through optical OCA glue, or can be directly formed on the surface of the photoelectric sensing structure 2 by a coating process, both of which belong to the protection scope of the present disclosure.
  • FIG. 11 is a schematic diagram of filling the non-visible light filter layer in the light-transmitting hole according to the embodiment of the disclosure. As shown in FIG. 11 , when the non-visible light filter layer 27 is integrated in the collimating structure 26, as an example, the invisible light The filter layer 27 is filled in the light transmission hole 261a.
  • the collimation structure 26 includes a medium light-transmitting layer, a lens layer 263 and a flat light-transmitting layer 264, at least one of the medium light-transmitting layer and the flat light-transmitting layer 264
  • the material is an organic material having a function of non-visible light absorption (eg, absorbing infrared light) and is reused as the non-visible light filter layer 27 .
  • the substrate 1 is a flexible substrate 1
  • a third insulating layer (not shown) is disposed between the substrate 1 and the photoelectric sensing structure 2 .
  • a third insulating layer with a certain thickness is first formed on the substrate 1.
  • the materials of the third insulating layer include SiNx and SiO2, which can block water and oxygen and prevent peeling. Water and oxygen penetrate from the back of the PI flexible substrate 1 to damage the device and optical film, and facilitate the deposition of the subsequent film layer; on the other hand, by adjusting the SiNx process conditions or the SiNx/SiO2 ratio, the film layer stress can be changed.
  • the stress of the film layer is offset, avoiding the accumulation of stress, and preventing the film layer from breaking due to excessive stress and spontaneous curling after the flexible device is peeled off.
  • FIG. 12 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device includes: a texture recognition module and a display panel 28 , wherein the texture recognition module can adopt any of the previous embodiments.
  • the display panel 28 is located on the side of the first shading pattern 3 away from the substrate 1 .
  • the display panel 28 may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel 28 or a quantum dot light emitting diode (Quantum Dot Light Emitting Diodes, QLED) display panel 28, etc. This is not specifically limited.
  • the OLED display panel 28 may be, for example, a flexible OLED display panel 28 .
  • the OLED display panel 28 and the QLED display panel 28 have self-luminous properties, and the luminescence of the display pixel units can also be controlled or modulated as required, which can facilitate pattern collection and help improve device integration.
  • the OLED display panel 28 generally includes a flexible OLED display backplane 281 , a polarizer 282 and a protective cover plate 283 that are sequentially stacked in a direction away from the pattern recognition module 100 , and the material of the protective cover plate 283 can be polyimide PI. .
  • the substrate of the flexible OLED display backplane 281 is a flexible substrate, and the specific material may be PI or other flexible materials.
  • the display panel 28 and the pattern recognition module 100 are fixed by optical glue. In other embodiments, the display panel 28 and the texture recognition module 100 are arranged at intervals. The detailed description will be given later in combination with specific situations.
  • FIG. 13 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • the display device further includes: a middle frame 400 , and the middle frame 400 includes a bottom plate 401 and an edge of the bottom plate 401
  • the side wall 402 formed by bending towards the front side, the bottom plate 401 and the side wall 402 form a receiving groove, the pattern recognition module 100 and the display panel 28 are fixed in the receiving groove, and the display panel 28 is located in the pattern recognition module 100 away from the bottom plate 401 side.
  • the texture recognition module 100 is fixed on the base plate 401 , and the display panel 28 and the texture recognition module 100 are fixed by optical glue, so as to realize the display panel 28 , the texture recognition module 100 and the middle frame 400 . fixed.
  • FIG. 14 is another schematic structural diagram of the display device provided by the embodiment of the present disclosure. As shown in FIG. 14 , what is different from the situation shown in FIG. 13 is that in the situation shown in FIG. 14 , the display panel 28 and the texture recognition module 100 They are fixed by optical glue, a stepped support structure 404 is formed on the side wall 402, and the display panel 28 is fixed on the stepped support structure 404. fixed.
  • FIG. 15 is another schematic structural diagram of the display device provided by the embodiment of the present disclosure. As shown in FIG. 15 , what is different from the situation shown in FIGS. 13 and 14 is that in the situation shown in FIG. 15 , the display panel 28 and the texture The identification modules 100 are arranged at intervals, and there is an air spacer 29 therebetween. At this time, the texture recognition module 100 is fixed on the bottom plate 401 and the display panel 28 is fixed on the stepped support structure 404 .
  • the minimum distance between the display panel 28 and the pattern recognition module 100 is greater than or equal to 100um.
  • the display panel 28 and the texture recognition module 100 are too close to cause electromagnetic coupling, which increases the noise of the photoelectric sensor 20 in the texture recognition module 100, resulting in poor final image quality; in addition, the display pixel units in the display panel 28 and texture recognition Moiré patterns will be formed between the pixel units for pattern recognition in the module 100, which will affect subsequent image processing and pattern recognition.
  • the distance between the display panel 28 and the texture recognition module 100 is increased, the coupling noise between the two is reduced, and the occurrence of moiré patterns is avoided. problem, which is conducive to improving the quality of texture imaging.
  • a through hole 403 is formed on the bottom plate 401, and the display device further includes: a flexible circuit board 501 for pattern recognition and the chip 502 for pattern recognition; the flexible circuit board 501 for pattern recognition passes through the through hole 403, and one end of the flexible circuit board 501 is electrically connected to the binding electrode located in the binding area in the pattern recognition module 100 (generally, the electrical connection is realized by the binding process), The other end is electrically connected to the chip 502 for pattern recognition located on the back of the base plate 401 (generally, the electrical connection is realized by a die-bonding film process).
  • the display chip (not shown) and the display flexible circuit board can also be electrically connected to the display panel 28 located in the accommodating groove in the same manner.
  • FIG. 17 is another schematic structural diagram of the display device provided by the embodiment of the present disclosure.
  • the flexible circuit board for pattern recognition is One end of 501 is electrically connected with the binding electrodes for pattern recognition in the peripheral area of the pattern recognition module 100, the other end of the flexible circuit board 501 for pattern recognition is electrically connected with the chip for pattern recognition, and the flexible circuit board 501 for pattern recognition and the The chips 502 for pattern recognition are all located in the accommodating grooves.
  • the display panel 28 further has functional layers such as an encapsulation layer and a touch control layer.
  • functional layers such as an encapsulation layer and a touch control layer.
  • the display device provided in this embodiment may be any product or component with a texture recognition function, such as a mobile phone, a tablet computer, a display, a notebook computer, etc., which is not specifically limited in the embodiment of the present disclosure.
  • an embodiment of the present disclosure also provides a method for preparing a pattern recognition module, which can be used to prepare the pattern recognition module provided by any of the foregoing embodiments.
  • FIG. 18 is a flowchart of a method for preparing a texture recognition module provided by an embodiment of the present disclosure. As shown in FIG. 18 , the preparation method of the texture recognition module includes:
  • Step S1 providing a substrate.
  • the substrate can be a glass substrate or a PI flexible substrate.
  • the glass substrate When the substrate is a flexible substrate, first, the glass substrate should be cleaned and the surface moisture should be dried to remove surface stains; then, liquid PI should be coated on the glass, or the PI film should be directly hot-pressed on the glass surface through a silane coupling agent.
  • a certain thickness of SiNx or SiNx+SiO2 can also be deposited on the clean PI surface as a third insulating layer, which is used to prevent water and oxygen from permeating from the back of PI after stripping, damaging the device and optics.
  • the film stress can be changed, which can offset the subsequent film stress, avoid stress accumulation, and prevent flexible devices from peeling off After that, the stress is too large, and the spontaneous curling leads to the rupture of the film layer.
  • the substrate is divided into a texture identification area and a peripheral area located around the texture identification area, and the texture identification area includes a photosensitive area.
  • Step S2 forming a photoelectric sensing structure on the substrate.
  • the photoelectric sensing structure is located on the substrate and in the pattern recognition area, and includes: a plurality of grid lines, a plurality of signal sensing lines, and a plurality of pixel units defined by the plurality of grid lines and the plurality of signal sensing lines ;
  • the pixel unit includes: a thin film transistor, the gate of the thin film transistor is electrically connected to the corresponding gate line, and the first electrode of the thin film transistor is electrically connected to the corresponding signal sensing line;
  • the pattern recognition area includes: a photosensitive area, located in the photosensitive area
  • the pixel unit inside also includes: a photoelectric sensor, the photoelectric sensor includes a third electrode, a photosensitive pattern and a fourth electrode that are sequentially stacked along the direction away from the substrate, and the third electrode is connected to the second electrode of the thin film transistor located in the same pixel unit;
  • the area ratio of the sensor to the corresponding pixel unit is 40% to 90%.
  • the photoelectric sensing structure after the photoelectric sensing structure is formed, structural steps such as forming bias traces (first/second light-shielding patterns), collimation structure, infrared filter layer, etc. may also be included.
  • bias traces first/second light-shielding patterns
  • collimation structure infrared filter layer
  • infrared filter layer etc.

Abstract

一种纹路识别模组，包括：基底（1），包括纹路识别区域（101）和位于纹路识别区域（101）周边的周边区域（102）；光电传感结构（2），位于基底（1）之上且在纹路识别区域（101）内，包括：多条栅线（11a）、多条信号感测线（15）以及由多条栅线（11a）和多条信号感测线（15）限定出的多个像素单元；其中，像素单元包括：薄膜晶体管（16），薄膜晶体管（16）的栅极（11）与对应的栅线（11a）电连接，薄膜晶体管（16）的第一电极（13）与对应的信号感测线（15）电连接；其中，纹路识别区域（101）包括：感光区（A1），位于感光区（A1）内的像素单元还包括：光电传感器（20），光电传感器（20）包括沿远离基底（1）方向依次层叠设置的第三电极（17）、感光图形（18）和第四电极（19），第三电极（17）与位于同一像素单元的薄膜晶体管（16）的第二电极（14）连接；光电传感器（20）与所对应的像素单元的面积比为40％～90％。

Description

纹路识别模组和显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种纹路识别模组和显示装置。
背景技术
在光学纹路识别过程中，一般是采用像素阵列的形式来进行识别。具体地，像素阵列包括呈阵列排布的多个纹路识别用像素单元，该像素单元包括：薄膜晶体管和光电传感器，薄膜晶体管可用于向光电传感器提供驱动信号以控制光电传感器进行工作，光电传感器用于接收检测光并输出相应的电信号，该电信号通过薄膜晶体管传递至信号感测线(sense line)，以供外部芯片进行处理，得到对应位置的谷脊信息。
发明内容
本公开实施例提供了一种纹路识别模组及其制备方法和显示装置。
第一方面，本公开实施例提供了一种纹路识别模组，包括：
基底，包括纹路识别区域和位于所述纹路识别区域周边的周边区域；
光电传感结构，位于所述基底之上且在所述纹路识别区域内，包括：多条栅线、多条信号感测线以及由多条栅线和多条信号感测线交叉限定出的多个像素单元；其中，所述像素单元包括：薄膜晶体管，所述薄膜晶体管的栅极与对应的栅线电连接，所述薄膜晶体管的第一电极与对应的信号感测线电连接；
其中，所述纹路识别区域包括：感光区，位于所述感光区内的像素单元还包括：光电传感器，所述光电传感器包括沿远离所述基底方向依次层叠设置的第三电极、感光图形和第四电极，所述第三电极与位于同一所述像素单元的所述薄膜晶体管的第二电极连接；
所述光电传感器与所对应的像素单元的面积比为40％～90％。
在一些实施例中，所述薄膜晶体管的沟道区域呈倒L型或弧形。
在一些实施例中，所述光电传感器在所述基底上的正投影与所述薄膜晶体管的有源层在所述基底上的正投影不交叠。
在一些实施例中，所述栅线沿第一方向延伸，所述信号感测线沿第二方向延伸，所述第一方向与所述第二方向垂直；
所述薄膜晶体管包括：栅极、有源层、第一电极和第二电极，所述第一电极在与所述基底所处平面相平行的截面的形状为矩形，所述第一电极具有在所述第一方向上相对设置的第一侧边和第二侧边以及在所述第二方向上相对设置的第三侧边和第四侧边，所述第一电极与位于自身的第一侧边最近的所述信号感测线电连接，所述栅极与位于所述第一电极的所述第三侧边最近的所述栅线电连接；
所述第二电极包括：第一导电部和第二导电部，所述第一导电部沿第一方向延伸且与所述第一电极的第二侧边相对设置，所述第二导电部沿第二方向延伸且与所述第一电极的第四侧边相对设置，所述第一导电部与所述第二导电部电连接。
在一些实施例中，所述第二电极还包括：第三导电部，所述第一导电部、所述第二导电部和所述第三导电部三者同层设置，第三导电部的延伸方向与所述第一方向和所述第二方向均相交，所述第三导电部的两端分别与所述第一导电部和所述第二导电部连接。
在一些实施例中，所述纹路识别区域还包括：位于所述感光区外围的虚拟区，位于所述虚拟区内的像素单元配置为向对应的所述信号感测线输出参考噪声信号。
在一些实施例中，所述感光图形背向所述基底的一侧依次设置有平坦化层和钝化层，所述第四电极位于所述钝化层背向所述基底的一侧且通过所述平坦化层和钝化层上的过孔与对应的感光图形电连接；
位于所述虚拟区内的像素单元还包括：第五电极和第六电极，所述 第五电极与位于所述虚拟区的薄膜晶体管的第二电极电连接，所述第五电极与所述第六电极之间包括所述平坦化层和所述钝化层。
在一些实施例中，所述薄膜晶体管远离所述基底的一侧形成有第一绝缘层，位于所述感光区的光电传感器通过所述第一绝缘层上的过孔与所述薄膜晶体管的第二电极连接；
所述感光图形背向所述基底的一侧依次设置有平坦化层和钝化层，所述第四电极位于所述钝化层背向所述基底的一侧且通过所述平坦化层和钝化层上的过孔与对应的感光图形电连接；
位于所述虚拟区内的像素单元还包括：第五电极和第六电极，所述第五电极与位于所述虚拟区的薄膜晶体管的第二电极电连接，所述第五电极与所述第三电极同层同材料设置，所述第六电极与所述第四电极同层同材料设置，所述第五电极与所述第六电极之间包括所述第一绝缘层、所述平坦化层和所述钝化层。
在一些实施例中，位于所述虚拟区内的像素单元还包括：传感器对照结构，所述传感器对照结构包括：沿远离所述基底方向依次层叠设置的第五电极、对照图形和第六电极，所述第五电极与位于所述虚拟区的薄膜晶体管的第二电极电连接，所述第五电极与所述第三电极同层同材料设置，所述第六电极与所述第四电极同层同材料设置；
所述对照图形的材料为非光电材料且介电常数与所述感光图形的介电常数大致相同。
在一些实施例中，还包括：第一遮光图形，位于所述光电传感器远离所述基底的一侧，所述第一遮光图形在所述基底上的正投影完全覆盖所述虚拟区且未覆盖所述感光区。
在一些实施例中，所述虚拟区位于所述感光区的一侧。
在一些实施例中，所述虚拟区位于所述感光区的相对两侧或相交两侧。
在一些实施例中，所述虚拟区位于所述感光区的四侧。
在一些实施例中，位于所述感光区内的像素单元所包含的所述薄膜晶体管，与位于所述虚拟区内的像素单元所包含的所述薄膜晶体管，二者结构、形状、大小均相同。
在一些实施例中，纹路识别模组还包括：
准直结构，位于所述光电传感结构远离基底的一侧，至少覆盖所述感光区；
所述准直结构包括：孔径层，所述孔径层包括：呈阵列排布的多个透光孔。
在一些实施例中，所述准直结构还包括：位于所述孔径层远离所述基底一侧且沿远离所述基底方向依次层叠设置的介质透光层、透镜层和平坦透光层；
所述透镜层包括与所述透光孔一一对应的多个凸透镜，所述凸透镜的光轴经过对应的透光孔。
在一些实施例中，所述凸透镜为平凸透镜，所述平凸透镜的平面表面朝向所述介质透光层且与所述介质透光层的表面贴合，所述平凸透镜的凸面表面朝向所述平坦透光层且与所述平坦透光层的表面相贴合。
在一些实施例中，一个所述光电传感器对应多个所述透光孔，一个所述透光孔对应一个所述光电传感器。
在一些实施例中，每个所述光电传感器所对应的所述透光孔的数量相同；
一个所述光电传感器所对应的透光孔数量包括：4～100个。
在一些实施例中，纹路识别模块还包括：
非可见光滤光层，位于所述光电传感器远离所述基底的一侧，配置为滤除透过光线中的非可见光线。
在一些实施例中，所述非可见光滤光层包括：红外滤光层，配置为 滤除透过光线中的红外光线。
在一些实施例中，所述红外滤光层包括：具有红外吸收功能的红外吸收层或者具有红外反射功能的红外反射层。
在一些实施例中，所述非可见光滤光层位于所述准直结构与所述光电传感器之间。
在一些实施例中，所述非可见光滤光层集成于所述准直结构内。
在一些实施例中，所述非可见光滤光层填充于所述透光孔内。
在一些实施例中，所述准直结构包括：沿远离所述基底方向依次层叠设置的所述孔径层、介质透光层、透镜层和平坦透光层，所述透镜层包括与所述透光孔一一对应的多个凸透镜，所述凸透镜的光轴经过对应的透光孔；
所述介质透光层和所述平坦透光层中的至少一者复用作所述非可见光滤光层。
在一些实施例中，所述光电传感结构包括：沿远离所述基底的方向依次层叠设置的栅极、栅绝缘层、有源层、第一导电电极层、第一绝缘层、感光图形、平坦化层、钝化层和第二导电电极层，所述第一遮光图形位于所述第二导电电极层远离所述基底的一侧；
所述第一导电电极层包括：所述第一电极、所述第二电极和所述第三电极，所述第二导电电极层包括：所述第四电极。
在一些实施例中，所述第四电极远离所述基底的一侧设置有第二绝缘层，在所述第二绝缘层远离所述基底的一侧且位于所述周边区域设置有偏置走线，所述第四电极延伸至所述周边区域并通过所述第二绝缘层上的过孔与所述偏置走线电连接。
在一些实施例中，偏置走线的材料包括金属材料，所述第一遮光图形与所述偏置走线同层设置。
在一些实施例中，纹路识别模块还包括：第二遮光图形，所述第二 遮光图形与所述偏置走线同层设置；
所述第二遮光图形在所述基底上的正投影完全覆盖所述薄膜晶体管内有源层的沟道区部分在所述基底上的正投影。
在一些实施例中，纹路识别模块还包括：位于所述第二遮光图形远离所述基底的一侧的阻隔层以及位于所述阻隔层远离所述基底一侧的接地屏蔽层，所述接地屏蔽层在所述基底上的正投影完全覆盖所述纹路识别区域。
在一些实施例中，所述接地屏蔽层通过所述阻隔层上的过孔与所述第一遮光图形和所述第二遮光图形电连接。
在一些实施例中，所述基底为柔性基底，所述基底与所述光电传感结构之间设置有第三绝缘层。
第二方面，本公开实施例还提供了一种显示装置，其中，包括：如第一方面提供的所述纹路识别模组，以及位于第一遮光图形远离所述基底一侧的显示面板。
在一些实施例中，所述显示面板与所述纹路识别模组之间通过光学胶固定；
或者，所述显示面板与所述纹路识别模组间隔设置。
在一些实施例中，所述显示面板为OLED显示面板，所述OLED显示面板包括沿远离所述纹路识别模组的方向依次层叠设置的OLED显示背板、偏光片和保护盖板，所述保护盖板的材料包括聚酰亚胺。
在一些实施例中，所述显示装置还包括：
中框，包括底板和所述底板的边缘朝正面一侧弯折所形成的侧壁，所述底板和所述侧壁形成容纳槽，所述纹路识别模组和所述显示面板固定于所述容纳槽内，所述显示面板位于所述纹路识别模组远离所述底板的一侧。
在一些实施例中，所述纹路识别模组固定于所述底板上。
在一些实施例中，所述侧壁上形成有台阶状支撑结构，所述显示面板固定于所述台阶状支撑结构上。
在一些实施例中，所述底板上形成有贯穿孔，所述显示装置还包括：纹路识别用柔性线路板和纹路识别用芯片；
纹路识别用柔性线路板穿过所述贯穿孔，其一端与纹路识别模组内位于周边区域的纹路识别用绑定电极电连接，另一端与位于所述底板背面的纹路识别用芯片电连接。
在一些实施例中，所述显示装置还包括：纹路识别用柔性线路板和纹路识别用芯片，纹路识别用柔性线路板的一端与纹路识别模组内位于周边区域的纹路识别用绑定电极电连接，纹路识别用柔性线路板的另一端与所述纹路识别用芯片电连接；
所述纹路识别用柔性线路板和纹路识别用芯片均位于所述容纳槽内。
第三方面，本公开实施例还提供了一种如第一方面中所述纹路识别模组的制备方法，其中，包括：
提供一基底，包括纹路识别区域和位于所述纹路识别区域周边的周边区域；
在所述基底上形成光电传感结构，所述光电传感结构位于所述基底之上且在所述纹路识别区域内，包括：多条栅线、多条信号感测线以及由多条栅线和多条信号感测线限定出的多个像素单元；其中，所述像素单元包括：薄膜晶体管，所述薄膜晶体管的栅极与对应的栅线电连接，所述薄膜晶体管的第一电极与对应的信号感测线电连接；所述纹路识别区域包括：感光区，位于所述感光区内的像素单元还包括：光电传感器，所述光电传感器包括沿远离所述基底方向依次层叠设置的第三电极、感光图形和第四电极，所述第三电极与位于同一所述像素单元的所述薄膜晶体管的第二电极连接；所述光电传感器与所对应的像素单元的面积比 为40％～90％。
附图说明
图1为本公开实施例提供的纹路识别模组的一种俯视示意图；
图2为本公开实施例提供的纹路识别模组在纹路识别区域的一种截面示意图；
图3为本公开实施例中一个像素单元及其所对应的一条栅线和信号感测线的一种俯视示意图；
图4a为本公开实施例提供的纹路识别模组的另一种俯视示意图；
图4b为本公开实施例提供的纹路识别模组的又一种俯视示意图；
图4c为本公开实施例提供的纹路识别模组的再一种俯视示意图；
图5为本公开实施例提供的纹路识别模组在纹路识别区域的另一种截面示意图；
图6为本公开实施例提供的纹路识别模组在纹路识别区域的又一种截面示意图；
图7为本公开实施例提供的纹路识别模组在纹路识别区域的再一种截面示意图；
图8为本公开实施例提供的纹路识别模组在纹路识别区域的再一种截面示意图；
图9a为本公开实施例提供的纹路识别模组在纹路识别区域的再一种截面示意图；
图9b为图9a中准直结构的一种截面示意图；
图9c为本公开实施例中一个光电传感器与多个透光孔相对应的一种俯视示意图；
图9d为本公开实施例中一个光电传感器与多个透明孔相对应的另一种俯视示意图；
图10为本公开实施例提供的纹路识别模组在纹路识别区域的再一种截面示意图；
图11为本公开实施例中红外滤光层填充于透光孔内的示意图；
图12为本公开实施例提供的显示装置的一种结构示意图；
图13为本公开实施例提供的显示装置的另一种结构示意图；
图14为本公开实施例提供的显示装置的又一种结构示意图；
图15为本公开实施例提供的显示装置的再一种结构示意图；
图16为图13至图15中底板背面的一种俯视示意图；
图17为本公开实施例提供的显示装置的再一种结构示意图；
图18为本公开实施例提供的纹路识别模组的一种制备方法流程图。
具体实施方式
为使本领域的技术人员更好地理解本公开的技术方案，下面结合附图对本公开提供的一种纹路识别模组及其制备方法和显示装置进行详细描述。
在下文中将参考附图更充分地描述示例实施例，但是所述示例实施例可以以不同形式来体现且不应当被解释为限于本文阐述的实施例。反之，提供这些实施例的目的在于使本公开透彻和完整，并将使本领域技术人员充分理解本公开的范围。附图中各部件的形状和大小不反应真实比例，目的只是示意说明本公开内容。
本文所使用的术语仅用于描述特定实施例，且不意欲限制本公开。如本文所使用的，单数形式“一个”和“该”也意欲包括复数形式，除非上下文另外清楚指出。还将理解的是，当本说明书中使用术语“包括”和/或“由……制成”时，指定存在所述特征、整体、步骤、操作、元件和/或组件，但不排除存在或添加一个或多个其它特征、整体、步骤、操作、元件、组件和/或其群组。在不冲突的情况下，本公开各实施例及实 施例中的各特征可相互组合。
除非另外限定，否则本文所用的所有术语(包括技术和科学术语)的含义与本领域普通技术人员通常理解的含义相同。还将理解，诸如那些在常用字典中限定的那些术语应当被解释为具有与其在相关技术以及本公开的背景下的含义一致的含义，且将不解释为具有理想化或过度形式上的含义，除非本文明确如此限定。
具有纹路识别功能的显示装置一般包括显示面板和光电传感结构，在进行纹路识别时，指纹与显示面板表面接触，显示面板发射出的检测光在指纹表面发生反射后射向光电传感结构，光电传感结构中的各光电传感器会基于接收到光线(经过指纹表面反射的检测光)生成相应的电信号，该电信号通过驱动晶体管、信号感测线等电学结构传递至外部芯片，外部芯片根据接收到的电信号识别出对应位置处纹路的谷脊。
图1为本公开实施例提供的纹路识别模组的一种俯视示意图，图2为本公开实施例提供的纹路识别模组在纹路识别区域的一种截面示意图，如图1和图2所示，该纹路识别模组包括：基底1和光电传感结构2。
其中，基底1包括纹路识别区域101和位于纹路识别区域101周边的周边区域102。其中，基底1可以为玻璃基底1或PI柔性基底1。
光电传感结构2位于基底1之上且在纹路识别区域内，包括：多条栅线11a、多条信号感测线15以及由多条栅线11a和多条信号感测线15交叉限定出的多个像素单元，像素单元包括：薄膜晶体管16，薄膜晶体管16的栅极11与对应的栅线电连接，薄膜晶体管16的第一电极13与对应的信号感测线15电连接。
纹路识别区域101包括感光区A1，位于感光区内的像素单元还包括：光电传感器20。光电传感器在基底上的正投影与薄膜晶体管的有源层在基底上的正投影不交叠。
在一些实施例中，薄膜晶体管16远离基底1的一侧形成有第一绝缘层5，位于感光区A1的光电传感器20通过第一绝缘层5上的过孔与对应的薄膜晶体管16的第二电极14连接。
位于感光区内位于感光区A1内的像素单元配置为根据接收到的光线产生对应的电信号(由光电传感器20实现)并向对应的信号感测线输出该电信号(由薄膜晶体管16来是实现)，以供进行纹路识别。光电传感器与所对应的像素单元的面积比为40％～90％。
光电传感器20可为PIN光电二极管或PN光敏二极管。具体地，光电传感器20包括：沿远离基底1方向依次层叠设置的第三电极17、感光图形18和第四电极19，第三电极17与位于同一像素单元内的薄膜晶体管16的第二电极14电连接，通过薄膜晶体管16可以控制施加在第三电极17上的电压，从而控制光电传感器20的工作状态。
感光图形18包括叠层设置的P型半导体层以及N型半导体层(例如N型Si层)，或者包括叠层设置的P型半导体层(例如P型Si层)、本征半导体层(例如本征Si层)以及N型半导体层(例如N型Si层)。例如，I层为a-Si材料，P层为a-Si掺杂B离子的材料，N层为a-Si掺杂P离子的材料。
在一些实施例中，第四电极19为透明电极，可以采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化镓锌(GZO)等透明金属氧化物等材料。在一些实施例中，在第四电极19与感光图形18之间设置有欧姆接触层21，用于减小第四电极19与感光图形18之间的接触电阻，欧姆接触层21的材料为金属材料且欧姆接触层21整体具有较佳的透光性。第三电极17为金属电极，采用铜(Cu)、铝(Al)、钛(Ti)等金属材料或者合金材料。
需要说明的是，本公开实施例中某个结构“透明”是指该结构可以透过光线，而不是指该结构透光率为100％。
在本公开实施例中，位于感光区A1内的像素单元向对应的信号感测线15输出与所接收到光线相对应的电信号，以供外部芯片进行处理，得到对应位置的谷脊信息，从而实现纹路识别。
需要说明的是，在纹路识别模组的周边区域102，一般包含有绑定区域，绑定区域内设置有绑定电极。根据功能的不同，绑定区一般包含栅极驱动芯片绑定区C1和数据驱动芯片绑定区C2，位于栅极驱动芯片绑定区内C1的绑定电极为栅极驱动芯片用绑定电极，位于数据驱动芯片绑定区C2内的绑定电极为数据驱动芯片用绑定电极。绑定区域和绑定电极的设置属于本领域的常规技术，本公开不进行赘述。
图3为本公开实施例中一个像素单元及其所对应的一条栅线和信号感测线的一种俯视示意图，如图3所示，薄膜晶体管16包括：栅极11、有源层12、第一电极13和第二电极14，第一电极13具体是指薄膜晶体管16的源极，第二电极14具体是指薄膜晶体管16的漏极。有源层12上位于第一电极13和第二电极14之间的区域为沟道区域，所述薄膜晶体管的沟道区域呈倒L型或弧形。
在一些实施例中，栅线11a沿第一方向X延伸，信号感测线15沿第二方向Y延伸，第一方向X与第二方向Y垂直；在图5中，第一方向X为水平方向，第二方向Y为竖直方向。第一电极13在与基底1所处平面相平行的截面的形状为矩形，第一电极13具有在第一方向上相对设置的第一侧边和第二侧边以及在第二方向上相对设置的第三侧边和第四侧边，第一电极13与位于自身的第一侧边最近的信号感测线15电连接，栅极11与位于第一电极13的第三侧边最近的栅线11a电连接；第二电极14包括：第一导电部14a和第二导电部14b，第一导电部14a沿第一方向延伸且与第一电极13的第二侧边相对设置，第二导电部14b沿第二方向延伸且与第一电极13的第四侧边相对设置，第一导电部14a与第二导电部14b电连接。
与传统薄膜晶体管16内源极和漏极为条状且相互平行的情况不同，在本公开实施例中，源极为矩形，漏极与源极上的两个侧边(第二侧边和第四侧边)相对设置，此时有源层12上的沟道区域宽度增大。在所需薄膜晶体管16的沟道宽长比一定的情况下，源极的尺寸可以相应减小(漏极的整体长度与传统薄膜晶体管16内条状漏极的长度基本相等)，此时源极与其他结构之间形成的交叠电容(例如源极与栅极11之间的电容)可以减小，有利于降低薄膜晶体管16的自身噪声，有利于提高纹路识别精准度。
在一些实施例中，第二电极14还包括：第三导电部14c，第一导电部14a、第二导电部14b和第三导电部14c三者同层设置，第三导电部14c的延伸方向与第一方向和第二方向均相交，第三导电部14c的两端分别与第一导电部14a和第二导电部14b连接。此时，有源层12上的沟道区域呈倒“L”型。
需要说明的是，上述具有倒“L”型沟道区域的薄膜晶体管16为本公开实施例中的一种可选实施例方案，其不会对本公开的技术方案产生限制。
在实际应用中发现，在感光区内的像素单元产生电信号并最终传递至外部芯片的过程中会受到噪声干扰，导致外部芯片接受到的电信号不准确，从而影响纹路识别精准度。为解决该技术问题，可在基于电信号进行成像之前，对外部芯片所接收到的感光区A1内的像素单元输出电信号进行降噪处理。
在一些实施例中，为便于后续能够对位于感光区A1内的像素单元所输出电信号进行降噪处理，在纹路识别区域101内还设置有位于感光区A1外围的虚拟(Dummy)区A2，位于虚拟区A2内的像素单元配置为向对应的信号感测线输出参考噪声信号，该参考噪声信号可用于对外部芯片所接收到的来自于感光区A1内像素单元所输出电信号进行降噪处理，有 利于提升对感光区A1内纹路信息的识别精准度。
在一些实施例中，虚拟区A2内像素单元的数量为多个，可将位于虚拟区A2内的全部像素单元所输出的噪声信号进行预设处理，以得到参考噪声信号(例如，对全部噪声信号求平均得到参考噪声信号，或者是选取电流值最大的噪声信号作为参考噪声信号，或者是选取电流值最小的噪声信号作为参考噪声信号等)；然后，基于参考噪声信号来对感光区A1内像素单元所输出的电信号进行降噪处理。作为一个示例，可以直接将感光区A1内像素单元所输出的电信号的电流(或电压)大小与参考噪声信号的电流(电压)大小进行差减处理。需要说明的是，基于噪声信号来对待降噪信号进行降噪处理的具体算法，本公开技术方案不作限定。
图4a为本公开实施例提供的纹路识别模组的另一种俯视示意图，图4b为本公开实施例提供的纹路识别模组的又一种俯视示意图，图4c为本公开实施例提供的纹路识别模组的再一种俯视示意图，如图1以及图4a～图4b所示，图1中示出了虚拟区A2位于感光区A1的一侧的情况，图4a中示出了一种虚拟区A2位于感光区A1的相对两侧的情况，图4b中示出了一种虚拟区A2位于感光区A1的相交两侧的情况，图4c中示出了一种虚拟区A2位于感光区A1的四侧的情况。
当然，在一些实施例中，虚拟区A2也可以位于感光区A1的不同三侧，此种情况未给出相应附图。
在一些实施例中，位于感光区A1内的像素单元所包含的薄膜晶体管16，与位于虚拟区A2内的像素单元所包含的薄膜晶体管16，二者结构、形状、大小均相同。此时，位于感光区A1内的像素单元所包含的薄膜晶体管16与位于虚拟区A2内的像素单元所包含的薄膜晶体管16的自身噪声相同或近似相同；此时基于虚拟区A2内的像素单元(薄膜晶体管16)所输出的噪声信号来对感光区A1内的像素单元(薄膜晶体管16)所输出的电信号进行降噪处理，降噪效果较佳，有利于提升纹路识别精准度。
参见图2所示，在一些实施例中，感光图形18背向基底1的一侧依次设置有平坦化层6和钝化层7，平坦化层6和钝化层7上形成有与感光图形18一一对应的过孔，以使感光图形18背向基底1一侧表面至少部分露出，第四电极19位于钝化层7背向基底1的一侧且通过平坦化层6和和钝化层7上的过孔与对应的感光图形18电连接；位于虚拟区A2内的像素单元还包括：第五电极17a和第六电极19a，所述第五电极17a与所述虚拟区的薄膜晶体管的第二电极14连接，第五电极17a与第六电极19a之间包括平坦化层6、钝化层7。可选地，第五电极与薄膜晶体管的第二电极可以同层也可以不同层设置。
参见图2所示，在一些实施例中，感光图形18背向基底1的一侧依次设置有平坦化层6和钝化层7，平坦化层6和钝化层7上形成有与感光图形18一一对应的过孔，以使感光图形18背向基底1一侧表面至少部分露出，第四电极19位于钝化层7背向基底1的一侧且通过平坦化层6和和钝化层7上的过孔与对应的感光图形18电连接；位于虚拟区A2内的像素单元还包括：第五电极17a和第六电极19a，所述第五电极17a与所述虚拟区的薄膜晶体管的第二电极14连接，第五电极17a与第三电极同层同材料设置，第六电极19a与第四电极同层同材料设置，第五电极17a与第六电极19a之间包括第一绝缘层5、平坦化层6、钝化层7。
在图2所示情况中，位于虚拟区A2内的像素单元内未设置感光图形18(由平坦化层填充)，即位于虚拟区A2内的像素单元不会产生光电效应，此时位于虚拟区A2内的像素单元所输出电信号可作为参考噪声信号。
图5为本公开实施例提供的纹路识别模组在纹路识别区域的另一种截面示意图，如图5所示，与图2中位于虚拟区A2内的像素单元不同，图5所示位于虚拟区A2内的像素单元不但包括薄膜晶体管16，还包括传感器对照结构25，传感器对照结构25包括：沿远离基底1方向依次 层叠设置的第五电极17a、对照图形24和第六电极19a，第五电极17a与对应的薄膜晶体管的第二电极14电连接，对照图形24的介电常数与感光图形18的介电常数大致相同且对照图形25采用非光电材料。其中，传感器对照结构25内第六电极19a和对照图形24的连接方式，与光电传感结构2内第四电极19和光电图形18的连接方式，二者相同。
在本公开实施例中，传感器对照结构25与光电传感结构2的结构类似且对照图形24的介电常数与感光图形18的介电常数相同，可使得位于虚拟区A2内的像素单元和位于感光区A1内的像素单元的自身噪声相同或近似相同，此时基于虚拟区A2内的像素单元所输出的噪声信号来对感光区A1内的像素单元所输出的电信号进行降噪处理，降噪效果较佳，有利于提升有利于提高纹路识别精准度。另外，即便虚拟区A2处存在光照，但由于对照图形采用非光电材料，因此对照图形也不会因光照而产生电流，从而能避免光照对位于虚拟区A2内的像素单元所输出的噪声信号产生影响。
图6为本公开实施例提供的纹路识别模组在纹路识别区域的又一种截面示意图，图7为本公开实施例提供的纹路识别模组在纹路识别区域的再一种截面示意图，如图6和图7所示，与图2和图5中所示情况不同，在图6所示情况中纹路识别模组还包括：第一遮光图形3，第一遮光图形3位于第六电极19a远离基底1的一侧，第一遮光图形3在基底1上的正投影完全覆盖虚拟区A2且未覆盖感光区A1。
通过设置第一遮光图形3可有效避免光线照射至位于虚拟区A2内的像素单元，以保证位于虚拟区A2内的像素单元所输出的噪声信号不受光照因素影响，有利于提升后续的降噪效果。
参见图2、图5～图7中所示，第三电极17、第五电极17a与第二电极14同层设置，即每个第三电极17、第五电极17a均与对应的第二电极14直接相连。
在一些实施例中，光电传感结构2包括：沿远离基底1的方向依次层叠设置的栅极11(一般采用金属材料，厚度为
Figure PCTCN2020132663-appb-000001
)、栅绝缘层4(一般采用无机绝缘层材料，包括：SiNx或SiO2)、有源层12(材料为a-Si或单晶硅)、第一导电电极层(一般采用金属材料，厚度为
Figure PCTCN2020132663-appb-000002
具体包括：第一电极13、第二电极14、第三电极17、第五电极17a、信号感测线15)、第一绝缘层5(一般采用无机绝缘层材料，包括：SiNx或SiO2)、感光图形18(厚度为
Figure PCTCN2020132663-appb-000003
的光电转换材料)、平坦化层6(厚度为
Figure PCTCN2020132663-appb-000004
的有机材料)、钝化层7(厚度为
Figure PCTCN2020132663-appb-000005
的SiNx或SiO2，以保证后续膜层与平坦化层6上表面的粘附性)、第二导电电极层(厚度为
Figure PCTCN2020132663-appb-000006
透明导电材料，具体包括：第四电极19、第六电极19a)。其中，栅极11、有源层12、第一电极13和第二电极14构成薄膜晶体管16，第三电极17、感光图形18和第四电极19构成光电传感器20。
对应的，在纹路识别区域101内各膜层掩模制作的工序包括：栅极11→栅绝缘层4→有源层12→第一导电电极层→第一绝缘层5→第三电极17→感光图形18→平坦化层6→钝化层7→第二导电电极层。第四电极19通过钝化层7和平坦化层6上的过孔与感光图形18电连接，其中平坦化层6和钝化层7可分别进行构图工艺，因此两者上的过孔大小不同；在一些实施例中，钝化层7上的过孔尺寸小于平坦化层6上的过孔尺寸。示例性地，钝化层7上的过孔半径比平坦化层6上所对应过孔半径小3.5um～4um。
需要说明的是，当虚拟区内存在对照图形24，且对照图形24的材料与感光图形18的材料不同时，则在制备第三电极17/第五电极17a和平坦化层6之间不但包括制备感光图形18的工序，还包括制备对照图形24的工序。
图8为本公开实施例提供的纹路识别模组在纹路识别区域的再一种 截面示意图，如图8所示，与图2、图5～图7中所示第三电极与第二电极同层设置不同，图8所示情况中第三电极17与第二电极14异层设置，每个第三电极17与对应的第二电极14通过第一绝缘层5上的过孔相连；此种情况也应属于本公开的保护范围。
另外，当光电传感器20的第三电极17通过第一绝缘层5上的过孔与薄膜晶体管16的第二电极14的电连接时，该连接过孔优选设于对照图形24的边缘位置，有利于减小光电传感器的漏电流。
再次参见图1～8所示，在一些实施例中，第四电极19远离基底1的一侧设置有第二绝缘层8，在第二绝缘层8远离基底1的一侧且位于周边区域设置有偏置走线22，第四电极19延伸至周边区域102并通过第二绝缘层8上的过孔与偏置走线22电连接。
在一些实施例中，偏置走线22的材料包括金属材料，第一遮光图形3与偏置走线22同层设置。即，第一遮光图形3可基于现有偏置走线22的生产工序得以同时制备，因此可有效缩短产品的生产周期，降低生产成本。另外，一般而言，偏置走线22与位于周边区域102内的绑定电极同层设置。
在一些实施例中，纹路识别模块还包括：第二遮光图形23，第二遮光图形23与偏置走线22同层设置，且第二遮光图形23在基底1上的正投影完全覆盖薄膜晶体管16内有源层12的沟道区部分在基底1上的正投影。第二遮光图形23用于避免外部光线照射至有源层12的沟道区，以避免薄膜晶体管16的电学特性因光照而产生偏移。
在一些实施例中，纹路识别模块还包括：阻隔层9和接地屏蔽层10，阻隔层9位于第二遮光图形23远离基底1的一侧，接地屏蔽层10位于阻隔层9远离基底1一侧，接地屏蔽层10在基底1上的正投影完全覆盖纹路识别区域101。在本公开实施例中，通过设置接地屏蔽层10，可以有效屏蔽显示面板28对光电传感器20的电磁耦合带来的噪声影响，有 利于提升纹路识别精准度。
在一些实施例中，接地屏蔽层10通过阻隔层9上的过孔与第二遮光图形23电连接，可有效防止第二遮光图形23上出现电荷堆积放电的问题。另外，在第一遮光图形3与偏置走线同层设置时，接地屏蔽层10通过阻隔层9上的过孔与第一遮光图形3电连接，可有效防止第一遮光图形3上出现电荷堆积放电的问题。
图9a为本公开实施例提供的纹路识别模组在纹路识别区域的再一种截面示意图，图9b为图9a中准直结构的一种截面示意图，图9c为本公开实施例中一个光电传感器与多个透光孔相对应的一种俯视示意图，图9d为本公开实施例中一个光电传感器与多个透明孔相对应的另一种俯视示意图，如图9a～图9d所示，在一些实施例中，纹路识别模组还包括：准直结构26，准直结构26位于光电传感结构2远离基底1的一侧，准直结构26至少覆盖感光区A2；准直结构26包括：孔径层261，孔径层261包括：呈阵列排布的多个透光孔261a。透光孔261a可起到对光线进行准直的作用。
在一些实施例中，一个光电传感器20对应多个透光孔261a，一个透光孔261a对应一个光电传感器20。进一步地，每个光电传感器20所对应的透光孔261a的数量相同；一个光电传感器20所对应的透光孔261a数量包括：4～100个。其中，光电传感器20所对应的透光孔261a的数量具体是指位于该光电传感器20内感光图形18所处区域内的透光孔261a数量。光电传感器20接收的光信号强度与该光电传感器20所对应的透光孔261a数量相关。一般而言，对应的透光孔261a数量越多，则光电传感器20接收的光信号强度越强，光电传感器20输出的电信号的电流大小越大，越有利于进行电信号检测。与此同时，当透光孔261a数量过多时，相邻透光孔261a之间的间距减小，出现光线串扰的风险越大，基于信号检测难度以及光线串扰风险因素的考虑，本公开实施例中 透光孔261a数量为4～100个；原则上，每个光电传感器20对应至少一个透光孔261a即可。另外，通过将各光电传感器20所对应的透光孔261a数量相同，有助于避免透光孔261a数量差异干扰到成像质量。
对应同一光电传感器20的多个透光孔261a在该光电传感器20内感光图形18所处区域内均匀分布。作为一个示例，参见图9c所示，对应同一光电传感器20的多个透光孔261a在行方向和列方向上呈矩阵排布，且在行方向上相邻或在列方向上相邻的两个透光孔261a之间距离相等。作为又一个示例，参见图9d所示，对应同一光电传感器20的多个透光孔261a呈六角排布，任意相邻的两个透光孔261a之间距离。当然，本公开实施例中的透光孔261a还可以采用其他排布方式，本公开不再一一举例描述。
参见图9b所示，在一些实施例中，准直结构26还包括：位于孔径层261远离基底1一侧且沿远离基底1方向依次层叠设置的介质透光层262、透镜层263和平坦透光层264；透镜层263包括与透光孔261a一一对应的多个凸透镜263a，凸透镜263a的光轴经过对应的透光孔261a。
进一步地，凸透镜为263a平凸透镜，平凸透镜263a的平面表面朝向介质透光层262且与介质透光层262的表面贴合，平凸透镜263a的凸面表面朝向平坦透光层264且与平坦透光层264的表面相贴合。
在本公开实施例中，凸透镜263a能够对经纹路反射的光线的传播方向进行调制，减小部分光线的倾斜角度，使得所形成的会聚光束的传播方向集中。孔径层261仅允许特定角度的会聚光束通过，对凸透镜输出的会聚光束进行准直处理，提高传感器接收的会聚光束的方向一致性。其中，孔径层261的透光孔261a与凸透镜263a一一对应，保证每个凸透镜263a汇聚的光线通过同样大小的小孔，进行相同准直，减小信号间的差异性。
需要说明的是，准直结构26可以通过光学OCA胶与光电传感结构2 贴合固定，或者通过薄膜沉积、薄膜图案化等工艺直接制备于光电传感结构2之上，该两种情况均属于本公开的保护范围。
图10为本公开实施例提供的纹路识别模组在纹路识别区域的再一种截面示意图，如图10所示，在一些实施例中，纹路识别模块还包括：非可见光滤光层27。其中，非可见光滤光层27位于光电传感器20远离基底1的一侧，配置为滤除透过光线中的非可见光线。
在一些实施例中，非可见光滤光层27为红外滤光层，配置为滤除透过光线中的红外光线。在强环境光下，透过手指的光绝大部分为红外光(波长范围在760nm～1mm)，而显示面板28射出经由指纹表面反射后形成的检测光为可见光(波长范围在400nm～700nm)。在本公开实施例中，红外滤光层配置为阻挡红外光线且能够使得可见光透过，以使得经过手指反射的检测光能够通过但透过手指的红外光无法通过，从而能减小环境光信号对光电传感器20的影响，提升产品的抗强光性能。
在一些实施例中，红外滤光层包括：具有红外吸收功能的红外吸收层或者具有红外反射功能的红外反射层。其中，当红外滤光层为具有红外吸收功能的红外吸收层时，红外滤光层可由具有红外滤光功能的材料构成；当红外滤光层为具有红外反射功能的红外反射层时，红外反射层可由具有红外反射功能的材料构成或者由具有不同介电常数的材料叠层构成。
在一些实施例中，在纹路识别模组包括准直结构26时，非可见光滤光层27位于准直结构26与光电传感器20之间或者非可见光滤光层27集成于准直结构26内。
参见图10所示，非可见光滤光层27作为一个独立的结构而设置在准直结构26与光电传感器20之间。
非可见光滤光层27可以通过光学OCA胶贴附在光电传感结构2之上，或者是采用镀膜工艺直接形成于光电传感结构2表面，该两种情况 均属于本公开的保护范围。
图11为本公开实施例中非可见光滤光层填充于透光孔内的示意图，如图11所示，当非可见光滤光层27集成于准直结构26内时，作为一个示例，非可见光滤光层27填充于透光孔261a内。
继续参见图9b所示，作为又一个示例，在准直结构26包括介质透光层、透镜层263和平坦透光层264时，介质透光层和平坦透光层264中的至少一者的材料为具有非可见光吸收(例如吸收红外光)功能的有机材料且复用作非可见光滤光层27。
在一些实施例中，基底1为柔性基底1，在基底1与光电传感结构2之间设置有第三绝缘层(未示出)。在PI柔性基底1上制备光电传感结构2之前，先在基底1上形成具有一定厚度的第三绝缘层，第三绝缘层的材料包括SiNx和SiO2，可以起到阻隔水氧，防止剥离后水氧从PI柔性基底1的背面渗透而损害器件和光学膜，并利于后续膜层的沉积；另一方面可以通过调节SiNx的工艺条件或者SiNx/SiO2配比，改变膜层应力，可以跟后续膜层应力相抵消，避免应力累计，防止柔性器件剥离之后应力过大、自发卷曲导致膜层断裂。
需要说明的是，上述各实施例中不同技术特征之间可以相互组合，通过技术特征组合方式所得到的纹路识别模组的技术方案，也属于本公开的保护范围。
基于同一发明构思，本公开实施例还提供了一种显示装置。图12为本公开实施例提供的显示装置的一种结构示意图，如图12所示，该显示装置包括：纹路识别模组以及显示面板28，其中纹路识别模组可采用前面任一实施例所提供的纹路识别模组100，显示面板28位于第一遮光图形3远离基底1的一侧。
在一些实施例中，显示面板28可以为有机发光二极管(Organic Light Emitting Diode，OLED)显示面板28或者量子点发光二极管 (Quantum Dot Light Emitting Diodes，QLED)显示面板28等，本公开的实施例对此不作具体限定。OLED显示面板28例如可以为柔性OLED显示面板28。例如，OLED显示面板28以及QLED显示面板28具有自发光特性，并且其显示像素单元的发光还可以根据需要进行控制或调制，从而可以为纹路采集提供便利，而且有助于提高装置的集成度。
OLED显示面板28一般包括沿远离所述纹路识别模组100的方向依次层叠设置的柔性OLED显示背板281、偏光片282和保护盖板283，保护盖板283的材料可以为聚酰亚胺PI。柔性OLED显示背板281的衬底为柔性衬底，具体材料可以是PI或其它柔性材料。
在一些实施例中，显示面板28与纹路识别模组100之间通过光学胶固定。在另一些实施例中，显示面板28与纹路识别模组100间隔设置。后面将结合具体情况进行详细描述。
图13为本公开实施例提供的显示装置的另一种结构示意图，如图13所示，在一些实施例中，显示装置还包括：中框400，中框400包括底板401和底板401的边缘朝正面一侧弯折所形成的侧壁402，底板401和侧壁402形成容纳槽，纹路识别模组100和显示面板28固定于容纳槽内，显示面板28位于纹路识别模组100远离底板401的一侧。
参见图13所示，纹路识别模组100固定于底板401上，显示面板28与纹路识别模组100之间通过光学胶固定，从而实现显示面板28、纹路识别模组100、中框400三者的固定。
图14为本公开实施例提供的显示装置的又一种结构示意图，如图14所示，与图13中所示情况不同的是，图14所示情况中显示面板28与纹路识别模组100之间通过光学胶固定，侧壁402上形成有台阶状支撑结构404，显示面板28固定于台阶状支撑结构404上，也可实现显示面板28、纹路识别模组100、中框400三者的固定。
图15为本公开实施例提供的显示装置的再一种结构示意图，如图 15所示，与图13和图14中所示情况不同的是，图15所示情况中，显示面板28与纹路识别模组100间隔设置，二者之间存在空气间隔层29。此时，纹路识别模组100固定于底板401上且显示面板28固定于台阶状支撑结构404上。
在一些实施例中，显示面板28与纹路识别模组100之间的最小间隔大于或等于100um。
显示面板28与纹路识别模组100距离太近会造成电磁耦合，增加纹路识别模组100内光电传感器20噪声，导致最终成像质量不佳；并且，显示面板28内的显示用像素单元与纹路识别模组100内纹路识别用像素单元之间会形成摩尔纹，影响后续图像处理及纹路识别。在本公开实施例中，通过将显示面板28与纹路识别模组100间隔设置，以增大显示面板28与纹路识别模组100之间距离，降低二者之间的耦合噪声以及避免摩尔纹的问题，有利于提升纹路成像质量。
图16为图13至图15中底板背面的一种俯视示意图，如图16所示，在一些实施例中，底板401上形成有贯穿孔403，显示装置还包括：纹路识别用柔性线路板501和纹路识别用芯片502；纹路识别用柔性线路板501穿过贯穿孔403，其一端与纹路识别模组100内位于绑定区域的绑定电极电连接(一般通过绑定工艺实现电连接)，另一端与位于底板401背面的纹路识别用芯片502电连接(一般通过固晶薄膜工艺实现电连接)。同样地，显示用芯片(未示出)和显示用柔性线路板也可以相同的方式与位于容纳槽内的显示面板28电连接。
图17为本公开实施例提供的显示装置的再一种结构示意图，如图17所示，与图13至图15中所示情况不同，在图17所示情况中，纹路识别用柔性线路板501的一端与纹路识别模组100内位于周边区域的纹路识别用绑定电极电连接，纹路识别用柔性线路板501的另一端与纹路识别用芯片电连接，且纹路识别用柔性线路板501和纹路识别用芯片502 均位于容纳槽内。
在一些实施例中，显示面板28还具有封装层、触控层等功能层，这些功能层可以参考相关技术，在此不再赘述。
本实施例提供的显示装置可以为手机、平板电脑、显示器、笔记本电脑等任何具有纹路识别功能的产品或部件，本公开的实施例对此不作具体限定。
基于同一发明沟通，本公开实施例还提供了一种纹路识别模组的制备方法，可用于制备前面任一实施例提供的纹路识别模组。图18为本公开实施例提供的纹路识别模组的一种制备方法流程图，如图18所示，该纹路识别模组的制备方法包括：
步骤S1、提供一基底。
其中，基底可以为玻璃基底或PI柔性基底。
当基底为柔性基底时，首先应清洗玻璃基板并烘干表面水汽，除去表面污渍；然后，将液态PI涂布在玻璃上，或者将PI膜材通过硅烷偶联剂直接热压在玻璃表面。
在步骤S1结束且在步骤S2开始之前，还可以在洁净的PI表面沉积一定厚度SiNx或者SiNx+SiO2，以作为第三绝缘层，用于防止剥离后水氧从PI背面渗透，损害器件和光学膜，并有利于后续膜层的沉积；另一方面可以通过调节SiNx的工艺条件或者SiNx/SiO2配比，改变膜层应力，可以跟后续膜层应力相抵消，避免应力累计，防止柔性器件剥离之后应力过大，自发卷曲导致膜层断裂。
其中，基底上划分有纹路识别区域和位于纹路识别区域周边的周边区域，纹路识别区域包括：感光区。
步骤S2、在基底上形成光电传感结构。
其中，光电传感结构位于基底之上且在纹路识别区域内，包括：多条栅线、多条信号感测线以及由多条栅线和多条信号感测线限定出的多 个像素单元；其中，像素单元包括：薄膜晶体管，薄膜晶体管的栅极与对应的栅线电连接，薄膜晶体管的第一电极与对应的信号感测线电连接；纹路识别区域包括：感光区，位于感光区内的像素单元还包括：光电传感器，光电传感器包括沿远离基底方向依次层叠设置的第三电极、感光图形和第四电极，第三电极与位于同一像素单元的薄膜晶体管的第二电极连接；光电传感器与所对应的像素单元的面积比为40％～90％。
在一些实施例中，在形成光电传感结构之后，还可包括形成偏置走线(第一/第二遮光图形)、准直结构、红外滤光层等结构步骤，对于光电传感结构、偏置走线准直结构、红外滤光层等结构的具体制备工序，可参见前面实施例中相应内容，此处不再赘述。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (41)

  1. 一种纹路识别模组，包括：
    基底，包括纹路识别区域和位于所述纹路识别区域周边的周边区域；
    光电传感结构，位于所述基底之上且在所述纹路识别区域内，包括：多条栅线、多条信号感测线、以及由多条栅线和多条信号感测线交叉限定出的多个像素单元，其中，所述像素单元包括：薄膜晶体管，所述薄膜晶体管的栅极与对应的栅线电连接，所述薄膜晶体管的第一电极与对应的信号感测线电连接；
    其中，所述纹路识别区域包括：感光区，位于所述感光区内的像素单元还包括：光电传感器，所述光电传感器包括沿远离所述基底方向依次层叠设置的第三电极、感光图形和第四电极，所述第三电极与位于同一所述像素单元的所述薄膜晶体管的第二电极连接；
    所述光电传感器与所对应的像素单元的面积比为40％～90％。
  2. 根据权利要求1所述的纹路识别模组，其中，所述薄膜晶体管的沟道区域呈倒L型或弧形。
  3. 根据权利要求1或2所述的纹路识别模组，其中，所述光电传感器在所述基底上的正投影与所述薄膜晶体管的有源层在所述基底上的正投影不交叠。
  4. 根据权利要求1～3中任一所述的纹路识别模组，其中，所述栅线沿第一方向延伸，所述信号感测线沿第二方向延伸，所述第一方向与所述第二方向垂直；
    所述薄膜晶体管包括：栅极、有源层、第一电极和第二电极，所述 第一电极在与所述基底所处平面相平行的截面的形状为矩形，所述第一电极具有在所述第一方向上相对设置的第一侧边和第二侧边以及在所述第二方向上相对设置的第三侧边和第四侧边，所述第一电极与位于自身的第一侧边最近的所述信号感测线电连接，所述栅极与位于所述第一电极的所述第三侧边最近的所述栅线电连接；
    所述第二电极包括：第一导电部和第二导电部，所述第一导电部沿第一方向延伸且与所述第一电极的第二侧边相对设置，所述第二导电部沿第二方向延伸且与所述第一电极的第四侧边相对设置，所述第一导电部与所述第二导电部电连接。
  5. 根据权利要求4所述的纹路识别模组，其中，所述第二电极还包括：第三导电部，所述第一导电部、所述第二导电部和所述第三导电部三者同层设置，第三导电部的延伸方向与所述第一方向和所述第二方向均相交，所述第三导电部的两端分别与所述第一导电部和所述第二导电部连接。
  6. 根据权利要求1～5中任一所述的纹路识别模组，其中，所述纹路识别区域还包括：位于所述感光区外围的虚拟区，位于所述虚拟区内的像素单元配置为向对应的所述信号感测线输出参考噪声信号。
  7. 根据权利要求6所述的纹路识别模组，其中，所述感光图形背向所述基底的一侧依次设置有平坦化层和钝化层，所述第四电极位于所述钝化层背向所述基底的一侧且通过所述平坦化层和钝化层上的过孔与对应的感光图形电连接；
    位于所述虚拟区内的像素单元还包括：第五电极和第六电极，所述第五电极与位于所述虚拟区的薄膜晶体管的第二电极电连接，所述第五 电极与所述第六电极之间包括所述平坦化层和所述钝化层。
  8. 根据权利要求6所述的纹路识别模组，其中，所述薄膜晶体管远离所述基底的一侧形成有第一绝缘层，位于所述感光区的光电传感器通过所述第一绝缘层上的过孔与所述薄膜晶体管的第二电极连接；
    所述感光图形背向所述基底的一侧依次设置有平坦化层和钝化层，所述第四电极位于所述钝化层背向所述基底的一侧且通过所述平坦化层和钝化层上的过孔与对应的感光图形电连接；
    位于所述虚拟区内的像素单元还包括：第五电极和第六电极，所述第五电极与位于所述虚拟区的薄膜晶体管的第二电极电连接，所述第五电极与所述第三电极同层同材料设置，所述第六电极与所述第四电极同层同材料设置，所述第五电极与所述第六电极之间包括所述第一绝缘层、所述平坦化层和所述钝化层。
  9. 根据权利要求6所述的纹路识别模组，其中，位于所述虚拟区内的像素单元还包括：传感器对照结构，所述传感器对照结构包括：沿远离所述基底方向依次层叠设置的第五电极、对照图形和第六电极，所述第五电极与位于所述虚拟区的薄膜晶体管的第二电极电连接，所述第五电极与所述第三电极同层同材料设置，所述第六电极与所述第四电极同层同材料设置；
    所述对照图形的材料为非光电材料且介电常数与所述感光图形的介电常数大致相同。
  10. 根据权利要求7～9所述的纹路识别模组，其中，还包括：第一遮光图形，位于所述第六电极远离所述基底的一侧，所述第一遮光图形在所述基底上的正投影完全覆盖所述虚拟区且未覆盖所述感光区。
  11. 根据权利要求6～10中任一所述的纹路识别模组，其中，所述虚拟区位于所述感光区的一侧。
  12. 根据权利要求6～10中任一所述的纹路识别模组，其中，所述虚拟区位于所述感光区的相对两侧或相交两侧。
  13. 根据权利要求6～10中任一所述的纹路识别模组，其中，所述虚拟区位于所述感光区的四侧。
  14. 根据权利要求6～13中任一所述的纹路识别模组，其中，位于所述感光区内的像素单元所包含的所述薄膜晶体管，与位于所述虚拟区内的像素单元所包含的所述薄膜晶体管，二者结构、形状、大小均相同。
  15. 根据权利要求1～14中任一所述的纹路识别模组，其中，还包括：
    准直结构，位于所述光电传感结构远离基底的一侧，至少覆盖所述感光区；
    所述准直结构包括：孔径层，所述孔径层包括：呈阵列排布的多个透光孔。
  16. 根据权利要求15所述的纹路识别模块，其中，所述准直结构还包括：位于所述孔径层远离所述基底一侧且沿远离所述基底方向依次层叠设置的介质透光层、透镜层和平坦透光层；
    所述透镜层包括与所述透光孔一一对应的多个凸透镜，所述凸透镜的光轴经过对应的透光孔。
  17. 根据权利要求16所述的纹路识别模块，其中，所述凸透镜为平凸透镜，所述平凸透镜的平面表面朝向所述介质透光层且与所述介质透光层的表面贴合，所述平凸透镜的凸面表面朝向所述平坦透光层且与所述平坦透光层的表面相贴合。
  18. 根据权利要求15所述的纹路识别模块，其中，一个所述光电传感器对应多个所述透光孔，一个所述透光孔对应一个所述光电传感器。
  19. 根据权利要求18所述的纹路识别模块，其中，每个所述光电传感器所对应的所述透光孔的数量相同；
    一个所述光电传感器所对应的透光孔数量包括：4～100个。
  20. 根据权利要求15所述的纹路识别模块，其中，还包括：
    非可见光滤光层，位于所述光电传感器远离所述基底的一侧，配置为滤除透过光线中的非可见光线。
  21. 根据权利要求20所述的纹路识别模块，其中，所述非可见光滤光层包括：红外滤光层，配置为滤除透过光线中的红外光线。
  22. 根据权利要求20所述的纹路识别模块，其中，所述红外滤光层包括：具有红外吸收功能的红外吸收层或者具有红外反射功能的红外反射层。
  23. 根据权利要求20～22中任一所述的纹路识别模块，其中，所述非可见光滤光层位于所述准直结构与所述光电传感器之间。
  24. 根据权利要求20～22中任一所述的纹路识别模块，其中，所述非可见光滤光层集成于所述准直结构内。
  25. 根据权利要求24所述的纹路识别模块，其中，所述非可见光滤光层填充于所述透光孔内。
  26. 根据权利要求24所述的纹路识别模块，其中，所述准直结构包括：沿远离所述基底方向依次层叠设置的所述孔径层、介质透光层、透镜层和平坦透光层，所述透镜层包括与所述透光孔一一对应的多个凸透镜，所述凸透镜的光轴经过对应的透光孔；
    所述介质透光层和所述平坦透光层中的至少一者复用作所述非可见光滤光层。
  27. 根据权利要求1～26中任一所述的纹路识别模块，其中，所述光电传感结构包括：沿远离所述基底的方向依次层叠设置的栅极、栅绝缘层、有源层、第一导电电极层、第一绝缘层、感光图形、平坦化层、钝化层和第二导电电极层，所述第一遮光图形位于所述第二导电电极层远离所述基底的一侧；
    所述第一导电电极层包括：所述第一电极、所述第二电极和所述第三电极，所述第二导电电极层包括：所述第四电极。
  28. 根据权利要求27所述的纹路识别模块，其中，所述第四电极远离所述基底的一侧设置有第二绝缘层，在所述第二绝缘层远离所述基底的一侧且位于所述周边区域设置有偏置走线，所述第四电极延伸至所述周边区域并通过所述第二绝缘层上的过孔与所述偏置走线电连接。
  29. 根据权利要求28所述的纹路识别模块，其中，偏置走线的材料包括金属材料，所述第一遮光图形与所述偏置走线同层同材料设置。
  30. 根据权利要求29所述的纹路识别模块，其中，还包括：第二遮光图形，所述第二遮光图形与所述偏置走线同层同材料设置；
    所述第二遮光图形在所述基底上的正投影完全覆盖所述薄膜晶体管内有源层的沟道区部分在所述基底上的正投影。
  31. 根据权利要求30所述的纹路识别模块，其中，还包括：位于所述第二遮光图形远离所述基底的一侧的阻隔层以及位于所述阻隔层远离所述基底一侧的接地屏蔽层，所述接地屏蔽层在所述基底上的正投影完全覆盖所述纹路识别区域。
  32. 根据权利要求31所述的纹路识别模块，其中，所述接地屏蔽层通过所述阻隔层上的过孔与所述第一遮光图形、所述第二遮光图形电连接。
  33. 根据权利要求1～32中任一所述的纹路识别模块，其中，所述基底为柔性基底，所述基底与所述光电传感结构之间设置有第三绝缘层。
  34. 一种显示装置，其中，包括：如权利要求1～33中任一所述的纹路识别模组，以及位于第一遮光图形远离所述基底一侧的显示面板。
  35. 根据权利要求34所述的显示装置，其中，所述显示面板与所述纹路识别模组之间通过光学胶固定；
    或者，所述显示面板与所述纹路识别模组间隔设置。
  36. 根据权利要求34或35所述的显示装置，其中，所述显示面板为OLED显示面板，所述OLED显示面板包括沿远离所述纹路识别模组的方向依次层叠设置的OLED显示背板、偏光片和保护盖板，所述保护盖板的材料包括聚酰亚胺。
  37. 根据权利要求34～36中任一所述的显示装置，其中，还包括：
    中框，包括底板和所述底板的边缘朝正面一侧弯折所形成的侧壁，所述底板和所述侧壁形成容纳槽，所述纹路识别模组和所述显示面板固定于所述容纳槽内，所述显示面板位于所述纹路识别模组远离所述底板的一侧。
  38. 根据权利要求37所述的显示装置，其中，所述纹路识别模组固定于所述底板上。
  39. 根据权利要求37或38所述的显示装置，其中，所述侧壁上形成有台阶状支撑结构，所述显示面板固定于所述台阶状支撑结构上。
  40. 根据权利要求37所述的显示装置，其中，所述底板上形成有贯穿孔，所述显示装置还包括：纹路识别用柔性线路板和纹路识别用芯片；
    纹路识别用柔性线路板穿过所述贯穿孔，其一端与纹路识别模组内位于周边区域的纹路识别用绑定电极电连接，另一端与位于所述底板背面的纹路识别用芯片电连接。
  41. 根据权利要求37所述的显示装置，其中，所述显示装置还包括： 纹路识别用柔性线路板和纹路识别用芯片，纹路识别用柔性线路板的一端与纹路识别模组内位于周边区域的纹路识别用绑定电极电连接，纹路识别用柔性线路板的另一端与所述纹路识别用芯片电连接；
    所述纹路识别用柔性线路板和纹路识别用芯片均位于所述容纳槽内。
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