WO2022104658A1 - Solid state imaging device - Google Patents

Solid state imaging device Download PDF

Info

Publication number
WO2022104658A1
WO2022104658A1 PCT/CN2020/130203 CN2020130203W WO2022104658A1 WO 2022104658 A1 WO2022104658 A1 WO 2022104658A1 CN 2020130203 W CN2020130203 W CN 2020130203W WO 2022104658 A1 WO2022104658 A1 WO 2022104658A1
Authority
WO
WIPO (PCT)
Prior art keywords
pixel
isolation region
transistors
imaging device
solid state
Prior art date
Application number
PCT/CN2020/130203
Other languages
French (fr)
Inventor
Takahashi Seiji
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to CN202080106038.0A priority Critical patent/CN116325780A/en
Priority to PCT/CN2020/130203 priority patent/WO2022104658A1/en
Publication of WO2022104658A1 publication Critical patent/WO2022104658A1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1463—Pixel isolation structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers

Definitions

  • the present application relates to a solid state imaging device.
  • a solid state imaging device may be used to convert light information into an electric signal.
  • the solid state imaging device comprises a plurality of pixels which are arranged in the form of a matrix. In order to isolate each pixel, pixel-to-pixel isolation regions may be provided.
  • the pixel-to-pixel isolation regions may be formed in two processes. That is, after a first pixel-to-pixel isolation region is formed in a first process, a second pixel-to-pixel isolation region is formed in a second process at the half pitch shifted position. Thereby, the pixel-to-pixel isolation regions may be formed by half pitch of the photomask.
  • a solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions.
  • the solid state imaging device includes: a first pixel-to-pixel isolation region formed in a first process; and a second pixel-to-pixel isolation region formed in a second process which differs from the first process.
  • Each unit pixel comprises: one or more light sensing areas; and one or more signal readout circuit areas.
  • Each light sensing area includes: one or more photodiodes; one or more transfer transistors; and a part of floating diffusion.
  • the signal readout circuit areas include a plurality of in-pixel transistors.
  • each unit pixel the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors.
  • Each photodiode and each transfer transistor are arranged in a section isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. Intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region are arranged in positions which differ from the floating diffusion and channel regions of the in-pixel transistors.
  • the signal readout circuit areas include one or more p-well pick-ups.
  • the plurality of in-pixel transistors comprise a reset transistor, a source follower transistor, and a row-select transistor.
  • One or more intersection regions are arranged in the same positions as the p-well pick-ups.
  • the signal readout circuit areas are arranged along row and column directions.
  • the signal readout circuit areas are arranged on a boundary of each unit pixel and between the light sensing areas.
  • a solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions.
  • the solid state imaging device includes: a first pixel-to-pixel isolation region formed in a first process; and a second pixel-to-pixel isolation region formed in a second process which differs from the first process.
  • Each unit pixel comprises: one or more light sensing areas; and one or more signal readout circuit areas.
  • Each light sensing area includes: one or more photodiodes; one or more transfer transistors; and a part of floating diffusion.
  • the signal readout circuit areas include a plurality of in-pixel transistors.
  • the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors.
  • Each photodiode and each transfer transistor are arranged in a section isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region.
  • Intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region are arranged in positions which differ from the floating diffusion. When the intersection regions are overlapped with channel regions of the in-pixel transistors, length of the overlapped regions is less than half length of the intersection regions.
  • FIG. 1 shows an exemplary block diagram of an imaging system.
  • FIG. 2 shows an exemplary circuit diagram of an imaging device.
  • FIG. 3 shows a layout of elements in one unit pixel of a solid state imaging device according to a first embodiment of the present application.
  • FIG. 4 shows how to form pixel-to-pixel isolation regions.
  • FIG. 5 shows a layout of elements in one unit pixel of a solid state imaging device according to a second embodiment of the present application.
  • FIG. 6 shows a layout of elements in one unit pixel of a solid state imaging device according to a third embodiment of the present application.
  • FIG. 7 shows a layout of elements in one unit pixel of a solid state imaging device according to a fourth embodiment of the present application.
  • FIG. 8 shows a layout of elements in one unit pixel of a solid state imaging device according to a fifth embodiment of the present application.
  • FIG. 9 shows allowable length of an overlapped region when an intersection region of pixel-to-pixel isolation regions is overlapped with a channel region of an in-pixel transistor.
  • FIG. 10A shows position of the cross section AA’ in a plan view of the imaging device.
  • FIG. 10B shows a cross-sectional view of the imaging device.
  • FIG. 11 shows another exemplary block diagram of an imaging system.
  • FIG. 12 shows various applications for a camera system.
  • a plurality of pixels are arranged in the form of a matrix on a substrate.
  • FIG. 1 shows an exemplary block diagram of an imaging system 101.
  • the imaging system 101 comprises a pixel array 109, a control circuit 105, a readout circuit 110, and a signal processing circuit 106.
  • a pixel array 109 a plurality of pixels are arranged in the form of a matrix on a substrate.
  • the control circuit 105 controls the pixel array 109, and the readout circuit 110 reads out image data.
  • the signal processing circuit 106 processes the image data read out by the readout circuit 110.
  • FIG. 2 shows an exemplary circuit diagram of an imaging device.
  • the imaging device comprises four photodiodes PD1 to PD4, four transfer transistors TX1 to TX4, a floating diffusion FD, a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL.
  • the reset transistor RST is turned on in response to a reset signal, and resets charge accumulated in the floating diffusion FD.
  • the photodiodes PD1 to PD4 generate charge corresponding to the amount of incident light by photoelectric conversion, and accumulate the generated charge.
  • One of the transfer transistors TX1 to TX4 is turned on in response to a transfer signal, and transfers charge accumulated in one of the photodiodes PD1 to PD4 to the floating diffusion FD.
  • Voltage of the floating diffusion FD is determined by the transferred charge. This voltage is applied to a gate of the source follower transistor SF.
  • the source follower transistor SF sends a pixel signal corresponding to the voltage of the floating diffusion FD to the row-select transistor SEL.
  • the row-select transistor SEL outputs Vout as the pixel signal in response to a row-select signal.
  • FIG. 3 shows a layout of elements in one unit pixel of a solid state imaging device according to a first embodiment of the present application.
  • One unit pixel comprises four light sensing areas, and one signal readout circuit area.
  • four light sensing areas include two green light sensing areas, one blue light sensing area, and one red light sensing area.
  • Each light sensing area includes one photodiode PD, one transfer transistor TX, and a part of a floating diffusion FD.
  • the signal readout circuit area includes one p-well pick-up PW, and three in-pixel transistors. If the photodiode is n-type, isolation regions and a well pick-up should be p-type.
  • isolation regions and a well pick-up should be n-type.
  • Three in-pixel transistors comprise a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL.
  • the number of elements included in the signal readout circuit area is not limited to the aforementioned number.
  • photodiodes PD are connected to four transfer transistors TX, respectively.
  • the four transfer transistors TX are connected to a floating diffusion FD.
  • the signal readout circuit area is arranged on a boundary of the unit pixel under the light sensing areas.
  • the floating diffusion FD and signal readout circuit are shared by four photodiodes PD and four transfer transistors TX.
  • Each light sensing area is isolated by pixel-to-pixel isolation regions.
  • the pixel-to-pixel isolation regions are formed in a grid shape so as to surround each light sensing area.
  • the pixel-to-pixel isolation regions prevent signal charges in a light sensing area to leak into an adjacent light sensing area.
  • the floating diffusion or the in-pixel transistors are formed between a light sensing area and an adjacent light sensing area, the pixel-to-pixel isolation regions are overlapped with these elements.
  • Depth of the pixel-to-pixel isolation region is deeper than the floating diffusion or in-pixel transistor regions. However, when the deep pixel-to-pixel isolation region is formed by a high energy ion implantation, well proximity effect occurs, and high dose region is formed near silicon surface.
  • FIG. 4 shows how to form the pixel-to-pixel isolation regions.
  • the pixel-to-pixel isolation regions are formed in two processes. That is, after a first pixel-to-pixel isolation region (1st DPW) is formed in a first process, a second pixel-to-pixel isolation region (2nd DPW) is formed in a second process at the position which is diagonally shifted by a half mask pitch. Thereby, the pixel-to-pixel isolation regions may be formed by half pitch of the photomask.
  • doses are implanted two times at intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. This influences performance of the floating diffusion and the in-pixel transistors.
  • intersection regions of the pixel-to-pixel isolation regions are not placed on the floating diffusion and channel regions of the in-pixel transistors.
  • the intersection regions may be placed on the p-well pick-up PW.
  • FIG. 5 shows a layout of elements in one unit pixel of a solid state imaging device according to a second embodiment of the present application.
  • the signal readout circuit area is arranged on boundaries of the unit pixel under the light sensing areas and on the right side of the light sensing areas.
  • the signal readout circuit area includes one p-well pick-up PW, and four in-pixel transistors.
  • Four in-pixel transistors comprise a dual conversion gain transistor DCG, a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL.
  • another reset transistor RST may be arranged.
  • the dual conversion gain transistor DCG and the reset transistor RST are arranged on a boundary of the unit pixel on the right side of the light sensing areas. The remainder of the constitution is the same as the first embodiment.
  • FIG. 6 shows a layout of elements in one unit pixel of a solid state imaging device according to a third embodiment of the present application.
  • the signal readout circuit area is arranged on boundaries of the unit pixel under the light sensing areas and on the right side of the light sensing areas.
  • the signal readout circuit area includes one p-well pick-up PW, and three in-pixel transistors. Three in-pixel transistors comprise a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL.
  • the p-well pick-up PW is arranged on a boundary of the unit pixel on the right side of the light sensing areas. The remainder of the constitution is the same as the first embodiment.
  • FIG. 7 shows a layout of elements in one unit pixel of a solid state imaging device according to a fourth embodiment of the present application.
  • One unit pixel comprises eight light sensing areas, and two signal readout circuit areas.
  • eight light sensing areas include four green light sensing areas, two blue light sensing areas, and two red light sensing areas.
  • Each light sensing area includes one photodiode PD, one transfer transistor TX, and a part of floating diffusion FD.
  • Two signal readout circuit areas are arranged between upper four light sensing areas and lower four light sensing areas, and on a boundary of the unit pixel under the light sensing areas.
  • the signal readout circuit area between the light sensing areas includes one p-well pick-up PW, and two in-pixel transistors.
  • These two in-pixel transistors comprise a row-select transistor SEL, and a source follower transistor SF.
  • the signal readout circuit area under the light sensing areas also includes one p-well pick-up PW, and two in-pixel transistors.
  • These two in-pixel transistors comprise a dual conversion gain transistor DCG, and a reset transistor RST. Instead of the dual conversion gain transistor DCG, another reset transistor RST may be arranged.
  • eight photodiodes PD are connected to eight transfer transistors TX, respectively.
  • the eight transfer transistors TX are connected to floating diffusion FD.
  • the floating diffusion FD and signal readout circuit are shared by eight photodiodes PD and eight transfer transistors TX.
  • FIG. 8 shows a layout of elements in one unit pixel of a solid state imaging device according to a fifth embodiment of the present application.
  • two p-well pick-ups PW are arranged on a boundary of the unit pixel on the right side of the light sensing areas.
  • the remainder of the constitution is the same as the fourth embodiment.
  • FIG. 9 shows an allowable length of an overlapped region when an intersection region of pixel-to-pixel isolation regions is overlapped with a channel region of an in-pixel transistor. That is, A ⁇ B/2 is allowable, where B is length of the intersection region, and A is length of the region where the intersection region is overlapped with the channel region of the in-pixel transistor. Such an arrangement reduces influence of the intersection region on the in-pixel transistor.
  • FIG. 10A shows position of the cross section AA’ in a plan view of the imaging device
  • FIG. 10B shows a cross-sectional view of the imaging device.
  • BEOL back end of line
  • metallic interconnections 316 are formed. Namely, a thick insulation file is formed, contact holes are formed, and a metallic film is deposited and patterned. Then, the imaging device placed on the substrate is connected to a logic circuit 312 placed on another substrate by bonding such as copper to copper bonding or other inter-silicon wafer connections.
  • DTIs deep trench isolations
  • Color filters 305 are provided within a layer at the position corresponding to the photodiodes 308.
  • Microlens 306 are provided at the position corresponding to the photodiodes 308.
  • 301 is a floating diffusion
  • 302 is a 1st DPW
  • 303 is a 2nd DPW
  • 307 is a well contact
  • 308 is an isolation STI or doping isolation
  • 314 is a transfer gate transistor.
  • FIG. 11 shows another exemplary block diagram of an imaging system 201.
  • the imaging system 201 includes an optical system 202 such as one or more lens, a shutter device 203, a solid-state image sensor 204, a control circuit 205, a signal processing circuit 206, a monitor 207, and a memory 208.
  • the solid-state image sensor 204 includes, for example, the pixel array 109 and the readout circuit 110 in FIG. 1, and obtains image data of a subject through the lens 202 and the shutter device 203, under the control of the control circuit 205.
  • the signal processing circuit 206 outputs the obtained image data to the monitor 207 or stores the image data in the memory 208.
  • the control circuit 205 and the signal processing circuit 206 in FIG. 11 correspond to the control circuit 105 and the signal processing circuit 106 in FIG. 1, respectively.
  • FIG. 12 shows various applications for a camera system.
  • the imaging device can be applied to, for example, a mobile phone camera, a digital camera, a network camera, a security and surveillance camera, a video camcorder, an automotive and transport camera, a medical camera, and machine visions.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

A solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions is provided. The solid state imaging device includes: a first pixel-to-pixel isolation region formed in a first process; and a second pixel-to-pixel isolation region formed in a second process which differs from the first process. Each unit pixel comprises: one or more light sensing areas; and one or more signal readout circuit areas. Each light sensing area includes: one or more photodiodes; one or more transfer transistors; and a part of a floating diffusion. The signal readout circuit areas include a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are arranged in a section isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. Intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region are arranged in positions which differ from the floating diffusion and channel regions of the in-pixel transistors.

Description

SOLID STATE IMAGING DEVICE TECHNICAL FIELD
The present application relates to a solid state imaging device.
BACKGROUND
A solid state imaging device may be used to convert light information into an electric signal. The solid state imaging device comprises a plurality of pixels which are arranged in the form of a matrix. In order to isolate each pixel, pixel-to-pixel isolation regions may be provided.
In order to minimize pixel size, it is necessary to minimize pitch of the pixel-to-pixel isolation regions. For this, it is also necessary to minimize pitch of a photomask to form the pixel-to-pixel isolation regions. However, the minimization of pitch of the photomask is limited.
The pixel-to-pixel isolation regions may be formed in two processes. That is, after a first pixel-to-pixel isolation region is formed in a first process, a second pixel-to-pixel isolation region is formed in a second process at the half pitch shifted position. Thereby, the pixel-to-pixel isolation regions may be formed by half pitch of the photomask.
However, in these processes, doses are implanted two times at intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. This influences performance of the device, and would induce fixed pattern noise on an outputted image.
SUMMARY
According to a first aspect of the present application, a solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions is provided. The solid state imaging device includes: a first pixel-to-pixel isolation region formed in a first process; and a second  pixel-to-pixel isolation region formed in a second process which differs from the first process. Each unit pixel comprises: one or more light sensing areas; and one or more signal readout circuit areas. Each light sensing area includes: one or more photodiodes; one or more transfer transistors; and a part of floating diffusion. The signal readout circuit areas include a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are arranged in a section isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. Intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region are arranged in positions which differ from the floating diffusion and channel regions of the in-pixel transistors.
According to a second aspect of the present application, the signal readout circuit areas include one or more p-well pick-ups. The plurality of in-pixel transistors comprise a reset transistor, a source follower transistor, and a row-select transistor. One or more intersection regions are arranged in the same positions as the p-well pick-ups.
According to a third aspect of the present application, the signal readout circuit areas are arranged along row and column directions.
According to a fourth aspect of the present application, the signal readout circuit areas are arranged on a boundary of each unit pixel and between the light sensing areas.
According to a fifth aspect of the present application, a solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions is provided. The solid state imaging device includes: a first pixel-to-pixel isolation region formed in a first process; and a second pixel-to-pixel isolation region formed in a second process which differs from the first process. Each unit pixel comprises: one or more light sensing areas; and one or more signal readout circuit areas. Each light sensing area includes: one or more photodiodes; one or more transfer transistors; and a part of floating diffusion. The signal readout circuit areas include a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are arranged in a section isolated by the first pixel-to-pixel isolation region and the  second pixel-to-pixel isolation region. Intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region are arranged in positions which differ from the floating diffusion. When the intersection regions are overlapped with channel regions of the in-pixel transistors, length of the overlapped regions is less than half length of the intersection regions.
BRIEF DESCRIPTION OF DRAWINGS
FIG. 1 shows an exemplary block diagram of an imaging system.
FIG. 2 shows an exemplary circuit diagram of an imaging device.
FIG. 3 shows a layout of elements in one unit pixel of a solid state imaging device according to a first embodiment of the present application.
FIG. 4 shows how to form pixel-to-pixel isolation regions.
FIG. 5 shows a layout of elements in one unit pixel of a solid state imaging device according to a second embodiment of the present application.
FIG. 6 shows a layout of elements in one unit pixel of a solid state imaging device according to a third embodiment of the present application.
FIG. 7 shows a layout of elements in one unit pixel of a solid state imaging device according to a fourth embodiment of the present application.
FIG. 8 shows a layout of elements in one unit pixel of a solid state imaging device according to a fifth embodiment of the present application.
FIG. 9 shows allowable length of an overlapped region when an intersection region of pixel-to-pixel isolation regions is overlapped with a channel region of an in-pixel transistor.
FIG. 10A shows position of the cross section AA’ in a plan view of the imaging device.
FIG. 10B shows a cross-sectional view of the imaging device.
FIG. 11 shows another exemplary block diagram of an imaging system.
FIG. 12 shows various applications for a camera system.
DESCRIPTION OF EMBODIMENTS
In a solid state imaging device according to the present application, a plurality of pixels are arranged in the form of a matrix on a substrate.
FIG. 1 shows an exemplary block diagram of an imaging system 101. The imaging system 101 comprises a pixel array 109, a control circuit 105, a readout circuit 110, and a signal processing circuit 106. In the pixel array 109, a plurality of pixels are arranged in the form of a matrix on a substrate. The control circuit 105 controls the pixel array 109, and the readout circuit 110 reads out image data. The signal processing circuit 106 processes the image data read out by the readout circuit 110.
FIG. 2 shows an exemplary circuit diagram of an imaging device. The imaging device comprises four photodiodes PD1 to PD4, four transfer transistors TX1 to TX4, a floating diffusion FD, a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL. The reset transistor RST is turned on in response to a reset signal, and resets charge accumulated in the floating diffusion FD. The photodiodes PD1 to PD4 generate charge corresponding to the amount of incident light by photoelectric conversion, and accumulate the generated charge. One of the transfer transistors TX1 to TX4 is turned on in response to a transfer signal, and transfers charge accumulated in one of the photodiodes PD1 to PD4 to the floating diffusion FD. Voltage of the floating diffusion FD is determined by the transferred charge. This voltage is applied to a gate of the source follower transistor SF. The source follower transistor SF sends a pixel signal corresponding to the voltage of the floating diffusion FD to the row-select transistor SEL. The row-select transistor SEL outputs Vout as the pixel signal in response to a row-select signal.
FIG. 3 shows a layout of elements in one unit pixel of a solid state imaging device according to a first embodiment of the present application. One unit pixel comprises four light sensing areas, and one signal readout circuit area. For example, four light sensing areas include two green light sensing areas, one blue light sensing area, and one red light sensing area. Each light sensing area includes one photodiode PD, one transfer transistor TX, and a part of a floating diffusion FD. The signal readout circuit area includes one p-well pick-up PW, and three in-pixel transistors. If the photodiode is n-type, isolation regions and a well pick-up should be p-type. If the photodiode is p-type, isolation regions and a well pick-up should be n-type. Three in-pixel transistors comprise a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL. However, the number of elements included in the signal readout circuit area is not limited to the aforementioned number.
In one unit pixel, four photodiodes PD are connected to four transfer  transistors TX, respectively. The four transfer transistors TX are connected to a floating diffusion FD. The signal readout circuit area is arranged on a boundary of the unit pixel under the light sensing areas. The floating diffusion FD and signal readout circuit are shared by four photodiodes PD and four transfer transistors TX.
Each light sensing area is isolated by pixel-to-pixel isolation regions. The pixel-to-pixel isolation regions are formed in a grid shape so as to surround each light sensing area. The pixel-to-pixel isolation regions prevent signal charges in a light sensing area to leak into an adjacent light sensing area. When the floating diffusion or the in-pixel transistors are formed between a light sensing area and an adjacent light sensing area, the pixel-to-pixel isolation regions are overlapped with these elements. Depth of the pixel-to-pixel isolation region is deeper than the floating diffusion or in-pixel transistor regions. However, when the deep pixel-to-pixel isolation region is formed by a high energy ion implantation, well proximity effect occurs, and high dose region is formed near silicon surface.
FIG. 4 shows how to form the pixel-to-pixel isolation regions. The pixel-to-pixel isolation regions are formed in two processes. That is, after a first pixel-to-pixel isolation region (1st DPW) is formed in a first process, a second pixel-to-pixel isolation region (2nd DPW) is formed in a second process at the position which is diagonally shifted by a half mask pitch. Thereby, the pixel-to-pixel isolation regions may be formed by half pitch of the photomask.
In these processes, doses are implanted two times at intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. This influences performance of the floating diffusion and the in-pixel transistors.
The intersection regions of the pixel-to-pixel isolation regions are not placed on the floating diffusion and channel regions of the in-pixel transistors. The intersection regions may be placed on the p-well pick-up PW. Such an arrangement minimizes dose influences to performance of the floating diffusion and the in-pixel transistors. Thereby, for example, Vth variation of the source follower transistor is suppressed, and fixed pattern noise on outputted image is reduced. Furthermore, random noise of the source follower transistor and reset noise are improved. Moreover, white pixel cluster caused by junction leakage of the floating diffusion is decreased.
FIG. 5 shows a layout of elements in one unit pixel of a solid state imaging device according to a second embodiment of the present application. In the second  embodiment, the signal readout circuit area is arranged on boundaries of the unit pixel under the light sensing areas and on the right side of the light sensing areas. The signal readout circuit area includes one p-well pick-up PW, and four in-pixel transistors. Four in-pixel transistors comprise a dual conversion gain transistor DCG, a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL. Instead of the dual conversion gain transistor DCG, another reset transistor RST may be arranged. The dual conversion gain transistor DCG and the reset transistor RST are arranged on a boundary of the unit pixel on the right side of the light sensing areas. The remainder of the constitution is the same as the first embodiment.
FIG. 6 shows a layout of elements in one unit pixel of a solid state imaging device according to a third embodiment of the present application. In the third embodiment, the signal readout circuit area is arranged on boundaries of the unit pixel under the light sensing areas and on the right side of the light sensing areas. The signal readout circuit area includes one p-well pick-up PW, and three in-pixel transistors. Three in-pixel transistors comprise a reset transistor RST, a source follower transistor SF, and a row-select transistor SEL. The p-well pick-up PW is arranged on a boundary of the unit pixel on the right side of the light sensing areas. The remainder of the constitution is the same as the first embodiment.
FIG. 7 shows a layout of elements in one unit pixel of a solid state imaging device according to a fourth embodiment of the present application. One unit pixel comprises eight light sensing areas, and two signal readout circuit areas. For example, eight light sensing areas include four green light sensing areas, two blue light sensing areas, and two red light sensing areas. Each light sensing area includes one photodiode PD, one transfer transistor TX, and a part of floating diffusion FD. Two signal readout circuit areas are arranged between upper four light sensing areas and lower four light sensing areas, and on a boundary of the unit pixel under the light sensing areas. The signal readout circuit area between the light sensing areas includes one p-well pick-up PW, and two in-pixel transistors. These two in-pixel transistors comprise a row-select transistor SEL, and a source follower transistor SF. The signal readout circuit area under the light sensing areas also includes one p-well pick-up PW, and two in-pixel transistors. These two in-pixel transistors comprise a dual conversion gain transistor DCG, and a reset transistor RST. Instead of the dual conversion gain transistor DCG, another reset transistor RST may be arranged.
In one unit pixel, eight photodiodes PD are connected to eight transfer  transistors TX, respectively. The eight transfer transistors TX are connected to floating diffusion FD. The floating diffusion FD and signal readout circuit are shared by eight photodiodes PD and eight transfer transistors TX.
FIG. 8 shows a layout of elements in one unit pixel of a solid state imaging device according to a fifth embodiment of the present application. In the fifth embodiment, two p-well pick-ups PW are arranged on a boundary of the unit pixel on the right side of the light sensing areas. The remainder of the constitution is the same as the fourth embodiment.
FIG. 9 shows an allowable length of an overlapped region when an intersection region of pixel-to-pixel isolation regions is overlapped with a channel region of an in-pixel transistor. That is, A≦B/2 is allowable, where B is length of the intersection region, and A is length of the region where the intersection region is overlapped with the channel region of the in-pixel transistor. Such an arrangement reduces influence of the intersection region on the in-pixel transistor.
FIG. 10A shows position of the cross section AA’ in a plan view of the imaging device, and FIG. 10B shows a cross-sectional view of the imaging device. Referring to FIG. 10B, back end of line (BEOL) process is carried out, and metallic interconnections 316 are formed. Namely, a thick insulation file is formed, contact holes are formed, and a metallic film is deposited and patterned. Then, the imaging device placed on the substrate is connected to a logic circuit 312 placed on another substrate by bonding such as copper to copper bonding or other inter-silicon wafer connections.
Then, deep trench isolations (DTIs) 304 are formed, in order to decrease crosstalk between photodiodes 308. Color filters 305 are provided within a layer at the position corresponding to the photodiodes 308. Microlens 306 are provided at the position corresponding to the photodiodes 308. For example, there may be different sizes of the photodiodes 308, and the photodiodes 308 may be arranged in staggered positions in the horizontal direction of FIG 10B. In FIG. 10B, 301 is a floating diffusion, 302 is a 1st DPW, 303 is a 2nd DPW, 307 is a well contact, 308 is an isolation STI or doping isolation, and 314 is a transfer gate transistor.
FIG. 11 shows another exemplary block diagram of an imaging system 201. The imaging system 201 includes an optical system 202 such as one or more lens, a shutter device 203, a solid-state image sensor 204, a control circuit 205, a signal processing circuit 206, a monitor 207, and a memory 208. The solid-state image sensor 204 includes, for example, the pixel array 109 and the readout circuit 110 in FIG. 1, and obtains image data of a subject through the lens 202 and the shutter device 203, under the control of the control circuit 205. The signal processing circuit 206 outputs the obtained image data to the monitor 207 or stores the image data in the memory 208. The control circuit 205 and the signal processing circuit 206 in FIG. 11 correspond to the control circuit 105 and the signal processing circuit 106 in FIG. 1, respectively.
FIG. 12 shows various applications for a camera system. The imaging device according to the embodiments of the present application can be applied to, for example, a mobile phone camera, a digital camera, a network camera, a security and surveillance camera, a video camcorder, an automotive and transport camera, a medical camera, and machine visions.

Claims (5)

  1. A solid state imaging device in which a plurality of unit pixels are arranged in the form of a matrix along row and column directions,
    the solid state imaging device includes: a first pixel-to-pixel isolation region formed in a first process; and a second pixel-to-pixel isolation region formed in a second process which differs from the first process,
    each unit pixel comprises: one or more light sensing areas; and one or more signal readout circuit areas,
    each light sensing area includes: one or more photodiodes; one or more transfer transistors; and a part of floating diffusion,
    the signal readout circuit areas include a plurality of in-pixel transistors,
    in each unit pixel, the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors,
    each photodiode and each transfer transistor are arranged in a section isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region, and
    intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region are arranged in positions which differ from the floating diffusion and channel regions of the in-pixel transistors.
  2. The solid state imaging device according to claim 1, the signal readout circuit areas include one or more p-well pick-ups,
    the plurality of in-pixel transistors comprise a reset transistor, a source follower transistor, and a row-select transistor, and
    one or more intersection regions are arranged in the same positions as the p-well pick-ups.
  3. The solid state imaging device according to claim 2, the signal readout circuit areas are arranged along row and column directions.
  4. The solid state imaging device according to claim 2, the signal readout circuit areas are arranged on a boundary of each unit pixel and between the light sensing areas.
  5. A solid state imaging device in which a plurality of unit pixels are arranged  in the form of a matrix along row and column directions,
    the solid state imaging device includes: a first pixel-to-pixel isolation region formed in a first process; and a second pixel-to-pixel isolation region formed in a second process which differs from the first process,
    each unit pixel comprises: one or more light sensing areas; and one or more signal readout circuit areas,
    each light sensing area includes: one or more photodiodes; one or more transfer transistors; and a part of floating diffusion,
    the signal readout circuit areas include a plurality of in-pixel transistors,
    in each unit pixel, the floating diffusion and the in-pixel transistors are shared by a plurality of photodiodes and transfer transistors,
    each photodiode and each transfer transistor are arranged in a section isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region,
    intersection regions of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region are arranged in positions which differ from the floating diffusion, and
    when the intersection regions are overlapped with channel regions of the in-pixel transistors, length of the overlapped regions is less than half length of the intersection regions.
PCT/CN2020/130203 2020-11-19 2020-11-19 Solid state imaging device WO2022104658A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202080106038.0A CN116325780A (en) 2020-11-19 2020-11-19 Solid-state imaging device
PCT/CN2020/130203 WO2022104658A1 (en) 2020-11-19 2020-11-19 Solid state imaging device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2020/130203 WO2022104658A1 (en) 2020-11-19 2020-11-19 Solid state imaging device

Publications (1)

Publication Number Publication Date
WO2022104658A1 true WO2022104658A1 (en) 2022-05-27

Family

ID=81708172

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/130203 WO2022104658A1 (en) 2020-11-19 2020-11-19 Solid state imaging device

Country Status (2)

Country Link
CN (1) CN116325780A (en)
WO (1) WO2022104658A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101258599A (en) * 2005-07-12 2008-09-03 美光科技公司 Pixel with transfer gate with no isolation edge
US20110019050A1 (en) * 2008-02-28 2011-01-27 Hirofumi Yamashita Solid-state imaging device and manufacturing method thereof
CN103403869A (en) * 2011-03-02 2013-11-20 索尼公司 Solid state imaging device and fabrication method therefor, and electronic instrument
US20160204144A1 (en) * 2015-01-13 2016-07-14 Yun Ki Lee Image sensors and methods of forming the same
CN110783352A (en) * 2018-07-25 2020-02-11 三星电子株式会社 Image sensor with selective light shielding for reference pixels
CN111508979A (en) * 2019-01-30 2020-08-07 三星电子株式会社 Image sensor with a plurality of pixels

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100819711B1 (en) * 2006-12-27 2008-04-04 동부일렉트로닉스 주식회사 Cmos image sensor and method for fabricating the same
JP5564874B2 (en) * 2009-09-25 2014-08-06 ソニー株式会社 Solid-state imaging device and electronic apparatus
JP2011082253A (en) * 2009-10-05 2011-04-21 Sony Corp Solid-state imaging device and method of manufacturing the same, and electronic equipment
KR102009192B1 (en) * 2013-02-05 2019-08-09 삼성전자주식회사 Unit pixel of image sensor and image sensor including the same
US9165959B2 (en) * 2013-02-25 2015-10-20 Omnivision Technologies, Inc. Image sensor with pixel units having mirrored transistor layout
KR102114344B1 (en) * 2013-06-05 2020-05-22 삼성전자주식회사 A method of generating a pixel array layout for a image sensor and a layout generating system using thereof
US10103190B2 (en) * 2016-05-13 2018-10-16 Semiconductor Components Industries, Llc Imaging sensor having floating region of imaging device on one substrate electrically coupled to another floating region formed on a second substrate
KR102524415B1 (en) * 2018-03-21 2023-04-24 에스케이하이닉스 주식회사 Image Sensor Having PD Bias Patterns
US10510835B2 (en) * 2018-04-27 2019-12-17 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device with low random telegraph signal noise
CN110290328B (en) * 2019-07-04 2021-11-09 Oppo广东移动通信有限公司 Focusing method, device, terminal and computer storage medium

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101258599A (en) * 2005-07-12 2008-09-03 美光科技公司 Pixel with transfer gate with no isolation edge
US20110019050A1 (en) * 2008-02-28 2011-01-27 Hirofumi Yamashita Solid-state imaging device and manufacturing method thereof
CN103403869A (en) * 2011-03-02 2013-11-20 索尼公司 Solid state imaging device and fabrication method therefor, and electronic instrument
US20160204144A1 (en) * 2015-01-13 2016-07-14 Yun Ki Lee Image sensors and methods of forming the same
CN110783352A (en) * 2018-07-25 2020-02-11 三星电子株式会社 Image sensor with selective light shielding for reference pixels
CN111508979A (en) * 2019-01-30 2020-08-07 三星电子株式会社 Image sensor with a plurality of pixels

Also Published As

Publication number Publication date
CN116325780A (en) 2023-06-23

Similar Documents

Publication Publication Date Title
CN107786822B (en) Image sensor with a plurality of pixels
US8716769B2 (en) Image sensors including color adjustment path
US20190148448A1 (en) Image sensor
JP5679653B2 (en) Photoelectric conversion device and imaging system using the same
KR101683296B1 (en) Solid-state imaging device, manufacturing method thereof, and electronic apparatus
US8614759B2 (en) Solid-state imaging device, drive method thereof and electronic apparatus
KR101640260B1 (en) Solid-state imaging device, method for manufacturing the same, and electronic apparatus
US8916917B2 (en) Solid-state imaging device
US8803062B2 (en) Photoelectric conversion device having a light-shielding film
US7667183B2 (en) Image sensor with high fill factor pixels and method for forming an image sensor
US11417691B2 (en) Image sensor including dummy patterns positioned between adjacent transfer gates
JP2014022448A (en) Solid-state imaging device
JP2010067774A (en) Photoelectric conversion device and imaging system
KR102575458B1 (en) Image sensor and method for fabricating the same
US20120104523A1 (en) Solid-state imaging device manufacturing method of solid-state imaging device, and electronic apparatus
JP2017195215A (en) Imaging device and method of manufacturing the same
US20210144319A1 (en) Systems and methods for generating high dynamic range images
WO2021117523A1 (en) Solid-state image sensor and electronic device
TW202006961A (en) Solid-state imaging device, method for fabricating solid-state imaging device, and electronic apparatus
US20070145443A1 (en) CMOS Image Sensor and Method of Manufacturing the Same
WO2022104658A1 (en) Solid state imaging device
JP2013162077A (en) Solid-state imaging device
WO2022067661A1 (en) Solid state imaging device with low fixed pattern noise
JP2012204492A (en) Solid state image pickup device
US20230299096A1 (en) Image sensor and manufacturing method of the same

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20961949

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20961949

Country of ref document: EP

Kind code of ref document: A1