CN116325780A - Solid-state imaging device - Google Patents
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- CN116325780A CN116325780A CN202080106038.0A CN202080106038A CN116325780A CN 116325780 A CN116325780 A CN 116325780A CN 202080106038 A CN202080106038 A CN 202080106038A CN 116325780 A CN116325780 A CN 116325780A
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- 238000003384 imaging method Methods 0.000 title claims abstract description 44
- 238000002955 isolation Methods 0.000 claims abstract description 62
- 238000009792 diffusion process Methods 0.000 claims abstract description 33
- 238000000034 method Methods 0.000 claims abstract description 25
- 239000011159 matrix material Substances 0.000 claims abstract description 8
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 5
- 239000000758 substrate Substances 0.000 description 4
- 238000010276 construction Methods 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
- H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14636—Interconnect structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
The present invention provides a solid-state imaging device in which a plurality of unit pixels are arranged in a matrix in a row direction and a column direction. The solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process. Each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions. Each light sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion. The signal readout circuit region includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. The intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a different location than the floating diffusion and the channel region of the transistor within the pixel.
Description
Technical Field
The present application relates to a solid-state imaging device.
Background
The solid-state imaging device may be used to convert optical information into an electrical signal. The solid-state imaging device includes a plurality of pixels arranged in a matrix. To isolate each pixel, a pixel-to-pixel isolation region may be provided.
In order to minimize the pixel size, it is desirable to minimize the pixel-to-pixel isolation pitch. For this reason, it is also desirable to minimize the pitch of the photomask to form pixel-to-pixel isolation regions. However, the minimization of photomask pitch is limited.
The pixel-to-pixel isolation region may be formed by two processes. That is, first, the first pixel to pixel isolation region is formed through the first process, and then the second pixel to pixel isolation region is formed at a position offset by half a pitch through the second process. Thus, the pixel-to-pixel isolation region may be formed by half the pitch of the photomask.
However, in these processes, the dose is implanted twice in the intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. This can affect the performance of the device and can create fixed pattern noise on the output image.
Disclosure of Invention
According to a first aspect of the present application, there is provided a solid-state imaging device in which a plurality of unit pixels are arranged in a matrix in a row direction and a column direction. The solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process. Each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions. Each light sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion. The signal readout circuit region includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. The intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a different location than the floating diffusion and the channel region of the transistor within the pixel.
According to a second aspect of the present application, the signal readout circuitry region includes one or more p-well potential regions. The plurality of in-pixel transistors includes a reset transistor, a source follower transistor, and a row select transistor. One or more crossover regions are disposed at the same location as the p-well potential region.
According to a third aspect of the present application, the signal readout circuit regions are arranged in a row direction and a column direction.
According to a fourth aspect of the present application, the signal readout circuit region is disposed on the boundary of each unit pixel and between the light sensing regions.
According to a fifth aspect of the present application, there is provided a solid-state imaging device in which a plurality of unit pixels are arranged in a matrix in a row direction and a column direction. The solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process. Each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions. Each light sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion. The signal readout circuit region includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. The intersection region of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a different location than the floating diffusion. When the intersection region overlaps with a channel region of a transistor in the pixel, a length of the overlap region is less than half a length of the intersection region.
Drawings
Fig. 1 is an exemplary block diagram of an imaging system.
Fig. 2 is an exemplary circuit diagram of an imaging device.
Fig. 3 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the first embodiment of the present application.
Fig. 4 shows how pixel-to-pixel isolation regions are formed.
Fig. 5 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the second embodiment of the present application.
Fig. 6 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the third embodiment of the present application.
Fig. 7 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the fourth embodiment of the present application.
Fig. 8 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the fifth embodiment of the present application.
Fig. 9 shows the allowable length of the overlap region created when the pixel-to-pixel isolation region intersection overlaps the channel region of the transistor within the pixel.
Fig. 10A shows the position of the cross section AA' in a plan view of the imaging apparatus.
Fig. 10B shows a cross-sectional view of the imaging apparatus.
Fig. 11 is another exemplary block diagram of an imaging system.
Fig. 12 shows various applications of the camera system.
Detailed Description
In the solid-state imaging device provided in the present application, a plurality of pixels are arranged in a matrix on a substrate.
Fig. 1 is an exemplary block diagram of an imaging system 101. The imaging system 101 includes a pixel array 109, a control circuit 105, a readout circuit 110, and a signal processing circuit 106. In the pixel array 109, a plurality of pixels are arranged in a matrix on a substrate. The control circuit 105 controls the pixel array 109, and the readout circuit 110 reads out image data. The signal processing circuit 106 processes the image data read by the readout circuit 110.
Fig. 2 is an exemplary circuit diagram of an imaging device. The imaging apparatus includes four photodiodes PD1 to PD4, four transfer transistors TX1 to TX4, a floating diffusion FD, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. The reset transistor RST is turned on in response to a reset signal, and resets the charge accumulated in the floating diffusion FD. The photodiodes PD1 to PD4 generate electric charges corresponding to the amount of incident light by photoelectric conversion, and accumulate the generated electric charges. One of the transfer transistors TX1 to TX4 is turned on in response to a transfer signal, and transfers the charge accumulated in one of the photodiodes PD1 to PD4 to the floating diffusion FD. The voltage of the floating diffusion FD is determined by the transferred charge. This voltage is applied to the gate of the source follower transistor SF. The source follower transistor SF transmits a pixel signal corresponding to the voltage of the floating diffusion FD to the row selection transistor SEL. The row selection transistor SEL outputs Vout as a pixel signal in response to a row selection signal.
Fig. 3 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the first embodiment of the present application. One unit pixel includes four light sensing regions and one signal readout circuit region. For example, the four light sensing regions include two green light sensing regions, one blue light sensing region, and one red light sensing region. Each light sensing region includes one photodiode PD, one transfer transistor TX, and a portion of the floating diffusion FD. The signal readout circuit region includes one p-well potential region PW and three in-pixel transistors. If the photodiode is n-type, the isolation region and the well potential region should be p-type. If the photodiode is p-type, the isolation region and the well potential region should be n-type. The three in-pixel transistors include a reset transistor RST, a source follower transistor SF, and a row select transistor SEL. However, the number of elements included in the signal readout circuit region is not limited to the above number.
In one unit pixel, four photodiodes PD are connected to four transfer transistors TX, respectively. The four transfer transistors TX are connected to the floating diffusion FD. The signal readout circuit region is disposed on a boundary of the unit pixel below the light sensing region. The floating diffusion FD and the signal readout circuit are shared by four photodiodes PD and four transfer transistors TX.
Each light sensing region is isolated by a pixel-to-pixel isolation region. The pixel-to-pixel isolation region is formed in a grid shape so as to surround each of the light sensing regions. The pixel-to-pixel isolation region prevents signal charges in the photo-sensing region from leaking into an adjacent photo-sensing region. When floating diffusion or in-pixel transistors are formed between the light sensing region and the adjacent light sensing region, the pixel-to-pixel isolation region overlaps these elements. The depth of the pixel to pixel isolation region is greater than the depth of the floating diffusion or transistor region within the pixel. However, when the deep pixel-to-pixel isolation region is formed by high-energy ion implantation, a well proximity effect occurs, and a high dose region is formed near the silicon surface.
Fig. 4 shows how pixel-to-pixel isolation regions are formed. The pixel-to-pixel isolation region is formed by two processes. That is, first pixel-to-pixel isolation regions (first DPWs) are formed first by a first process, and then second pixel-to-pixel isolation regions (second DPWs) are formed at positions diagonally offset by half a mask pitch by a second process. Thus, the pixel-to-pixel isolation region may be formed by half the pitch of the photomask.
In these processes, the dose is implanted twice in the intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. This can affect the floating diffusion and the performance of the transistors within the pixel.
The pixel-to-pixel isolation region intersection is not placed over the floating diffusion and the channel region of the transistor within the pixel. The crossover region may be placed over the p-well potential region PW. Such a setting minimizes the effect of dose on floating diffusion and the performance of transistors within the pixel. Thus, for example, vth variation of the source follower transistor is suppressed, fixed pattern noise on the output image is reduced, reset noise and random noise of the source follower transistor are also reduced, and white pixel clusters due to junction leakage of floating diffusion are also reduced.
Fig. 5 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the second embodiment of the present application. In the second embodiment, the signal readout circuit region is disposed below the light sensing region and on the boundary of the unit pixels on the right side of the light sensing region. The signal readout circuit region includes one p-well potential region PW and four in-pixel transistors. The four in-pixel transistors include a dual conversion gain transistor DCG, a reset transistor RST, a source follower transistor SF, and a row select transistor SEL. Instead of setting the dual conversion gain transistor DCG, another reset transistor RST may be set. The dual conversion gain transistor DCG and the reset transistor RST are disposed on the boundary of the unit pixel on the right side of the light sensing region. The rest of the construction is the same as in the first embodiment.
Fig. 6 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the third embodiment of the present application. In the third embodiment, the signal readout circuit region is disposed below the light sensing region and on the boundary of the unit pixels on the right side of the light sensing region. The signal readout circuit region includes one p-well potential region PW and three in-pixel transistors. The three in-pixel transistors include a reset transistor RST, a source follower transistor SF, and a row select transistor SEL. The p-well potential region PW is disposed on the boundary of the unit pixel on the right side of the light sensing region. The rest of the construction is the same as in the first embodiment.
Fig. 7 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the fourth embodiment of the present application. One unit pixel includes eight light sensing regions and two signal readout circuit regions. For example, the eight light sensing regions include four green light sensing regions, two blue light sensing regions, and two red light sensing regions. Each light sensing region includes one photodiode PD, one transfer transistor TX, and a portion of the floating diffusion FD. The two signal readout circuit regions are disposed between the upper four light sensing regions and the lower four light sensing regions, and are disposed on the boundaries of the unit pixels below the light sensing regions. The signal readout circuit region between the light sensing regions includes one p-well potential region PW and two in-pixel transistors. The two in-pixel transistors include a row selection transistor SEL and a source follower transistor SF. The signal readout circuitry area below the photo-sensing area also includes a p-well potential region PW and two in-pixel transistors. The two in-pixel transistors include a dual conversion gain transistor DCG and a reset transistor RST. Instead of setting the dual conversion gain transistor DCG, another reset transistor RST may be set.
In one unit pixel, eight photodiodes PD are connected to eight transfer transistors TX, respectively. Eight transfer transistors TX are connected to the floating diffusion FD. The floating diffusion FD and the signal readout circuit are shared by eight photodiodes PD and eight transfer transistors TX.
Fig. 8 shows a layout of elements in one unit pixel of the solid-state imaging device provided in the fifth embodiment of the present application. In the fifth embodiment, two p-well potential regions PW are provided on the boundary of the unit pixel on the right side of the light sensing region. The rest of the construction is the same as in the fourth embodiment.
Fig. 9 shows the allowable length of the overlap region created when the pixel-to-pixel isolation region intersection overlaps the channel region of the transistor within the pixel. That is, A+.B/2 is permissible, where B is the length of the intersection region and A is the length of the overlap region created when the intersection region overlaps the channel region of the transistor within the pixel. Such an arrangement reduces the impact of the crossover region on the transistors within the pixel.
Fig. 10A shows the position of the cross section AA' in a plan view of the imaging apparatus, and fig. 10B shows the cross section view of the imaging apparatus. Referring to fig. 10B, a back end of line (BEOL) process is performed, thus forming a metal interconnect 316. In other words, a thick insulating film is formed, contact holes are formed, a metal film is deposited and patterned. The imaging device placed on the substrate is then connected to logic 312 placed on another substrate by copper-copper bonding or other inter-silicon bonding.
Thus, deep trench isolation (deep trench isolation, DTI) 304 is formed to reduce cross-talk between photodiodes 308. The color filter 305 is provided in one layer at a position corresponding to the photodiode 308. The microlens 306 is disposed at a position corresponding to the photodiode 308. For example, the size of the photodiodes 308 may be different, and the photodiodes 308 may be staggered in the horizontal direction of fig. 10B. In fig. 10b,301 is a floating diffusion, 302 is a first DPW,303 is a second DPW,307 is a well contact, 308 is an isolation STI or doped isolation, and 314 is a pass gate transistor.
Fig. 11 is another exemplary block diagram of an imaging system 201. The imaging system 201 includes an optical system 202 (e.g., one or more lenses), a shutter device 203, a solid-state image sensor 204, a control circuit 205, a signal processing circuit 206, a display 207, and a memory 208. The solid-state image sensor 204 includes, for example, the pixel array 109 and the readout circuit 110 in fig. 1, and acquires image data of an object through the lens 202 and the shutter device 203 under the control of the control circuit 205. The signal processing circuit 206 outputs the acquired image data to the display 207 or stores the image data in the memory 208. The control circuit 205 and the signal processing circuit 206 in fig. 11 correspond to the control circuit 105 and the signal processing circuit 106 in fig. 1, respectively.
Fig. 12 shows various applications of the camera system. The imaging device provided by the embodiment of the application can be applied to, for example, a mobile phone camera, a digital camera, a network camera, a security monitoring camera, a video camera, an automobile and traffic camera, a medical camera and machine vision.
Claims (5)
1. A solid-state imaging device characterized in that a plurality of unit pixels are arranged in a matrix in a row direction and a column direction;
the solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process;
each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions;
each light sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion;
the signal readout circuit region includes a plurality of in-pixel transistors;
in each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors;
each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region;
the intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a different location than the floating diffusion and the channel region of the transistor within the pixel.
2. The solid-state imaging device according to claim 1, wherein the signal readout circuit region includes one or more p-well potential regions;
the plurality of in-pixel transistors includes a reset transistor, a source follower transistor, and a row select transistor;
one or more crossover regions are disposed at the same location as the p-well potential region.
3. The solid-state imaging device according to claim 2, wherein the signal readout circuit regions are arranged in a row direction and a column direction.
4. The solid-state imaging device according to claim 2, wherein the signal readout circuit region is disposed on a boundary of each unit pixel and between the light sensing regions.
5. A solid-state imaging device characterized in that a plurality of unit pixels are arranged in a matrix in a row direction and a column direction;
the solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process;
each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions;
each light sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion;
the signal readout circuit region includes a plurality of in-pixel transistors;
in each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors;
each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region;
the intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a different location than the floating diffusion;
when the intersection region overlaps with a channel region of a transistor in the pixel, a length of the overlap region is less than half a length of the intersection region.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2020/130203 WO2022104658A1 (en) | 2020-11-19 | 2020-11-19 | Solid state imaging device |
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| CN116325780A true CN116325780A (en) | 2023-06-23 |
| CN116325780B CN116325780B (en) | 2024-06-11 |
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| WO (1) | WO2022104658A1 (en) |
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| CN116325780B (en) | 2024-06-11 |
| WO2022104658A1 (en) | 2022-05-27 |
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