CN116325780A - Solid-state imaging device - Google Patents

Abstract

The present invention provides a solid-state imaging device, wherein a plurality of unit pixels are arranged in a matrix along row and column directions. The solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process. Each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions. Each photo-sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion. The signal readout circuit area includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. An intersection region of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a different position from the floating diffusion and the channel region of the intra-pixel transistor.

Description

solid state imaging device

technical field

The present application relates to a solid-state imaging device.

Background technique

Solid-state imaging devices can be used to convert optical information into electrical signals. This solid-state imaging device includes a plurality of pixels arranged in a matrix. To isolate each pixel, a pixel-to-pixel isolation region may be provided.

In order to minimize the pixel size, the pixel-to-pixel isolation spacing needs to be minimized. For this reason, it is also necessary to minimize the pitch of the photomask to form pixel-to-pixel isolation regions. However, the minimization of the photomask pitch is limited.

The pixel-to-pixel isolation region can be formed by two processes. That is to say, first the first pixel-to-pixel isolation region is formed through the first process, and then the second pixel-to-pixel isolation region is formed at a position offset by half the pitch through the second process. Therefore, pixel-to-pixel isolation regions can be formed by half the pitch of the photomask.

However, in these processes, the dose is implanted twice in the intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. This affects the performance of the device and can produce fixed pattern noise on the output image.

Contents of the invention

According to a first aspect of the present application, there is provided a solid-state imaging device in which a plurality of unit pixels are arranged in a matrix in a row direction and a column direction. The solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process. Each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions. Each photo-sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion. The signal readout circuit area includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. An intersection region of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a different position from the floating diffusion and the channel region of the intra-pixel transistor.

According to the second aspect of the present application, the signal readout circuit region includes one or more p-well potential regions. The plurality of in-pixel transistors include reset transistors, source follower transistors, and row select transistors. One or more crossing regions are arranged at the same position as the p-well potential region.

According to the third aspect of the present application, the signal readout circuit area is arranged along the row direction and the column direction.

According to the fourth aspect of the present application, the signal readout circuit region is disposed on the boundary of each unit pixel and between the photo-sensing regions.

According to a fifth aspect of the present application, there is provided a solid-state imaging device in which a plurality of unit pixels are arranged in a matrix in a row direction and a column direction. The solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process. Each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions. Each photo-sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion. The signal readout circuit area includes a plurality of in-pixel transistors. In each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors. Each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. An intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a position different from that of the floating diffusion. When the intersection area overlaps with the channel area of the transistor in the pixel, the length of the overlapping area is less than half the length of the intersection area.

Description of drawings

FIG. 1 is an exemplary block diagram of an imaging system.

FIG. 2 is an exemplary circuit diagram of an imaging device.

FIG. 3 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the first embodiment of the present application.

Figure 4 shows how pixel-to-pixel isolation regions are formed.

FIG. 5 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the second embodiment of the present application.

FIG. 6 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the third embodiment of the present application.

FIG. 7 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the fourth embodiment of the present application.

FIG. 8 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the fifth embodiment of the present application.

FIG. 9 shows the allowable length of the overlapping region produced when the intersection region of the pixel-to-pixel isolation region overlaps the channel region of the transistor in the pixel.

FIG. 10A shows the position of section AA' in a plan view of the imaging device.

FIG. 10B shows a cross-sectional view of the imaging device.

11 is another exemplary block diagram of an imaging system.

Figure 12 illustrates various applications of the camera system.

Detailed ways

In the solid-state imaging device provided in the present application, a plurality of pixels are arranged on a substrate in the form of a matrix.

FIG. 1 is an exemplary block diagram of an imaging system 101 . Imaging system 101 includes pixel array 109 , control circuitry 105 , readout circuitry 110 and signal processing circuitry 106 . In the pixel array 109, a plurality of pixels are arranged in a matrix on a substrate. The control circuit 105 controls the pixel array 109, and the readout circuit 110 reads out image data. The signal processing circuit 106 processes the image data read out by the readout circuit 110 .

FIG. 2 is an exemplary circuit diagram of an imaging device. The imaging device includes four photodiodes PD1 to PD4, four transfer transistors TX1 to TX4, a floating diffusion FD, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. The reset transistor RST is turned on in response to a reset signal, and resets charges accumulated in the floating diffusion FD. The photodiodes PD1 to PD4 generate charges corresponding to the amount of incident light by photoelectric conversion, and accumulate the generated charges. One of the transfer transistors TX1 to TX4 is turned on in response to a transfer signal, and transfers charges accumulated in one of the photodiodes PD1 to PD4 to the floating diffusion FD. The voltage of the floating diffusion FD is determined by the transferred charges. This voltage is applied to the gate of the source follower transistor SF. The source follower transistor SF transmits a pixel signal corresponding to the voltage of the floating diffusion FD to the row selection transistor SEL. The row selection transistor SEL outputs Vout as a pixel signal in response to a row selection signal.

FIG. 3 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the first embodiment of the present application. One unit pixel includes four light sensing regions and one signal readout circuit region. For example, the four light sensing areas include two green light sensing areas, one blue light sensing area and one red light sensing area. Each photo-sensing area includes a photodiode PD, a transfer transistor TX and a part of the floating diffusion FD. The signal readout circuit area includes a p-well potential area PW and three transistors in the pixel. If the photodiode is n-type, the isolation and well potential regions should be p-type. If the photodiode is p-type, the isolation region and well potential region should be n-type. The three in-pixel transistors include a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. However, the number of elements included in the signal readout circuit region is not limited to the above-mentioned number.

In one unit pixel, four photodiodes PD are respectively connected to four transfer transistors TX. Four transfer transistors TX are connected to the floating diffusion FD. The signal readout circuit area is disposed on the boundary of the unit pixel under the light sensing area. The floating diffusion FD and the signal readout circuit are shared by four photodiodes PD and four transfer transistors TX.

Each photo-sensing area is isolated by a pixel-to-pixel isolation region. The pixel-to-pixel isolation region is formed in a grid shape so as to surround each light sensing region. The pixel-to-pixel isolation region prevents signal charges in the photo-sensing region from leaking into adjacent photo-sensing regions. When floating diffusions or intra-pixel transistors are formed between a photo-sensing region and adjacent photo-sensing regions, pixel-to-pixel isolation regions overlap these elements. The depth of the pixel-to-pixel isolation region is greater than the depth of the floating diffusion or transistor region within the pixel. However, when deep pixel-to-pixel isolation regions are formed by high-energy ion implantation, well proximity effects occur and high-dose regions form near the silicon surface.

Figure 4 shows how pixel-to-pixel isolation regions are formed. The pixel-to-pixel isolation regions are formed by two processes. That is to say, first the first pixel-to-pixel isolation region (first DPW) is formed through the first process, and then the second pixel-to-pixel isolation region (first DPW) is formed at a position where the diagonal line is offset by half the mask pitch through the second process. second DPW). Therefore, pixel-to-pixel isolation regions can be formed by half the pitch of the photomask.

In these processes, the dose is implanted twice in the intersection of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region. This affects the floating diffusion and the performance of the transistors within the pixel.

Pixel-to-pixel isolation region intersection regions are not placed over floating diffusions and channel regions of transistors within pixels. The cross region may be placed on the p-well potential region PW. Such an arrangement minimizes the impact of the dose on the floating diffusion and the performance of the transistors within the pixel. Thus, for example, the Vth variation of the source follower transistor is suppressed, the fixed pattern noise on the output image is reduced, reset noise and random noise of the source follower transistor are also reduced, and also the junction leakage due to the floating diffusion is reduced. clusters of white pixels.

FIG. 5 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the second embodiment of the present application. In the second embodiment, the signal readout circuit region is disposed below the photo-sensing region and on the boundary of the unit pixel on the right side of the photo-sensing region. The signal readout circuit area includes a p-well potential area PW and four transistors in the pixel. The four in-pixel transistors include a dual conversion gain transistor DCG, a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. A further reset transistor RST may be provided instead of the dual conversion gain transistor DCG. The dual conversion gain transistor DCG and the reset transistor RST are disposed on the boundary of the unit pixel on the right side of the light sensing area. The rest of the construction is the same as that of the first embodiment.

FIG. 6 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the third embodiment of the present application. In the third embodiment, the signal readout circuit area is disposed below the light sensing area and on the boundary of the unit pixel on the right side of the light sensing area. The signal readout circuit area includes a p-well potential area PW and three transistors in the pixel. The three in-pixel transistors include a reset transistor RST, a source follower transistor SF, and a row selection transistor SEL. The p-well potential region PW is disposed on the boundary of the unit pixel on the right side of the photo-sensing region. The rest of the construction is the same as that of the first embodiment.

FIG. 7 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the fourth embodiment of the present application. One unit pixel includes eight light sensing regions and two signal readout circuit regions. For example, the eight light sensing areas include four green light sensing areas, two blue light sensing areas and two red light sensing areas. Each photo-sensing area includes a photodiode PD, a transfer transistor TX and a part of the floating diffusion FD. The two signal readout circuit areas are arranged between the upper four photo-sensing areas and the lower four photo-sensing areas, and are arranged on the boundary of the unit pixel below the photo-sensing areas. The signal readout circuit area between the photo-sensing areas includes a p-well potential area PW and two transistors in the pixel. These two in-pixel transistors include a row selection transistor SEL and a source follower transistor SF. The signal readout circuit area below the photo-sensing area also includes a p-well potential area PW and two transistors in the pixel. These two in-pixel transistors include a dual conversion gain transistor DCG and a reset transistor RST. A further reset transistor RST may be provided instead of the dual conversion gain transistor DCG.

In one unit pixel, eight photodiodes PD are respectively connected to eight transfer transistors TX. Eight transfer transistors TX are connected to the floating diffusion FD. The floating diffusion FD and the signal readout circuit are shared by eight photodiodes PD and eight transfer transistors TX.

FIG. 8 shows the layout of elements in a unit pixel of the solid-state imaging device provided by the fifth embodiment of the present application. In the fifth embodiment, two p-well potential regions PW are disposed on the boundary of the unit pixel on the right side of the photo-sensing region. The rest of the construction is the same as that of the fourth embodiment.

FIG. 9 shows the allowable length of the overlapping region produced when the intersection region of the pixel-to-pixel isolation region overlaps the channel region of the transistor in the pixel. That is, A≦B/2 is acceptable, where B is the length of the intersection region, and A is the length of the overlapping region generated when the intersection region overlaps with the channel region of the transistor in the pixel. Such an arrangement reduces the influence of the intersection region on the transistors in the pixel.

FIG. 10A shows the position of section AA' in a plan view of the imaging device, and FIG. 10B shows a cross-sectional view of the imaging device. Referring to FIG. 10B , a back end of line (BEOL) process is performed, thereby forming metal interconnections 316 . In other words, a thick insulating film is formed, a contact hole is formed, a metal film is deposited and patterned. The imaging device placed on the substrate is then connected to the logic circuit 312 placed on the other substrate through bonding such as copper-to-copper bonding or other silicon-to-silicon connections.

Thus, deep trench isolation (DTI) 304 is formed to reduce crosstalk between photodiodes 308 . The color filter 305 is provided in one layer at a position corresponding to the photodiode 308 . The microlens 306 is provided at a position corresponding to the photodiode 308 . For example, the size of the photodiodes 308 may be different, and the photodiodes 308 may be staggered in the horizontal direction of FIG. 10B . In FIG. 10B , 301 is a floating diffusion, 302 is a first DPW, 303 is a second DPW, 307 is a well contact, 308 is an isolation STI or doped isolation, and 314 is a transfer gate transistor.

FIG. 11 is another exemplary block diagram of imaging system 201 . Imaging system 201 includes optical system 202 (eg, one or more lenses), shutter device 203 , solid-state image sensor 204 , control circuitry 205 , signal processing circuitry 206 , display 207 and memory 208 . The solid-state image sensor 204 includes, for example, the pixel array 109 and the readout circuit 110 in FIG. The signal processing circuit 206 outputs the acquired image data to the display 207 or stores the image data in the memory 208 . The control circuit 205 and the signal processing circuit 206 in FIG. 11 correspond to the control circuit 105 and the signal processing circuit 106 in FIG. 1 , respectively.

Figure 12 illustrates various applications of the camera system. The imaging device provided by the embodiments of the present application can be applied to, for example, mobile phone cameras, digital cameras, network cameras, security surveillance cameras, video cameras, automobile and traffic cameras, medical cameras, and machine vision.

Claims (5)

1. A solid-state imaging device, characterized in that a plurality of unit pixels are arranged in the form of a matrix along the row direction and the column direction; The solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process; Each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions; Each photo-sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion; The signal readout circuit area includes a plurality of transistors in pixels; In each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors; each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region; An intersection region of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a different position from the floating diffusion and the channel region of the intra-pixel transistor. 2. The solid-state imaging device according to claim 1, wherein the signal readout circuit region comprises one or more p-well potential regions; The plurality of intra-pixel transistors include reset transistors, source follower transistors, and row select transistors; One or more crossing regions are arranged at the same position as the p-well potential region. 3. The solid-state imaging device according to claim 2, wherein the signal readout circuit area is arranged along a row direction and a column direction. 4. The solid-state imaging device according to claim 2, wherein the signal readout circuit region is provided on a boundary of each unit pixel and between the photo-sensing regions. 5. A solid-state imaging device, characterized in that a plurality of unit pixels are arranged in the form of a matrix along the row direction and the column direction; The solid-state imaging device includes a first pixel-to-pixel isolation region formed by a first process and a second pixel-to-pixel isolation region formed by a second process different from the first process; Each unit pixel includes one or more light sensing regions and one or more signal readout circuit regions; Each photo-sensing region includes one or more photodiodes, one or more transfer transistors, and a portion of a floating diffusion; The signal readout circuit area includes a plurality of transistors in pixels; In each unit pixel, the floating diffusion and the in-pixel transistor are shared by a plurality of photodiodes and transfer transistors; each photodiode and each transfer transistor are disposed in a portion isolated by the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region; an intersection region of the first pixel-to-pixel isolation region and the second pixel-to-pixel isolation region is disposed at a position different from that of the floating diffusion; When the intersection area overlaps with the channel area of the transistor in the pixel, the length of the overlapping area is less than half the length of the intersection area.

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