WO2022067661A1

WO2022067661A1 - Solid state imaging device with low fixed pattern noise

Info

Publication number: WO2022067661A1
Application number: PCT/CN2020/119391
Authority: WO
Inventors: Takahashi Seiji
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2020-09-30
Filing date: 2020-09-30
Publication date: 2022-04-07
Also published as: CN116235280A; CN116235280A8

Abstract

An imaging device (201), wherein a sidewall spacer (74) width of a transfer gate device (TX) is wider than the sidewall spacer (71, 72, 73) width of other in-pixel devices. It can decrease GIDL and GISL in photodiodes (PD) and floating diffusion (FD) regions, while tightening contact and gate pitch of in-pixel devices.

Description

SOLID STATE IMAGING DEVICE WITH LOW FIXED PATTERN NOISE

TECHNICAL FIELD

The present invention relates to an imaging device and a manufacturing method thereof.

BACKGROUND

High resolution imaging devices such as an image sensor of a camera in a mobile device have been developed, and the number of pixels arranged in an imaging device is increasing. As pixel size shrinks, it is unavoidable to reduce sidewall spacer width of devices such as transistors on a semiconductor substrate. As a result, an electric field becomes higher in order to satisfy constant voltage scaling. Especially, gate induced drain leakage (GIDL) and gate induced source leakage (GISL) become more serious.

In a prior art, a sidewall spacer disposed on a photodiode (PD) side is narrower than that disposed on a floating diffusion (FD) side so that effective photodiode area increases and full well capacity improves. However, this will result in a GISL issue during charge integration, and lead to higher fixed pattern noise and higher dark signal non-uniformity.

SUMMARY

An imaging device is provided to decrease GIDL and GISL in photodiodes and floating diffusion regions, while tightening contact and gate pitch of in-pixel devices.

According to a first aspect, an imaging device is provided, wherein the imaging device includes a plurality of pixels, each pixel includes a transfer gate device, a reset device, a source follower device, and a row select device, and a sidewall spacer width of the transfer gate device is wider than a sidewall spacer width of other in-pixel devices.

In a possible implementation manner of the first aspect, a difference between the sidewall spacer width of the transfer gate device and the sidewall spacer width of the other in-pixel devices is equal to or greater than 3 nanometers.

According to a second aspect, an imaging device is provided, wherein a sidewall spacer width of a transfer gate device and a sidewall spacer width of a source side of an adjacent device, which is a device other than the transfer gate device and is arranged adjacent to a floating diffusion, are wider than the sidewall spacer width of a drain side of the adjacent device, and the sidewall spacer width of a source follower device, a row-select device, and other in-pixel devices.

In a possible implementation manner of the second aspect, the sidewall spacer width of the transfer gate device and the sidewall spacer width of the source side of the adjacent device are wider than the sidewall spacer width of a drain side of the adjacent device, and the sidewall spacer width of a source follower device, a row-select device, and other in-pixel devices by 3 nanometers or more.

According to a third aspect, an imaging device is provided, wherein the imaging device includes a plurality of pixels, each pixel includes a transfer gate device, a reset device, a source follower device, and a row select device, and a gate offset spacer width of the transfer gate device is wider than a gate offset spacer width of other in-pixel devices.

In a possible implementation manner of the third aspect, a difference between the gate offset spacer width of the transfer gate device and the gate offset spacer width of the other in-pixel devices is equal to or greater than 3 nanometers.

According to a fourth aspect, an imaging device is provided, wherein a gate offset spacer width of a transfer gate device and a gate offset spacer width of a source side of an adjacent device, which is a device other than the transfer gate device and is arranged adjacent to a floating diffusion, are wider than the gate offset spacer width of a drain side of the adjacent device, and the gate offset spacer width of a source follower device, a row-select device, and other in-pixel devices.

In a possible implementation manner of the fourth aspect, the gate offset spacer width of the transfer gate device and the gate offset spacer width of the source side of the adjacent device are wider than the gate offset spacer width of a drain side of the adjacent device, and the gate offset spacer width of a source follower device, a row-select device, and other in-pixel devices by 3 nanometers or more.

According to a fifth aspect, a manufacturing method of an imaging device is provided, wherein the method includes: forming gate offset spacers at both sides of a transfer gate device and other in-pixel devices; forming an insulation film over the transfer gate device and the other in-pixel devices; etching the insulation film over the other in-pixel devices by isotropic etching; and etching the insulation film over the transfer gate device and the other in-pixel devices by anisotropic etching.

According to a sixth aspect, a manufacturing method of an imaging device is provided, wherein the method includes: forming gate offset spacers at both sides of a transfer gate device, an adjacent device which is a device other than the transfer gate device and is arranged adjacent to a floating diffusion, and other in-pixel devices; forming an insulation film over the transfer gate device, the adjacent device, and the other in-pixel devices; etching the insulation film over the other in-pixel devices and a drain side of the adjacent device by isotropic etching; and etching the insulation film over the transfer gate device, the adjacent device, and the other in-pixel devices by anisotropic etching.

According to a seventh aspect, a manufacturing method of an imaging device is provided, wherein the method includes: forming an insulation film over a transfer gate device and other in-pixel devices; etching the insulation film over the other in-pixel devices by isotropic etching; etching the insulation film over the transfer gate device and the other in-pixel devices by anisotropic etching; and forming sidewall spacers at both sides of the transfer gate device and the other in-pixel devices.

According to an eighth aspect, a manufacturing method of an imaging device is provided, wherein the method includes: forming an insulation film over a transfer gate device, an adjacent device which is a device other than the transfer gate device and is arranged adjacent to a floating diffusion, and other in-pixel devices; etching the insulation film over the other in-pixel devices and a drain side of the adjacent device by isotropic etching; etching the insulation film over the transfer gate device, the adjacent device, and the other in-pixel devices by anisotropic etching; and forming sidewall spacers at both sides of the transfer gate device, the adjacent device, and the other in-pixel devices.

BRIEF DESCRIPTION OF DRAWINGS

To describe the technical solutions in the embodiments of the present invention or in the prior art more clearly, the following briefly introduces the accompanying drawings required for describing the embodiments or the prior art. The accompanying drawings in the following description show merely some embodiments of the present invention, and a person of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.

FIG. 1 shows an example block diagram of an imaging system 201;

FIG. 2 shows an example circuit diagram of an imaging device;

FIG. 3 shows a top view of an example circuit layout formed on a semiconductor substrate for the imaging device shown in FIG. 2 according to an embodiment of the present invention;

FIG. 4 shows a cross-sectional view of a part of the imaging device formed on the semiconductor substrate according to the embodiment of the present invention;

FIG. 5 shows a top view of an example circuit layout formed on a semiconductor substrate for the imaging device shown in FIG. 2 according to another embodiment of the present invention;

FIG. 6 shows a cross-sectional view of a part of the imaging device formed on the semiconductor substrate according to the embodiment of the present invention;

FIG. 7 shows an example circuit diagram of an imaging device;

FIG. 8 shows a top view of an example circuit layout formed on a semiconductor substrate for the imaging device shown in FIG. 7 according to an embodiment of the present invention;

FIG. 9 shows an example circuit diagram of the imaging device in which two sets of the PDs and the TXs share the in-pixel devices.

FIG. 10 shows an example circuit diagram of the imaging device in which four sets of the PDs and the TXs share the in-pixel devices;

FIG. 11 shows a top view of an example circuit layout formed on a semiconductor substrate for the imaging device shown in FIG. 10 according to another embodiment of the present invention;

FIG. 12 shows a cross-sectional view of a part of the imaging device in which the difference between the sidewall spacer width of the TX and the sidewall spacer width of the other in-pixel devices is made by a source/drain (S/D) sidewall spacer;

FIG. 13 shows a cross-sectional view of a part of the imaging device in which the difference between the sidewall spacer width of the TX and the sidewall spacer width of the other in-pixel devices is made by a gate offset spacer;

FIG. 14 to FIG. 21 show examples of a first to eighth cross-sectional views of a substrate on which an imaging device is manufactured according to an example of a manufacturing process; and

FIG. 22 to FIG. 25 show examples of a first to fourth cross-sectional views of a substrate on which an imaging device is manufactured according to an example of another manufacturing process;

FIG. 26 shows another example block diagram of an imaging system 201; and

FIG. 27 shows various applications for a camera system.

DESCRIPTION OF EMBODIMENTS

The following clearly and completely describes the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. The described embodiments are only some but not all of the embodiments of the present invention. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protected scope of the present invention.

FIG. 1 shows an example block diagram of an imaging system 201. The imaging system 201 includes a control circuit 205, a pixel array 209, a readout circuit 210, a signal processing circuit 206. The pixel array 205 is a two-dimensional array of pixels. Each pixel may be an imaging device as shown in FIG. 2. The pixels are arranged in rows (R1 to Ry) and columns (C1 to Cx) to obtain image data of a subject. The control circuit 205 controls the pixel array 209, for example, generates a shutter signal. The image data is readout by the readout circuit 210 via bit lines and sent to the signal processing circuit 206.

FIG. 2 shows an example circuit diagram of an imaging device which may be a pixel in FIG. 1. A photodiode (PD) converts light into an electrical charge. The electrical charge is selectively transmitted to a floating diffusion (FD) via a transfer gate device (TX) . The FD is connected to a gate of a source follower device (SF) , and an output signal (Vout) is transmitted to a signal line via a row select device (SEL) . A current source (Icolumn) is connected between the SEL and a ground. Accordingly, if gates of the TX and the SEL are turned on, the output signal corresponding to the electrical signal from the PD is obtained on the signal line. A reset device (RST) selectively resets an electrical charge accumulated in the FD. A dual conversion gain device (DCG) (not shown in FIG. 2, but shown in FIG. 7) may be connected between the RST and the FD, in order to realize high dynamic range by combining two types of gains.

FIG. 3 shows a top view of an example circuit layout formed on a semiconductor substrate for the imaging device shown in FIG. 2 according to an embodiment of the present invention. It should be noted that the width of a sidewall spacer 74 is wider than the width of

sidewall spacers

71, 72, and 73. FIG. 4 shows a cross-sectional view of a part of the imaging device formed on the semiconductor substrate according to the embodiment of the present invention. The sidewall spacer width on the FD side is sensitive to GIDL. Therefore, the sidewall spacer width (Wt) of the TX is wider than the sidewall spacer width (Wd) of the other in-pixel devices including the RST, the SF, the SEL, and the DCG. The difference between Wt and Wd is equal to or greater than 3 nm (nano meter) . The transfer gate device (TX) can be a planar or a vertical.

FIG. 5 shows a top view of an example circuit layout formed on a semiconductor substrate for the imaging device shown in FIG. 2 according to another embodiment of the present invention. It should be noted that the width of the sidewall spacer 74 and the width of the right side (the side where wiring shown as a bold line is arranged between the FD and the RST) of the sidewall spacer 73 are wider than the width of the left, upper, and lower sides (the sides where wiring is not arranged between the FD and the RST) of the sidewall spacer 73, and the width of the

sidewall spacers

71 and 72. FIG. 6 shows a cross-sectional view of a part of the imaging device formed on the semiconductor substrate according to the embodiment of the present invention. The sidewall spacer width of the TX and the source side (S) of the RST are wider than the drain side (D) of the RST, and the source and drain (S/D) sides of the SF, the SEL, the other in-pixel devices.

As described above, the DCG device may be connected between the RST device and the FD as shown in FIG. 7. FIG. 8 shows a top view of an example circuit layout formed on a semiconductor substrate for the imaging device shown in FIG. 7 according to another embodiment of the present invention. It should be noted that the width of the sidewall spacer 74 and the width of the right side (the side where wiring shown as a bold line is arranged between the FD and the DCG) of the sidewall spacer 75 are wider than the width of the left, upper, and lower sides (the sides where wiring is not arranged between the FD and the DCG) of the sidewall spacer 75, and the width of the

sidewall spacers

71, 72, and 73. In FIG. 5, the RST is a device other than the TX and is arranged adjacent to the FD. In FIG. 8, the DCG is a device other than the TX and is arranged adjacent to the FD.

The imaging devices in FIG. 2 and FIG. 7 include one PD. However, in-pixel devices may be shared by multiple PDs. The imaging device in FIG. 9 includes two sets of the PDs and the TXs, and the other in-pixel devices are shared. The imaging device in FIG. 10 includes four sets of the PDs and the TXs, and the other in-pixel devices are shared. FIG. 11 shows a top view of an example circuit layout formed on a semiconductor substrate for the imaging device shown in FIG. 10 according to another embodiment of the present invention. It should be noted that the width of the sidewall spacers 74 and the width of the lower side (the side where wiring shown as a bold line is arranged between the FD and the DCG) of the sidewall spacer 75 are wider than the width of the left, right, and upper sides (the sides where wiring is not arranged between the FD and the DCG) of the sidewall spacer 75, and the width of the

sidewall spacers

71, 72, and 73. The embodiments of the present invention can be applied for more than 4 sets of the PDs and the TXs that share the in-pixel devices as well.

In FIG. 4, the difference between the sidewall spacer width of the TX and the sidewall spacer width of the other in-pixel devices is made by a source/drain (S/D) sidewall spacer as shown in FIG. 12. Material of the S/D sidewall spacer can be oxide (SiO2) , silicon nitride (Si3N4) , silicon oxynitride (SiON) or other insulator material. The S/D sidewall spacer can be single or multiple layers. The above difference may be made by a gate offset spacer as shown in FIG. 13. Material of the gate offset spacer can be oxide (SiO2) , silicon nitride (Si3N4) , silicon oxynitride (SiON) or other insulator material. A manufacturing process for the latter case will be described below with reference to FIG. 14 to FIG. 21, and a manufacturing process for the former case will be described below with reference to FIG. 22 to FIG. 25.

With reference to FIG. 14 to FIG. 21, the following describes an example of a manufacturing process of an imaging device according to an embodiment of the present invention. FIG. 14 to FIG. 21 show examples of a first to eighth cross-sectional views of a substrate on which an imaging device is manufactured.

Referring to FIG. 14, a raw material, for example, a semiconductor substrate 10 is provided. In order to prevent interference with neighboring imaging devices, a shallow trench isolation (STI) process is carried out to form

field oxide films

21 and 22 in the substrate 10. In another embodiment, each device can be separated only by impurities without the STI. A mask is formed to expose the region where a PD is to be formed, and ion impurities are implanted into the substrate 10 to form a PD extending to a predetermined depth. In the case of n-type photodiode, phosphorus or arsenic or a combination thereof is implanted, and Boron or BF2 is used for isolation. In the case of p-type photodiode, Boron or BF2 are implanted and phosphorus or arsenic or a combination thereof is used for isolation.

Next, referring to FIG. 15, a gate insulation film is formed on the substrate 10, a conductive film is formed thereon, a patterning process is carried out to form gate patterns 41 to 44 (the gate insulation film is separated into 31 to 34) , and a resist pattern is removed.

Next, as shown in FIG. 16, an insulation film is formed over the substrate 10 for gate offset spacer deposition. Material of this insulation film can be oxide (SiO2) , silicon nitride (Si3N4) , silicon oxynitride (SiON) or other insulator material As shown in FIG. 17, a mask is formed to cover the PD and the TX. In addition to the PD and the TX, the mask may be formed to cover the right half of the RST. As shown in FIG. 18, the insulation film in the area where the mask is not formed is etched to some extent by isotropic etching, and a thin film remains.

Next, referring to FIG. 19, the mask is removed, and the upper side of the thick film which covers the PD and the TX is etched by anisotropic etching. The upper side of the thin film is over-etched. A first ion-implantation mask is formed to cover the PD and the TX, and lightly doped regions 51 to 54 are formed at both sides of the SEL, SF, and RST by injecting ion impurities, and the first ion-implantation mask is removed.

Next, referring to FIG. 20, an insulation film is formed over the substrate 10 and then etched to form spacers 71a to 74b at the both sides of the SEL, SF, RST, and TX. Material of this insulation file can be can be oxide (SiO2) , silicon nitride (Si3N4) , silicon oxynitride (SiON) or other insulator material. A second ion-implantation mask is formed to cover the PD and the TX. Ion impurities are implanted into the substrate 10 to form heavily doped regions 61 to 64, and the FD. In the case of n-type photodiode, n-type conductive layers are made, and in the case of p-type photodiode, p-type conductive layers are made. The heavily doped regions 61 to 64 are self-aligned to their corresponding spacers, and the lightly doped region 52 between the SEL and the SF is divided into two parts and the lightly doped region 53 between the SF and the RST is divided into two parts. The second ion-implantation mask is removed.

Next, referring to FIG. 21, back end of line (BEOL) process is carried out, and metallic interconnections 81 to 88 are formed. Namely, a thick insulation file is formed, contact holes are formed, and a metallic film is deposited and patterned. Then, the imaging device placed on the substrate 10 is connected to a logic circuit placed on another substrate 11 by bonding such as copper to copper bonding or other inter-silicon wafer connections.

Then, deep trench isolations (DTIs) 91 and 92 are formed, in order to decrease crosstalk between the PDs.

Metal grids

101 and 102 are placed on an insulation film of the back of the substrate 10 at the border of the pixels, in order to restrain a flare and a ghost. Color filters are provided within a layer 110 at the position corresponding to the PDs.

Microlens

121 and 122 are provided at the position corresponding to the PDs. For example, there may be different sizes of the PDs, and the PDs may be arranged in staggered positions in the horizontal direction of FIG. 21.

With reference to FIG. 22 to FIG. 25, the following describes an example of another manufacturing process of an imaging device according to an embodiment of the present invention. FIG. 22 to FIG. 25 show examples of a first to fourth cross-sectional views of a substrate on which an imaging device is manufactured.

Referring to FIG. 22, after the same process as described with reference to FIG. 14 to FIG. 16 is performed, the upper side of the insulation film is etched by anisotropic etching, a first ion-implantation mask is formed to cover the PD and the TX, lightly doped regions are formed at both sides of the SEL, SF, and RST by injecting ion impurities, and the first ion-implantation mask is removed. An insulation film is formed over the substrate 10. Material this insulation film can be oxide (SiO2) , silicon nitride (Si3N4) , silicon oxynitride (SiON) or other insulator material.

Next, referring to FIG. 23, a mask is formed to cover the PD and the TX. In addition to the PD and the TX, the mask may be formed to cover the right half of the RST. The film in the area where the mask is not formed is etched to some extent by isotropic etching, and a thin film remains.

Next, referring to FIG. 24, the mask is removed, and the upper side of the insulation film is etched by anisotropic etching, and the upper side of the thin film is over-etched.

Next, referring to FIG. 25, a second ion-implantation mask is formed to cover the PD and the TX, ion impurities are implanted into the substrate to form heavily doped regions 61 to 64 of N-type conductive layers, and the FD. The heavily doped regions 61 to 64 are self-aligned to their corresponding spacers, and the lightly doped region 52 between the SEL and the SF is divided into two parts and the lightly doped region 53 between the SF and the RST is divided into two parts. The second ion-implantation mask is removed. After that, the same process as described with reference to FIG. 21 is performed.

The imaging device according to the embodiments of the present application can be applied to an imaging system 201 such as a camera system. FIG. 26 shows another example block diagram of an imaging system 201. The imaging system 201 includes an optical system 202 such as one or more lens, a shutter device 203, a solid-state image sensor 204, a control circuit 205, a signal processing circuit 206, a monitor 207, and a memory 208. The solid-state image sensor 204 includes, for example, the pixel array 209 and the readout circuit 210 in FIG. 1, and obtains image data of a subject through the lens 202 and the shutter device 203, under the control of the control circuit 205. The signal processing circuit 206 outputs the obtained image data to the monitor 207 or stores the image data in the memory 208.

FIG. 27 shows various applications for a camera system. The imaging device according to the embodiment of the present invention can be applied to, for example, a mobile phone camera, a digital camera, a network camera, a security and surveillance camera, a video camcorder, an automotive and transport camera, a medical camera, and machine visions.

The embodiment of the present invention can be applied to array devices and different substrates such as bulk silicon, silicon-on-insulator substrate, silicon-germanium substrate, and other photosensitive substrates.

The embodiment of the present invention can reduce GIDL in a floating diffusion node, leading to better fixed pattern noise. This allows to tighten pixel device related design rule, and improve source follower device ransom noise and RTS noise by enlarging the device size. Wider sidewall spacer of the TX can enhance conversion gain because of lower parasitic capacitance, which will result in lower pixel and circuit noise.

What is disclosed above are merely exemplary embodiments of the present invention, and are certainly not intended to limit the protection scope of the present invention. A person of ordinary skill in the art may understand that all or some of the processes that implement the foregoing embodiments and equivalent modifications made in accordance with the claims of the present invention shall fall within the scope of the present invention.

Claims

An imaging device, comprising a plurality of pixels, wherein each pixel comprises a transfer gate device, a reset device, a source follower device, and a row select device,

wherein a sidewall spacer width of the transfer gate device is wider than a sidewall spacer width of other in-pixel devices.
The imaging device according to claim 1, wherein a difference between the sidewall spacer width of the transfer gate device and the sidewall spacer width of the other in-pixel devices is equal to or greater than 3 nanometers.
An imaging device, wherein

a sidewall spacer width of a transfer gate device and a sidewall spacer width of a source side of an adjacent device, which is a device other than the transfer gate device and is arranged adjacent to a floating diffusion, are wider than the sidewall spacer width of a drain side of the adjacent device, and the sidewall spacer width of a source follower device, a row-select device, and other in-pixel devices.
The imaging device according to claim 3, wherein the sidewall spacer width of the transfer gate device and the sidewall spacer width of the source side of the adjacent device are wider than the sidewall spacer width of a drain side of the adjacent device, and the sidewall spacer width of a source follower device, a row-select device, and other in-pixel devices by 3 nanometers or more.
An imaging device, comprising a plurality of pixels, wherein each pixel comprises a transfer gate device, a reset device, a source follower device, and a row select device,

wherein a gate offset spacer width of the transfer gate device is wider than a gate offset spacer width of other in-pixel devices.
The imaging device according to claim 5, wherein a difference between the gate offset spacer width of the transfer gate device and the gate offset spacer width of the other in-pixel devices is equal to or greater than 3 nanometers.
An imaging device, wherein

a gate offset spacer width of a transfer gate device and a gate offset spacer width of a source side of an adjacent device, which is a device other than the transfer gate device and is arranged adjacent to a floating diffusion, are wider than the gate offset spacer width of a drain side of the adjacent device, and the gate offset spacer width of a source follower device, a row-select device, and other in-pixel devices.
The imaging device according to claim 7, wherein the gate offset spacer width of the transfer gate device and the gate offset spacer width of the source side of the adjacent device are wider than the gate offset spacer width of a drain side of the adjacent device, and the gate offset spacer width of a source follower device, a row-select device, and other in-pixel devices by 3 nanometers or more.
A manufacturing method of an imaging device, comprising:

forming gate offset spacers at both sides of a transfer gate device and other in-pixel devices;

forming an insulation film over the transfer gate device and the other in-pixel devices;

etching the insulation film over the other in-pixel devices by isotropic etching; and

etching the insulation film over the transfer gate device and the other in-pixel devices by anisotropic etching.
A manufacturing method of an imaging device, comprising:

forming gate offset spacers at both sides of a transfer gate device, an adjacent device which is a device other than the transfer gate device and is arranged adjacent to a floating diffusion, and other in-pixel devices;

forming an insulation film over the transfer gate device, the adjacent device, and the other in-pixel devices;

etching the insulation film over the other in-pixel devices and a drain side of the adjacent device by isotropic etching; and

etching the insulation film over the transfer gate device, the adjacent device, and the other in-pixel devices by anisotropic etching.
A manufacturing method of an imaging device, comprising:

forming an insulation film over a transfer gate device and other in-pixel devices;

etching the insulation film over the other in-pixel devices by isotropic etching;

etching the insulation film over the transfer gate device and the other in-pixel devices by anisotropic etching; and

forming sidewall spacers at both sides of the transfer gate device and the other in-pixel devices.
A manufacturing method of an imaging device, comprising:

forming an insulation film over a transfer gate device, an adjacent device which is a device other than the transfer gate device and is arranged adjacent to a floating diffusion, and other in-pixel devices;

etching the insulation film over the other in-pixel devices and a drain side of the adjacent device by isotropic etching;

etching the insulation film over the transfer gate device, the adjacent device, and the other in-pixel devices by anisotropic etching; and

forming sidewall spacers at both sides of the transfer gate device, the adjacent device, and the other in-pixel devices.