WO2022095580A1 - 供电电路、供电方法、音频功率放大器和集成电路 - Google Patents

供电电路、供电方法、音频功率放大器和集成电路 Download PDF

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Publication number
WO2022095580A1
WO2022095580A1 PCT/CN2021/116871 CN2021116871W WO2022095580A1 WO 2022095580 A1 WO2022095580 A1 WO 2022095580A1 CN 2021116871 W CN2021116871 W CN 2021116871W WO 2022095580 A1 WO2022095580 A1 WO 2022095580A1
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Prior art keywords
circuit
reference voltage
count value
voltage range
audio
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PCT/CN2021/116871
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English (en)
French (fr)
Inventor
卢杰
柯毅
刘德珩
马可铮
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武汉市聚芯微电子有限责任公司
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Priority to CN202180042318.4A priority Critical patent/CN115943562B/zh
Priority to US18/266,256 priority patent/US20240106394A1/en
Publication of WO2022095580A1 publication Critical patent/WO2022095580A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H03F1/0216—Continuous control
    • H03F1/0222—Continuous control by using a signal derived from the input signal
    • H03F1/0227—Continuous control by using a signal derived from the input signal using supply converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/181—Low-frequency amplifiers, e.g. audio preamplifiers
    • H03F3/183—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only
    • H03F3/187—Low-frequency amplifiers, e.g. audio preamplifiers with semiconductor devices only in integrated circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
    • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
    • H03F3/217—Class D power amplifiers; Switching amplifiers
    • H03F3/2173—Class D power amplifiers; Switching amplifiers of the bridge type
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/03—Indexing scheme relating to amplifiers the amplifier being designed for audio applications
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/511—Many discrete supply voltages or currents or voltage levels can be chosen by a control signal in an IC-block amplifier circuit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/78—A comparator being used in a controlling circuit of an amplifier

Definitions

  • the invention relates to the technical field of power amplifiers, and in particular, to a power supply circuit, a method, an audio power amplifier and an integrated circuit.
  • the audio power amplifier In the application process of the audio power amplifier, its output power will be limited by the output voltage of its own power supply.
  • a boosted DC-DC (DC-DC) circuit or a charge-pump (Charge-Pump) circuit is used as the audio power amplifier.
  • the power supply circuit can increase the power supply voltage of the audio power amplifier to achieve the purpose of increasing the output signal amplitude of the audio power amplifier, thereby increasing the output power.
  • embodiments of the present invention provide a power supply circuit, a power supply method, an audio power amplifier, and an integrated circuit.
  • a power supply circuit for an audio power amplifier comprising: a detection sub-circuit for detecting a voltage of an audio signal input to the audio power amplifier, the voltage of the audio signal corresponding to the audio frequency output power of the power amplifier; a control sub-circuit for determining a target reference voltage range according to a voltage range of the audio signal within a predetermined period, the target reference voltage range being selected from a plurality of predetermined reference voltage ranges, and the audio a voltage range of the signal within the predetermined period is included in the target reference voltage range; and a power supply circuit for generating a power supply matching the output power of the audio power amplifier based on the target reference voltage range voltage to power the audio power amplifier.
  • the plurality of predetermined reference voltage ranges include a first reference voltage range and a second reference voltage range, and a lower limit of the first reference voltage range is greater than a lower limit of the second reference voltage range value, the upper limit value of the first reference voltage range is smaller than the upper limit value of the second reference voltage range.
  • control sub-circuit includes: a first comparison circuit for selecting a reference voltage range from the plurality of predetermined reference voltage ranges to be the same as the audio signal detected by the detection sub-circuit Voltage comparison; a counting circuit for counting when the first comparison circuit determines that the voltage of the audio signal exceeds the reference voltage range selected by the first comparison circuit. The count value of the counting circuit is fed back to the first comparison circuit, and the first comparison circuit selects the next predetermined reference voltage range based on the count value of the counting circuit until the voltage of the audio signal falls within the desired range. within the reference voltage range selected by the first comparison circuit.
  • the first comparison circuit includes: a first data selector for selecting and outputting an upper limit value of one of the plurality of predetermined reference voltage ranges; a first comparator whose non-inverting input The terminal receives the voltage of the audio signal detected by the detection sub-circuit, the negative input terminal receives the output of the first data selector; the second data selector is used to select and output the plurality of predetermined reference a lower limit value of one of the voltage ranges; and a second comparator, the positive-phase input terminal of which receives the output of the second data selector, and the negative-phase input terminal receives the voltage of the audio signal detected by the detection sub-circuit .
  • the counting circuit includes: a first logical OR circuit for performing a logical OR operation on the output of the first comparator and the output of the second comparator; and a counter for all The output signal of the first logical OR circuit is counted.
  • the count value of the counter is fed back to the first data selector and the second data selector, and the first data selector and the second data selector are selected from the plurality of data selectors based on the count value.
  • a corresponding reference voltage range is selected from the predetermined reference voltage ranges.
  • control sub-circuit further includes: a second comparison circuit for comparing the voltage of the audio signal detected by the detection sub-circuit with a control voltage; an edge detection circuit for passing detecting the output of the second comparison circuit to determine the moment when the audio signal intersects the contrast voltage, thereby determining the predetermined period; and a trigger circuit for determining the audio signal and the reference voltage in the edge detection circuit
  • a second comparison circuit for comparing the voltage of the audio signal detected by the detection sub-circuit with a control voltage
  • an edge detection circuit for passing detecting the output of the second comparison circuit to determine the moment when the audio signal intersects the contrast voltage, thereby determining the predetermined period
  • a trigger circuit for determining the audio signal and the reference voltage in the edge detection circuit
  • control voltage is the common mode voltage of the audio signal.
  • the edge detection circuit determines when the audio signal crosses over and/or under the control voltage by detecting a rising edge and/or a falling edge of the output signal of the second comparison circuit .
  • the edge detection circuit further outputs a reset signal to the counting circuit to reset the count value of the counting circuit when it is determined that the audio signal intersects the contrast voltage.
  • control sub-circuit further includes: a third comparison circuit, configured to compare the current count value of the counting circuit with the count value stored by the trigger circuit, so as to determine the difference between the counting circuit and the counting circuit. Whether the reference voltage range corresponding to the current count value increases or decreases relative to the reference voltage range corresponding to the count value stored by the trigger circuit.
  • the third comparison circuit determines that the reference voltage range corresponding to the current count value of the counting circuit is increased relative to the reference voltage range corresponding to the count value stored by the trigger circuit, and the edge detection circuit determines that the When the audio signal crosses the contrast voltage, the trigger circuit updates the count value stored by the trigger circuit with the current count value of the count circuit, and outputs the count value.
  • control sub-circuit further includes: a delay circuit for determining, in the third comparison circuit, a reference voltage range corresponding to the current count value of the counting circuit relative to the value stored in the trigger circuit
  • a delay circuit for determining, in the third comparison circuit, a reference voltage range corresponding to the current count value of the counting circuit relative to the value stored in the trigger circuit
  • the third comparison circuit still determines that the reference voltage range corresponding to the current count value of the counting circuit is reduced relative to the reference voltage range corresponding to the count value stored by the trigger circuit, and the When the edge detection circuit determines that the audio signal and the contrast voltage intersect, the trigger circuit updates the count value stored in the trigger circuit with the current count value of the count circuit, and outputs the count value.
  • the power supply circuit adjusts a resistance value of a feedback resistor in the power supply circuit according to a signal received from the control subcircuit indicating the target reference voltage range to produce a value that is consistent with the The output power of the audio power amplifier is matched to the voltage.
  • the power supply electronics circuit selects the reference voltage for use in the power supply electronics circuit based on a signal received from the control sub-circuit indicating the target reference voltage range to generate a voltage compatible with the audio power amplifier the output power to match the voltage.
  • a method of supplying power to an audio power amplifier comprising: detecting a voltage of an audio signal input to the audio power amplifier, the voltage of the audio signal corresponding to the output power of the audio power amplifier; A target reference voltage range is determined according to a voltage range of the audio signal within a predetermined period, the target reference voltage range is selected from a plurality of predetermined reference voltage ranges, and the voltage range of the audio signal within the predetermined period is included within the target reference voltage range; and based on the target reference voltage range, generating a supply voltage matching the output power of the audio power amplifier to power the audio power amplifier.
  • determining the target reference voltage range includes: selecting, by the first comparison circuit, a reference voltage range from the plurality of predetermined reference voltage ranges to compare with the voltage of the audio signal; Count when the voltage of the audio signal exceeds the selected reference voltage range.
  • the first comparison circuit selects the next predetermined reference voltage range based on the count value of the counting circuit until the voltage of the audio signal falls within the selected reference voltage range.
  • determining the target reference voltage range further comprises: comparing, by a second comparison circuit, the voltage of the audio signal with a control voltage; determining, by an edge detection circuit, the output of the second comparison circuit determining the predetermined period of time when the audio signal crosses the contrast voltage; and determining the audio signal crosses the contrast voltage by the trigger circuit in the edge detection circuit, and the current count value of the counting circuit
  • the count value stored by the trigger circuit is different, the count value stored by the trigger circuit is updated with the current count value of the count circuit, and the count value is output, and the count value output by the trigger circuit indicates the target reference voltage range.
  • the method further includes providing a reset signal to the counting circuit to reset the count value of the counting circuit when the edge detection circuit determines that the audio signal intersects the contrast voltage.
  • determining the target reference voltage range further includes: comparing, by a third comparison circuit, the current count value of the counting circuit with the count value stored by the trigger circuit to determine the current count value of the counting circuit.
  • the reference voltage range corresponding to the value increases or decreases relative to the reference voltage range corresponding to the count value stored by the trigger circuit; and when the third comparison circuit determines the reference voltage corresponding to the current count value of the count circuit.
  • the range is increased with respect to the reference voltage range corresponding to the count value stored by the trigger circuit, and when the edge detection circuit determines that the audio signal intersects the reference voltage, the trigger circuit uses the count circuit's output signal.
  • the current count value updates the count value stored in the flip-flop circuit, and outputs the count value.
  • determining the target reference voltage range further includes: determining, in the third comparison circuit, a reference voltage range corresponding to the current count value of the counting circuit relative to a reference corresponding to the count value stored by the trigger circuit
  • the delay circuit starts timing a predetermined time period; and when the predetermined time period elapses, the third comparison circuit still determines that the reference voltage range corresponding to the current count value of the counting circuit is relative to the trigger
  • the reference voltage range corresponding to the count value stored in the circuit is reduced, and when the edge detection circuit determines that the audio signal intersects the reference voltage, the trigger circuit updates the trigger with the current count value of the count circuit
  • the circuit stores the count value and outputs the count value.
  • generating a supply voltage that matches the output power of the audio power amplifier includes adjusting a resistance value of a feedback resistor for use in an electronic circuit or selecting the electronic circuit according to the target reference voltage range The reference voltage used in to generate a voltage that matches the output power of the audio power amplifier.
  • an audio power amplifier comprising: an audio power amplifying circuit; and the above-mentioned power supply circuit for supplying power to the audio power amplifying circuit.
  • an integrated circuit including the audio power amplifier described above.
  • an electronic device comprising: the above-mentioned audio power amplifier, which receives an audio signal and power-amplifies the audio signal; and a speaker, which plays the audio signal.
  • the power supply circuit detects the output power of the audio power amplifier, and generates a power supply voltage that matches the output power of the audio power amplifier, so as to realize the adaptive adjustment of the output voltage of the power supply circuit.
  • the power supply circuit can reduce the output power supply voltage, so that the power supply circuit in the power supply circuit and the power tube in the audio power amplifier flow through the power tube. The current is reduced, thereby reducing the conduction loss caused to the power tube in the power supply circuit and the power tube in the audio power amplifier, improving the power supply efficiency of the power supply circuit and the working efficiency of the audio power amplifier.
  • FIG. 1 is a structural block diagram of a power supply circuit according to an embodiment of the present invention.
  • FIG. 2 is a circuit diagram of an audio power amplifier according to an embodiment of the present invention.
  • FIG. 3 is a block diagram of a control sub-circuit according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram illustrating the timing of outputting a pulse signal by an edge detection circuit according to an embodiment of the present invention
  • FIG. 5 is a block diagram of a control sub-circuit according to another embodiment of the present invention.
  • FIG. 6 is a circuit diagram of a control sub-circuit according to an embodiment of the present invention.
  • FIG. 7 is a circuit diagram of a power supply circuit according to an embodiment of the present invention.
  • FIG. 8 is a circuit diagram of a feedback resistance adjusting component in a power supply circuit according to an embodiment of the present invention.
  • FIG. 9 is a circuit diagram of a reference voltage adjustment component of a power supply electronic circuit according to an embodiment of the present invention.
  • FIG. 10 is a schematic diagram of the output voltage of the electronic power supply circuit changing with the output voltage of the audio power amplifier according to an embodiment of the present invention
  • FIG. 11 is a block diagram of an audio power amplifier according to an embodiment of the present invention.
  • FIG. 12 is a flowchart of a method of powering an audio power amplifier according to an embodiment of the present invention.
  • the output voltage (ie, the power supply voltage) of the power supply circuit of the audio power amplifier is usually a constant voltage.
  • the output voltage of the power supply circuit is usually a larger Voltage.
  • the power supply circuit still supplies the audio power amplifier with a large voltage, which will make the current flowing through the power tube in the power supply circuit larger, causing the power tube on the power tube.
  • the conduction loss of the audio power amplifier is relatively large; in addition, the output power of the audio power amplifier is small, and the power supply voltage for the audio power amplifier is relatively large, which will cause the driving loss of the audio power amplifier (that is, the power tube in the audio power amplifier). current) is larger, which in turn reduces the working efficiency of the audio power amplifier.
  • the power supply circuit detects the output power of the audio power amplifier, and generates a power supply voltage that matches the output power of the audio power amplifier, thereby realizing the output voltage adaptation of the power supply circuit.
  • the power supply circuit can reduce the output power supply voltage, so that the power tube in the power supply circuit and the power in the audio power amplifier The current flowing through the tube is reduced, thereby reducing the conduction loss caused to the power tube in the power supply circuit and the power tube in the audio power amplifier, improving the power supply efficiency of the power supply circuit, and improving the audio power amplifier. work efficiency.
  • An embodiment of the present invention provides a power supply circuit, which is applied to an audio power amplifier 1 (see FIG. 2 ). As shown in FIG.
  • the detection sub-circuit 11 is used to detect the voltage of the audio signal input to the audio power amplifier 1, hereinafter referred to as the first voltage, and the output power of the audio power amplifier 1 can be determined based on the first voltage.
  • the control sub-circuit 12 is configured to determine a target reference voltage range according to a range of voltages of the audio signal within a predetermined period, the target reference voltage range being selected from a plurality of predetermined reference voltage ranges and including the The voltage range of the audio signal.
  • the electronic circuit 13 is configured to generate a supply voltage matching the output power of the audio power amplifier 1 based on the target reference voltage range, so as to supply power to the audio power amplifier 1 .
  • the power supply voltage generated by the electronic circuit 13 that matches the output power of the audio power amplifier 1 means: when the output power of the audio power amplifier 1 is small, the voltage generated by the electronic circuit 13 is small; when the output power of the audio power amplifier 1 is large , the voltage generated by the electronic circuit 13 is large; that is, the voltage generated by the electronic circuit 13 increases as the output power of the audio power amplifier 1 increases, and decreases as the output power of the audio power amplifier 1 decreases; in this way, the power supply is realized.
  • the adaptive adjustment of the output voltage of the circuit 10 can improve the power supply efficiency of the power supply circuit 10 and the working efficiency of the audio power amplifier 1 .
  • the audio power amplifier 1 may be a digital audio power amplifier or an analog audio power amplifier.
  • the power supply circuit 13 may be a boost-type DC-DC circuit or a Charge-Pump circuit.
  • the first voltage of the audio signal input to the audio power amplifier 1 may be detected in a suitable manner.
  • FIG. 2 shows an embodiment in which the audio power amplifier 1 is a class D audio power amplifier including a class D audio power amplifier circuit 20 , wherein the power supply circuit 10 supplies power to the class D audio power amplifier circuit 20 . Since the class D audio power amplifier 1 has a structure of double-ended input and double-ended output, in order to detect the first voltage, it is necessary to convert the dual-circuit voltage signal input to the audio power amplifier 1 into a single-circuit voltage signal; therefore, as shown in Figure 2 As shown, the detection sub-circuit 11 may include an operational amplifier OPAMP3 and a plurality of resistors R S1 , R S2 .
  • the gain of the voltage from input to output can be calculated by the following formula:
  • a Class_D represents the gain of the audio power amplifier 1 from the input voltage to the output voltage
  • R fb , R in , R 1 , R 4 , R 5 and R 6 represent each of the two channels included in the audio power amplifier resistor on.
  • the gain of the voltage from input to output can be calculated by the following formula:
  • a sig represents the gain of the detection sub-circuit 11 from the input voltage to the output voltage
  • R fb represents the resistance of the input buffer of each channel of the two channels included in the audio power amplifier 1
  • R S1 and R S2 represent the detection sub-circuit 11 Resistors on each of the two input channels included.
  • V o_Class_D represents the output voltage of the audio power amplifier 1
  • V sig represents the output voltage of the detection sub-circuit 11
  • V sig is the first voltage detected by the detection sub-circuit 11 .
  • P o_Class_D represents the output power of the audio power amplifier 1
  • P o_sig represents the output power of the detection sub-circuit 11 .
  • the output power P o_Class_D of the audio power amplifier 1 can be determined based on formula (5), that is, the output power of the audio power amplifier 1 can be detected by detecting the first voltage.
  • the control sub-circuit 12 may include a first comparison circuit 31 and a counting circuit 32 .
  • the first comparison circuit 31 may select one reference voltage range from a plurality of predetermined reference voltage ranges to compare with the first voltage of the audio signal detected by the detection sub-circuit 11 .
  • the counting circuit 32 may count when the first comparison circuit 31 determines that the first voltage of the audio signal exceeds the reference voltage range selected by the first comparison circuit 31 .
  • the count value of the counting circuit 32 can be fed back to the first comparison circuit 31, and the first comparison circuit 31 can select the next predetermined reference voltage range based on the count value of the counting circuit 32 until the first voltage of the audio signal falls within the first comparison circuit within the reference voltage range selected by the circuit 31 .
  • control sub-circuit 12 may further include a second comparison circuit 34 , an edge detection circuit 35 and a trigger circuit 33 .
  • the second comparison circuit 34 may compare the first voltage of the audio signal detected by the detection sub-circuit 11 with a control voltage such as the common mode voltage V cm of the audio signal.
  • the edge detection circuit 35 can determine the predetermined period by detecting the output of the second comparison circuit 34 to determine that the audio signal crosses the reference voltage, that is, the moment when the first voltage of the audio signal is equal to the reference voltage .
  • the trigger circuit 33 updates the trigger with the current count value of the count circuit 32 when the edge detection circuit 35 determines that the audio signal intersects the control voltage and the current count value of the count circuit 32 is different from the count value stored in the trigger circuit 33
  • the count value stored in the circuit 33 is outputted.
  • the count value output by the trigger circuit 33 indicates the target reference voltage range determined by the control sub-circuit 12 .
  • the detection sub-circuit 11 outputs the first voltage to the control sub-circuit 12 after detecting the first voltage of the audio signal; the control sub-circuit 12 determines the difference between the preset X reference voltage ranges and the first voltage within the predetermined period
  • a target reference voltage range corresponding to the range, the target reference voltage range is represented by a target code
  • the voltage range of the audio signal (also referred to as the first signal hereinafter) input to the audio power amplifier 1 is implemented in time domain segmentation coding, That is, the range of the voltage amplitude of the first signal within a predetermined period is encoded; different encodings correspond to different ranges of the voltage amplitude of the first signal, which in turn correspond to different output power ranges of the audio power amplifier 1, that is, to realize the audio power
  • the different ranges of the output power of the amplifier 1 are encoded; in this way, the voltage amplitude of the first signal can be converted from an analog quantity to a digital quantity (that is, the encoding), and then the voltage amplitude
  • the first comparison circuit 31 may include multiple data selectors (Multiplexer), and X number of data selectors may be preset in the first comparison circuit 31 by configuring the data selectors reference voltage ranges, and each of the X reference voltage ranges corresponds to a code.
  • the first comparison circuit 31 may include a first data selector MUX1 and a second data selector MUX2. Both the first data selector MUX1 and the second data selector MUX2 are X data selectors, and the value of X can be 4, 6, 8, 16, etc.
  • the first data selector MUX1 is used to output the upper limit voltage of one of the X reference voltage ranges
  • the second data selector MUX2 is used to output the lower limit voltage of one of the X reference voltage ranges
  • each reference voltage in the X reference voltage ranges The code corresponding to the range can be represented by the channel corresponding to the upper limit voltage and the lower limit voltage of the reference voltage range.
  • the control sub-circuit 12 may be a digital circuit
  • the coding of the reference voltage range may be binary coding
  • the number of bits of the coding is equal to log 2 X.
  • the code is a 3-bit binary code
  • the channels 0-7 of the first data selector MUX1 correspond to the reference voltages Vref1H-Vref8H respectively, and Vref1H ⁇ Vref2H ⁇ Vref3H ⁇ Vref4H ⁇ Vref5H ⁇ Vref6H ⁇ Vref7H ⁇ Vref8H.
  • Channels 0-7 of the second data selector MUX2 correspond to the reference voltages Vref1L-Vref8L respectively, and Vref1L>Vref2L>Vref3L>Vref4L>Vref5L>Vref6L>Vref7L>Vref8L.
  • the X reference voltage ranges can be respectively represented as Vref1 (Vref1L, Vref1H), Vref2 (Vref2L, Vref2H), Vref3 (Vref3L, Vref3H), Vref4 (Vref4L, Vref4H), Vref5 (Vref5L, Vref5H), Vref6 (Vref6L, Vref6H), Vref7 (Vref7L, Vref7H), and Vref8 (Vref8L, Vref8H), and Vref8 contains Vref7, Vref7 contains Vref6, Vref6 contains Vref5, Vref5 contains Vref4, Vref4 contains Vref3, Vref3 contains Vref2, and Vref2 contains Vref1.
  • the reference voltage range Vref1 (Vref1L, Vref1H) corresponds to code 000 (representing the 0th channel)
  • the reference voltage range Vref2 (Vref2L, Vref2H) corresponds to the code 001 (representing the 1st channel)
  • the reference voltage range Vref8 (Vref8L, Vref8H) corresponds to Code 111 (representing the 7th channel).
  • the first comparison circuit 31 may further include a plurality of comparators (Comparator), such as the first comparator COMP1 and the second comparator COMP2 shown in FIG. 6 , the first comparator COMP1 compares the first voltage Vsig with the predetermined reference voltage range. The upper limit voltage is compared, and the second comparator COMP2 compares the first voltage Vsig with the lower limit voltage of the predetermined reference voltage range.
  • the non-inverting input terminal of the first comparator COMP1 may receive the first voltage Vsig, and the inverting input terminal may receive the upper limit voltage of the predetermined reference voltage range output by the first data selector MUX1.
  • the first comparator COMP1 If the first voltage Vsig is greater than the upper limit voltage of the predetermined reference voltage range currently selected by the first data selector MUX1, the first comparator COMP1 outputs a high level; if the first voltage Vsig is smaller than the predetermined reference voltage range currently selected by the first data selector MUX1 The upper limit voltage of the reference voltage range, the first comparator COMP1 outputs a low level.
  • the non-inverting input terminal of the second comparator COMP2 can receive the lower limit voltage of the predetermined reference voltage range output by the second data selector MUX2, and the inverting input terminal can receive the first voltage Vsig.
  • the second comparator COMP2 If the lower limit voltage of the predetermined reference voltage range currently selected by the second data selector MUX2 is greater than the first voltage Vsig, the second comparator COMP2 outputs a high level; if the lower limit voltage of the predetermined reference voltage range currently selected by the second data selector MUX2 If the voltage is lower than the first voltage Vsig, the second comparator COMP2 outputs a low level.
  • a high level may represent data "1”
  • a low level may represent data "0".
  • the counting circuit 32 may include a first logical OR device OR1 and a counter (Counter) CT1.
  • the counter CT1 may be a binary counter, the number of bits of which may be equal to the number of bits of the code representing the reference voltage range predefined in the first comparison circuit 31 .
  • the relationship can be: Vref1 (Vref1L, Vref1H) corresponds to code 000, Vref2 (Vref2L, Vref2H) corresponds to code 001, Vref3 (Vref3L, Vref3H) corresponds to code 010, Vref4 (Vref4L, Vref4H) corresponds to code 011, Vref5 (Vref5L, Vref5H) Corresponding to code 100, Vref6 (Vref6L, Vref6H) corresponds to code 101, Vref7 (Vref7L, Vref7H) corresponds to code 110, and Vref8 (Vref8L, Vref8H) corresponds to code 111
  • the first logical OR device OR1 may perform a logical OR operation on the output of the first comparator COMP1 and the output of the second comparator COMP2. That is to say, when the first voltage Vsig is greater than the upper limit voltage selected by the first data selector MUX1 or smaller than the lower limit voltage selected by the second data selector MUX2, the first logic OR device OR1 outputs a high level; when the first voltage Vsig When falling within the voltage range defined by the upper limit voltage selected by the first data selector MUX1 and the lower limit voltage selected by the second data selector MUX2, the first logical OR device OR1 outputs a low level.
  • the counter CT1 counts when the first voltage Vsig exceeds the voltage range selected by the first data selector MUX1 and the second data selector MUX2 to generate a 3-bit counter code Q ⁇ 2:0>.
  • the counter code Q ⁇ 2:0> is fed back to the first comparison circuit 31, and the first data selector MUX1 and the second data selector MUX2 select the corresponding reference voltage range based on the counter code Q ⁇ 2:0> until the first voltage
  • both the first comparator COMP1 and the second comparator COMP2 output a low level, and the count value of the counter CT1 does not change any more .
  • the count code of the counter CT1 may be 000, and the first data selector MUX1 and the second data selector MUX2 select the minimum reference voltage range Vref1 (Vref1L, Vref1H) corresponding to the code 000.
  • the counter CT1 may be reset to the initial code of 000.
  • the audio signal provided to the audio power amplifier 1, that is, the first signal is usually a sinusoidal AC voltage signal, and the edge detection circuit 35 is substantially used to perform edge detection on the first signal.
  • the second comparison circuit 34 may include a third comparator COMP3 that compares the first voltage Vsig with a reference voltage such as the common mode voltage Vcm of the first signal, hereinafter the common mode voltage Vcm may also be referred to as the second voltage .
  • the second comparison circuit 34 can output a high-level signal to the edge detection circuit 35, and when the second voltage is less than the second voltage, the first The second comparison circuit 34 may output a low-level signal to the edge detection circuit 35, for example, the high-level signal may be the power supply signal VDD, and the low-level signal may be the ground signal GND; the edge detection circuit 35 is detecting When the signal output from the second comparison circuit 34 changes from a low-level signal to a high-level signal to generate a rising edge, and/or from a high-level signal to a low-level signal to generate a falling edge, it can be determined that the detected signal is detected.
  • the “edge” of the first signal that is, it is detected that the first voltage is equal to the second voltage, and a pulse signal is output to the trigger circuit 33 to trigger the trigger circuit 33 to generate the target code.
  • the edge detection circuit 35 can generate a pulse signal when a rising edge or a falling edge is detected, that is, a pulse signal is generated when a predetermined period equal to one period of the first signal elapses; it can also be detected when the rising edge and falling edge are detected.
  • the pulse signal is generated at the edge time, that is, the pulse signal is generated when a predetermined period equal to a half period of the first signal elapses.
  • the pulse signal may be supplied to the flip-flop circuit 33 to output a target code, and may also be supplied to the counting circuit 32 as a reset signal RST to reset the count value of the counting circuit 32 to 000.
  • the trigger circuit 33 may include a trigger, such as a D flip-flop (D Flip-Flop) DFF; the trigger DFF has a memory function, that is, the trigger circuit 33 can store the last determined target code BST ⁇ 2:0>.
  • the trigger circuit 33 may be different from the target code BST ⁇ 2:0> stored by the trigger circuit 33 when the current count value Q ⁇ 2:0> of the counting circuit 32, and the edge detection circuit 35 determines that the first voltage Vsig intersects the control voltage Vcm ( ie equal), the target code BST ⁇ 2:0> stored in the flip-flop circuit 33 is updated with the current count value Q ⁇ 2:0> of the counting circuit 32, and the updated target code BST ⁇ 2:0> is output. It can be understood that if the current count value Q ⁇ 2:0> of the counting circuit 32 is the same as the target code BST ⁇ 2:0> stored in the trigger circuit 33, the trigger circuit 33 does not need to update the target code BST ⁇ 2:0>.
  • the control sub-circuit 12 can output the target code BST ⁇ 2:0> to the power supply circuit 13, and the power supply circuit 13 can provide the corresponding voltage to the audio power amplifier circuit 20 according to the target code BST ⁇ 2:0>, which will be further described below Detailed Description.
  • FIG. 6 shows specific electronic components and circuits for implementing the first comparison circuit 31, the counting circuit 32, the trigger circuit 33, the second comparison circuit 34 and the edge detection circuit 35, it should be understood that other electronic components may also be used and circuits to implement these components to achieve the functions described above.
  • the voltage amplitude of the first signal varies irregularly, and there may be a situation in which the voltage amplitude of the first signal is small in the first half cycle and suddenly increases in the second half cycle. If the power supply circuit 13 provides a lower supply voltage to the audio power amplifier circuit 20 in response to the target code provided by the control subcircuit 12 because the voltage amplitude of the first signal is smaller in the first half cycle, then when the second half cycle When the voltage amplitude of the first signal suddenly increases, the power supply voltage provided by the electronic circuit 13 cannot meet the output power requirement of the audio power amplifier circuit 20, so noise may be generated. To avoid this problem, in some embodiments, the control sub-circuit 12 may further include a delay circuit for extending the time for determining the target code.
  • the control sub-circuit 12 may further include a third comparison circuit 51 and a delay circuit 52 .
  • the third comparison circuit 51 is used to compare the current count value Q ⁇ 2:0> of the counting circuit 32 with the target code BST ⁇ 2:0> stored in the flip-flop circuit 33, so as to determine the current count value Q ⁇ of the counting circuit 32 Whether the reference voltage range corresponding to 2:0> increases or decreases relative to the target reference voltage range corresponding to the target code BST ⁇ 2:0> stored in the trigger circuit 33 .
  • the trigger circuit 33 can update the target code BST ⁇ 2:0> stored therein with the current count value Q ⁇ 2:0>, and output the updated target code. If the reference voltage range corresponding to the current count value Q ⁇ 2:0> is smaller than the target reference voltage range corresponding to the target code BST ⁇ 2:0>, the delay circuit 52 starts timing the preset time period.
  • the trigger circuit 33 can update the target code BST ⁇ 2:0> stored therein with the current count value Q ⁇ 2:0>, and output the updated target code.
  • the preset duration may be preset according to requirements, such as 250 milliseconds. The preset duration may be set to be greater than a duration corresponding to half, one or more cycles of the first signal.
  • the third comparison circuit 51 may include a digital comparator Dig COMP, which compares the current count value Q ⁇ 2:0> of the counting circuit 32 and the target code BST ⁇ 2:0> stored in the flip-flop circuit 33.
  • the output of the digital comparator Dig COMP and the output of the edge detection circuit 35 may be provided to the first logical sum circuit AND1.
  • the edge detection circuit 35 detects the edge of the first signal at which the first voltage Vsig is equal to the reference voltage Vcm, and the digital comparator Dig COMP determines that the current count value Q ⁇ 2:0> of the counting circuit 32 is greater than the flip-flop circuit
  • the first logic sum circuit AND1 outputs a high level or a pulse signal, so that the trigger circuit 33 updates the target code stored in it with the current count value Q ⁇ 2:0> BST ⁇ 2:0>, and output the updated target code.
  • the output of the digital comparator Dig COMP is also supplied to the delay circuit 52 via the inverter Inv1, and the output of the delay circuit 52 and the output of the edge detection circuit 35 are supplied to the second logical sum circuit AND2.
  • the digital comparator Dig COMP When the current count value Q ⁇ 2:0> of the counting circuit 32 is smaller than the target code BST ⁇ 2:0> stored in the trigger circuit 33, the digital comparator Dig COMP outputs a low-level signal, which is inverted by the inverter Inv1 After the signal becomes a high level, it is provided to the delay circuit 52, and the delay circuit 52 starts timing a predetermined period of time in response to the high level signal.
  • the second logic sum circuit AND2 When the current count value Q ⁇ 2:0> is still smaller than the target code BST ⁇ 2:0> after the preset time period elapses, and the edge detection circuit 35 determines that the first voltage Vsig intersects the control voltage Vcm, the second logic sum circuit AND2 outputs a high-level signal, causing the flip-flop circuit 33 to update the target code BST ⁇ 2:0> stored therein with the current count value Q ⁇ 2:0> and output the updated target code.
  • the outputs of the first logical AND circuit AND1 and the second logical AND circuit AND2 may be provided to the second logical OR circuit OR2 , and the output of the second logical OR circuit OR2 is provided to the flip-flop circuit 33 .
  • the edge detection circuit 35 detects the edge of the first signal at which the first voltage Vsig is equal to the reference voltage Vcm, and the digital comparator Dig COMP determines the current count value Q ⁇ 2 of the counting circuit 32: 0> is greater than the target code BST ⁇ 2:0> stored in the trigger circuit 33, the first logical sum circuit AND1 outputs a high level or a pulse signal; when the edge detection circuit 35 detects the edge of the first signal (at the edge The first voltage Vsig is equal to the reference voltage Vcm), and the digital comparator Dig COMP still determines that the current count value Q ⁇ 2:0> of the counting circuit 32 is smaller than the target code BST stored in the trigger circuit 33 after the delay circuit 52 delays for a predetermined period of time When ⁇ 2:0>, the second logical sum circuit AND2 outputs a high level or a pulse signal.
  • the second logic OR circuit OR2 When any one of the first logic AND circuit AND1 and the second logic AND circuit AND2 outputs a high level or a pulse signal, the second logic OR circuit OR2 outputs a high level or a pulse signal to instruct the trigger circuit 33 to use the current count value Q ⁇ 2:0> Updates the target code BST ⁇ 2:0> stored therein and outputs the updated target code.
  • the first data selector MUX 1 selects the upper limit voltage VrefH of the corresponding reference voltage range according to the count value Q ⁇ 2:0> output by the counter CT1 , and output to the first comparator COMP1; the first comparator COMP1 compares the first voltage Vsig with the upper limit voltage VrefH of the selected reference voltage range, and outputs a high level signal when Vsig is greater than VrefH , and when Vsig is greater than VrefH When it is less than VrefH, a low-level signal is output; at the same time, the second data selector MUX2 selects the lower limit voltage VrefL of the corresponding reference voltage range according to the count value Q ⁇ 2:0> output by the counter CT1, and outputs it to the second comparator COMP2; The second comparator COMP2 compares the first voltage V sig with
  • the two level signals output by the first comparator COMP1 and the second comparator COMP2 are input to the first logical OR circuit OR1, and when either of the input two level signals is a high level signal, Output a high level signal, at this time, the first voltage V sig is greater than VrefH of the current target reference voltage or V sig is less than VrefL of the current target reference voltage, that is, the first voltage V sig is in the first and second data selectors MUX1 and MUX2 Outside the reference voltage range (VrefL, VrefH) selected according to the count value Q ⁇ 2:0> output by the counter CT1; the first logical OR circuit OR1 outputs a low level signal when the two input level signals are both low level signals level signal, at this time, the first voltage Vsig is less than the upper limit voltage VrefH of the currently selected reference voltage range and greater than the lower limit voltage VrefL of the currently selected reference voltage range, that is, the first voltage Vsig falls within the first and second data
  • the counter CT1 counts the high-level signal output by the first logical OR circuit OR1, and the count value Q ⁇ 2:0> changes in the order of “000 ⁇ 001 ⁇ 010 ⁇ 011 ⁇ 100 ⁇ 101 ⁇ 110 ⁇ 111”.
  • Different count values Q ⁇ 2:0> correspond to different reference voltage ranges: Q ⁇ 2:0> is 000 corresponding to Vref1 (Vref1L, Vref1H), Q ⁇ 2:0> is 001 corresponding to Vref2 (Vref2L, Vref2H), Q ⁇ 2:0> is 010 corresponding to Vref3 (Vref3L, Vref3H), Q ⁇ 2:0> is 011 corresponding to Vref4 (Vref4L, Vref4H), Q ⁇ 2:0> is 100 corresponding to Vref5 (Vref5L, Vref5H), Q ⁇ 2 :0> is 101 corresponding to Vref6 (Vref6L, Vref6H), Q ⁇ 2:0> is 110
  • the first signal may not be a regular sine wave signal as shown in FIG. 4 , for example, the voltage amplitude of the first signal may be small in the first half cycle and suddenly increase in the second half cycle, so The change order of the count value Q ⁇ 2:0> and the change order of the reference voltage ranges selected by the first and second data selectors MUX1 and MUX2 are also different in the first half cycle and the second half cycle.
  • the peak value of the voltage amplitude of the first signal in the first half cycle is V H
  • the peak value of the voltage amplitude in the second half cycle is VL
  • the maximum value of the first voltage V sig in the current cycle is V H
  • V sig The minimum value in the current cycle is VL , and it is assumed that V H is smaller than Vref3H and larger than Vref2H, and VL is smaller than Vref5L and larger than Vref6L.
  • V sig gradually increases to V H in the process
  • Q ⁇ 2:0> changes in the order of "000 ⁇ 001 ⁇ 010”
  • the reference voltage range selected by the first and second data selectors MUX1 and MUX2 is in accordance with "Vref1
  • the sequence of ⁇ 101” changes, with the change of Q ⁇ 2:0>, the reference voltage ranges selected by the first and second data selectors MUX1 and MUX2 follow the sequence of “Vref1 ⁇ Vref2 ⁇ Vref3 ⁇ Vref4 ⁇ Vref5 ⁇ Vref6” Variety.
  • the third comparator COMP3 compares the first voltage V sig detected by the detection sub-circuit 11 with a reference voltage such as the common mode voltage Vcm of the audio signal to determine when the first signal passes the common mode voltage Vcm. When Vsig is less than Vcm, the third comparator COMP3 outputs a low-level signal, and when Vsig is greater than Vcm, the third comparator COMP3 outputs a high-level signal.
  • the edge detection circuit 35 determines that the first signal passes through or The common mode voltage Vcm is passed down, and a reset pulse signal is output to the counter CT1 to reset the count value Q ⁇ 2:0> to the initial value of 000.
  • the count value Q ⁇ 2:0> is reset to the initial value of 000, and the corresponding reference voltage range is Vref1 (Vref1L, Vref1H ), when the first voltage Vsig falls In the case outside the reference voltage range Vref1, the count value Q ⁇ 2:0> of the counter CT1 is increased from 000 to 001, and the first and second data selectors MUX1 and MUX2 select according to the count value Q ⁇ 2:0>
  • the reference voltage range becomes Vref2 (Vref2L, Vref2H). This process is repeated until the first voltage Vsig falls within the reference voltage range selected by the first and second data selectors MUX1 and MUX2, or the counter CT1 reaches the maximum count value.
  • the digital comparator Dig COMP compares the current count value Q ⁇ 2:0> of the counter CT1 with the target code BST ⁇ 2:0> stored in the trigger circuit 33, when Q ⁇ 2:0> is greater than BST ⁇ 2:0> When Q ⁇ 2:0> is less than BST ⁇ 2:0>, Dig COMP outputs a low level signal.
  • the edge detection circuit 35 determines that the first voltage Vsig crosses the common-mode voltage Vcm
  • the second logic sum circuit AND2 outputs a high-level signal
  • the second logical OR circuit OR2 outputs a high-level signal
  • the flip-flop DFF updates the target code BST ⁇ 2:0 stored in the flip-flop DFF with the current count value Q ⁇ 2:0> of the counter CT1 in response to the high-level signal >, and output the updated target code BST ⁇ 2:0> to control the electronic circuit 13 to provide the corresponding power supply voltage.
  • the delay circuit 52 can avoid that the voltage amplitude of the first signal is small in the first half cycle and suddenly becomes large in the second half cycle, and the power supply voltage provided by the electronic circuit 13 according to the voltage amplitude of the first signal in the first half cycle is insufficient In order to satisfy the problem of the output power of the audio power amplifier circuit 20 when the voltage amplitude of the first signal increases in the second half cycle.
  • Vcm is equal to 40V
  • Q ⁇ 2:0>000 corresponds to Vref1 (35V, 45V)
  • Q ⁇ 2:0>001 corresponds to Vref2 (30V, 50V)
  • Q ⁇ 2:0>010 corresponds to Vref3 (25V, 55V)
  • Q ⁇ 2:0>011 corresponds to Vref4 (20V, 60V)
  • Q ⁇ 2:0>100 corresponds to Vref5 (15V, 65V)
  • Q ⁇ 2:0>110 corresponds to Vref7 (5V, 75V)
  • Q ⁇ 2:0>111 corresponds to Vref8 (0V, 80V); and it is assumed that the first signal is in the first cycle
  • the peak value of the voltage amplitude in the first half cycle is 48V
  • the peak value of the voltage amplitude in the second half cycle is 26V, that is, the maximum value of V sig in
  • BST ⁇ 2:0> is 001, and the initial value of V sig in the first cycle is 40V; then, for the first cycle of the first signal, in the process of V sig gradually increasing from 40V, Q ⁇ 2: 0> is the initial value of 000.
  • the target reference voltage determined by MUX1 and MUX2 is Vref1 (35V, 45V).
  • Vref1 35V, 45V.
  • V sig is greater than Vcm
  • COMP3 always outputs a high-level signal
  • the edge detection circuit 35 does not detect the signal edge.
  • BST ⁇ 2:0> remains 001
  • MUX1 outputs a high-level signal
  • MUX2 outputs a low-level signal
  • the output signal of OR1 changes from a low-level signal to a high-level signal
  • the level signal generates a rising edge, triggers the count value Q ⁇ 2:0> of the counter CT1 to increase by 1, and changes from 000 to 001.
  • the reference voltage range selected by MUX1 and MUX2 changes from Vref1 (35V, 45V) to Vref2 (30V, 50V), at this time V sig is greater than Vcm, COMP3 always outputs a high-level signal, and the edge detection circuit 35 has not detected the signal edge of the first signal, so BST ⁇ 2:0> still remains 001; when V sig increases In the process of decreasing to 40V after reaching the peak value of 48V, both MUX1 and MUX2 output a low-level signal, OR1 also outputs a low-level signal, and the counter CT1 does not count, that is, the count value Q ⁇ 2:0> is still For 001, the reference voltage range selected by MUX1 and MUX2 is always Vref2 (30V, 50V), until Vsig is reduced to 40V, the edge detection circuit 35 detects the edge of the first signal and outputs a pulse signal, the counter CT1 responds to The edge detection circuit 35 outputs The output pulse signal resets the count value Q
  • the flip-flop circuit 33 Before Q ⁇ 2:0> is reset to the initial value, the flip-flop circuit 33 compares the count value Q ⁇ 2:0>001 with its stored target code BST ⁇ 2:0>001, and since the two are the same, the flip-flop circuit 33 The target code BST ⁇ 2:0> is not updated, and BST ⁇ 2:0> is still 001.
  • Q ⁇ 2:0> is 010, which is greater than BST ⁇ 2:0>001 stored in the trigger circuit 33 , the digital comparator Dig COMP also outputs a high-level signal, causing AND1 to output a high-level signal, and then OR2 to output a high-level signal.
  • the flip-flop DFF updates its stored target code BST ⁇ 2:0> with the count value Q ⁇ 2:0>010 of the counter CT1 in response to the high level signal, and outputs the updated target code BST ⁇ 2:0>010 .
  • the power supply circuit 13 may be a boost-type DC-DC circuit, as shown in FIG. 7 .
  • the principle of the step-up DC-DC circuit is known and will not be described in detail here.
  • the negative feedback control loop in the power supply circuit 13 will clamp one input voltage V fb of the error amplifier EA to be equal to its other input voltage V ref , where V ref is the reference voltage of the power supply circuit 13 and V fb is the supply voltage V fb .
  • V ref is the reference voltage of the power supply circuit 13
  • V fb is the supply voltage V fb .
  • the feedback voltage of the electronic circuit 13 Based on this principle, the following formula can be obtained:
  • V O represents the output voltage of the electronic supply circuit 13
  • R fb1 and R fb2 represent the feedback resistance of the electronic supply circuit 13 . It can be seen that the electronic circuit 13 can adjust the output voltage V O by adjusting its own feedback resistors R fb1 and R fb2 or the reference voltage V ref used by itself. Therefore, in some embodiments, a supply voltage matching the output power of the audio power amplifier 1 can be generated by adjusting the feedback resistance or the reference voltage of the power supply circuit 13 .
  • the target code output by the control sub-circuit 12 can be used to control multiple switches to connect or disconnect multiple resistors, so that the feedback resistance ratio of the electronic circuit 13 is changed, so that the electronic circuit 13 A supply voltage that matches the output power of the audio power amplifier 1 is generated.
  • the power supply circuit 13 includes feedback resistors R t3 , R t2 and R t1 , each of which has a switch in parallel, via BST ⁇ 2: 0> To control these switches, these feedback resistors can be connected or short-circuited, so as to adjust the feedback resistance ratio of the electronic circuit 13. For example, when BST ⁇ 2:0> is 010, R t3 and R t1 are connected, and R t2 is short-circuited. At this time, the feedback resistance ratio of the electronic circuit 13 can be calculated by the following formula:
  • the output voltage of the electronic circuit 13 can be calculated by the following formula:
  • the target code output by the control sub-circuit 12 may be used to control the reference voltage V ref used by the electronic circuit 13 to regulate the supply voltage generated by the electronic circuit 13 .
  • the third data selector MUX3 can selectively output one of the 8 input signals Vref1 to Vref8 as Vref , so that the electronic circuit 13 can generate a corresponding power supply voltage, which can Calculated by formula (6).
  • FIG. 10 shows an example in which the output voltage V O of the power supply circuit 13 may vary with the output voltage V O_PowerAmplifier of the audio power amplifier 1 .
  • an embodiment of the present invention further provides an audio power amplifier.
  • the audio power amplifier includes an audio power amplifier circuit 1101 and a power supply circuit 1102 ; wherein the power supply circuit 1102 is any of the above-mentioned power supply circuits.
  • the power supply circuit according to a power supply circuit embodiment; the power supply circuit 1102 supplies power to the audio power amplifier by supplying power to the audio power amplifier circuit 1101; the audio power amplifier circuit 1101 is a digital audio power amplifier circuit or an analog Audio power amplifier circuit.
  • an embodiment of the present invention further provides an integrated circuit, including the audio power amplifier shown in FIG. 11 .
  • an embodiment of the present invention further provides an electronic device, including a speaker and the audio power amplifier shown in FIG. 11 .
  • the audio power amplifier provides the audio signal to the speaker after power amplifying the audio signal.
  • an embodiment of the present invention also provides a power supply method, which is applied to an audio power amplifier. As shown in FIG. 12 , the method includes the following steps:
  • Step 1201 Detect the first voltage of the audio signal provided to the audio power amplifier to determine the output power of the audio power amplifier
  • Step 1202 Determine a target reference voltage range according to the voltage range of the audio signal within a predetermined period, the target reference voltage range is selected from a plurality of predetermined reference voltage ranges, and the voltage of the audio signal within the predetermined period range is contained within the target reference voltage range;
  • Step 1203 Based on the target reference voltage range, generate a supply voltage matching the output power of the audio power amplifier to supply power to the audio power amplifier.
  • determining the target reference voltage range includes: selecting, by the first comparison circuit, a reference voltage range from the plurality of predetermined reference voltage ranges to compare with the voltage of the audio signal; Count when the voltage of the audio signal exceeds the selected reference voltage range. Wherein, the first comparison circuit selects the next predetermined reference voltage range based on the count value of the counting circuit until the voltage of the audio signal falls within the selected reference voltage range.
  • determining the target reference voltage range further comprises: comparing, by a second comparison circuit, the voltage of the audio signal with a control voltage; determining, by an edge detection circuit, the output of the second comparison circuit determining the predetermined period of time when the audio signal crosses the contrast voltage; and determining the audio signal crosses the contrast voltage by the trigger circuit in the edge detection circuit, and the current count value of the counting circuit
  • the count value stored by the trigger circuit is different, the count value stored by the trigger circuit is updated with the current count value of the count circuit, and the count value is output, and the count value output by the trigger circuit indicates the target reference voltage range.
  • the method further includes providing a reset signal to the counting circuit to reset the count value of the counting circuit when the edge detection circuit determines that the audio signal intersects the contrast voltage.
  • determining the target reference voltage range further includes: comparing, by a third comparison circuit, the current count value of the counting circuit with the count value stored by the trigger circuit to determine the current count value of the counting circuit.
  • the reference voltage range corresponding to the value increases or decreases relative to the reference voltage range corresponding to the count value stored by the trigger circuit; and when the third comparison circuit determines the reference voltage corresponding to the current count value of the count circuit.
  • the range is increased with respect to the reference voltage range corresponding to the count value stored by the trigger circuit, and when the edge detection circuit determines that the audio signal intersects the reference voltage, the trigger circuit uses the count circuit's output signal.
  • the current count value updates the count value stored in the flip-flop circuit, and outputs the count value.
  • determining the target reference voltage range further includes: determining, in the third comparison circuit, a reference voltage range corresponding to the current count value of the counting circuit relative to a reference corresponding to the count value stored by the trigger circuit
  • the delay circuit starts timing a predetermined time period; and when the predetermined time period elapses, the third comparison circuit still determines that the reference voltage range corresponding to the current count value of the counting circuit is relative to the trigger
  • the reference voltage range corresponding to the count value stored in the circuit is reduced, and when the edge detection circuit determines that the audio signal intersects the reference voltage, the trigger circuit updates the trigger with the current count value of the count circuit
  • the circuit stores the count value and outputs the count value.
  • generating a supply voltage that matches the output power of the audio power amplifier includes adjusting a resistance value of a feedback resistor for use in an electronic circuit or selecting the electronic circuit according to the target reference voltage range The reference voltage used in to generate a voltage that matches the output power of the audio power amplifier.
  • each component or each step can be decomposed and/or recombined. These disaggregations and/or recombinations should be considered as equivalents of the present application.

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Abstract

本发明公开了一种供电电路、供电方法、音频功率放大器和集成电路。一种应用于音频功率放大器的供电电路可包括：检测子电路，用于检测输入到所述音频功率放大器的音频信号的电压，所述音频信号的电压对应于所述音频功率放大器的输出功率；控制子电路，用于根据所述音频信号在预定时段内的电压范围确定目标参考电压范围，所述目标参考电压范围选自多个预定的参考电压范围，并且所述音频信号在所述预定时段内的电压范围被包含在所述目标参考电压范围内；以及供电子电路，用于基于所述目标参考电压范围，产生与所述音频功率放大器的输出功率相匹配的供电电压，以为所述音频功率放大器供电。

Description

供电电路、供电方法、音频功率放大器和集成电路 技术领域
本发明涉及功率放大器技术领域，尤其涉及一种供电电路、方法、音频功率放大器和集成电路。
背景技术
音频功率放大器在应用过程中，其输出功率会受到自身的供电电源输出电压的限制，一般会以升压型直流转直流(DC-DC)电路或电荷泵(Charge-Pump)电路作为音频功率放大器的供电电路。供电电路可以通过将音频功率放大器的供电电压升高，以达到提高音频功率放大器输出信号幅度，从而提高输出功率的目的。
然而，相关技术中，音频功率放大器的供电电路尚需优化。
发明内容
为解决相关技术问题，本发明实施例提供一种供电电路、供电方法、音频功率放大器和集成电路。
根据一实施例，提供一种用于音频功率放大器的供电电路，包括：检测子电路，用于检测输入到所述音频功率放大器的音频信号的电压，所述音频信号的电压对应于所述音频功率放大器的输出功率；控制子电路，用于根据所述音频信号在预定时段内的电压范围确定目标参考电压范围，所述目标参考电压范围选自多个预定的参考电压范围，并且所述音频信号在所述预定时段内的电压范围被包含在所述目标参考电压范围内；以及供电子电路，用于基于所述目标参考电压范围，产生与所述音频功率放大器的输出功率相匹配的供电电压，以为所述音频功率放大器供电。
在一些实施例中，所述多个预定的参考电压范围包括第一参考电压范围和 第二参考电压范围，所述第一参考电压范围的下限值大于所述第二参考电压范围的下限值，所述第一参考电压范围的上限值小于所述第二参考电压范围的上限值。
在一些实施例中，所述控制子电路包括：第一比较电路，用于从所述多个预定的参考电压范围中选择一个参考电压范围与所述检测子电路检测到的所述音频信号的电压相比较；计数电路，用于在所述第一比较电路确定所述音频信号的电压超出所述第一比较电路选择的参考电压范围时，进行计数。所述计数电路的计数值被反馈给所述第一比较电路，所述第一比较电路基于所述计数电路的计数值选择下一个预定的参考电压范围，直到所述音频信号的电压落在所述第一比较电路选择的参考电压范围内。
在一些实施例中，所述第一比较电路包括：第一数据选择器，用于选择并输出所述多个预定的参考电压范围之一的上限值；第一比较器，其正相输入端接收所述检测子电路检测到的所述音频信号的电压，负相输入端接收所述第一数据选择器的输出；第二数据选择器，用于选择并输出所述多个预定的参考电压范围之一的下限值；以及第二比较器，其正相输入端接收所述第二数据选择器的输出，负相输入端接收所述检测子电路检测到的所述音频信号的电压。
在一些实施例中，所述计数电路包括：第一逻辑或电路，用于对所述第一比较器的输出和所述第二比较器的输出执行逻辑或操作；以及计数器，用于对所述第一逻辑或电路的输出信号进行计数。所述计数器的计数值被反馈给所述第一数据选择器和所述第二数据选择器，所述第一数据选择器和所述第二数据选择器基于所述计数值从所述多个预定的参考电压范围中选择一个对应的参考电压范围。
在一些实施例中，所述控制子电路还包括：第二比较电路，用于将所述检测子电路检测到的所述音频信号的电压与一对照电压相比较；边沿检测电路，用于通过检测所述第二比较电路的输出来确定所述音频信号与所述对照电压相交的时刻，从而确定所述预定时段；以及触发电路，用于在所述边沿检测电路确定所述音频信号与所述对照电压相交，并且所述计数电路的当前计数值与所 述触发电路储存的计数值不同时，用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值，所述触发电路输出的计数值指示所述目标参考电压范围。
在一些实施例中，所述对照电压是所述音频信号的共模电压。
在一些实施例中，所述边沿检测电路通过检测所述第二比较电路的输出信号的上升沿和/或下降沿来确定所述音频信号上穿和/或下穿经过所述对照电压的时刻。
在一些实施例中，所述边沿检测电路在确定所述音频信号与所述对照电压相交时，还向所述计数电路输出复位信号以复位所述计数电路的计数值。
在一些实施例中，所述控制子电路还包括：第三比较电路，用于将所述计数电路的当前计数值与所述触发电路储存的计数值相比较，以确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大还是减小。当所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
在一些实施例中，所述控制子电路还包括：延时电路，用于在所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小时，开始计时预定时长。当经过所述预定时长后所述第三比较电路仍确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
在一些实施例中，所述供电子电路根据从所述控制子电路接收到的指示所述目标参考电压范围的信号调整所述供电子电路中的反馈电阻器的电阻值，以 产生与所述音频功率放大器的输出功率相匹配的电压。
在一些实施例中，所述供电子电路根据从所述控制子电路接收到的指示所述目标参考电压范围的信号选择所述供电子电路中使用的参考电压，以产生与所述音频功率放大器的输出功率相匹配的电压。
根据另一实施例，提供一种向音频功率放大器供电的方法，包括：检测输入到所述音频功率放大器的音频信号的电压，所述音频信号的电压对应于所述音频功率放大器的输出功率；根据所述音频信号在预定时段内的电压范围确定目标参考电压范围，所述目标参考电压范围选自多个预定的参考电压范围，并且所述音频信号在所述预定时段内的电压范围被包含在所述目标参考电压范围内；以及基于所述目标参考电压范围，产生与所述音频功率放大器的输出功率相匹配的供电电压，以为所述音频功率放大器供电。
在一些实施例中，确定目标参考电压范围包括：由第一比较电路从所述多个预定的参考电压范围中选择一个参考电压范围与所述音频信号的电压相比较；以及由计数电路在所述音频信号的电压超出所选择的参考电压范围时，进行计数。所述第一比较电路基于所述计数电路的计数值选择下一个预定的参考电压范围，直到所述音频信号的电压落在所选择的参考电压范围内。
在一些实施例中，确定目标参考电压范围还包括：由第二比较电路将所述音频信号的电压与一对照电压相比较；由边沿检测电路通过检测所述第二比较电路的输出来确定所述音频信号与所述对照电压相交的时刻，从而确定所述预定时段；以及由触发电路在所述边沿检测电路确定所述音频信号与所述对照电压相交，并且所述计数电路的当前计数值与所述触发电路储存的计数值不同时，用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值，所述触发电路输出的计数值指示所述目标参考电压范围。
在一些实施例中，所述方法还包括：当所述边沿检测电路确定所述音频信号与所述对照电压相交时，向所述计数电路提供复位信号以复位所述计数电路的计数值。
在一些实施例中，确定目标参考电压范围还包括：由第三比较电路将所述 计数电路的当前计数值与所述触发电路储存的计数值相比较，以确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大还是减小；以及当所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，由所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
在一些实施例中，确定目标参考电压范围还包括：在所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小时，由延时电路开始计时预定时长；以及当经过所述预定时长后所述第三比较电路仍确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，由所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
在一些实施例中，产生与所述音频功率放大器的输出功率相匹配的供电电压包括：根据所述目标参考电压范围调整供电子电路中使用的反馈电阻器的电阻值或者选择所述供电子电路中使用的参考电压，以产生与所述音频功率放大器的输出功率相匹配的电压。
根据另一实施例，提供一种音频功率放大器，包括：音频功率放大电路；以及用于为所述音频功率放大电路供电的上述供电电路。
根据另一实施例，提供一种集成电路，其包括上述音频功率放大器。
根据另一实施例，提供一种电子设备，包括：上述音频功率放大器，其接收音频信号并且对所述音频信号进行功率放大；以及扬声器，用于播放所述音频信号。
在本发明的实施例中，供电电路检测音频功率放大器的输出功率大小，并产生与所述音频功率放大器的输出功率大小匹配的供电电压，实现了供电电路 的输出电压自适应调节，如此，在需要减小所述音频功率放大器的输出功率的场景下，所述供电电路能够减小输出的供电电压，致使在所述供电电路中的功率管和所述音频功率放大器中的功率管上流过的电流减小，进而减小了对所述供电电路中的功率管和所述音频功率放大器中的功率管造成的导通损耗，提高供电电路的供电效率，并提高音频功率放大器的工作效率。
附图说明
图1为根据本发明一实施例的供电电路的结构框图；
图2为根据本发明一实施例的音频功率放大器的电路图；
图3为根据本发明一实施例的控制子电路的框图；
图4为根据本发明一实施例的边沿检测电路输出脉冲信号的时机的示意图；
图5为根据本发明另一实施例的控制子电路的框图；
图6为根据本发明一实施例的控制子电路的电路图；
图7为根据本发明一实施例的供电子电路的电路图；
图8为根据本发明一实施例的供电子电路中的反馈电阻调节部件的电路图；
图9为根据本发明一实施例的供电子电路的参考电压调节部件的电路图；
图10为根据本发明一实施例的供电子电路的输出电压随着音频功率放大器的输出电压变化的示意图；
图11为根据本发明一实施例的音频功率放大器的框图；
图12为根据本发明一实施例的为音频功率放大器供电的方法的流程图。
具体实施方式
以下结合附图及实施例对本发明的技术方案作进一步详细的阐述。
相关技术中，音频功率放大器的供电电路的输出电压(即供电电压)通常是恒定的电压，为了使得音频功率放大器的输出功率满足一些应用场景的需求，供电电路的输出电压通常为一个较大的电压。然而，对于一些需要音频功率放大器输出较小功率的应用场景，供电电路仍以较大的电压为音频功率放大器供 电，会使得在供电电路中的功率管上流过的电流较大，造成功率管上的导通损耗较大；另外，音频功率放大器的输出功率较小，而为音频功率放大器供电的供电电压较大，会使得音频功率放大器的驱动损耗(也即在音频功率放大器中的功率管上流过的电流)较大，进而使得音频功率放大器的工作效率降低。
基于此，在本发明的各种实施例中，供电电路检测音频功率放大器的输出功率大小，并产生与所述音频功率放大器的输出功率大小匹配的供电电压，实现了供电电路的输出电压自适应，如此，在需要减小所述音频功率放大器的输出功率的场景下，所述供电电路能够减小输出的供电电压，致使在所述供电电路中的功率管和所述音频功率放大器中的功率管上流过的电流减小，进而减小了对所述供电电路中的功率管和所述音频功率放大器中的功率管造成的导通损耗，提高供电电路的供电效率，并提高音频功率放大器的工作效率。
本发明实施例提供了一种供电电路，应用于音频功率放大器1(见图2)，如图1所示，供电电路10包括：检测子电路11、控制子电路12和供电子电路13。
检测子电路11用于检测输入到音频功率放大器1的音频信号的电压，下文称为第一电压，基于所述第一电压可以确定音频功率放大器1的输出功率大小。
控制子电路12用于根据在预定时段内所述音频信号的电压的范围确定目标参考电压范围，所述目标参考电压范围选自多个预定的参考电压范围并且包含在所述预定时段内所述音频信号的电压范围。
供电子电路13用于基于所述目标参考电压范围，产生与音频功率放大器1的输出功率相匹配的供电电压，以为音频功率放大器1供电。
这里，供电子电路13产生与音频功率放大器1的输出功率相匹配的供电电压是指：音频功率放大器1的输出功率小时，供电子电路13产生的电压小；音频功率放大器1的输出功率大时，供电子电路13产生的电压大；即供电子电路13产生的电压随着音频功率放大器1的输出功率提高而提高，并随着音频功率放大器1的输出功率降低而降低；如此，实现了供电电路10的输出电压自适应调节，能够提高供电电路10的供电效率，并提高音频功率放大器1的工作效率。
在一些实施例中，音频功率放大器1可以是数字音频功率放大器，也可以是模拟音频功率放大器。供电子电路13可以是升压型DC-DC电路或Charge-Pump电路。
在一些实施例中，可以以适当的方式检测输入到音频功率放大器1的音频信号的第一电压。图2示出了音频功率放大器1为包括D类音频功率放大电路20的D类音频功率放大器的实施例，其中供电电路10为D类音频功率放大电路20供电。由于D类音频功率放大器1为双端输入和双端输出的结构，为了检测所述第一电压，需要将输入音频功率放大器1的双路电压信号转换为单路电压信号；因此，如图2所示，检测子电路11可以包括运算放大器OPAMP3和多个电阻器R S1、R S2。
对于图2所示的音频功率放大器1，电压从输入到输出的增益可以通过以下公式计算：
Figure PCTCN2021116871-appb-000001
其中，A Class_D表示音频功率放大器1从输入电压到输出电压的增益，R fb、R in、R 1、R 4、R 5和R 6表示所述音频功率放大器包含的两路通道中每路通道上的电阻。
对于图2所示的检测子电路11，电压从输入到输出的增益可以通过以下公式计算：
Figure PCTCN2021116871-appb-000002
其中，A sig表示检测子电路11从输入电压到输出电压的增益，R fb表示音频功率放大器1包含的两路通道中每路通道的输入缓冲区的电阻，R S1和R S2表示检测子电路11包含的两路输入通道中每路输入通道上的电阻。
图2所示的音频功率放大器1的输出电压与图2所示的检测子电路11的输出电压的关系可以通过以下公式表示：
Figure PCTCN2021116871-appb-000003
其中，V o_Class_D表示音频功率放大器1的输出电压，V sig表示检测子电路11 的输出电压。这里，V sig即检测子电路11检测得到的第一电压。
利用功率等于电压的平方除以电阻的原理以及公式(3)，可以得到以下公式：
Figure PCTCN2021116871-appb-000004
其中，P o_Class_D表示音频功率放大器1的输出功率，P o_sig表示检测子电路11的输出功率。
利用公式(3)和公式(4)可以得到以下公式：
Figure PCTCN2021116871-appb-000005
可见，检测得到第一电压V sig后，能够基于公式(5)确定音频功率放大器1的输出功率P o_Class_D，即可以通过检测第一电压来检测音频功率放大器1的输出功率大小。
在一实施例中，如图3所示，控制子电路12可以包括第一比较电路31和计数电路32。第一比较电路31可以从多个预定的参考电压范围中选择一个参考电压范围与检测子电路11检测到的音频信号的第一电压相比较。计数电路32可以在第一比较电路31确定音频信号的第一电压超出第一比较电路31选择的参考电压范围时，进行计数。计数电路32的计数值可以被反馈给第一比较电路31，第一比较电路31可以基于计数电路32的计数值选择下一个预定的参考电压范围，直到音频信号的第一电压落在第一比较电路31选择的参考电压范围内。
在图3所示的实施例中，控制子电路12还可以包括第二比较电路34、边沿检测电路35和触发电路33。第二比较电路34可以将检测子电路11检测到的音频信号的第一电压与一对照电压例如所述音频信号的共模电压V cm进行比较。边沿检测电路35可以通过检测第二比较电路34的输出来确定所述音频信号与所述对照电压相交，即所述音频信号的第一电压等于所述对照电压的时刻，从而确定所述预定时段。触发电路33在边沿检测电路35确定所述音频信号与所述对照电压相交，并且计数电路32的当前计数值与触发电路33中存储的计 数值不同时，用计数电路32的当前计数值更新触发电路33中存储的计数值，并且输出所述计数值。触发电路33输出的计数值指示控制子电路12确定的目标参考电压范围。
这里，检测子电路11检测得到音频信号的第一电压后，向控制子电路12输出第一电压；控制子电路12通过确定预设的X个参考电压范围中，与预定时段内第一电压的范围对应的一个目标参考电压范围，所述目标参考电压范围由一目标编码表示，实现对输入音频功率放大器1的音频信号(后面也称为第一信号)的电压范围进行时域分段编码，即对预定时段内第一信号的电压幅度的范围进行编码；不同的编码对应于第一信号的电压幅度的不同范围，进而对应于音频功率放大器1的不同输出功率范围，即实现了对音频功率放大器1的输出功率的不同范围进行编码；如此，能够将第一信号的电压幅度由模拟量转换为数字量(即所述编码)，进而通过所述数字量将第一信号的电压幅度与音频功率放大器1的输出功率进行关联，从而实现供电电路10的输出电压自适应调整。
在一些实施例中，如图6所示，第一比较电路31可以包含多个数据选择器(Multiplexer)，并可以通过对数据选择器进行配置来实现在第一比较电路31中预先设置X个参考电压范围，并且所述X个参考电压范围中的每个参考电压范围对应于一编码。具体地，第一比较电路31可以包括第一数据选择器MUX1和第二数据选择器MUX2，第一数据选择器MUX1和第二数据选择器MUX2均为X路数据选择器，X的取值可以为4、6、8、16等。第一数据选择器MUX1用于输出X个参考电压范围之一的上限电压，第二数据选择器MUX2用于输出X个参考电压范围之一的下限电压，X个参考电压范围中每个参考电压范围对应的编码可以由该参考电压范围的上限电压和下限电压对应的通道表示。在一实施例中，控制子电路12可以为数字电路，参考电压范围的编码可以为二进制编码，编码的位数等于log 2X。示例性地，当X的取值为8时，编码为3位二进制编码，第一数据选择器MUX1的第0-7路通道分别对应于参考电压Vref1H-Vref8H，并且Vref1H<Vref2H<Vref3H<Vref4H<Vref5H<Vref6H<Vref7H<Vref8H。 第二数据选择器MUX2的第0-7路通道分别对应于参考电压Vref1L-Vref8L，并且Vref1L>Vref2L>Vref3L>Vref4L>Vref5L>Vref6L>Vref7L>Vref8L。所述X个参考电压范围分别可以表示为Vref1(Vref1L，Vref1H)、Vref2(Vref2L，Vref2H)、Vref3(Vref3L，Vref3H)、Vref4(Vref4L，Vref4H)、Vref5(Vref5L，Vref5H)、Vref6(Vref6L，Vref6H)、Vref7(Vref7L，Vref7H)和Vref8(Vref8L，Vref8H)，并且Vref8包含Vref7，Vref7包含Vref6，Vref6包含Vref5，Vref5包含Vref4，Vref4包含Vref3，Vref3包含Vref2，Vref2包含Vref1。参考电压范围Vref1(Vref1L，Vref1H)对应编码000(表征第0路通道)，参考电压范围Vref2(Vref2L，Vref2H)对应编码001(表征第1路通道)，参考电压范围Vref8(Vref8L，Vref8H)对应编码111(表征第7路通道)。
第一比较电路31还可以包括多个比较器(Comparator)，例如图6所示的第一比较器COMP1和第二比较器COMP2，第一比较器COMP1将第一电压Vsig与预定参考电压范围的上限电压进行比较，第二比较器COMP2将第一电压Vsig与预定参考电压范围的下限电压进行比较。例如，第一比较器COMP1的正相输入端可接收第一电压Vsig，反相输入端可接收第一数据选择器MUX1输出的预定参考电压范围的上限电压。如果第一电压Vsig大于第一数据选择器MUX1当前选择的预定参考电压范围的上限电压，则第一比较器COMP1输出高电平；如果第一电压Vsig小于第一数据选择器MUX1当前选择的预定参考电压范围的上限电压，则第一比较器COMP1输出低电平。第二比较器COMP2的正相输入端可接收第二数据选择器MUX2输出的预定参考电压范围的下限电压，反相输入端可接收第一电压Vsig。如果第二数据选择器MUX2当前选择的预定参考电压范围的下限电压大于第一电压Vsig，则第二比较器COMP2输出高电平；如果第二数据选择器MUX2当前选择的预定参考电压范围的下限电压小于第一电压Vsig，则第二比较器COMP2输出低电平。为了描述方便，高电平可以表示数据“1”，低电平可以表示数据“0”。
计数电路32可以包括第一逻辑或器件OR1和计数器(Counter)CT1。计数器CT1可以是二进制计数器，其比特数可以等于表示第一比较电路31中预 定义的参考电压范围的编码的比特数。例如当第一比较电路31中预定义了X＝8个参考电压范围时，计数器CT1可以为log 2X＝3比特计数器，X个参考电压范围中每个参考电压范围与计数器CT1的编码的对应关系可以为：Vref1(Vref1L，Vref1H)对应编码000、Vref2(Vref2L，Vref2H)对应编码001、Vref3(Vref3L，Vref3H)对应编码010、Vref4(Vref4L，Vref4H)对应编码011、Vref5(Vref5L，Vref5H)对应编码100、Vref6(Vref6L，Vref6H)对应编码101、Vref7(Vref7L，Vref7H)对应编码110、以及Vref8(Vref8L，Vref8H)对应编码111。第一逻辑或器件OR1可以对第一比较器COMP1的输出和第二比较器COMP2的输出执行逻辑或操作。也就是说，当第一电压Vsig大于第一数据选择器MUX1选择的上限电压或小于第二数据选择器MUX2选择的下限电压时，第一逻辑或器件OR1输出高电平；当第一电压Vsig落入第一数据选择器MUX1选择的上限电压和第二数据选择器MUX2选择的下限电压定义的电压范围内时，第一逻辑或器件OR1输出低电平。计数器CT1在第一电压Vsig超出第一数据选择器MUX1和第二数据选择器MUX2选择的电压范围内时进行计数，产生3比特计数器编码Q<2:0>。计数器编码Q<2:0>被反馈给第一比较电路31，第一数据选择器MUX1和第二数据选择器MUX2基于计数器编码Q<2:0>选择对应的参考电压范围，直到第一电压Vsig落在第一数据选择器MUX1和第二数据选择器MUX2选择的参考电压范围内时，第一比较器COMP1和第二比较器COMP2都输出低电平，计数器CT1的计数值不再发生变化。初始时，计数器CT1的计数编码可以为000，第一数据选择器MUX1和第二数据选择器MUX2选择与编码000对应的最小参考电压范围Vref1(Vref1L，Vref1H)。当预定时段到期时，计数器CT1可以被复位到初始编码000。
提供给音频功率放大器1的音频信号即所述第一信号通常为正弦交流电压信号，边沿检测电路35实质上用于对所述第一信号进行边沿检测。具体地，第二比较电路34可包括第三比较器COMP3，其对第一电压Vsig和对照电压例如第一信号的共模电压Vcm进行比较，下文中共模电压Vcm也可以被称为第二电压。在所述第一电压大于所述第二电压的情况下，第二比较电路34可以向边 沿检测电路35输出高电平信号，在所述第二电压小于所述第二电压的情况下，第二比较电路34可以向边沿检测电路35输出低电平信号，示例性地，所述高电平信号可以是电源信号VDD，所述低电平信号可以是地信号GND；边沿检测电路35在检测到第二比较电路34输出的信号由低电平信号变为高电平信号产生上升沿，和/或由高电平信号变为低电平信号产生下降沿的情况下，可以确定检测到所述第一信号的“边沿”，即检测到了所述第一电压等于所述第二电压的情况，并向触发电路33输出脉冲信号，以触发所述触发电路33产生目标编码。可以理解，边沿检测电路35可以在检测到上升沿或下降沿时产生脉冲信号，也就是在与第一信号的一个周期相等的预定时段过去时产生脉冲信号；也可以在检测到上升沿和下降沿时都产生脉冲信号，也就是在与第一信号的半个周期相等的预定时段过去时产生脉冲信号。所述脉冲信号可以被提供给触发电路33以使其输出目标编码，并且也可以作为复位信号RST被提供给计数电路32，以使得计数电路32的计数值复位到000。
触发电路33可以包括触发器，例如D触发器(D Flip-Flop)DFF；触发器DFF具备记忆功能，即触发电路33可以存储上一次确定的目标编码BST<2:0>。触发电路33可以在计数电路32的当前计数值Q<2:0>与触发电路33存储的目标编码BST<2:0>不同，并且边沿检测电路35确定第一电压Vsig与对照电压Vcm相交(即相等)时，用计数电路32的当前计数值Q<2:0>更新触发电路33中存储的目标编码BST<2:0>，并且输出更新后的目标编码BST<2:0>。可以理解，如果计数电路32的当前计数值Q<2:0>与触发电路33中存储的目标编码BST<2:0>相同，则触发电路33不需要更新目标编码BST<2:0>。
控制子电路12可以向供电子电路13输出目标编码BST<2:0>，供电子电路13可以根据目标编码BST<2:0>向音频功率放大电路20提供对应的电压，其将在下面进一步详细描述。
虽然图6示出了用于实现第一比较电路31、计数电路32、触发电路33、第二比较电路34和边沿检测电路35的具体电子元件和电路，但是应理解，也可以用其他电子元件和电路来实现这些部件，以实现上面描述的功能。
在一些应用场景中，第一信号的电压幅度不规律地变化，可能存在第一信号的电压幅度在前半个周期较小，在后半个周期突然变大的情况。如果因为第一信号的电压幅度在前半个周期较小，供电子电路13响应于控制子电路12提供的目标编码而提供较低的供电电压给音频功率放大电路20，那么当在后半个周期第一信号的电压幅度突然变大时，供电子电路13提供的供电电压并不能满足音频功率放大电路20的输出功率的需要，因此可能会产生杂音。为了避免该问题，在一些实施例中，控制子电路12还可以包括用于延长确定目标编码的时间的延时电路。如图5所示，控制子电路12还可以包括第三比较电路51和延时电路52。第三比较电路51用于将计数电路32的当前计数值Q<2:0>与触发电路33中存储的目标编码BST<2:0>进行比较，从而确定计数电路32的当前计数值Q<2:0>对应的参考电压范围相对于触发电路33中存储的目标编码BST<2:0>对应的目标参考电压范围是增大还是减小。如果当前计数值Q<2:0>对应的参考电压范围相对于目标编码BST<2:0>对应的目标参考电压范围增大，则当边沿检测电路35确定第一电压Vsig与对照电压Vcm相交时，触发电路33可以用当前计数值Q<2:0>更新存储在其中的目标编码BST<2:0>，并输出更新后的目标编码。如果当前计数值Q<2:0>对应的参考电压范围相对于目标编码BST<2:0>对应的目标参考电压范围减小，则延时电路52开始计时预设时长。当所述预设时长过去之后，如果边沿检测电路35确定第一电压Vsig与对照电压Vcm相交时当前计数值Q<2:0>对应的参考电压范围仍然小于目标编码BST<2:0>对应的目标参考电压范围，则触发电路33可以用当前计数值Q<2:0>更新存储在其中的目标编码BST<2:0>，并输出更新后的目标编码。这里，所述预设时长可以根据需求预先设置，比如250毫秒。所述预设时长可以设置为大于所述第一信号的半个、一个或更多周期对应的时长。
参照图6，第三比较电路51可以包括数字比较器Dig COMP，其对计数电路32的当前计数值Q<2:0>和触发电路33中存储的目标编码BST<2:0>进行比较。数字比较器Dig COMP的输出和边沿检测电路35的输出可以提供给第一逻辑和电路AND1。当边沿检测电路35检测到第一信号的边沿(在该边沿处第一 电压Vsig等于对照电压Vcm)，并且数字比较器Dig COMP确定计数电路32的当前计数值Q<2:0>大于触发电路33中存储的目标编码BST<2:0>时，第一逻辑和电路AND1输出高电平或者脉冲信号，以使触发电路33用当前计数值Q<2:0>更新存储在其中的目标编码BST<2:0>，并输出更新后的目标编码。数字比较器Dig COMP的输出还经反相器Inv1提供给延时电路52，延时电路52的输出和边沿检测电路35的输出被提供给第二逻辑和电路AND2。当计数电路32的当前计数值Q<2:0>小于触发电路33中存储的目标编码BST<2:0>时，数字比较器Dig COMP输出低电平信号，其经反相器Inv1反相成高电平信号后被提供给延时电路52，延时电路52响应于该高电平信号开始计时预定时长。当所述预设时长过去之后当前计数值Q<2:0>仍然小于目标编码BST<2:0>，并且边沿检测电路35确定第一电压Vsig与对照电压Vcm相交时，第二逻辑和电路AND2输出高电平信号，使触发电路33用当前计数值Q<2:0>更新存储在其中的目标编码BST<2:0>并且输出更新后的目标编码。第一逻辑和电路AND1和第二逻辑和电路AND2的输出可以被提供给第二逻辑或电路OR2，第二逻辑或电路OR2的输出被提供给触发电路33。如前所述，当边沿检测电路35检测到第一信号的边沿(在该边沿处第一电压Vsig等于对照电压Vcm)，并且数字比较器Dig COMP确定计数电路32的当前计数值Q<2:0>大于触发电路33中存储的目标编码BST<2:0>时，第一逻辑和电路AND1输出高电平或者脉冲信号；当边沿检测电路35检测到第一信号的边沿(在该边沿处第一电压Vsig等于对照电压Vcm)，并且在延时电路52延迟预定时长之后数字比较器Dig COMP仍然确定计数电路32的当前计数值Q<2:0>小于触发电路33中存储的目标编码BST<2:0>时，第二逻辑和电路AND2输出高电平或者脉冲信号。当第一逻辑和电路AND1和第二逻辑和电路AND2中的任意一个输出高电平或者脉冲信号时，第二逻辑或电路OR2输出高电平或脉冲信号以指示触发电路33用当前计数值Q<2:0>更新存储在其中的目标编码BST<2:0>并且输出更新后的目标编码。
下面简要概述图6所示的控制子电路12的操作过程。检测子电路11检测到的第一电压V sig输入给控制子电路12后，第一数据选择器MUX 1根据计数 器CT1输出的计数值Q<2:0>选择对应的参考电压范围的上限电压VrefH，并输出到第一比较器COMP1；第一比较器COMP1将第一电压V sig与所选择的参考电压范围的上限电压VrefH进行比较，在V sig大于VrefH时输出高电平信号，在V sig小于VrefH时输出低电平信号；同时，第二数据选择器MUX2根据计数器CT1输出的计数值Q<2:0>选择对应的参考电压范围的下限电压VrefL，并输出到第二比较器COMP2；第二比较器COMP2将第一电压V sig与所选择的参考电压范围的下限电压VrefL进行比较，在V sig小于VrefL时输出高电平信号，在V sig大于VrefL时输出低电平信号。
第一比较器COMP1和第二比较器COMP2输出的两个电平信号输入至第一逻辑或电路OR1，其在输入的两个电平信号中的任一个电平信号为高电平信号时，输出高电平信号，此时，第一电压V sig大于当前目标参考电压的VrefH或V sig小于当前目标参考电压的VrefL，即第一电压V sig在第一和第二数据选择器MUX1和MUX2根据计数器CT1输出的计数值Q<2:0>选择的参考电压范围(VrefL，VrefH)之外；第一逻辑或电路OR1在输入的两个电平信号均为低电平信号时，输出低电平信号，此时，第一电压V sig小于当前选择的参考电压范围的上限电压VrefH且大于当前选择的参考电压范围的下限电压VrefL，即第一电压V sig落入第一和第二数据选择器MUX1和MUX2根据计数器CT1输出的计数值Q<2:0>选择的参考电压范围(VrefL，VrefH)内。计数器CT1对第一逻辑或电路OR1输出的高电平信号进行计数，计数值Q<2:0>按照“000→001→010→011→100→101→110→111”的顺序变化。不同的计数值Q<2:0>对应不同的参考电压范围：Q<2:0>为000对应Vref1(Vref1L，Vref1H)，Q<2:0>为001对应Vref2(Vref2L，Vref2H)，Q<2:0>为010对应Vref3(Vref3L，Vref3H)，Q<2:0>为011对应Vref4(Vref4L，Vref4H)，Q<2:0>为100对应Vref5(Vref5L，Vref5H)，Q<2:0>为101对应Vref6(Vref6L，Vref6H)，Q<2:0>为110对应Vref7(Vref7L，Vref7H)，Q<2:0>为111对应Vref8(Vref8L，Vref8H)；因此，随着计数值Q<2:0>的变化，第一和第二数据选择器MUX1和MUX2选择的参考电压范围按照“Vref1→Vref2→Vref3→Vref4→Vref5→Vref6→Vref7→Vref8”的顺 序变化。在一些示例中，所述第一信号可能并非如图4所示的规则的正弦波信号，例如所述第一信号的电压幅度可能在前半周期较小，并在后半周期突然变大，因此在前半周期和后半周期中计数值Q<2:0>的变化顺序以及第一和第二数据选择器MUX1和MUX2选择的参考电压范围的变化顺序也不同。示例性地，所述第一信号在前半周期电压幅度的峰值为V H，在后半周期电压幅度的峰值为V L，即第一电压V sig在当前周期的最大值为V H，V sig在当前周期的最小值为V L，并假设V H小于Vref3H大于Vref2H，V L小于Vref5L大于Vref6L，此时，在所述第一信号的前半周期，在V sig逐渐增大至V H的过程中，Q<2:0>按照“000→001→010”的顺序变化，随着Q<2:0>的变化，第一和第二数据选择器MUX1和MUX2选择的参考电压范围按照“Vref1→Vref2→Vref3”的顺序变化；在所述第一信号的后半周期，在V sig逐渐减小至V L的过程中，Q<2:0>按照“000→001→010→011→100→101”的顺序变化，随着Q<2:0>的变化，第一和第二数据选择器MUX1和MUX2选择的参考电压范围按照“Vref1→Vref2→Vref3→Vref4→Vref5→Vref6”的顺序变化。
第三比较器COMP3将检测子电路11检测得到的第一电压V sig与对照电压例如音频信号的共模电压Vcm进行比较以确定第一信号经过共模电压Vcm的时机。V sig小于Vcm时，第三比较器COMP3输出低电平信号，V sig大于Vcm时，第三比较器COMP3输出高电平信号。边沿检测电路35在检测到第三比较器COMP3的输出信号由低电平信号变为高电平信号，和/或由高电平信号变为低电平信号时，确定第一信号上穿或下穿经过共模电压Vcm，并向计数器CT1输出复位脉冲信号以将计数值Q<2:0>复位为初始值000。这样，第一信号每次经过共模电压Vcm时，计数值Q<2:0>被复位为初始值000，其对应的参考电压范围为Vref1(Vref1L，Vref1H)，在第一电压V sig落在参考电压范围Vref1之外的情况下，计数器CT1的计数值Q<2:0>由000增大到001，第一和第二数据选择器MUX1和MUX2根据计数值Q<2:0>选择的参考电压范围变为Vref2(Vref2L，Vref2H)。重复该过程，直到第一电压V sig落在第一和第二数据选择器MUX1和MUX2选择的参考电压范围内，或者计数器CT1达到最大计数值。
数字比较器Dig COMP将计数器CT1的当前计数值Q<2:0>与触发电路33中储存的目标编码BST<2:0>进行比较，当Q<2:0>大于BST<2:0>时，Dig COMP输出高电平信号，当Q<2:0>小于BST<2:0>时，Dig COMP输出低电平信号。在Q<2:0>大于BST<2:0>(表示与Q<2:0>对应的当前选择的参考电压范围大于与BST<2:0>对应的前一个输出的目标参考电压范围)且所述第一信号经过共模电压Vcm时，第二逻辑或器件OR2向触发器DFF输出高电平信号或脉冲信号，触发器DFF响应于第二逻辑或器件OR2输出的高电平或脉冲信号用计数器CT1的当前计数值Q<2:0>更新触发器DFF中存储的目标编码BST<2:0>，并且输出更新后的目标编码BST<2:0>以控制供电子电路13提供相应的供电电压。当Q<2:0>小于BST<2:0>(表示与Q<2:0>对应的当前选择的参考电压范围落在与BST<2:0>对应的前一个输出的目标参考电压范围内)时，数字比较器Dig COMP输出低电平信号经反相器Inv1变成高电平信号后被提供给延时电路52，延时电路52响应于该高电平信号开始计时预定时长。在计时期满且数字比较器Dig COMP仍输出低电平信号的情况下，当边沿检测电路35确定第一电压Vsig穿过共模电压Vcm时，第二逻辑和电路AND2输出高电平信号，使第二逻辑或电路OR2输出高电平信号，触发器DFF响应于该高电平信号用计数器CT1的当前计数值Q<2:0>更新触发器DFF中存储的目标编码BST<2:0>，并且输出更新后的目标编码BST<2:0>以控制供电子电路13提供相应的供电电压。这样，延时电路52能够避免第一信号的电压幅度在前半个周期较小，在后半个周期突然变大，供电子电路13根据前半个周期中第一信号的电压幅度提供的供电电压不足以满足后半个周期中第一信号的电压幅度增大时音频功率放大电路20的输出功率的问题。
示例性地，基于图6所对应的实施例，假设Vcm等于40V，Q<2:0>000对应Vref1(35V，45V)，Q<2:0>001对应Vref2(30V，50V)，Q<2:0>010对应Vref3(25V，55V)，Q<2:0>011对应Vref4(20V，60V)，Q<2:0>100对应Vref5(15V，65V)，Q<2:0>101对应Vref6(10V，70V)，Q<2:0>110对应Vref7(5V，75V)，Q<2:0>111对应Vref8(0V，80V)；并假设所述第一信号在第一周期的 前半周期电压幅度的峰值为48V，在后半周期电压幅度的峰值为26V，即V sig在第一周期的最大值为48V，最小值为26V，同时，假设触发器DFF在上一周期保存的BST<2:0>为001，V sig在第一周期的初始值为40V；那么，对于所述第一信号的第一周期，在V sig由40V逐渐增大的过程中，Q<2:0>为初始值000，MUX1和MUX2确定的目标参考电压为Vref1(35V，45V)，在V sig小于45V且V sig大于40V的情况下，MUX1和MUX2均输出低电平信号，OR1也输出低电平信号，无法触发计数器CT的计数值加1，即Q<2:0>仍为000，此时V sig大于Vcm，COMP3一直输出高电平信号，边沿检测电路35未检测到信号边沿，因此BST<2:0>保持为001；在V sig增大至45V以上的情况下，MUX1输出高电平信号，MUX2输出低电平信号，OR1的输出信号由低电平信号变为高电平信号，产生上升沿，触发计数器CT1的计数值Q<2:0>加1，由000变为001，MUX1和MUX2选择的参考电压范围由Vref1(35V，45V)变为Vref2(30V，50V)，此时V sig大于Vcm，COMP3一直输出高电平信号，边沿检测电路35仍未检测到第一信号的信号边沿，因此BST<2:0>仍保持为001；在V sig增大至峰值48V后开始减小并减小至40V的过程中，MUX1和MUX2均输出低电平信号，OR1也输出低电平信号，计数器CT1不进行计数，即计数值Q<2:0>仍为001，MUX1和MUX2选择的参考电压范围也一直为Vref2(30V，50V)，直至V sig减小至40V时，边沿检测电路35检测到第一信号的边沿并且输出脉冲信号，计数器CT1响应于边沿检测电路35输出的脉冲信号将计数值Q<2:0>由001复位为初始值000。在Q<2:0>复位为初始值之前，触发电路33将计数值Q<2:0>001与其存储的目标编码BST<2:0>001相比，由于二者相同，因此触发电路33不更新目标编码BST<2:0>，BST<2:0>仍为001。可见，在第一周期的前半周期，在V sig由40V逐渐增大至电压幅度峰值48V后又下降至40V的过程中，Q<2:0>按照“000→001→000”的顺序变化，随着Q<2:0>的变化，MUX1和MUX2选择的参考电压范围按照“Vref1→Vref2→Vref1”的顺序变化，而BST<2:0>保持不变，一直为001。在第一周期的后半周期，与上述流程相似，在V sig由40V逐渐减小至最小值26V后又增大至40V的过程中，Q<2:0>按照“000→001→010 →000”的顺序变化，随着Q<2:0>的变化，MUX1和MUX2选择的参考电压范围按照“Vref1→Vref2→Vref3→Vref1”的顺序变化。在V sig增大至40V时，边沿检测电路35检测到第一信号的边沿并且输出脉冲信号，此时Q<2:0>为010，大于触发电路33中存储的BST<2:0>001，数字比较器Dig COMP也输出高电平信号，致使AND1输出高电平信号，进而OR2输出高电平信号。触发器DFF响应于该高电平信号用计数器CT1的计数值Q<2:0>010更新其存储的目标编码BST<2:0>，并且输出更新后的目标编码BST<2:0>010。
示例性地，供电子电路13可以是升压型DC-DC电路，如图7所示。升压型DC-DC电路的原理是已知的，这里不再详细描述。供电子电路13中的负反馈控制环路会将误差放大器EA的一个输入电压V fb嵌位到等于其另一个输入电压V ref，其中V ref是供电子电路13的参考电压，V fb是供电子电路13的反馈电压。基于这个原理可以得到以下公式：
Figure PCTCN2021116871-appb-000006
其中，V O表示供电子电路13的输出电压，R fb1和R fb2表示供电子电路13的反馈电阻。可见，供电子电路13能够通过调整自身的反馈电阻R fb1和R fb2或自身使用的参考电压V ref来调整输出电压V O。因此，在一些实施例中，可以通过调节供电子电路13的反馈电阻或参考电压来产生与音频功率放大器1的输出功率匹配的供电电压。
在一实施例中，可以利用控制子电路12输出的目标编码来控制多个开关，以接入或断开多个电阻器，使得供电子电路13的反馈电阻比例发生改变，从而供电子电路13产生与音频功率放大器1的输出功率大小匹配的供电电压。示例性地，如图8所示，供电子电路13包括反馈电阻器R t3、R t2和R t1，每个反馈电阻器R t3、R t2和R t1具有并联的开关，通过BST<2:0>来控制这些开关可以接入或短路这些反馈电阻器，从而调整供电子电路13的反馈电阻比例。例如，在BST<2:0>为010的情况下，R t3和R t1被接入，R t2短路，此时供电子电路13的反馈电阻比例可以通过以下公式进行计算：
Figure PCTCN2021116871-appb-000007
基于公式(7)，此时供电子电路13的输出电压可以通过以下公式进行计算：
Figure PCTCN2021116871-appb-000008
在一些实施例中，可以使用控制子电路12输出的目标编码来控制供电子电路13使用的参考电压V ref以调节供电子电路13产生的供电电压。例如，如图9所示，供电子电路13包括第三数据选择器MUX3，其选择性输出X个输入信号中的一个作为供电子电路13中使用的参考电压V ref，其中log 2X是目标编码BST<2:0>的比特数。例如，当log 2X＝3时，第三数据选择器MUX3具有8个输入信号Vref1至Vref8。根据目标编码BST<2:0>的值，第三数据选择器MUX3可以选择性输出8个输入信号Vref1至Vref8中的一个作为V ref，从而供电子电路13可以产生相应的供电电压，其可以通过公式(6)进行计算。图10示出了供电子电路13的输出电压V O可以随着音频功率放大器1的输出电压V O_PowerAmplifier而变化的示例。
基于上述供电电路，本发明实施例还提供了一种音频功率放大器，如图11所示，所述音频功率放大器包括音频功率放大电路1101和供电电路1102；其中，所述供电电路1102为上述任一供电电路实施例所述的供电电路；所述供电电路1102通过为所述音频功率放大电路1101供电来为所述音频功率放大器供电；所述音频功率放大电路1101为数字音频功率放大电路或模拟音频功率放大电路。
基于上述供电电路，本发明实施例还提供了一种集成电路，包括图11所示的音频功率放大器。
基于上述供电电路，本发明实施例还提供了一种电子设备，包括扬声器和图11所示的音频功率放大器。所述音频功率放大器在对音频信号进行功率放大后，将所述音频信号提供给所述扬声器。
基于上述供电电路，本发明实施例还提供了一种供电方法，应用于音频功率放大器，如图12所示，所述方法包括以下步骤：
步骤1201：检测提供给音频功率放大器的音频信号的第一电压来确定所述音频功率放大器的输出功率；
步骤1202：根据所述音频信号在预定时段内的电压范围确定目标参考电压范围，所述目标参考电压范围选自多个预定的参考电压范围，并且所述音频信号在所述预定时段内的电压范围被包含在所述目标参考电压范围内；
步骤1203：基于所述目标参考电压范围，产生与所述音频功率放大器的输出功率相匹配的供电电压，以为所述音频功率放大器供电。
在一些实施例中，确定目标参考电压范围包括：由第一比较电路从所述多个预定的参考电压范围中选择一个参考电压范围与所述音频信号的电压相比较；以及由计数电路在所述音频信号的电压超出所选择的参考电压范围时，进行计数。其中，所述第一比较电路基于所述计数电路的计数值选择下一个预定的参考电压范围，直到所述音频信号的电压落在所选择的参考电压范围内。
在一些实施例中，确定目标参考电压范围还包括：由第二比较电路将所述音频信号的电压与一对照电压相比较；由边沿检测电路通过检测所述第二比较电路的输出来确定所述音频信号与所述对照电压相交的时刻，从而确定所述预定时段；以及由触发电路在所述边沿检测电路确定所述音频信号与所述对照电压相交，并且所述计数电路的当前计数值与所述触发电路储存的计数值不同时，用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值，所述触发电路输出的计数值指示所述目标参考电压范围。
在一些实施例中，所述方法还包括：当所述边沿检测电路确定所述音频信号与所述对照电压相交时，向所述计数电路提供复位信号以复位所述计数电路的计数值。
在一些实施例中，确定目标参考电压范围还包括：由第三比较电路将所述计数电路的当前计数值与所述触发电路储存的计数值相比较，以确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大还是减小；以及当所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对 应的参考电压范围增大，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，由所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
在一些实施例中，确定目标参考电压范围还包括：在所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小时，由延时电路开始计时预定时长；以及当经过所述预定时长后所述第三比较电路仍确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，由所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
在一些实施例中，产生与所述音频功率放大器的输出功率相匹配的供电电压包括：根据所述目标参考电压范围调整供电子电路中使用的反馈电阻器的电阻值或者选择所述供电子电路中使用的参考电压，以产生与所述音频功率放大器的输出功率相匹配的电压。
以上结合具体实施例描述了本申请的基本原理，但是，需要指出的是，在本申请中提及的优点、优势、效果等仅是示例而非限制，不能认为这些优点、优势、效果等是本申请的各个实施例必须具备的。另外，上述公开的具体细节仅是为了示例的作用和便于理解的作用，而非限制，上述细节并不限制本申请为必须采用上述具体的细节来实现。而是，本领域技术人员在本申请的教导下，容易想到许多形式和细节上的变化，这些变化都应落入本申请的权利要求所限定的范围内。
本申请中涉及的器件、装置、设备、系统的方框图仅作为例示性的例子并且不意图要求或暗示必须按照方框图示出的方式进行连接、布置、配置。如本领域技术人员将认识到的，可以按任意方式连接、布置、配置这些器件、装置、设备、系统。诸如“包括”、“包含”、“具有”等等的词语是开放性词汇，指“包括但不限于”，且可与其互换使用。这里所使用的词汇“或”和“和”指词汇“和 /或”，且可与其互换使用，除非上下文明确指示不是如此。这里所使用的词汇“诸如”指词组“诸如但不限于”，且可与其互换使用。
还需要指出的是，在本申请的装置、设备和方法中，各部件或各步骤是可以分解和/或重新组合的。这些分解和/或重新组合应视为本申请的等效方案。
提供所公开的方面的以上描述以使本领域的任何技术人员能够做出或者使用本申请。对这些方面的各种修改对于本领域技术人员而言是非常显而易见的，并且在此定义的一般原理可以应用于其他方面而不脱离本申请的范围。因此，本申请不意图被限制到在此示出的方面，而是按照与在此公开的原理和新颖的特征一致的最宽范围。
为了例示和描述的目的已经给出了以上描述。此外，此描述不意图将本申请的实施例限制到在此公开的形式。尽管以上已经讨论了多个示例方面和实施例，但是本领域技术人员将认识到其某些变型、修改、改变、添加和子组合。

Claims (23)

  1. 一种用于音频功率放大器的供电电路，包括：
    检测子电路，用于检测输入到所述音频功率放大器的音频信号的电压，所述音频信号的电压对应于所述音频功率放大器的输出功率；
    控制子电路，用于根据所述音频信号在预定时段内的电压范围确定目标参考电压范围，所述目标参考电压范围选自多个预定的参考电压范围，并且所述音频信号在所述预定时段内的电压范围被包含在所述目标参考电压范围内；以及
    供电子电路，用于基于所述目标参考电压范围，产生与所述音频功率放大器的输出功率相匹配的供电电压，以为所述音频功率放大器供电。
  2. 根据权利要求1所述的供电电路，其中，所述多个预定的参考电压范围包括第一参考电压范围和第二参考电压范围，所述第一参考电压范围的下限值大于所述第二参考电压范围的下限值，所述第一参考电压范围的上限值小于所述第二参考电压范围的上限值。
  3. 根据权利要求1所述的供电电路，其中，所述控制子电路包括：
    第一比较电路，用于从所述多个预定的参考电压范围中选择一个参考电压范围与所述检测子电路检测到的所述音频信号的电压相比较；
    计数电路，用于在所述第一比较电路确定所述音频信号的电压超出所述第一比较电路选择的参考电压范围时，进行计数，
    其中，所述计数电路的计数值被反馈给所述第一比较电路，所述第一比较电路基于所述计数电路的计数值选择下一个预定的参考电压范围，直到所述音频信号的电压落在所述第一比较电路选择的参考电压范围内。
  4. 根据权利要求3所述的供电电路，其中，所述第一比较电路包括：
    第一数据选择器，用于选择并输出所述多个预定的参考电压范围之一的上限值；
    第一比较器，其正相输入端接收所述检测子电路检测到的所述音频信号的 电压，负相输入端接收所述第一数据选择器的输出；
    第二数据选择器，用于选择并输出所述多个预定的参考电压范围之一的下限值；以及
    第二比较器，其正相输入端接收所述第二数据选择器的输出，负相输入端接收所述检测子电路检测到的所述音频信号的电压。
  5. 根据权利要求4所述的供电电路，其中，所述计数电路包括：
    第一逻辑或电路，用于对所述第一比较器的输出和所述第二比较器的输出执行逻辑或操作；以及
    计数器，用于对所述第一逻辑或电路的输出信号进行计数，
    其中，所述计数器的计数值被反馈给所述第一数据选择器和所述第二数据选择器，所述第一数据选择器和所述第二数据选择器基于所述计数值从所述多个预定的参考电压范围中选择一个对应的参考电压范围。
  6. 根据权利要求3所述的供电电路，其中，所述控制子电路还包括：
    第二比较电路，用于将所述检测子电路检测到的所述音频信号的电压与一对照电压相比较；
    边沿检测电路，用于通过检测所述第二比较电路的输出来确定所述音频信号与所述对照电压相交的时刻，从而确定所述预定时段；以及
    触发电路，用于在所述边沿检测电路确定所述音频信号与所述对照电压相交，并且所述计数电路的当前计数值与所述触发电路储存的计数值不同时，用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值，所述触发电路输出的计数值指示所述目标参考电压范围。
  7. 根据权利要求6所述的供电电路，其中，所述对照电压是所述音频信号的共模电压。
  8. 根据权利要求6所述的供电电路，其中，所述边沿检测电路通过检测所述第二比较电路的输出信号的上升沿和/或下降沿来确定所述音频信号上穿和/或下穿经过所述对照电压的时刻。
  9. 根据权利要求6所述的供电电路，其中，所述边沿检测电路在确定所述 音频信号与所述对照电压相交时，还向所述计数电路输出复位信号以复位所述计数电路的计数值。
  10. 根据权利要求6所述的供电电路，其中，所述控制子电路还包括：
    第三比较电路，用于将所述计数电路的当前计数值与所述触发电路储存的计数值相比较，以确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大还是减小，
    其中，当所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
  11. 根据权利要求10所述的供电电路，其中，所述控制子电路还包括：
    延时电路，用于在所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小时，开始计时预定时长，
    其中，当经过所述预定时长后所述第三比较电路仍确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
  12. 根据权利要求1所述的供电电路，其中，所述供电子电路根据从所述控制子电路接收到的指示所述目标参考电压范围的信号调整所述供电子电路中的反馈电阻器的电阻值，以产生与所述音频功率放大器的输出功率相匹配的电压。
  13. 根据权利要求1所述的供电电路，其中，所述供电子电路根据从所述控制子电路接收到的指示所述目标参考电压范围的信号选择所述供电子电路中使用的参考电压，以产生与所述音频功率放大器的输出功率相匹配的电压。
  14. 一种向音频功率放大器供电的方法，包括：
    检测输入到所述音频功率放大器的音频信号的电压，所述音频信号的电压对应于所述音频功率放大器的输出功率；
    根据所述音频信号在预定时段内的电压范围确定目标参考电压范围，所述目标参考电压范围选自多个预定的参考电压范围，并且所述音频信号在所述预定时段内的电压范围被包含在所述目标参考电压范围内；以及
    基于所述目标参考电压范围，产生与所述音频功率放大器的输出功率相匹配的供电电压，以为所述音频功率放大器供电。
  15. 根据权利要求14所述的方法，其中，确定目标参考电压范围包括：
    由第一比较电路从所述多个预定的参考电压范围中选择一个参考电压范围与所述音频信号的电压相比较；以及
    由计数电路在所述音频信号的电压超出所选择的参考电压范围时，进行计数，
    其中，所述第一比较电路基于所述计数电路的计数值选择下一个预定的参考电压范围，直到所述音频信号的电压落在所选择的参考电压范围内。
  16. 根据权利要求15所述的方法，其中，确定目标参考电压范围还包括：
    由第二比较电路将所述音频信号的电压与一对照电压相比较；
    由边沿检测电路通过检测所述第二比较电路的输出来确定所述音频信号与所述对照电压相交的时刻，从而确定所述预定时段；以及
    由触发电路在所述边沿检测电路确定所述音频信号与所述对照电压相交，并且所述计数电路的当前计数值与所述触发电路储存的计数值不同时，用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值，所述触发电路输出的计数值指示所述目标参考电压范围。
  17. 根据权利要求16所述的方法，还包括：
    当所述边沿检测电路确定所述音频信号与所述对照电压相交时，向所述计数电路提供复位信号以复位所述计数电路的计数值。
  18. 根据权利要求16所述的方法，其中，确定目标参考电压范围还包括：
    由第三比较电路将所述计数电路的当前计数值与所述触发电路储存的计数值相比较，以确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大还是减小；以及
    当所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围增大，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，由所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
  19. 根据权利要求18所述的方法，其中，确定目标参考电压范围还包括：
    在所述第三比较电路确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小时，由延时电路开始计时预定时长；以及
    当经过所述预定时长后所述第三比较电路仍确定与所述计数电路的当前计数值对应的参考电压范围相对于与所述触发电路储存的计数值对应的参考电压范围减小，并且所述边沿检测电路确定所述音频信号与所述对照电压相交时，由所述触发电路用所述计数电路的当前计数值更新所述触发电路储存的计数值，并且输出所述计数值。
  20. 根据权利要求14所述的方法，其中，产生与所述音频功率放大器的输出功率相匹配的供电电压包括：
    根据所述目标参考电压范围调整供电子电路中使用的反馈电阻器的电阻值或者选择所述供电子电路中使用的参考电压，以产生与所述音频功率放大器的输出功率相匹配的电压。
  21. 一种音频功率放大器，包括：
    音频功率放大电路；以及
    权利要求1至13中的任一项所述的供电电路，所述供电电路用于为所述音频功率放大电路供电。
  22. 一种集成电路，包括权利要求21所述的音频功率放大器。
  23. 一种电子设备，包括：
    权利要求21所述的音频功率放大器，其接收音频信号并且对所述音频信号进行功率放大；以及
    扬声器，用于播放所述音频信号。
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