WO2022095418A1 - 一种集成电路装置及其形成方法 - Google Patents

一种集成电路装置及其形成方法 Download PDF

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Publication number
WO2022095418A1
WO2022095418A1 PCT/CN2021/095834 CN2021095834W WO2022095418A1 WO 2022095418 A1 WO2022095418 A1 WO 2022095418A1 CN 2021095834 W CN2021095834 W CN 2021095834W WO 2022095418 A1 WO2022095418 A1 WO 2022095418A1
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Prior art keywords
layer
forming
sub
region
contact hole
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English (en)
French (fr)
Inventor
王蒙蒙
黄信斌
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/388,145 priority Critical patent/US11769725B2/en
Publication of WO2022095418A1 publication Critical patent/WO2022095418A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H10W20/493—Fuses, i.e. interconnections changeable from conductive to non-conductive
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections

Definitions

  • the present application relates to the technical field of semiconductor manufacturing, and in particular, to an integrated circuit device and a method for forming the same.
  • a fuse is a resistive structure in an integrated circuit device.
  • the purpose of adjusting the internal electrical functions or electrical parameters of the integrated circuit is achieved by fusing the fuse.
  • the first metal layer, the second metal layer, and the metal connection layer between the first metal layer and the second metal layer are often used as fuses.
  • the structure of the wire can effectively avoid the problem of overlay offset caused by the corrosion of the alignment marks.
  • the purpose of this application is to provide an integrated circuit device and a method for forming the same, which are used to solve the problems of complex fuse structure and cumbersome manufacturing process in the existing fuse, reduce the fusing energy of the fuse, and realize the improvement of the process yield of the integrated circuit device. increase and reduce manufacturing costs.
  • an embodiment of the present application provides a method for forming an integrated circuit device, which includes the following steps:
  • a substrate is provided, the substrate includes a first region and a second region located outside the first region, the substrate interior has a first plug located in the first region and the second region the second plug;
  • a contact hole exposing the first conductive layer and a trench located above the contact hole and communicating with the contact hole are formed in the first area, and the second plug is formed in the second area the second opening;
  • a conductive connection layer is formed in the contact hole, a second conductive layer is formed in the trench, and a fuse is formed in the second opening.
  • the specific steps of forming the isolation layer covering the first conductive layer and the first cover layer include:
  • a second sub-isolation layer covering the first sub-isolation layer is formed, and the first sub-isolation layer and the second sub-isolation layer together constitute an isolation layer.
  • a contact hole exposing the first conductive layer and a trench located above the contact hole and communicating with the contact hole are formed in the first region, and the second region exposing the contact hole is formed.
  • the specific steps of the second opening of the second plug include:
  • a contact hole exposing the first conductive layer and a trench located above the contact hole and communicating with the contact hole are formed in the first region, and the second region exposing the contact hole is formed.
  • the specific steps of the second opening of the second plug include:
  • the second sub-isolation layer and the first sub-isolation layer at the bottom of the initial trench are etched, and the second sub-isolation layer, the first sub-isolation layer and the first sub-isolation layer at the bottom of the window are etched.
  • a cover layer, a contact hole exposing the first conductive layer and a trench located above the contact hole and communicating with the contact hole are formed in the first region, and a contact hole is formed in the second region exposing the contact hole the second opening of the second plug.
  • the specific steps of forming a conductive connection layer in the contact hole, forming a second conductive layer in the trench, and forming a fuse in the second opening include:
  • a fuse is formed in the opening.
  • a second capping layer is formed covering the second conductive layer, the fuse and the isolation layer.
  • an integrated circuit device including:
  • a substrate the substrate includes a first area and a second area outside the first area, the substrate has a first plug located in the first area and a first plug located in the second area inside the substrate Two plugs, the substrate surface has a first cover layer and an isolation layer located on the surface of the first cover layer;
  • a first conductive layer located in the first cover layer of the first region, and electrically connected to the first plug
  • a conductive connection layer located on the surface of the first conductive layer
  • a second conductive layer located on the surface of the conductive connection layer, one end of the conductive connection layer is electrically connected to the first conductive layer, and the other end is electrically connected to the second conductive layer;
  • the fuse located in the second area, the fuse has a solid columnar structure and penetrates the isolation layer and the first cover layer, the bottom surface of the fuse is electrically connected to the second plug, and the The top surface of the fuse is flush with the top surface of the second conductive layer.
  • the materials of the fuse, the second conductive layer and the conductive connection layer are the same.
  • the isolation layer includes:
  • the second sub-isolation layer covers the surface of the first sub-isolation layer, and the thickness of the second sub-isolation layer is larger than that of the first sub-isolation layer.
  • a second cover layer covers the surface of the second conductive layer, the fuse and the isolation layer.
  • the second region for forming the fuse in the process of forming the first conductive layer, the second region for forming the fuse is not processed, and in the process of forming the conductive connection layer and the second conductive layer At the same time, the fuse is formed, so that the formed fuse has a simple solid columnar structure, which has nothing to do with the structure of the first conductive layer and the second conductive layer, which not only simplifies the structure of the fuse, but only requires lower energy.
  • the fuse is blown, and the manufacturing process of the entire integrated circuit device is simplified, the manufacturing process cost of the integrated circuit device is reduced, and the yield of the integrated circuit device is improved.
  • FIG. 1 is a flowchart of a method for forming an integrated circuit device in a specific embodiment of the present application
  • 2A-2J are schematic cross-sectional views of main processes in the process of forming an integrated circuit device in a specific embodiment of the present application;
  • 3A-3B are schematic cross-sectional views of main processes in the process of forming an integrated circuit device according to another specific embodiment of the present application.
  • FIG. 1 is a flowchart of the method for forming an integrated circuit device in the specific embodiment of the present application. Schematic diagram of the main process cross-section during the process of the device. As shown in FIG. 1 , FIG. 2A and FIG. 2I , the method for forming an integrated circuit device provided by this specific embodiment includes the following steps:
  • a substrate 20 is provided, the substrate 20 includes a first region I and a second region II located outside the first region I, and the substrate 20 has a second region located inside the first region I.
  • the substrate 20 may be a single-layer structure, or may be a multi-layer structure composed of multiple semiconductor layers.
  • the multi-layers mentioned in this specific embodiment refer to two or more layers.
  • the specific material of the substrate 20 can be selected by those skilled in the art according to actual needs. This specific embodiment is described by taking the material of the substrate 20 as an oxide material (eg, silicon dioxide) as an example.
  • first region I of the substrate 20 is used to form a double-layer damascene structure, and is electrically connected to an external pad;
  • the upper part of the second region II of the substrate 20 is used to form a fuse, and the purpose of adjusting the electrical performance or electrical parameters of the integrated circuit device is achieved by blowing the fuse.
  • a specific method for forming the first plug 21 and the second plug 22 in the substrate 20 may be to etch the substrate 20 first, and then form the first plug in the first region I. through holes, and a second through hole is formed in the second region II; after that, the first through hole and the second through hole are filled with a conductive material, such as metal tungsten or doped polysilicon, and the first through hole and the second through hole are formed at the same time.
  • a plug 21 and the second plug 22; finally, chemical mechanical polishing (CMP) may be used for planarization, so that the top surface of the first plug 21 and the top surface of the second plug 22 are The face is flush with the top face of the substrate 20 .
  • CMP chemical mechanical polishing
  • Step S12 forming a first cover layer 23 covering the substrate 20 , as shown in FIG. 2B .
  • the first capping layer may be deposited by a chemical vapor deposition process, a physical vapor deposition process or an atomic layer deposition process 23 , so that the first cover layer 23 covers the top surface of the first plug 21 , the top surface of the second plug 22 and the top surface of the substrate 20 .
  • the material of the first cover layer 23 is an insulating material, and the specific type thereof can be selected by those skilled in the art according to actual needs.
  • the thickness of the first cover layer 23 can be set according to the thickness of the first conductive layer to be formed subsequently.
  • step S13 the first capping layer 23 is etched, and a first opening 24 exposing the first plug 21 is formed in the first region I, as shown in FIG. 2C.
  • the material of the first cover layer 23 is an insulating material.
  • the first covering layer 23 is formed through the And the first opening 24 of the first plug 21 in the substrate 20 is exposed.
  • the first cover layer 23 above the second region II of the substrate 20 is not etched, on the one hand to ensure that the subsequently formed fuse does not have a first conductive layer structure and no material of the first conductive layer remains; on the other hand, since only the first cover layer 23 above the first region I is etched, the alignment difficulty can be reduced, thereby simplifying the etching process.
  • the inner diameter of the first opening 24 can be set by those skilled in the art according to the specific structure of the first conductive layer to be formed.
  • step S14 a first conductive layer 25 is formed in the first opening 24, as shown in FIG. 2D.
  • the first opening 24 is filled with conductive materials such as metal copper to form the first conductive layer 25 .
  • the chemical mechanical polishing process is used to planarize the first conductive layer 25 , so that the top surface of the first conductive layer 25 (ie the surface of the first conductive layer 25 facing away from the substrate 20 ) and the The top surface of the first cover layer 23 (ie, the surface of the first cover layer 23 facing away from the substrate 20 ) is flush.
  • Step S15 forming an isolation layer covering the first conductive layer 25 and the first cover layer 23 , as shown in FIG. 2E .
  • the isolation layer may be a single-layer structure or a multi-layer structure, which can be selected by those skilled in the art according to actual needs.
  • the specific steps of forming the isolation layer covering the first conductive layer 25 and the first cover layer 23 include:
  • first sub-isolation layer 26 covering the first conductive layer 25 and the first cover layer 23;
  • a second sub-isolation layer 27 covering the first sub-isolation layer 26 is formed, and the first sub-isolation layer 26 and the second sub-isolation layer 27 together constitute an isolation layer.
  • the first sub-isolation layer 26 covering the top surface of the first conductive layer 25 and the top surface of the first cover layer 23 is formed; then, the first sub-isolation layer 26 is formed covering the first sub-isolation layer 26 the second sub-isolation layer 27 .
  • the first sub-isolation layer 26 and the second sub-isolation layer 27 have a With a certain etching selectivity ratio (for example, the etching selectivity ratio is greater than 3), the morphology of the contact holes, trenches and second openings to be formed subsequently can be controlled by selective etching.
  • the first sub-isolation layer 26 can be a single-layer structure, and its material is a nitride material, such as silicon nitride; the first sub-isolation layer 26 can also be made of SIN/SICN/SION composed of multi-layer structures.
  • the material of the second sub-isolation layer 27 may be an oxide material, such as silicon dioxide.
  • Step S16 forming a contact hole 31 exposing the first conductive layer 25 and a trench 30 located above the contact hole 31 and communicating with the contact hole 31 in the first region I, and forming the second Region II forms a second opening 32 exposing the second plug 22, as shown in FIG. 2G.
  • a contact hole 31 exposing the first conductive layer 25 and a trench 30 located above the contact hole 31 and communicating with the contact hole 31 are formed in the first region I, and are formed in the first region I.
  • the specific steps of forming the second opening 32 exposing the second plug 22 in the second region II include:
  • the second sub-isolation layer 27 located in the first region I and the second region II is etched, an initial contact hole 28 exposing the first sub-isolation layer 26 is formed in the first region I, and forming an initial second opening 29 through the second sub-isolation layer 27 in the second region II, as shown in FIG. 2F ;
  • the second sub-isolation layer 27 on the sidewall of the initial contact hole 28 and the first sub-isolation layer 26 on the bottom of the initial contact hole 28 are etched, and all the bottom of the initial second opening 29 is etched.
  • the first sub-isolation layer 26 and the first cover layer 23 form a contact hole 31 in the first region I exposing the first conductive layer 25 and a contact hole 31 located above the contact hole 31 and connected to the contact hole 31 connected to the groove 30, and a second opening 32 exposing the second plug 22 is formed in the second region II, as shown in FIG. 2G .
  • the material of the second sub-isolation layer 27 is the same as the material of the first cover layer 23 .
  • the second sub-isolation layer 27 is first etched by using the first sub-isolation layer 26 as an etch stop layer , forming the initial contact hole 28 penetrating the second sub-isolation layer 27 on the first region I at a position corresponding to the first conductive layer 25 , and forming the initial contact hole 28 on the second region II with The position corresponding to the second plug 22 forms the initial second opening 29 penetrating the second sub-isolation layer 27 .
  • the first sub-isolation layer 26 at the bottom of the initial contact hole 28 is etched along the initial contact hole 28 to expose the first conductive layer 25 , and the first sub-isolation layer 26 is etched along the initial second opening 29 at the same time.
  • the first sub-isolation layer 26 exposes the first cover layer 23 on the second region II. Etching the sidewall of the upper part of the initial contact hole 28, expanding the opening size of the upper part of the initial contact hole 28, and making the upper parts of a plurality of the initial contact holes 28 communicate, forming an inner diameter larger than one of the initial contact holes 28 of the grooves 30 .
  • the opening width of the upper portion of the initial contact holes 28 may only be enlarged, without making the adjacent initial contact holes 28 communicate with each other.
  • the etching of the first capping layer 23 is continued along the initial second opening 29 to expose the second plug 23 .
  • the material of the second sub-isolation layer 27 is set to be the same as the material of the first capping layer 23 , so that during the process of etching to form the trench 30 , the first capping layer is simultaneously
  • the layer 23 is etched to form the second opening 32, which can save the etching steps, reduce the etching cost, and improve the etching efficiency.
  • FIGS. 3A-3B are schematic cross-sectional views of main processes in the process of forming an integrated circuit device according to another specific embodiment of the present application. As shown in FIGS.
  • a contact hole 31 exposing the first conductive layer 25 is formed in the first region I, and a contact hole 31 located above the contact hole 31 and connected to the contact hole 31 is formed in the first region I.
  • a window 41 that does not penetrate the second sub-isolation layer 27 is formed in the second region II;
  • the second sub-isolation layer 27 and the first sub-isolation layer 26 at the bottom of the initial trench 40 are etched, and the second sub-isolation layer 27 and the first sub-isolation layer at the bottom of the window 41 are etched layer 26 and the first cover layer 23, in the first region I form a contact hole 31 exposing the first conductive layer 25 and a trench located above the contact hole 31 and communicated with the contact hole 31 30.
  • a second opening 32 for exposing the second plug 22 is formed in the second region II, as shown in FIG. 3B .
  • step S17 a conductive connection layer 33 is formed in the contact hole 31 , a second conductive layer 34 is formed in the trench 30 , and a fuse 35 is formed in the second opening 32 .
  • the specific steps of forming the conductive connection layer 33 in the contact hole 31 , forming the second conductive layer 34 in the trench 30 , and forming the fuse 35 in the second opening 32 include: :
  • the materials of the conductive connection layer 33 , the second conductive layer 34 , and the fuse 35 may all be the same as the materials of the first conductive layer 25 , for example, all are metal copper materials.
  • the materials of the conductive connection layer 33 , the second conductive layer 34 , the fuse 35 and the first conductive layer 25 may be different according to actual needs.
  • the cross-sectional shape of the fuse 35 may be circular or rectangular with rounded corners.
  • the method for forming the integrated circuit device further includes the following steps:
  • a second capping layer covering the second conductive layer 34, the fuse 35 and the isolation layer is formed.
  • the second cover layer may be a single-layer structure or a multi-layer structure.
  • the second covering layer is an example of a multi-layer structure for description. As shown in Figure 2I,
  • the second cover layer includes a first protective layer 36 and a second protective layer 37 .
  • the first protective layer 36 can be a single-layer structure, and its material is a nitride material, such as silicon nitride; the first protective layer 36 can also be a multi-layer structure composed of SIN/SICN/SION.
  • the material of the second protective layer 37 is an oxide material, such as silicon dioxide.
  • a third capping layer 381 and a fourth capping layer may be sequentially formed on the second capping layer 382, and by etching the fourth covering layer 382, the third covering layer 381 and the second protective layer 37 located in the second region II, forming through the fourth covering layer 382, the The third cover layer 381 and the second protective layer 37, and expose the third opening 39 of the first protective layer 36, as shown in FIG. 2J.
  • the fuse 35 may be blown through the third opening 39 .
  • the third capping layer 381 is a single-layer structure (the material thereof is a hard mask material, such as silicon nitride or silicon oxynitride), or a multi-layer structure.
  • the fourth cover layer 382 can also be a single-layer structure (the material thereof is an organic mask material, such as amorphous carbon), or a multi-layer structure.
  • the present embodiment also provides an integrated circuit device.
  • the integrated circuit device provided by this specific embodiment can be formed by the method shown in FIG. 1 , FIG. 2A- FIG. 2J or FIG. 3A- FIG. 3B , and the specific structure of the integrated circuit device can be referred to FIG. 2I and FIG. 2J .
  • the integrated circuit device provided by this specific embodiment includes:
  • the substrate 20 includes a first area I and a second area II located outside the first area I, and inside the substrate 20 has a first plug 21 located in the first area I and the second plug 22 located in the second region II, the surface of the substrate 20 has a first cover layer 23 and an isolation layer located on the surface of the first cover layer 23;
  • the first conductive layer 25 is located in the first cover layer 23 of the first region I, and is electrically connected to the first plug 21;
  • the conductive connection layer 33 is located on the surface of the first conductive layer 25;
  • the second conductive layer 34 is located on the surface of the conductive connection layer 33, one end of the conductive connection layer 33 is electrically connected to the first conductive layer 25, and the other end is electrically connected to the second conductive layer 34;
  • the fuse 35 is located in the second area II.
  • the fuse 35 has a solid columnar structure and penetrates the isolation layer and the first cover layer 23.
  • the bottom surface of the fuse 35 is connected to the second plug.
  • the plug 22 is electrically connected, and the top surface of the fuse 35 is flush with the top surface of the second conductive layer 34 .
  • the materials of the fuse 35 , the second conductive layer 34 and the conductive connection layer 33 are the same.
  • the isolation layer includes:
  • the first sub-isolation layer 26 covers the surface of the first cover layer 23;
  • the second sub-isolation layer 27 covers the surface of the first sub-isolation layer 26 , and the thickness of the second sub-isolation layer 27 is larger than that of the first sub-isolation layer 26 .
  • the material of the second sub-isolation layer 27 is the same as the material of the first cover layer 23 .
  • the integrated circuit device further includes:
  • the second cover layer covers the surface of the second conductive layer 34 , the fuse 35 and the isolation layer.
  • the second region for forming the fuse in the process of forming the first conductive layer, is not processed, and in the process of forming the conductive connection layer and the second conductive layer At the same time, the fuse is formed, so that the formed fuse has a simple solid columnar structure, which has nothing to do with the structure of the first conductive layer and the second conductive layer, which not only simplifies the structure of the fuse, but only requires lower energy.
  • the fuse is blown, and the manufacturing process of the entire integrated circuit device is simplified, the manufacturing process cost of the integrated circuit device is reduced, and the yield of the integrated circuit device is improved.

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Abstract

本申请公开了一种集成电路装置及其形成方法。所述集成电路装置的形成方法包括如下步骤：提供包括第一区域和第二区域的衬底，所述衬底内部具有第一插塞和第二插塞；形成覆盖所述衬底的第一覆盖层；于所述第一区域形成暴露所述第一插塞的第一开口；于所述第一开口内形成第一导电层；形成覆盖所述第一导电层和所述第一覆盖层的隔离层；于所述第一区域形成暴露所述第一导电层的接触孔和与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口；于所述接触孔内形成导电连接层、于所述沟槽内形成第二导电层、并于所述第二开口内形成熔丝。本申请简化了熔丝的结构，使得仅需要较低的能量就可以熔断熔丝，而且简化了制造流程。

Description

一种集成电路装置及其形成方法
交叉引用
本申请基于申请号为202011221558.4、申请日为2020年11月05日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请涉及半导体制造技术领域，尤其涉及一种集成电路装置及其形成方法。
背景技术
熔丝是集成电路装置中的一个电阻型结构。在集成电路装置中，通过熔丝的熔断，达到调整集成电路内部电性功能或者电学参数的目的。在具有双层大马士革结构的集成电路装置中，多采用第一金属层、第二金属层以及位于所述第一金属层和第二金属层之间的金属连接层共同作为熔丝，此种熔丝的结构能够有效的避免因对准标记的腐蚀而导致的套刻偏移问题。
但是，由于这种熔丝结构复杂，制程工艺繁琐，在后续的熔丝熔断过程中需要较大的熔断能量，且经常会出现熔断不完全的现象，从而导致工艺参数难以控制以及熔断能量的浪费，间接增加了集成电路装置的制造成本。
因此，如何简化集成电路装置中的熔丝的结构，降低熔丝的熔断能量，是目前亟待解决的技术问题。
发明内容
本申请的目的是提供一种集成电路装置及其形成方法，用于解决现有的熔丝结构复杂、制程工艺繁琐的问题，并降低熔丝的熔断能量，实现对集成电路装置制程良率的提高以及制造成本的降低。
为了解决上述问题，本申请实施例中提供了一种集成电路装置的形成方法，包括如下步骤：
提供一衬底，所述衬底包括第一区域和位于所述第一区域外部的第二区域，所述衬底内部具有位于所述第一区域的第一插塞和位于所述第二区域的第二插塞；
形成覆盖所述衬底的第一覆盖层；
刻蚀所述第一覆盖层，于所述第一区域形成暴露所述第一插塞的第一开口；
于所述第一开口内形成第一导电层；
形成覆盖所述第一导电层和所述第一覆盖层的隔离层；
于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口；
于所述接触孔内形成导电连接层、于所述沟槽内形成第二导电层、并于所述第二开口内形成熔丝。
可选的，形成覆盖所述第一导电层和所述第一覆盖层的隔离层的具体步骤包括：
形成覆盖所述第一导电层和所述第一覆盖层的第一子隔离层；
形成覆盖所述第一子隔离层的第二子隔离层，所述第一子隔离层和所述第二子隔离层共同构成隔离层。
可选的，于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口的具体步骤包括：
刻蚀位于所述第一区域和所述第二区域的所述第二子隔离层，于所述第一区域形成暴露所述第一子隔离层的初始接触孔、并于所述第二区域形成贯穿所述第二子隔离层的初始第二开口；
刻蚀所述初始接触孔侧壁的所述第二子隔离层和所述初始接触孔底部的所述第一子隔离层、并刻蚀所述初始第二开口底部的所述第一子隔离层和所述第一覆盖层，于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口。
可选的，于所述第一区域形成暴露所述第一导电层的接触孔和位 于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口的具体步骤包括：
刻蚀位于所述第一区域和所述第二区域的所述第二子隔离层，于所述第一区域形成未贯穿所述第二子隔离层的初始沟槽、并于所述第二区域形成未贯穿所述第二子隔离层的窗口；
刻蚀所述初始沟槽底部的所述第二子隔离层和第一子隔离层、并刻蚀所述窗口底部的所述第二子隔离层、所述第一子隔离层和所述第一覆盖层，于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口。
可选的，于所述接触孔内形成导电连接层、于所述沟槽内形成第二导电层、并于所述第二开口内形成熔丝的具体步骤包括：
填充导电材料于所述接触孔、所述沟槽和所述第二开口内，于所述接触孔内形成导电连接层、于所述沟槽内形成第二导电层、并于所述第二开口内形成熔丝。
可选的，还包括如下步骤：
形成覆盖所述第二导电层、所述熔丝和所述隔离层的第二覆盖层。
为了解决上述问题，本申请实施例还提供了一种集成电路装置，包括：
衬底，所述衬底包括第一区域和位于所述第一区域外部的第二区域，所述衬底内部具有位于所述第一区域的第一插塞和位于所述第二区域的第二插塞，所述衬底表面具有第一覆盖层和位于所述第一覆盖层表面的隔离层；
第一导电层，位于所述第一区域的所述第一覆盖层内，且与所述第一插塞电连接；
导电连接层，位于所述第一导电层表面；
第二导电层，位于所述导电连接层表面，所述导电连接层的一端电连接所述第一导电层、另一端电连接所述第二导电层；
熔丝，位于所述第二区域，所述熔丝呈实心柱状结构、并贯穿所 述隔离层和所述第一覆盖层，所述熔丝的底面与所述第二插塞电连接、所述熔丝的顶面与所述第二导电层的顶面平齐。
可选的，所述熔丝、所述第二导电层和所述导电连接层的材料相同。
可选的，所述隔离层包括：
第一子隔离层，覆盖于所述第一覆盖层表面；
第二子隔离层，覆盖于所述第一子隔离层表面，且所述第二子隔离层的厚度大于所述第一子隔离层。
可选的，还包括：
第二覆盖层，覆盖于所述第二导电层、所述熔丝和所述隔离层表面。
本申请实施例提供的集成电路装置及其形成方法，在形成第一导电层的过程中，不对用于形成熔丝的第二区域进行处理，在形成导电连接层和第二导电层的过程中同时形成熔丝，使得形成的熔丝呈简单的实心柱状结构，与第一导电层和第二导电层的结构无关，不仅简化了熔丝的结构，使得仅仅只需要较低的能量就可以实现熔丝的熔断，而且简化了整个集成电路装置的制造流程，降低了集成电路装置的制程成本，也提高了集成电路装置的良率。
附图说明
通过以下参照附图对本发明实施例的描述，本发明的上述以及其他目的、特征和优点将更为清楚，在附图中：
附图1是本申请具体实施方式中集成电路装置的形成方法流程图；
附图2A-2J是本申请一具体实施方式在形成集成电路装置的过程中主要的工艺截面示意图；
附图3A-3B是本申请另一具体实施方式在形成集成电路装置的过程中主要的工艺截面示意图。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。但是应该理解，这些描述只是示例性的，而并非要限制本发明的范围。此外，在以下说明中，省略了对公知结构和技术的描述，以避免不必要地混淆本发明的概念。
本具体实施方式提供了一种集成电路装置的形成方法，附图1是本申请具体实施方式中集成电路装置的形成方法流程图，附图2A-2J是本申请一具体实施方式在形成集成电路装置的过程中主要的工艺截面示意图。如图1、图2A图2I所示，本具体实施方式提供的集成电路装置的形成方法，包括如下步骤：
步骤S11，提供一衬底20，所述衬底20包括第一区域Ⅰ和位于所述第一区域Ⅰ外部的第二区域Ⅱ，所述衬底20内部具有位于所述第一区域Ⅰ的第一插塞21和位于所述第二区域Ⅱ的第二插塞22，如图2A所示。
具体来说，所述衬底20可以为单层结构，也可以为由多个半导体层构成的多层结构。本具体实施方式中所述的多层是指两层及两层以上。所述衬底20的具体材料，本领域技术人员可以根据实际需要进行选择，本具体实施方式以所述衬底20的材料为氧化物材料(例如二氧化硅)为例进行说明。
所述衬底20的所述第一区域Ⅰ上方用于形成双层大马士革结构，并与外界焊盘电连接；
所述衬底20的所述第二区域Ⅱ的上方用于形成熔丝，通过熔断所述熔丝达到调整所述集成电路装置的电学性能或者电性参数的目的。
于所述衬底20内形成所述第一插塞21和所述第二插塞22的具体方法，可以是先对所述衬底20进行刻蚀，于所述第一区域Ⅰ形成第一通孔、并于所述第二区域Ⅱ形成第二通孔；之后，采用导电材料，例如金属钨或者掺杂多晶硅填充所述第一通孔和所述第二通孔，同时形成所述第一插塞21和所述第二插塞22；最后，可以采用化学机械研磨工艺(CMP)进行平坦化处理，使得所述第一插塞21 的顶面、所述第二插塞22的顶面与所述衬底20的顶面平齐。
步骤S12，形成覆盖所述衬底20的第一覆盖层23，如图2B所示。
具体来说，在对所述第一插塞21和所述第二插塞22进行平坦化处理之后，可以采用化学气相沉积工艺、物理气相沉积工艺或者原子层沉积工艺沉积所述第一覆盖层23，使得所述第一覆盖层23覆盖所述第一插塞21的顶面、所述第二插塞22的顶面和所述衬底20的顶面。其中，所述第一覆盖层23的材料为绝缘材料，其具体类型本领域技术人员可以根据实际需要进行选择。所述第一覆盖层23的厚度可以根据后续所要形成的第一导电层的厚度进行设置。
步骤S13，刻蚀所述第一覆盖层23，于所述第一区域Ⅰ形成暴露所述第一插塞21的第一开口24，如图2C所示。
具体来说，所述第一覆盖层23的材料为绝缘材料。通过对所述衬底20的所述第一区域Ⅰ上方的所述第一覆盖层23进行刻蚀，以所述第一插塞21为刻蚀截止层，形成贯穿所述第一覆盖层23且暴露所述衬底20中的所述第一插塞21的所述第一开口24。
在本次刻蚀过程中，不对所述衬底20的所述第二区域Ⅱ上方的所述第一覆盖层23进行刻蚀，一方面确保后续形成的熔丝中不具有第一导电层结构以及不残留第一导电层的材料；另一方面由于仅对所述第一区域Ⅰ上方的所述第一覆盖层23进行刻蚀，可以降低对准难度，从而简化刻蚀工艺。所述第一开口24的内径尺寸，本领域技术人员可以根据所要形成的第一导电层的具体结构进行设置。
步骤S14，于所述第一开口24内形成第一导电层25，如图2D所示。
具体来说，采用金属铜等导电材料填充满所述第一开口24，形成所述第一导电层25。之后，采用化学机械研磨工艺对所述第一导电层25进行平坦化处理，使得所述第一导电层25的顶面(即所述第一导电层25背离所述衬底20的表面)与所述第一覆盖层23的顶面(即所述第一覆盖层23背离所述衬底20的表面)平齐。
步骤S15，形成覆盖所述第一导电层25和所述第一覆盖层23 的隔离层，如图2E所示。
所述隔离层可以为单层结构，也可以为多层结构，本领域技术人员可以根据实际需要进行选择。为了确保后续形成的所述接触孔的形貌，本具体实施方式中，形成覆盖所述第一导电层25和所述第一覆盖层23的隔离层的具体步骤包括：
形成覆盖所述第一导电层25和所述第一覆盖层23的第一子隔离层26；
形成覆盖所述第一子隔离层26的第二子隔离层27，所述第一子隔离层26和所述第二子隔离层27共同构成隔离层。
具体来说，首先，形成覆盖所述第一导电层25顶面和所述第一覆盖层23顶面的所述第一子隔离层26；然后，形成覆盖所述第一子隔离层26的所述第二子隔离层27。通过形成相互层叠的所述第一子隔离层26和所述第二子隔离层27，通过选择合适的材料，使得所述第一子隔离层26与所述第二子隔离层27之间具有一定的刻蚀选择比(例如刻蚀选择比大于3)，可以通过选择性刻蚀控制后续所要形成的接触孔、沟槽和第二开口的形貌。在本具体实施方式中，所述第一子隔离层26可以为单层结构，其材料为氮化物材料，例如氮化硅；所述第一子隔离层26也可为由SIN/SICN/SION构成的多层结构。所述第二子隔离层27的材料可以为氧化物材料，例如二氧化硅。
步骤S16，于所述第一区域Ⅰ形成暴露所述第一导电层25的接触孔31和位于所述接触孔31上方且与所述接触孔31连通的沟槽30、并于所述第二区域Ⅱ形成暴露所述第二插塞22的第二开口32，如图2G所示。
可选实施例中，于所述第一区域Ⅰ形成暴露所述第一导电层25的接触孔31和位于所述接触孔31上方且与所述接触孔31连通的沟槽30、并于所述第二区域Ⅱ形成暴露所述第二插塞22的第二开口32的具体步骤包括：
刻蚀位于所述第一区域Ⅰ和所述第二区域Ⅱ的所述第二子隔离层27，于所述第一区域Ⅰ形成暴露所述第一子隔离层26的初始接 触孔28、并于所述第二区域Ⅱ形成贯穿所述第二子隔离层27的初始第二开口29，如图2F所示；
刻蚀所述初始接触孔28侧壁的所述第二子隔离层27和所述初始接触孔28底部的所述第一子隔离层26、并刻蚀所述初始第二开口29底部的所述第一子隔离层26和所述第一覆盖层23，于所述第一区域Ⅰ形成暴露所述第一导电层25的接触孔31和位于所述接触孔31上方且与所述接触孔31连通的沟槽30、并于所述第二区域Ⅱ形成暴露所述第二插塞22的第二开口32，如图2G所示。
为了简化刻蚀步骤，可选实施例中，所述第二子隔离层27的材料与所述第一覆盖层23的材料相同。
具体来说，在形成所述第一子隔离层26和所述第二子隔离层27之后，先以所述第一子隔离层26为刻蚀截止层刻蚀所述第二子隔离层27，于所述第一区域Ⅰ上、与所述第一导电层25对应的位置形成贯穿所述第二子隔离层27的所述初始接触孔28，并于所述第二区域Ⅱ上、与所述第二插塞22对应的位置形成贯穿所述第二子隔离层27的所述初始第二开口29。接着，沿所述初始接触孔28刻蚀所述初始接触孔28底部的所述第一子隔离层26、暴露所述第一导电层25，并同时沿所述初始第二开口29刻蚀所述第一子隔离层26、暴露位于所述第二区域Ⅱ上的所述第一覆盖层23。刻蚀所述初始接触孔28上部的侧壁，扩大所述初始接触孔28上部的开口尺寸，并使得多个所述初始接触孔28的上部连通，形成内径尺寸大于一个所述初始接触孔28的所述沟槽30。在其他具体实施方式中，也可以仅仅扩大所述初始接触孔28的上部的开口宽度，而无需使相邻的所述初始接触孔28连通。之后，沿所述初始第二开口29继续刻蚀所述第一覆盖层23，暴露所述第二插塞23。本具体实施方式将所述第二子隔离层27的材料设置为与所述第一覆盖层23的材料相同，从而在刻蚀形成所述沟槽30的过程中，同时对所述第一覆盖层23进行刻蚀以形成所述第二开口32，能够节省刻蚀步骤，降低刻蚀成本，提高刻蚀效率。
本具体实施方式是以在双层大马士革结构中先形成所述接触孔 31、再形成所述沟槽为例进行说明。在其他具体实施方式中，可以先形成双层大马士革结构中的沟槽、再形成用于连接相邻两层导电层的接触孔。附图3A-3B是本申请另一具体实施方式在形成集成电路装置的过程中主要的工艺截面示意图。如图3A-3B所示，在其他具体实施方式中，于所述第一区域Ⅰ形成暴露所述第一导电层25的接触孔31和位于所述接触孔31上方且与所述接触孔31连通的沟槽30、并于所述第二区域Ⅱ形成暴露所述第二插塞22的第二开口32的具体步骤：
包括：刻蚀位于所述第一区域Ⅰ和所述第二区域Ⅱ的所述第二子隔离层27，于所述第一区域Ⅰ形成未贯穿所述第二子隔离层27的初始沟槽40、并于所述第二区域Ⅱ形成未贯穿所述第二子隔离层27的窗口41；
刻蚀所述初始沟槽40底部的所述第二子隔离层27和第一子隔离层26、并刻蚀所述窗口41底部的所述第二子隔离层27、所述第一子隔离层26和所述第一覆盖层23，于所述第一区域Ⅰ形成暴露所述第一导电层25的接触孔31和位于所述接触孔31上方且与所述接触孔31连通的沟槽30、并于所述第二区域Ⅱ形成暴露所述第二插塞22的第二开口32，如图3B所示。
步骤S17，于所述接触孔31内形成导电连接层33、于所述沟槽30内形成第二导电层34、并于所述第二开口32内形成熔丝35。
可选实施例中，于所述接触孔31内形成导电连接层33、于所述沟槽30内形成第二导电层34、并于所述第二开口32内形成熔丝35的具体步骤包括：
填充导电材料于所述接触孔31、所述沟槽30和所述第二开口32内，于所述接触孔31内形成导电连接层33、于所述沟槽30内形成第二导电层34、并于所述第二开口32内形成熔丝35。
具体来说，所述导电连接层33、所述第二导电层34、所述熔丝35的材料可以均与所述第一导电层25的材料相同，例如均为金属铜材料。本领域技术人员也可以根据实际需要将所述导电连接层33、 所述第二导电层34、所述熔丝35和所述第一导电层25的材料设置为不同。所述熔丝35的截面形状可以为圆形，也可以为圆角矩形。
可选实施例中，所述集成电路装置的形成方法还包括如下步骤：
形成覆盖所述第二导电层34、所述熔丝35和所述隔离层的第二覆盖层。
具体来说，所述第二覆盖层可以为单层结构，也可以为多层结构。在本具体实施方式中，以所述第二覆盖层为多层结构为例进行说明。如图2I所示，
所述第二覆盖层包括第一保护层36和第二保护层37。所述第一保护层36可以为单层结构，其材料为氮化物材料，例如氮化硅；所述第一保护层36也可为由SIN/SICN/SION构成的多层结构。所述第二保护层37的材料为氧化物材料，例如二氧化硅。
在形成包括所述第一保护层36和所述第二保护层37的所述第二覆盖层之后，可以再在所述第二覆盖层之上依次形成第三覆盖层381和第四覆盖层382，并通过刻蚀位于所述第二区域Ⅱ的所述第四覆盖层382、所述第三覆盖层381和所述第二保护层37，形成贯穿所述第四覆盖层382、所述第三覆盖层381和所述第二保护层37、并暴露所述第一保护层36的第三开口39，如图2J所示。
后续可以通过所述第三开口39对所述熔丝35进行熔断。其中，所述第三覆盖层381为单层结构(其材料为硬掩模材料，例如氮化硅或者氮氧化硅)，也可以为多层结构。所述第四覆盖层382也可以为单层结构(其材料为有机掩膜材料，例如无定形碳)，也可以为多层结构。
不仅如此，本具体实施方式还提供了一种集成电路装置。本具体实施方式提供的集成电路装置可以采用如图1、图2A-图2J或者图3A-图3B所示的方法形成，所述集成电路装置的具体结构可参见图2I和图2J。如图2I、图2J所示，本具体实施方式提供的集成电路装置，包括：
衬底20，所述衬底20包括第一区域Ⅰ和位于所述第一区域Ⅰ外部的第二区域Ⅱ，所述衬底20内部具有位于所述第一区域Ⅰ的第 一插塞21和位于所述第二区域Ⅱ的第二插塞22，所述衬底20表面具有第一覆盖层23和位于所述第一覆盖层23表面的隔离层；
第一导电层25，位于所述第一区域Ⅰ的所述第一覆盖层23内，且与所述第一插塞21电连接；
导电连接层33，位于所述第一导电层25表面；
第二导电层34，位于所述导电连接层33表面，所述导电连接层33的一端电连接所述第一导电层25、另一端电连接所述第二导电层34；
熔丝35，位于所述第二区域Ⅱ，所述熔丝35呈实心柱状结构、并贯穿所述隔离层和所述第一覆盖层23，所述熔丝35的底面与所述第二插塞22电连接、所述熔丝35的顶面与所述第二导电层34的顶面平齐。
可选实施例中，所述熔丝35、所述第二导电层34和所述导电连接层33的材料相同。
可选实施例中，所述隔离层包括：
第一子隔离层26，覆盖于所述第一覆盖层23表面；
第二子隔离层27，覆盖于所述第一子隔离层26表面，且所述第二子隔离层27的厚度大于所述第一子隔离层26。
可选实施例中，所述第二子隔离层27的材料与所述第一覆盖层23的材料相同。
可选实施例中，所述集成电路装置还包括：
第二覆盖层，覆盖于所述第二导电层34、所述熔丝35和所述隔离层表面。
本具体实施方式提供的集成电路装置及其形成方法，在形成第一导电层的过程中，不对用于形成熔丝的第二区域进行处理，在形成导电连接层和第二导电层的过程中同时形成熔丝，使得形成的熔丝呈简单的实心柱状结构，与第一导电层和第二导电层的结构无关，不仅简化了熔丝的结构，使得仅仅只需要较低的能量就可以实现熔丝的熔断，而且简化了整个集成电路装置的制造流程，降低了集成电路装置的制程成本，也提高了集成电路装置的良率。
应当理解的是，本发明的上述具体实施方式仅仅用于示例性说明或解释本发明的原理，而不构成对本发明的限制。因此，在不偏离本发明的精神和范围的情况下所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。此外，本发明所附权利要求旨在涵盖落入所附权利要求范围和边界、或者这种范围和边界的等同形式内的全部变化和修改例。

Claims (14)

  1. 一种集成电路装置的形成方法，其特征在于，包括如下步骤：
    提供一衬底，所述衬底包括第一区域和位于所述第一区域外部的第二区域，所述衬底内部具有位于所述第一区域的第一插塞和位于所述第二区域的第二插塞；
    形成覆盖所述衬底的第一覆盖层；
    刻蚀所述第一覆盖层，于所述第一区域形成暴露所述第一插塞的第一开口；
    于所述第一开口内形成第一导电层；
    形成覆盖所述第一导电层和所述第一覆盖层的隔离层；
    于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口；
    于所述接触孔内形成导电连接层、于所述沟槽内形成第二导电层、并于所述第二开口内形成熔丝。
  2. 根据权利要求1所述的集成电路装置的形成方法，其特征在于，形成覆盖所述第一导电层和所述第一覆盖层的隔离层的具体步骤包括：
    形成覆盖所述第一导电层和所述第一覆盖层的第一子隔离层；
    形成覆盖所述第一子隔离层的第二子隔离层，所述第一子隔离层和所述第二子隔离层共同构成隔离层。
  3. 根据权利要求2所述的集成电路装置的形成方法，其特征在于，于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口的具体步骤包括：
    刻蚀位于所述第一区域和所述第二区域的所述第二子隔离层，于所述第一区域形成暴露所述第一子隔离层的初始接触孔、并于所述第二区域形成贯穿所述第二子隔离层的初始第二开口；
    刻蚀所述初始接触孔侧壁的所述第二子隔离层和所述初始接触孔底部的所述第一子隔离层、并刻蚀所述初始第二开口底部的所述第一子隔离层和所述第一覆盖层，
    于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口。
  4. 根据权利要求2所述的集成电路装置的形成方法，其特征在于，于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口的具体步骤包括：
    刻蚀位于所述第一区域和所述第二区域的所述第二子隔离层，于所述第一区域形成未贯穿所述第二子隔离层的初始沟槽、并于所述第二区域形成未贯穿所述第二子隔离层的窗口；
    刻蚀所述初始沟槽底部的所述第二子隔离层和第一子隔离层、并刻蚀所述窗口底部的所述第二子隔离层、所述第一子隔离层和所述第一覆盖层，
    于所述第一区域形成暴露所述第一导电层的接触孔和位于所述接触孔上方且与所述接触孔连通的沟槽、并于所述第二区域形成暴露所述第二插塞的第二开口。
  5. 根据权利要求2所述的集成电路装置的形成方法，其特征在于，所述第二子隔离层的材料与所述第一覆盖层的材料相同。
  6. 根据权利要求1所述的集成电路装置的形成方法，其特征在于，于所述接触孔内形成导电连接层、于所述沟槽内形成第二导电层、并于所述第二开口内形成熔丝的具体步骤包括：
    填充导电材料于所述接触孔、所述沟槽和所述第二开口内，于所述接触孔内形成导电连接层、于所述沟槽内形成第二导电层、并于所述第二开口内形成熔丝。
  7. 根据权利要求1所述的集成电路装置的形成方法，其特征在于，还包括如下步骤：
    形成覆盖所述第二导电层、所述熔丝和所述隔离层的第二覆盖 层。
  8. 根据权利要求7所述的集成电路装置的形成方法，其特征在于，第二覆盖层包括：
    第一保护层，覆盖于所述第二导电层、所述熔丝和所述隔离层表面；
    第二保护层，覆盖于所述第一保护层表面。
  9. 根据权利要求8所述的集成电路装置的形成方法，其特征在于，在所述第二覆盖层之上依次形成第三覆盖层和第四覆盖层；
    刻蚀位于所述第二区域Ⅱ的所述第四覆盖层、所述第三覆盖层和所述第二保护层，形成贯穿所述第四覆盖层、所述第三覆盖层和所述第二保护层、并暴露所述第一保护层的第三开口。
  10. 一种集成电路装置，其特征在于，包括：
    衬底，所述衬底包括第一区域和位于所述第一区域外部的第二区域，所述衬底内部具有位于所述第一区域的第一插塞和位于所述第二区域的第二插塞，所述衬底表面具有第一覆盖层和位于所述第一覆盖层表面的隔离层；
    第一导电层，位于所述第一区域的所述第一覆盖层内，且与所述第一插塞电连接；
    导电连接层，位于所述第一导电层表面；
    第二导电层，位于所述导电连接层表面，所述导电连接层的一端电连接所述第一导电层、另一端电连接所述第二导电层；
    熔丝，位于所述第二区域，所述熔丝呈实心柱状结构、并贯穿所述隔离层和所述第一覆盖层，所述熔丝的底面与所述第二插塞电连接、所述熔丝的顶面与所述第二导电层的顶面平齐。
  11. 根据权利要求10所述的集成电路装置，其特征在于，所述熔丝、所述第二导电层和所述导电连接层的材料相同。
  12. 根据权利要求10所述的集成电路装置，其特征在于，所述隔离层包括：
    第一子隔离层，覆盖于所述第一覆盖层表面；
    第二子隔离层，覆盖于所述第一子隔离层表面，且所述第二子隔 离层的厚度大于所述第一子隔离层。
  13. 根据权利要求12所述的集成电路装置，其特征在于，所述第二子隔离层的材料与所述第一覆盖层的材料相同。
  14. 根据权利要求10所述的集成电路装置，其特征在于，还包括：
    第二覆盖层，覆盖于所述第二导电层、所述熔丝和所述隔离层表面。
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