WO2022090858A1 - 半導体装置、表示装置、および電子機器 - Google Patents

半導体装置、表示装置、および電子機器 Download PDF

Info

Publication number
WO2022090858A1
WO2022090858A1 PCT/IB2021/059548 IB2021059548W WO2022090858A1 WO 2022090858 A1 WO2022090858 A1 WO 2022090858A1 IB 2021059548 W IB2021059548 W IB 2021059548W WO 2022090858 A1 WO2022090858 A1 WO 2022090858A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
transistor
potential
signal
block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/IB2021/059548
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
吉本智史
楠紘慈
渡邉一徳
川島進
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to KR1020237013828A priority Critical patent/KR20230092925A/ko
Priority to JP2022558371A priority patent/JP7660134B2/ja
Priority to CN202180071692.7A priority patent/CN116490914A/zh
Priority to US18/033,710 priority patent/US20230395022A1/en
Publication of WO2022090858A1 publication Critical patent/WO2022090858A1/ja
Anticipated expiration legal-status Critical
Priority to JP2025058311A priority patent/JP7837450B2/ja
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K39/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic radiation-sensitive element covered by group H10K30/00
    • H10K39/30—Devices controlled by radiation
    • H10K39/32—Organic image sensors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0857—Static memory circuit, e.g. flip-flop
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/14—Detecting light within display terminals, e.g. using a single or a plurality of photosensors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays

Definitions

  • Patent Document 1 discloses a technique in which a circuit such as a shift register is composed of a unipolar transistor.
  • a sensor element or the like can be incorporated into the pixel to enhance the functionality.
  • a capacitance sensor into the display device, it can function as a touch panel.
  • an optical sensor into the display device, it is possible to provide an image pickup function, a non-contact input function, or the like.
  • one aspect of the present invention is to provide a semiconductor device for driving two different circuits.
  • one of the objects is to provide a semiconductor device for driving a pixel having a first circuit and a second circuit.
  • one of the purposes is to provide a display device having the above-mentioned semiconductor device.
  • Another object of the present invention is to provide a method for driving the semiconductor device, the display device, and the like.
  • one of the purposes is to provide a new semiconductor device, display device, or the like.
  • a semiconductor device for driving two different circuits can be provided.
  • a semiconductor device for driving a pixel having a first circuit and a second circuit can be provided.
  • a display device having the above-mentioned semiconductor device it is possible to provide a method for driving the semiconductor device, the display device, and the like.
  • a new semiconductor device, display device, or the like can be provided.
  • FIG. 1 is a block diagram illustrating a semiconductor device according to an aspect of the present invention.
  • the semiconductor device 20 is a sequential circuit that sequentially outputs signal potentials to the outside, and is also called a shift register. Note that FIG. 1 is a schematic diagram, and details such as the signal potential input to each element, the power supply potential, and the connection form between the elements are omitted.
  • the terminal LIN2 is electrically connected to the input terminal (terminal to which the shift signal LIN is input) of the flip-flop circuit 10 in the 37th stage and the switch circuit 19 described later.
  • the terminal SWIN2 is electrically connected to the output terminal (terminal for outputting the signal potential SROUT) of the fifth-stage flip-flop circuit 10.
  • the terminal LIN1 is electrically connected to the input terminal (terminal to which the shift signal LIN is input) of the 37th stage flip-flop circuit 10.
  • the terminal SWIN2 is electrically connected to the output terminal (terminal for outputting the signal potential SROUT) of the 37th stage flip-flop circuit 10.
  • FIG. 12A shows a block diagram of the switch circuit 12 included in the semiconductor device 20b
  • FIG. 12B shows an example of the circuit diagram of the switch circuit 12. Refer to FIG. 12B for the connection form of the transistor and the capacitor constituting the switch circuit 12, and the description thereof will be omitted.
  • the signal potential GLA1 can be output to the wiring to which the external circuit is connected. Further, by inputting the signal potential FN_A and the pulse width control signal A_PWCA, a transistor corresponding to a pull-down resistor can be operated to stabilize the potential of the wiring to VSS.
  • the signal potential GLB2 can be output to the wiring to which the external circuit is connected. Further, by inputting the signal potential FN_B and the pulse width control signal B_PWCB, a transistor corresponding to a pull-down resistor can be operated to stabilize the potential of the wiring to VSS.
  • an n-channel transistor can be used as a component.
  • the semiconductor material that can be used in the channel forming region of the n-channel transistor is preferably silicon or a metal oxide.
  • High-quality polycrystalline silicon can be easily obtained by using a laser crystallization step or the like.
  • High-quality polycrystalline silicon can also be obtained by a solid-phase growth method in which a metal catalyst such as nickel or palladium is added to amorphous silicon and heated. Further, the polycrystalline silicon formed by the solid phase growth method using a metal catalyst may be irradiated with a laser to further improve the crystallinity. Since the metal catalyst remains in the polysilicon and deteriorates the electrical characteristics of the transistor, it is preferable to provide a region to which phosphorus or noble gas is added in addition to the channel forming region and allow the metal catalyst to be captured in the region. ..
  • the OS transistor Since the OS transistor has a large energy gap in the semiconductor layer, it can exhibit an extremely low off-current characteristic of several yA / ⁇ m (current value per 1 ⁇ m of channel width). Therefore, when the OS transistor is used in the pixel circuit of the display device, the data potential can be held in the pixel circuit for a long time.
  • the semiconductor device of one aspect of the present invention can be used in a drive circuit (for example, a low driver) of the display device.
  • a drive circuit for example, a low driver
  • the OS transistor has characteristics different from those of the Si transistor, such as no impact ionization, avalanche breakdown, and short channel effect, and can form a highly reliable circuit. In addition, variations in electrical characteristics due to crystallinity non-uniformity, which is a problem with Si transistors, are unlikely to occur with OS transistors.
  • an oxide semiconductor having a low carrier concentration is used as the semiconductor layer.
  • the semiconductor layer has a carrier concentration of 1 ⁇ 10 17 / cm 3 or less, preferably 1 ⁇ 10 15 / cm 3 or less, more preferably 1 ⁇ 10 13 / cm 3 or less, and more preferably 1 ⁇ 10 11 / cm.
  • Oxide semiconductors having a carrier concentration of 3 or less, more preferably less than 1 ⁇ 10 10 / cm 3 and 1 ⁇ 10 -9 / cm 3 or more, can be used.
  • Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. It can be said that the oxide semiconductor is an oxide semiconductor having a low defect level density and stable characteristics.
  • the concentration of the alkali metal or alkaline earth metal in the semiconductor layer is 1 ⁇ 10 18 atoms / cm 3 or less, preferably 2 ⁇ 10 16 atoms / cm 3 or less.
  • the nitrogen concentration in the semiconductor layer is preferably 5 ⁇ 10 18 atoms / cm 3 or less.
  • the oxide semiconductor constituting the semiconductor layer when the oxide semiconductor constituting the semiconductor layer contains hydrogen, it reacts with oxygen bonded to a metal atom to become water, which may form an oxygen deficiency in the oxide semiconductor. If the channel formation region in the oxide semiconductor contains oxygen deficiency, the transistor may have normally-on characteristics. In addition, a defect containing hydrogen in an oxygen deficiency may function as a donor and generate electrons as carriers. In addition, a part of hydrogen may be combined with oxygen that is bonded to a metal atom to generate an electron as a carrier. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen tends to have normally-on characteristics.
  • the hydrogen concentration obtained by secondary ion mass spectrometry is less than 1 ⁇ 10 20 atoms / cm 3 , preferably 1 ⁇ 10 19 atoms / cm. It is less than 3 , more preferably less than 5 ⁇ 10 18 atoms / cm 3 , and even more preferably less than 1 ⁇ 10 18 atoms / cm 3 .
  • the semiconductor layer may have, for example, a non-single crystal structure.
  • the non-single crystal structure includes, for example, a CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor) having crystals oriented on the c-axis, a polycrystalline structure, a microcrystal structure, or an amorphous structure.
  • CAAC-OS C-Axis Aligned Crystalline Oxide Semiconductor
  • the amorphous structure has the highest defect level density
  • CAAC-OS has the lowest defect level density.
  • the oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and has no crystal component.
  • the oxide film having an amorphous structure is, for example, a completely amorphous structure and has no crystal portion.
  • CAC Cloud-Aligned Complex
  • the oxide semiconductor preferably contains at least indium. In particular, it preferably contains indium and zinc. Also, in addition to them, aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lantern, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium, etc. One or more selected from the above may be included.
  • CAC-OS in In-Ga-Zn oxide is an indium oxide (hereinafter, InO).
  • InO indium oxide
  • X1 X1 is a real number larger than 0
  • In X2 Zn Y2 O Z2 X2, Y2, and Z2 are real numbers larger than 0
  • gallium With an oxide (hereinafter, GaO X3 (X3 is a real number larger than 0)) or gallium zinc oxide (hereinafter, Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers larger than 0)).
  • Ga X4 Zn Y4 O Z4 X4, Y4, and Z4 are real numbers larger than 0
  • IGZO is a common name and may refer to one compound consisting of In, Ga, Zn, and O. As a typical example, it is represented by InGaO 3 (ZnO) m1 (m1 is a natural number) or In (1 + x0) Ga (1-x0) O 3 (ZnO) m0 (-1 ⁇ x0 ⁇ 1, m0 is an arbitrary number). Crystalline compounds can be mentioned.
  • the crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure.
  • the CAAC structure is a crystal structure in which a plurality of IGZO nanocrystals have a c-axis orientation and are connected without orientation on the ab plane.
  • CAC-OS relates to the material composition of oxide semiconductors.
  • CAC-OS is a region that is observed in the form of nanoparticles mainly composed of Ga in a material structure containing In, Ga, Zn, and O, and nanoparticles mainly composed of In. The regions observed in the shape are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.
  • the CAC-OS does not include a laminated structure of two or more types of films having different compositions. For example, it does not include a structure consisting of two layers, a film containing In as a main component and a film containing Ga as a main component.
  • CAC-OS has a region observed in the form of nanoparticles mainly composed of the metal element and a nano portion containing In as a main component.
  • the regions observed in the form of particles refer to a configuration in which the regions are randomly dispersed in a mosaic pattern.
  • the CAC-OS can be formed by a sputtering method, for example, under the condition that the substrate is not intentionally heated.
  • a sputtering method one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas may be used as the film forming gas. good.
  • the lower the flow rate ratio of the oxygen gas to the total flow rate of the film-forming gas at the time of film formation is preferable, and for example, the flow rate ratio of the oxygen gas is preferably 0% or more and less than 30%, preferably 0% or more and 10% or less. ..
  • CAC-OS is characterized by the fact that no clear peak is observed when measured using the ⁇ / 2 ⁇ scan by the Out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. Have. That is, from the X-ray diffraction measurement, it can be seen that the orientation of the measurement region in the ab plane direction and the c axis direction is not observed.
  • XRD X-ray diffraction
  • the CAC-OS has a ring-shaped high-brightness region (ring region) and the ring in an electron beam diffraction pattern obtained by irradiating an electron beam (also referred to as a nanobeam electron beam) having a probe diameter of 1 nm. Multiple bright spots are observed in the area. Therefore, from the electron diffraction pattern, it can be seen that the crystal structure of CAC-OS has an nc (nano-crystal) structure having no orientation in the planar direction and the cross-sectional direction.
  • nc nano-crystal
  • GaO X3 is the main component by EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX). It can be confirmed that the region and the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component have a structure in which they are unevenly distributed and mixed.
  • EDX energy dispersive X-ray spectroscopy
  • CAC-OS has a structure different from that of the IGZO compound in which metal elements are uniformly distributed, and has properties different from those of the IGZO compound. That is, the CAC-OS is phase-separated into a region containing GaO X3 or the like as a main component and a region containing In X2 Zn Y2 O Z2 or InO X1 as a main component, and a region containing each element as a main component. Has a mosaic-like structure.
  • the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component is a region having higher conductivity than the region in which GaO X3 or the like is the main component. That is, the conductivity as an oxide semiconductor is exhibited by the carrier flowing through the region where In X2 Zn Y2 O Z2 or InO X1 is the main component. Therefore, a high field effect mobility ( ⁇ ) can be realized by distributing the region containing In X2 Zn Y2 O Z2 or InO X1 as a main component in the oxide semiconductor in a cloud shape.
  • the region in which GaO X3 or the like is the main component is a region having higher insulating properties than the region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. That is, since the region containing GaO X3 or the like as the main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be realized.
  • CAC-OS when CAC-OS is used for a semiconductor device, the insulation caused by GaO X3 and the like and the conductivity caused by In X2 Zn Y2 O Z2 or InO X1 act in a complementary manner, resulting in high efficiency. On current (Ion) and high field effect mobility ( ⁇ ) can be achieved.
  • CAC-OS is suitable as a constituent material for various semiconductor devices.
  • semiconductor device 20a and the semiconductor device 20b described above use the n-channel transistor as a component, a p-channel transistor may be used as a component.
  • FIG. 15 is a block diagram of a semiconductor device 20c using a p-channel transistor as a component of a circuit.
  • the connection configuration of each element circuit is the same as that of the semiconductor device 20a shown in FIGS. 3 and 4, and a part thereof is shown in FIG.
  • the configurations of the switch circuit 16 and the switch circuit 17, and the signals input to them are different from those of the semiconductor device 20a, in addition to the fact that the p-channel transistor is a component of the circuit.
  • FIG. 16A shows a block diagram of the flip-flop circuit 10
  • FIG. 16B shows an example of a circuit diagram of the flip-flop circuit 10 composed of a p-channel transistor.
  • the flip-flop circuit 10 shown in FIG. 16B is provided with a power supply potential obtained by inverting the power supply potential (VDD, VSS) shown in FIG. 5B.
  • FIG. 17A shows a block diagram of the switch circuit 12, and FIG. 17B shows an example of a circuit diagram of the switch circuit 12 composed of a p-channel transistor.
  • FIG. 6B for the connection form of the transistor and the capacitor constituting the switch circuit 12, and the description thereof will be omitted. Further, for the description of the input signal and the output signal, the description of FIG. 6B can be referred to.
  • the switch circuit 12 shown in FIG. 17B is provided with a power supply potential obtained by inverting the power supply potential (VDD, VSS) shown in FIG. 6B.
  • FIG. 18A shows a block diagram of the circuit 13, and FIG. 18B shows an example of a circuit diagram of the circuit 13 composed of a p-channel transistor.
  • FIG. 7B for the connection form of the transistor and the capacitor constituting the circuit 13, and the description thereof will be omitted. Further, for the description of the input signal and the output signal, the description of FIG. 7B can be referred to.
  • the circuit 13 shown in FIG. 18B is provided with a power supply potential obtained by inverting the power supply potential (whether, VSS) shown in FIG. 7B.
  • FIG. 18C shows a block diagram of the circuit 14, and FIG. 18D shows an example of a circuit diagram of the circuit 14 composed of a p-channel transistor.
  • FIG. 18D for the connection form of the transistor and the capacitor constituting the circuit 14, and the description thereof will be omitted. Further, for the description of the input signal and the output signal, the description of FIG. 7D can be referred to.
  • the circuit 14 shown in FIG. 18D is provided with a power supply potential obtained by inverting the power supply potential (VDD, VSS) shown in FIG. 7D.
  • FIG. 19A shows a block diagram of the switch circuit 16
  • FIG. 19B shows an example of a circuit diagram of the switch circuit 16 composed of a p-channel transistor. Refer to FIG. 19B for the connection form of the transistors constituting the switch circuit 16, and the description thereof will be omitted.
  • the input signals are the selection signal SEL_A, the selection signal SEL_B1, and the selection signal SEL_B2.
  • the selection signal SEL_B1 or the selection signal SEL_B2 is input, the signal potential SEL_B is generated.
  • the signal potential SEL_B is input to the switch circuit 12 described above. By inputting the selection signal SEL_B to the switch circuit 12, the output of the signal potential from the circuit 14 to the outside can be enabled.
  • the selection signal SEL_A is input, a valid signal potential SEL_B is not generated.
  • FIG. 19C shows a block diagram of the switch circuit 17, and FIG. 19D shows an example of a circuit diagram of the switch circuit 17 composed of a p-channel transistor. Refer to FIG. 19D for the connection form of the transistors constituting the switch circuit 17, and the description thereof will be omitted.
  • the input signals are the selection signal SEL_A, the selection signal SEL_B1, and the selection signal SEL_B2.
  • the selection signal SEL_B1 or the selection signal SEL_B2 is input, the signal potential SEL_C is generated.
  • the signal potential SEL_C is input to the switch circuit 18 and the switch circuit 19 which will be described later.
  • the selection signal SEL_A is input, a valid signal potential SEL_B is not generated.
  • FIG. 20A shows a block diagram of the switch circuit 18, and FIG. 20B shows an example of a circuit diagram of the switch circuit 18 composed of a p-channel transistor.
  • FIG. 20B for the connection form of the transistors constituting the switch circuit 18, and the description thereof will be omitted. Further, for the description of the input signal and the output signal, the description of FIG. 9B can be referred to.
  • the circuit 14 shown in FIG. 20B is provided with a power supply potential obtained by inverting the power supply potential (VDD, VSS) shown in FIG. 9B.
  • FIG. 21A shows a block diagram of the switch circuit 19, and FIG. 21B shows an example of a circuit diagram of the switch circuit 19 composed of a p-channel transistor.
  • FIG. 21B for the connection form of the transistors constituting the switch circuit 19, and the description thereof will be omitted. Further, for the description of the input signal and the output signal, the description of FIG. 10B can be referred to.
  • the circuit 14 shown in FIG. 21B is provided with a power supply potential obtained by inverting the power supply potential (VDD, VSS) shown in FIG. 10B.
  • the signal potential paths output from the circuit 13 and the circuit 14 are each one is shown, but different timings can be obtained by increasing the control signal PWC input to the switch circuit 12, the circuit 13 and the circuit 14.
  • the signal potential can be output from two or more paths.
  • FIG. 22 is a block diagram of the semiconductor device 20d showing an example in which the signal potential paths output from the circuit 13 and the circuit 14 are each two.
  • the signal potential GLA1 and the signal potential GLA2 can be output from the circuit 13 at different timings. Further, the signal potential GLB1 and the signal potential GLB2 can be output from the circuit 14 at different timings.
  • the input signal differs from the semiconductor device 20c shown in FIG. 5 in that the pulse width control signal PWC increases to the pulse width control signals PWCA (PWCA1 to PWCA4) and the pulse width control signals PWCB (PWCB1 to PWCB4). Further, the configurations of the switch circuit 12, the circuit 13, and the circuit 14 are different from those of the semiconductor device 20c.
  • the flip-flop circuit 10, the switch circuits 16, 17, the switch circuits 18, 19 (not shown) of the semiconductor device 20d, and the configuration of connecting these elements to each other may be the same as those of the semiconductor device 20c. can.
  • FIG. 23A shows a block diagram of the switch circuit 12 included in the semiconductor device 20d
  • FIG. 23B shows an example of a circuit diagram of the switch circuit 12 composed of a p-channel transistor.
  • the switch circuit 12 shown in FIG. 23B is provided with a power supply potential obtained by inverting the power supply potential (VDD, VSS) shown in FIG. 12B.
  • FIG. 24A shows a block diagram of the circuit 13 included in the semiconductor device 20d
  • FIG. 24B shows an example of a circuit diagram of the circuit 13 composed of a p-channel transistor.
  • Refer to FIG. 24B for the connection form of the transistor and the capacitor constituting the circuit 13, and the description thereof will be omitted. Further, for the description of the input signal and the output signal, the description of FIG. 13B can be referred to.
  • the circuit 13 shown in FIG. 23B is provided with a power supply potential obtained by inverting the power supply potential (VDD, VSS) shown in FIG. 13B.
  • FIG. 25A shows a block diagram of the circuit 14 included in the semiconductor device 20d
  • FIG. 25B shows an example of a circuit diagram of the circuit 14 composed of a p-channel transistor.
  • FIG. 25B for the connection form of the transistor and the capacitor constituting the circuit 14, and the description thereof will be omitted. Further, for the description of the input signal and the output signal, the description of FIG. 14B can be referred to.
  • the circuit 14 shown in FIG. 23B is provided with a power supply potential obtained by inverting the power supply potential (whether, VSS) shown in FIG. 14B.
  • Si transistor As the p-channel transistor.
  • polycrystalline silicon or single crystal silicon capable of forming a transistor having high mobility even in the p-channel type.
  • the configuration is not limited to the configuration in which all the transistors of the pixel circuit and the drive circuit are formed of Si transistors, and the drive circuit may be formed of Si transistors and the pixel circuit may be formed of OS transistors. Alternatively, some transistors included in the pixel circuit and the drive circuit may be formed by one of the Si transistor or the OS transistor, and the other transistor may be formed by the other of the Si transistor or the OS transistor.
  • the above configuration may be appropriately determined according to the functions required for the display device and the like.
  • This embodiment can be carried out in combination with at least a part thereof as appropriate in combination with other embodiments described in the present specification.
  • FIG. 26 is a diagram illustrating a display device according to an aspect of the present invention.
  • the display device includes a pixel array 23 having pixels 24 arranged in the column direction and the row direction, a circuit 40, a circuit 41, and a circuit 42.
  • the wiring connecting each block shown in FIG. 26 is simplified and may differ from the actual number of wirings.
  • Pixel 24 has a circuit 25 and a circuit 26.
  • the circuit 25 has a function of emitting light for display.
  • the circuit 26 has a function of detecting light.
  • the circuit 25 and the circuit 26 can also be referred to as sub-pixels.
  • the circuit 25 has a light emitting device (also referred to as a light emitting element) that emits visible light.
  • a light emitting device it is preferable to use an EL element such as an OLED (Organic Light Emitting Diode) or a QLED (Quantum-dot Light Emitting Diode).
  • the light emitting substances of the EL element include fluorescent substances (fluorescent materials), phosphorescent substances (phosphorescent materials), inorganic compounds (quantum dot materials, etc.), and substances showing thermal activated delayed fluorescence (thermally activated delayed fluorescence). (Thermally Activated Fluorescence: TADF) material) and the like.
  • an LED such as a micro LED (Light Emitting Diode) can also be used.
  • the circuit 26 has a light receiving device (also referred to as a light receiving element).
  • a light receiving device for example, a pn type or pin type photodiode can be used.
  • a photoelectric conversion element that detects incident light and generates an electric charge can be used. In the light receiving device, the amount of electric charge generated is determined based on the amount of incident light.
  • an organic photodiode having an organic compound in the photoelectric conversion layer As the light receiving device, it is preferable to use an organic photodiode having an organic compound in the photoelectric conversion layer.
  • Organic photodiodes can be easily made thinner, lighter, and larger in area. In addition, since it has a high degree of freedom in shape and design, it can be applied to various display devices.
  • a photodiode using amorphous silicon, crystalline silicon (single crystal silicon, polycrystalline silicon, microcrystalline silicon, etc.), metal oxide, or the like can be used as the light receiving device.
  • the photoelectric conversion layer of the photodiode When an organic compound is used for the photoelectric conversion layer of the photodiode, it is possible to have sensitivity from ultraviolet light to infrared light by appropriately selecting the material.
  • amorphous silicon When amorphous silicon is used for the photoelectric conversion layer, it is mainly sensitive to visible light, and when crystalline silicon is used, it is sensitive from visible light to infrared light.
  • the metal oxide Since the metal oxide has a large energy gap, when the metal oxide is used for the photoelectric conversion layer, it has high sensitivity mainly to light having higher energy than visible light.
  • the metal oxide for example, the In—M—Zn-based oxide described in the first embodiment can be used.
  • an organic EL element is used as a light emitting device
  • an organic photodiode is used as a light receiving device.
  • Organic photodiodes have many layers that can have the same configuration as organic EL devices. Therefore, the light receiving device can be built in the display device without significantly increasing the manufacturing process.
  • the photoelectric conversion layer of the light receiving device and the light emitting layer of the light emitting device may be formed separately, and the other layers may have the same configuration for the light emitting device and the light receiving device.
  • the circuit 40 is a low driver (gate driver) for driving the circuit 25 and the circuit 26.
  • the semiconductor device 20a, the semiconductor device 20b, the semiconductor device 20c, or the semiconductor device 20d described in the first embodiment can be used.
  • the circuit 41 is a column driver (source driver) that supplies image data or the like to the circuit 25.
  • a shift register circuit or a decoder circuit can be used.
  • the circuit 42 is a read circuit for data output by the circuit 26.
  • the circuit 42 has, for example, an A / D conversion circuit, and has a function of converting analog data output from the circuit 26 into digital data.
  • the circuit 42 may have a CDS circuit that performs a correlated double sampling process on the output data of the circuit 26.
  • a selection circuit multiplexer circuit
  • it may have a column driver that outputs digital data to the outside.
  • the circuit 26 can have a function as an input interface.
  • the circuit 26 has a light receiving device, and can read out position information of an object close to the display device from a change in the amount of light reaching the pixel array 23. Therefore, the same operation as the touch panel can be performed without contact. In addition, operations such as pointers can be performed non-contactly.
  • the object may be brought into contact with the display device and the imaging data may be acquired by the circuit 26.
  • imaging data such as fingerprints or palm prints can be acquired at high resolution. That is, the biometric authentication function can be added to the display device.
  • the image pickup data can be obtained by receiving the light emitted by the circuit 25 and reflected by the object by the circuit 26. At this time, the light emitted by the circuit 25 is preferably green light or white light.
  • FIG. 27A shows an example of the pixel circuit PIX1 applicable to the circuit 25.
  • the pixel circuit PIX1 includes a light emitting device EL, a transistor M1, a transistor M2, a transistor M3, and a capacitor C1.
  • a light emitting diode is used as the light emitting device EL. It is preferable to use an organic EL element that emits visible light as the light emitting device EL.
  • the gate is electrically connected to the wiring G1
  • one of the source or the drain is electrically connected to the wiring S1
  • the other of the source or the drain is electrically connected to one electrode of the capacitor C1 and the gate of the transistor M2.
  • One of the source or drain of the transistor M2 is electrically connected to the wiring V2
  • the other is electrically connected to one of the anode of the light emitting device EL and the source or drain of the transistor M3.
  • the gate is electrically connected to the wiring G2, and the other of the source or the drain is electrically connected to the wiring V0.
  • the cathode of the light emitting device EL is electrically connected to the wiring V1.
  • a constant potential is supplied to the wiring V1 and the wiring V2, respectively.
  • Light emission can be performed by setting the anode side of the light emitting device EL to a high potential and the cathode side to a low potential.
  • the transistor M1 is controlled by a signal supplied to the wiring G1 and functions as a selection transistor for controlling the selection state of the pixel circuit PIX1. Further, the transistor M2 functions as a drive transistor that controls the current flowing through the light emitting device EL according to the potential supplied to the gate.
  • the potential supplied to the wiring S1 is supplied to the gate of the transistor M2, and the emission luminance of the light emitting device EL can be controlled according to the potential.
  • the transistor M3 is controlled by a signal supplied to the wiring G2.
  • the potential between the transistor M3 and the light emitting device EL can be reset to the constant potential supplied from the wiring V0, and the potential can be written to the gate of the transistor M2 with the source potential of the transistor M2 stabilized. Can be done.
  • FIG. 27B shows an example of the pixel circuit PIX2 applicable to the circuit 25.
  • the pixel circuit PIX2 has a boosting function.
  • the pixel circuit PIX2 includes a light emitting device EL, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a capacitor C2 and a capacitor C3.
  • the gate is electrically connected to the wiring G1, one of the source and the drain is electrically connected to the wiring S1, and the other of the source and the drain is one electrode of the capacitor C2 and one electrode of the capacitor C3. And electrically connected to the gate of the transistor M7.
  • the gate is electrically connected to the wiring G2, one of the source or drain is electrically connected to the wiring VRW, and the other of the source or drain is the other electrode of the capacitor C2, the source or drain of the transistor M6. Electrically connect to one.
  • the gate of the transistor M6 is electrically connected to the wiring G1 and the other of the source or drain is electrically connected to the other electrode of the capacitor C3, one of the source or drain of the transistor M7, and the anode of the light emitting device EL.
  • the other of the source or drain of the transistor M7 is electrically connected to the wiring V2.
  • the transistor M4 and the transistor M6 are controlled by the signal supplied to the wiring G1, and the transistor M5 is controlled by the signal supplied to the wiring G2.
  • the transistor M7 functions as a drive transistor that controls the current flowing through the light emitting device EL according to the potential supplied to the gate.
  • the potential between the transistor M7 and the light emitting device EL can be reset to a constant potential (for example, reset potential VRES) supplied from the wiring VRW. Therefore, the potential of the wiring S1 can be written to the gate of the transistor M7 in a state where the source potential of the transistor M7 is stabilized. Further, by setting the reset potential VRES to the same potential as the wiring V1 or a potential lower than the wiring V1, the light emission of the light emitting device EL can be suppressed.
  • a constant potential for example, reset potential VRES
  • the emission intensity of the light emitting device EL can be increased.
  • the boosting function of the pixel circuit PIX2 will be described with reference to the timing chart shown in FIG. 27C.
  • the node to which the gate of the transistor M7 is connected is referred to as a node ND.
  • the transistor M4 conducts and the potential D1 of the wiring S1 is supplied to the node ND. Further, the transistor M5 and the transistor M6 are conducted, and the reset potential VRES is supplied to the other electrode of the capacitor C2.
  • the actual increase in the potential of the node ND is (C 2 / (C ND + C 2 )) ⁇ (VW-VRES) according to the capacity ratio of the capacity of the node ND and the capacitor C2.
  • C ND is the capacitance of the node ND
  • C 2 is the capacitance of the capacitor C 2
  • VRES 0
  • the increase in the potential of the node ND becomes VW. Therefore, the node ND is boosted from the potential D1 to the potential D1 + VW.
  • the potential of the node ND By boosting the potential of the node ND, a larger current can be passed through the light emitting device EL, and the light emitting brightness can be increased.
  • the dark part is reduced by increasing the emission brightness, so that more detailed image pickup data can be obtained.
  • a high-output source driver since a high-output source driver is not required, the manufacturing cost can be reduced.
  • FIG. 27D shows an example of the pixel circuit PIX3 applicable to the circuit 26.
  • the pixel circuit PIX3 includes a light receiving device PD, a transistor M9, a transistor M10, a transistor M11, a transistor M12, and a capacitor C4.
  • a photodiode is used as the light receiving device PD is shown.
  • the cathode is electrically connected to the wiring V1 and the anode is electrically connected to either the source or the drain of the transistor M9.
  • the gate is electrically connected to the wiring G4, and the other of the source or drain is electrically connected to one electrode of the capacitor C4, one of the source or drain of the transistor M10 and the gate of the transistor M11.
  • the gate is electrically connected to the wiring G5, and the other of the source or the drain is electrically connected to the wiring V4.
  • one of the source and the drain is electrically connected to the wiring V3, and the other of the source and the drain is electrically connected to one of the source and the drain of the transistor M12.
  • the gate is electrically connected to the wiring G6, and the other of the source or the drain is electrically connected to the wiring OUT.
  • a constant potential is supplied to the wiring V1, the wiring V3, and the wiring V4, respectively.
  • the transistor M10 is controlled by a signal supplied to the wiring G5, and has a function of resetting the potential of the node (charge reading unit) connected to the gate of the transistor M11 to the potential supplied to the wiring V4.
  • the transistor M9 is controlled by a signal supplied to the wiring G4, and has a function of controlling the timing at which the potential of the node changes according to the amount of electric charge stored in the light receiving device PD.
  • the transistor M11 functions as an amplification transistor that outputs according to the potential of the node.
  • the transistor M12 is controlled by a signal supplied to the wiring G6, and functions as a selection transistor for reading out an output corresponding to the potential of the node by an external circuit connected to the wiring OUT.
  • an OS transistor to the transistor included in the pixel circuits PIX1 to PIX3.
  • the OS transistor can realize a very small off-current.
  • the small off-current characteristic of the OS transistor makes it possible to retain the charge stored in the capacitor connected in series with the transistor for a long period of time.
  • an OS transistor in the circuit 26 it is possible to hold the charge for a long period of time, so we apply a global shutter method that simultaneously stores charges in all pixels without complicating the circuit configuration and operation method. be able to. Further, by using an OS transistor for other transistors as well, the manufacturing cost can be reduced.
  • a Si transistor can also be used as the transistor included in the pixel circuits PIX1 to PIX3.
  • silicon having high crystallinity such as single crystal silicon or polycrystalline silicon because high field effect mobility can be realized and higher speed operation becomes possible.
  • an OS transistor may be used for one or more, and a Si transistor may be used in addition to the OS transistor.
  • a back gate may be provided in each transistor as shown in FIG. 27E.
  • the on-current can be increased.
  • the threshold voltage of the transistor can be adjusted.
  • the configuration in which the back gate is provided in the transistor can also be applied to FIGS. 27A to 27D. It can also be applied to a semiconductor device that can use the OS transistor shown in the first embodiment.
  • FIGS. 27A to 27E show an example in which an n-channel type transistor is used, a p-channel type transistor can also be used.
  • the semiconductor devices 20a to 20d described in the first embodiment can be used for the circuit 40.
  • the semiconductor device 20b is used for the circuit 40.
  • FIG. 28 shows a form of connection between a part of the circuit 40 (one-stage flip-flop circuit 10 and output circuit 11 (switch circuit 12, circuit 13, circuit 14)) and the circuit 25 and the circuit 26 included in the pixel 24. It is a figure which shows.
  • the circuit 25 uses the pixel circuit PIX2 shown in FIG. 27B
  • the circuit 26 uses the pixel circuit PIX3 shown in FIG. 27C.
  • FIG. 28 illustrates a configuration in which one circuit 25 and one circuit 26 are provided on the pixel 24. If the display and imaging data conform to grayscale, this configuration can be used. In order to display colors, a circuit 25 that emits at least each of the three primary colors of light is required. Therefore, as shown in FIG. 29A, the pixel 24 is provided with a circuit 25 (R) that emits red light, a circuit 25 (G) that emits green light, and a circuit 25 (B) that emits blue light. Can be used.
  • the light emitting device EL included in the circuit 25 can be formed by using a light emitting device that emits red, green, or blue light.
  • a light emitting device that emits white light may be used for the light emitting device EL included in the circuit 25, and a color filter for red, green, or blue may be provided on the light emitting device.
  • the pixel 24 when acquiring color imaging data, as shown in FIG. 29B, the pixel 24 includes a circuit 26 (R) for capturing red light, a circuit 26 (G) for capturing green light, and a circuit 26 (G) for capturing blue light.
  • a configuration having the circuit 26 (B) can be used. These are formed by using a light emitting device having a photoelectric conversion layer that absorbs light of one color more strongly than light of another color among red, green, or blue light as the light receiving device PD included in the circuit 26. can do.
  • a light emitting device having a photoelectric conversion layer having absorption in the red, green, and blue wavelength bands may be used for the light receiving device PD included in the circuit 26, and a red, green, or blue color filter may be provided on the light receiving device. ..
  • the circuit 13 is electrically output with the wiring G1 and the wiring G2.
  • the signal potential GLA1 output by the circuit 13 can be supplied to the wiring G1.
  • the signal potential GLA2 output by the circuit 13 can be supplied to the wiring G2.
  • the circuit 14 is electrically output with the wiring G5 and the wiring G6.
  • the signal potential GLB1 output by the circuit 14 can be supplied to the wiring G5.
  • the signal potential GLB2 output by the circuit 14 can be supplied to the wiring G6.
  • the wiring G5 is electrically connected to the gate of the transistor M10 included in the circuit 26.
  • the transistor M10 is a transistor for a reset operation that resets the potential of the gate of the transistor M11 to the potential of the wiring V4.
  • the OS transistor for the transistor M9, the transistor M10, and the like it is possible to apply the global shutter method in which the charge storage operation is performed simultaneously in all the pixels.
  • the circuit 14 has the configuration shown in FIGS. 30A and 30B.
  • the selection circuit 50 is electrically connected to the wiring VRW.
  • the selection circuit 50 can supply either the reset potential VRES or the boost potential VW described above to the wiring VRW.
  • the operation of the circuit 40 and the pixel 24 shown in FIGS. 26 and 28 will be described with reference to the timing charts shown in FIGS. 31 to 34.
  • the operation is as follows: writing of image data to all circuits 25 (normal light emission, mode A), writing of boosted data to all circuits 25 (high brightness light emission, mode B), and reading of imaging data from all circuits 26. (Mode C) and reading of the imaging data from the specific circuit 26 (mode D) will be described separately.
  • the number of rows of the pixel 24 is 2340, and the circuit 40 can output the signal potential for driving the pixel 24 having the number of rows.
  • the input signals described in the timing chart are clock signals CLK1 to CLK4 input to the circuit 40, pulse width control signals PWCA1 to PWCA4, pulse width control signals PWCB1 to PWCB4, and a start pulse signal SP.
  • the reset power supply potential RSVSS is always set to a low potential.
  • the output signals described in the timing chart are the signal potentials GLA1 [1] to GLA1 [2340], the signal potentials GLA2 [1] to GLA2 [2340], and the signal potentials GLA1 [DUM] of the dummy stage output by the circuit 13 of the circuit 40. , The signal potential of the dummy stage GLA2 [DUM].
  • the signal potentials GLB1 [1] to GLB1 [2340], the signal potentials GLB2 [1] to GLB2 [2340], the signal potentials GLB1 [DUM] of the dummy stage, and the dummy output by the circuit 14 of the circuit 40 are shown.
  • the signal potential GLB2 [DUM] of the stage is described, the signal potential for conducting the transistor of the circuit 26 is not output from the circuit 14 at the operation timings of the mode A and the mode B.
  • the operation of the mode A utilizes the first mode, which is the operation of the semiconductor device 20 described with reference to FIG. First, a start pulse signal is input, and then clock signals CLK1 to CLK4 are sequentially input. Further, the pulse width control signals PWCA1 to PWCA4 and the pulse width control signals PWCB1 to PWCB4 are sequentially input in parallel with the clock signals CLK1 to CLK4.
  • the pulse of the signal potential GLA1 and the pulse of the signal potential GLA2 are sequentially output from the first stage to the dummy stage with the same pulse width and the same timing.
  • the signal potential GLA1 is supplied to the wiring G1 to conduct the transistor M4 and the transistor M6 of the circuit 25.
  • the signal potential GLA2 is supplied to the wiring G2 to conduct the transistor M5 of the circuit 25.
  • the selection circuit 50 supplies a reset potential VRES (for example, a low potential such as 0V) to the wiring VRW (see FIG. 28).
  • VRES reset potential
  • the reset potential VRES is supplied to the source of the transistor M7 of the circuit 25, and the gate (node ND) of the transistor M7 becomes the data potential supplied from the wiring S1. That is, the data potential can be written to the node ND in a state where the source potential of the transistor M7 is stable.
  • the light emitting device EL emits light according to the data potential.
  • the operation of the mode B utilizes the first mode, which is the operation of the semiconductor device 20 described with reference to FIG.
  • the start pulse signal is input, and then the clock signals CLK1 to CLK4 are sequentially input.
  • the pulse width control signals PWCA1 to PWCA4 and the pulse width control signals PWCB1 to PWCB4 are sequentially input in parallel with the clock signals CLK1 to CLK4.
  • the difference from writing image data (normal light emission) is that the pulse width of the pulse width control signal PWCA is smaller than the pulse width of the pulse width control signal PWCB.
  • the pulse of the signal potential GLA1 and the pulse of the signal potential GLA2 start to be output at the same timing, but the pulse of the signal potential GLA1 ends to be output first.
  • the boosting operation described with reference to FIG. 27C can be performed.
  • the selection circuit 50 performs an operation of switching the potential supplied to the wiring VRW from the reset potential VRES to the potential VW (see FIG. 28).
  • mode C reading (mode C) of the imaging data from all the circuits 26 will be described using the timing chart shown in FIG. 33.
  • mode C since the imaging data is read from the circuit 26 of the pixels 24 in all rows, high-resolution imaging data can be obtained.
  • the operation of the mode C utilizes the first mode, which is the operation of the semiconductor device 20 described with reference to FIG.
  • the image pickup operation is performed by utilizing the light emission in the operation of the mode A or the mode B. Therefore, it is performed following the operation of mode A or mode B.
  • mode C In the operation of mode C, first, the imaging operation by the circuit 26 is performed. In this operation, the power supply potential RSVSS for reset described with reference to FIG. 30 is inverted to a high potential, so that the circuit 14 outputs a high potential as the signal potential GLB1. By this operation, the charge reading unit can be reset at the same time for all the circuits 26. Subsequently, after the exposure period, the charge accumulated in the light receiving device is transferred to the charge readout unit to hold the potential of the charge readout unit. This is the imaging operation.
  • the start pulse signal is first input, and then the clock signals CLK1 to CLK4 are sequentially input. Further, the pulse width control signals PWCA1 to PWCA4 are sequentially input in parallel with the clock signals CLK1 to CLK4. Further, the pulse width control signals PWCB1 to PWCB4 having a pulse width waveform smaller than the pulse width control signal PWCA are input with a delay to the pulses of the pulse width control signals PWCA1 to PWCA4.
  • the pulse of the signal potential GLB2 is output first, the pulse of the signal potential GLB1 is output with a delay, and both are output at the same timing.
  • the difference can be read out by the CDS circuit included in the circuit 42 shown in FIG.
  • the difference is a potential obtained by subtracting the reset potential from the data potential (including the reset potential), and corresponds to the data from which the noise component is removed.
  • the reading (mode D) of the imaging data from the specific circuit 26 will be described using the timing chart shown in FIG. 34.
  • the imaging data is read from the circuit 26 in a specific row, so that the imaging data can be acquired at high speed.
  • the operation of the mode D utilizes the second mode, which is the operation of the semiconductor device 20 described with reference to FIG.
  • the image pickup operation by the circuit 26 is performed as in the mode C.
  • the input signal is the same as in mode C, and the signal potential GLB1 [1: 4] and the signal potential GLB2 [1: 4] are sequentially output, but the signal potential GLB1 [5:36] and the signal potential GLB2 [5:36]. ] Is not output. Further, the signal potential GLB1 [37:40] and the signal potential GLB2 [37:40] are sequentially output.
  • the circuit 26 in the first line (the circuit 26 in which the signal potential GLB1 [1] and the signal potential GLB2 [1] are input) is sequentially read from the circuit 26 in the fourth line, and the fifth to 36th lines are sequentially read out.
  • the circuit 26 of the above is not read, and the circuit 26 of the 37th line to the 40th line is read.
  • mode A, mode B, mode C, and mode D are sequentially switched without duplication. For example, it is possible to perform operations such as switching from mode A to mode B, mode A to mode D, mode B to mode C, and mode C to mode A.
  • the display operation in mode B involves a boosting operation, there are more operation steps than in mode A.
  • the mode C performs the reading operation from the pixels of all the rows, the number of operation steps is larger than the reading operation from the pixels of the specific row in the mode D.
  • the mode A, the mode B, the mode C, and the mode D may be operated at the frame frequencies suitable for each.
  • the mode A may be operated at 60 Hz, and the mode B may be operated by switching to 30 Hz.
  • the mode B may be operated at 30 Hz, and the mode C may be operated by switching to 10 Hz.
  • the mode A may be operated at 60 Hz, and the mode D may be operated without changing the frame frequency.
  • This embodiment can be carried out in combination with at least a part thereof as appropriate in combination with other embodiments described in the present specification.
  • FIG. 35 shows an example of a cross section of a region including a part of the circuit 40, a part of the circuit 25, and a part of the circuit 26 in the pixel 24 of the display device shown in FIG. 26.
  • the display device shown in FIG. 35 has a transistor 201, a transistor 205, a transistor 206, a light emitting device 190, a light receiving device 110, and the like between the substrate 151 and the substrate 152.
  • the substrate 152 and the insulating layer 214 are adhered to each other via the adhesive layer 142.
  • a solid sealing structure, a hollow sealing structure, or the like can be applied to the sealing of the light emitting device 190 and the light receiving device 110.
  • the space 143 surrounded by the substrate 152, the adhesive layer 142, and the insulating layer 214 is filled with an inert gas (nitrogen, argon, etc.), and a hollow sealing structure is applied.
  • the adhesive layer 142 may be provided so as to overlap with the light emitting device 190. Further, the region surrounded by the substrate 152, the adhesive layer 142 and the insulating layer 214 may be filled with a resin different from that of the adhesive layer 142.
  • the light emitting device 190 has a laminated structure in which the pixel electrode 191 and the common layer 112, the light emitting layer 193, the common layer 114, and the common electrode 115 are laminated in this order from the insulating layer 214 side.
  • the pixel electrode 191 is connected to the conductive layer 222b of the transistor 206 via an opening provided in the insulating layer 214.
  • the transistor 206 has a function of controlling the drive of the light emitting device 190.
  • the end of the pixel electrode 191 is covered with a partition wall 216.
  • the light receiving device 110 has a laminated structure in which the pixel electrode 111, the common layer 112, the photoelectric conversion layer 113, the common layer 114, and the common electrode 115 are laminated in this order from the insulating layer 214 side.
  • the pixel electrode 111 is electrically connected to the conductive layer 222b of the transistor 205 via an opening provided in the insulating layer 214.
  • the end portion of the pixel electrode 111 is covered with a partition wall 216.
  • the pixel electrode 111 and the pixel electrode 191 can be manufactured by the same material and the same process.
  • the common layer 112, the common layer 114, and the common electrode 115 are used for both the light receiving device 110 and the light emitting device 190.
  • the light receiving device 110 and the light emitting device 190 can all have the same configuration except that the configurations of the photoelectric conversion layer 113 and the light emitting layer 193 are different. As a result, the light receiving device 110 can be built in the display device without significantly increasing the manufacturing process.
  • a light-shielding layer 148 is provided on the surface of the substrate 152 on the substrate 151 side.
  • the light-shielding layer 148 has openings at positions overlapping with the light-receiving device 110 and at positions overlapping with the light-emitting device 190.
  • an optical filter 149 such as a color filter is provided at a position overlapping the light receiving device 110. It should be noted that the configuration may be such that the optical filter 149 is not provided.
  • An insulating layer 211, an insulating layer 213, an insulating layer 215, and an insulating layer 214 are provided on the substrate 151 in this order.
  • a part of the insulating layer 211 functions as a gate insulating layer of each transistor.
  • a part of the insulating layer 213 functions as a gate insulating layer of each transistor.
  • the insulating layer 215 is provided so as to cover the transistor.
  • the insulating layer 214 is provided so as to cover the transistor and has a function as a flattening layer.
  • the number of gate insulating layers and the number of insulating layers covering the transistors are not limited, and may be a single layer or two or more layers, respectively.
  • the insulating layer can function as a barrier layer.
  • hafnium oxide film, yttrium oxide film, zirconium oxide film, gallium oxide film, tantalum oxide film, magnesium oxide film, lanthanum oxide film, cerium oxide film or neodymium oxide film may be used.
  • two or more of the above-mentioned insulating films may be laminated and used.
  • the organic insulating film often has a lower barrier property against impurities than the inorganic insulating film. Therefore, the organic insulating film preferably has an opening near the end of the display device. This makes it possible to prevent impurities from diffusing from the end of the display device through the organic insulating film.
  • the organic insulating film may be formed so that the end portion of the organic insulating film is located inside the end portion of the display device so that the organic insulating film is not exposed at the end portion of the display device.
  • an opening is formed in the insulating layer 214.
  • the structure of the transistor included in the display device of this embodiment is not particularly limited.
  • a planar type transistor, a stagger type transistor, an inverted stagger type transistor and the like can be used.
  • a top gate type or a bottom gate type transistor structure may be used.
  • gates may be provided above and below the semiconductor layer on which the channel is formed.
  • the crystallinity of the semiconductor material used for the transistor is also not particularly limited, and a semiconductor having crystalline properties other than an amorphous semiconductor, a single crystal semiconductor, or a single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or a partially crystalline region) is provided. Any of the semiconductors) may be used. It is preferable to use a single crystal semiconductor or a semiconductor having crystallinity because deterioration of transistor characteristics can be suppressed.
  • optical members can be arranged on the outside of the substrate 152.
  • the optical member include a polarizing plate, a retardation plate, a light diffusing layer (diffusing film, etc.), an antireflection layer, a light collecting film, and the like.
  • an antistatic film for suppressing the adhesion of dust, a water-repellent film for preventing the adhesion of dirt, a hard coat film for suppressing the occurrence of scratches due to use, a shock absorbing layer, etc. are arranged on the outside of the substrate 152. You may.
  • FIGS. 37E and 37G are perspective views showing a foldable portable information terminal 9201. Further, FIG. 37E is a perspective view of a state in which the mobile information terminal 9201 is expanded, FIG. 37G is a folded state, and FIG. 37F is a perspective view of a state in which one of FIGS. 37E and 37G is in the process of changing to the other.
  • the mobile information terminal 9201 is excellent in portability in the folded state, and is excellent in the listability of the display due to the wide seamless display area in the unfolded state.
  • the display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a radius of curvature of 1 mm or more and 150 mm or less.
  • the operation of the television device 7100 shown in FIG. 38A can be performed by the operation switch provided in the housing 7101 or the remote control operation machine 7111 which is a separate body.
  • a touch panel may be applied to the display unit 7500, and the television device 7100 may be operated by touching the touch panel.
  • the remote controller 7111 may have a display unit in addition to the operation buttons.
  • the television device 7100 may have a receiver for television broadcasting or a communication device for network connection.
  • the digital signage 7300 or the digital signage 7400 can be linked with the information terminal 7311 such as a smartphone owned by the user by wireless communication.
  • the display of the display unit 7500 can be switched by displaying the information of the advertisement displayed on the display unit 7500 on the screen of the information terminal unit 7311 or by operating the information terminal unit 7311.
  • the digital signage 7300 or the digital signage 7400 can be made to execute a game using the information terminal 7311 as an operating means (controller). As a result, an unspecified number of users can participate in and enjoy the game at the same time.
  • a display device can be applied to the display unit 7500 in FIGS. 38A to 38D.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
PCT/IB2021/059548 2020-10-30 2021-10-18 半導体装置、表示装置、および電子機器 Ceased WO2022090858A1 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
KR1020237013828A KR20230092925A (ko) 2020-10-30 2021-10-18 반도체 장치, 표시 장치, 및 전자 기기
JP2022558371A JP7660134B2 (ja) 2020-10-30 2021-10-18 半導体装置、表示装置、および電子機器
CN202180071692.7A CN116490914A (zh) 2020-10-30 2021-10-18 半导体装置、显示装置以及电子设备
US18/033,710 US20230395022A1 (en) 2020-10-30 2021-10-18 Semiconductor apparatus, display device, and electronic device
JP2025058311A JP7837450B2 (ja) 2020-10-30 2025-03-31 半導体装置および表示装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-182536 2020-10-30
JP2020182536 2020-10-30

Publications (1)

Publication Number Publication Date
WO2022090858A1 true WO2022090858A1 (ja) 2022-05-05

Family

ID=81383658

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2021/059548 Ceased WO2022090858A1 (ja) 2020-10-30 2021-10-18 半導体装置、表示装置、および電子機器

Country Status (5)

Country Link
US (1) US20230395022A1 (https=)
JP (2) JP7660134B2 (https=)
KR (1) KR20230092925A (https=)
CN (1) CN116490914A (https=)
WO (1) WO2022090858A1 (https=)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009128776A (ja) * 2007-11-27 2009-06-11 Nec Electronics Corp ドライバ及び表示装置
JP2015232602A (ja) * 2014-06-09 2015-12-24 株式会社ジャパンディスプレイ 表示装置
JP2016142880A (ja) * 2015-01-30 2016-08-08 株式会社ジャパンディスプレイ 表示装置
WO2018197985A1 (ja) * 2017-04-27 2018-11-01 株式会社半導体エネルギー研究所 表示ユニット、表示装置、および電子機器
WO2020136495A1 (ja) * 2018-12-28 2020-07-02 株式会社半導体エネルギー研究所 表示装置

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0736406A (ja) * 1993-07-23 1995-02-07 Seiko Epson Corp ドットマトリクス型表示装置及びその駆動方法
JP3342995B2 (ja) * 1995-08-17 2002-11-11 シャープ株式会社 画像表示装置およびそれを用いたプロジェクタ
US6724012B2 (en) * 2000-12-14 2004-04-20 Semiconductor Energy Laboratory Co., Ltd. Display matrix with pixels having sensor and light emitting portions
JP5558446B2 (ja) * 2011-09-26 2014-07-23 株式会社東芝 光電変換装置及びその製造方法
US9041453B2 (en) 2013-04-04 2015-05-26 Semiconductor Energy Laboratory Co., Ltd. Pulse generation circuit and semiconductor device
US9261991B2 (en) 2013-05-28 2016-02-16 Google Technology Holdings LLC Multi-layered sensing with multiple resolutions
TWI679624B (zh) * 2014-05-02 2019-12-11 日商半導體能源研究所股份有限公司 半導體裝置
US10394368B2 (en) 2016-05-31 2019-08-27 Microsoft Technology Licensing, Llc Touch-sensitive display device
KR102264130B1 (ko) 2016-09-09 2021-06-11 센셀, 인크. 터치 센서 상의 입력을 검출하고 특징화하기 위한 시스템
CN108109592B (zh) * 2016-11-25 2022-01-25 株式会社半导体能源研究所 显示装置及其工作方法
KR102924769B1 (ko) * 2016-12-29 2026-02-06 엘지디스플레이 주식회사 게이트 구동회로를 포함하는 표시패널
CN110178174B (zh) * 2018-09-28 2020-05-08 华为技术有限公司 一种栅极驱动电路及其控制方法、移动终端
US11475827B2 (en) * 2020-01-22 2022-10-18 Innolux Corporation Electronic device for reducing power consumption

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009128776A (ja) * 2007-11-27 2009-06-11 Nec Electronics Corp ドライバ及び表示装置
JP2015232602A (ja) * 2014-06-09 2015-12-24 株式会社ジャパンディスプレイ 表示装置
JP2016142880A (ja) * 2015-01-30 2016-08-08 株式会社ジャパンディスプレイ 表示装置
WO2018197985A1 (ja) * 2017-04-27 2018-11-01 株式会社半導体エネルギー研究所 表示ユニット、表示装置、および電子機器
WO2020136495A1 (ja) * 2018-12-28 2020-07-02 株式会社半導体エネルギー研究所 表示装置

Also Published As

Publication number Publication date
CN116490914A (zh) 2023-07-25
JP7660134B2 (ja) 2025-04-10
JP2025092672A (ja) 2025-06-19
JPWO2022090858A1 (https=) 2022-05-05
KR20230092925A (ko) 2023-06-26
JP7837450B2 (ja) 2026-03-30
US20230395022A1 (en) 2023-12-07

Similar Documents

Publication Publication Date Title
JP7566117B2 (ja) 表示装置及び電子機器
JP7650822B2 (ja) 表示装置、表示モジュール及び電子機器
US20250057004A1 (en) Display module and electronic device
JP7689525B2 (ja) 表示装置
TWI901688B (zh) 顯示裝置的驅動方法
WO2021064509A1 (ja) 表示装置
US12349576B2 (en) Display apparatus, display module, and electronic device
JP7658951B2 (ja) 表示装置
US20260075330A1 (en) Semiconductor device, method for driving semiconductor device, and electronic device
JP2025164772A (ja) 表示装置
WO2021165788A1 (ja) 半導体装置
WO2021220141A1 (ja) 表示装置、表示モジュール、及び電子機器
JP7660134B2 (ja) 半導体装置、表示装置、および電子機器
US12142215B2 (en) Semiconductor device, display apparatus, and electronic device
JP2026074116A (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21885453

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2022558371

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 202180071692.7

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21885453

Country of ref document: EP

Kind code of ref document: A1