WO2022088372A1 - 一种微纳米结构定点缺陷掺杂的方法及nv色心传感器 - Google Patents

一种微纳米结构定点缺陷掺杂的方法及nv色心传感器 Download PDF

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WO2022088372A1
WO2022088372A1 PCT/CN2020/132797 CN2020132797W WO2022088372A1 WO 2022088372 A1 WO2022088372 A1 WO 2022088372A1 CN 2020132797 W CN2020132797 W CN 2020132797W WO 2022088372 A1 WO2022088372 A1 WO 2022088372A1
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micro
nano
doping
sacrificial layer
self
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French (fr)
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王孟祺
王亚
孙浩宇
叶翔宇
余佩
刘航宇
王鹏飞
石发展
杜江峰
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中国科学技术大学
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0405—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising semiconducting carbon, e.g. diamond, diamond-like carbon
    • H01L21/041—Making n- or p-doped regions
    • H01L21/0415—Making n- or p-doped regions using ion implantation
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/005—Bulk micromachining
    • B81C1/00507—Formation of buried layers by techniques other than deposition, e.g. by deep implantation of elements
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388—Etch mask forming
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388—Etch mask forming
    • B81C1/00404—Mask characterised by its size, orientation or shape
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436—Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/00523—Etching material
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
    • C23C14/48—Ion implantation
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01D—MEASURING NOT SPECIALLY ADAPTED FOR A SPECIFIC VARIABLE; ARRANGEMENTS FOR MEASURING TWO OR MORE VARIABLES NOT COVERED IN A SINGLE OTHER SUBCLASS; TARIFF METERING APPARATUS; MEASURING OR TESTING NOT OTHERWISE PROVIDED FOR
    • G01D5/00—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable
    • G01D5/26—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light
    • G01D5/268—Mechanical means for transferring the output of a sensing member; Means for converting the output of a sensing member to another variable where the form or nature of the sensing member does not constrain the means for converting; Transducers not specially adapted for a specific variable characterised by optical transfer means, i.e. using infrared, visible, or ultraviolet light using optical fibres
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/20—Arrangements or instruments for measuring magnetic variables involving magnetic resonance
    • G01R33/24—Arrangements or instruments for measuring magnetic variables involving magnetic resonance for measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/26—Arrangements or instruments for measuring magnetic variables involving magnetic resonance for measuring direction or magnitude of magnetic fields or magnetic flux using optical pumping

Definitions

  • the invention relates to the fields of micro-nano processing technology and quantum information technology, in particular to a method and application for doping fixed-point defects of micro-nano structures based on a self-alignment process.
  • Solid-state quantum systems are widely used and studied in the field of quantum information because they can be integrated and deviceized.
  • point defects in solids are protected by solid materials and usually have good spin properties and optical properties, so they have become a hot spot in the research and application of solid-state quantum computing, quantum precision measurement, etc., such as nitrogen-vacancy color in diamond center (NV), silicon-vacancy color center (SiV), nickel-nitrogen color center (NE8), point defects in silicon carbide, etc.
  • NV color center in diamond has become one of the main solid-state systems in the field of quantum information due to its superior spin coherence time at room temperature, optical initialization readout methods, and mature microwave control methods.
  • NV color centers as single-spin quantum sensors exhibit outstanding advantages such as nano-spatial resolution, single-spin detection sensitivity, relaxed working conditions, non-destructiveness and no need for magnetic shielding.
  • the fluorescence emitted by point defects is mostly in The total reflection effect occurs at the interface, which requires the preparation of micro-nano structures to improve the optical fluorescence collection efficiency.
  • optical fluorescence collection efficiency is closely related to the spatial position of defects in the micro-nano optical structure.
  • the spatial positioning accuracy of defects in the center of the structure is required to reach 50 nm to have a strong effect.
  • Traditional methods of doping through maskless ion implantation are difficult to control the spatial location of defects in the structure, and usually less than 10% of the optical structure achieves the desired enhancement effect.
  • the spatial position uncertainty caused by process defects is the key to restrict the effect of optical structure and yield.
  • it is necessary to align the micro-nano structure with the defect doping, so as to realize the fixed-point defect doping of the micro-nano structure.
  • Electron beam lithography overlay using electron beam imaging to achieve alignment [Nano Lett.2010, 10, 3168-3172]
  • AFM tip is used to prepare pinhole mask combination, and AFM imaging is used to achieve alignment [Applied Physics A, 2008, 91(4): 567-571, Patent: US7126139B2].
  • the present invention provides a method and application for doping micro-nano structure fixed-point defects based on a self-alignment process, which is used to at least partially solve the problem that the traditional mask-free defect doping process is difficult to control defects in the micro-nano structure.
  • technical issues such as spatial location.
  • One aspect of the present invention provides a method for doping micro-nano structure fixed-point defects based on a self-alignment process, comprising: S1, sequentially forming a sacrificial layer and a photoresist layer on the surface of a crystal substrate; S2, according to the micro-nano pattern The photoresist layer lithography the mask hole; S3, isotropically etch the sacrificial layer through the mask hole, and enlarge the micro-nano pattern to the sacrificial layer; S4, perform ion implantation on the exposed crystal surface under the mask hole.
  • Impurity remove the photoresist layer, deposit mask material
  • S6 remove the sacrificial layer, transfer the micro-nano enlarged pattern in the sacrificial layer to the pattern of the mask material
  • S7 etch the exposed crystal surface, remove the surface mask material and annealed to form specific defects.
  • the sacrificial layer and the photoresist layer in S1 form a double-layer thin film structure, and the formation methods include coating and vapor deposition.
  • the materials of the sacrificial layer in S1 include PMGI (polydimethylglutarimide), SiO 2 , and SiN.
  • the mask hole in S2 is a micro-nano pattern proportionally reduced pattern, and the mask hole is located just above the center of the underlying structure pattern.
  • the ion species implanted in S4 is related to the doping defect species, and the ion penetration depth cannot exceed the thickness of the photoresist layer.
  • the deposition of the mask material in S5 adopts a coating process, including evaporation coating and sputtering coating.
  • the sacrificial layer is removed by stripping.
  • a dry etching process is used for etching the exposed crystal surface, including plasma etching, reactive ion etching, and inductively coupled plasma etching.
  • Another aspect of the present invention provides an NV color center sensor, wherein the NV color center in the NV color center sensor is prepared by the aforementioned method.
  • the embodiments of the present invention provide a method and application for doping micro-nano structure fixed-point defects based on a self-alignment process, which realizes the fixed-point doping in the micro-nano structure and effectively improves the accuracy of the position of defects in the micro-nano structure. ; remove the influence of spatial position uncertainty on the optical structure effect and yield; and obtain a high-quality NV color center sensor prepared by this method.
  • FIG. 1 schematically shows a flow chart of a method for doping micro-nano structure fixed-point defects based on a self-alignment process according to an embodiment of the present invention
  • FIG. 2 schematically shows a schematic diagram of the doping of fixed-point defects in micro-nano structures based on a self-alignment process according to an embodiment of the present invention
  • the first embodiment of the present invention provides a method for doping micro-nano structure fixed-point defects based on a self-alignment process, please refer to FIG. 1, including: S1, forming a sacrificial layer and a photoresist layer on the surface of the crystal substrate in sequence; S2, photolithography mask holes in the photoresist layer according to the micro-nano patterns; S3, isotropically etch the sacrificial layer through the mask holes to enlarge the micro-nano patterns to the sacrificial layer; S4, expose the bottom of the mask holes S5, remove the photoresist layer and deposit the mask material; S6, remove the sacrificial layer, transfer the micro-nano enlarged pattern in the sacrificial layer to the pattern of the mask material; S7, engrave the exposed crystal surface etch, remove surface mask material and anneal to form specific defects.
  • the lower layer structure is a sacrificial layer that can be isotropically etched
  • the top layer structure is a photoresist
  • a mask is prepared on the top layer resin structure according to the shape of the micro-nano structure by a photolithography process. Holes; the underlying structure is isotropically etched by using the etching solution to pass through the mask holes.
  • the pattern of the mask hole is enlarged to the underlying structure to realize the patterning of the underlying structure; the top structure is used as a mask, and the exposed crystal surface under the mask hole is doped by ion implantation; the top photoresist is removed and deposited by a coating process Mask material; remove the underlying structure material by stripping, and realize the transfer of the underlying structure pattern to the mask material pattern; use the mask material pattern as an anti-etching mask, and use the dry etching process to perform a dry etching process on the exposed crystal surface. Etching forms micro-nano structures. The remaining mask material on the surface is then removed and annealed to form specific defects.
  • the sacrificial layer and the photoresist layer in S1 form a double-layer thin film structure, and the formation methods include coating and vapor deposition.
  • the photoresist layer is used to prepare mask holes for ion implantation by S2 photolithography, and the sacrificial layer is used for S3 isotropic etching to form patterns, and is coated by S5 and removed by S6 to form an etching mask.
  • the coating process forms a film structure by spin coating or spraying, and is often used for materials such as photoresist, PMGI, and spin-coated SiO 2 layers; vapor deposition forms a film structure by physical vapor deposition or chemical vapor deposition, often used for SiO 2 , SiN Material.
  • the photoresist material includes ultraviolet photoresist and electronic photoresist.
  • the materials of the sacrificial layer in S1 include PMGI, SiO 2 , and SiN.
  • the sacrificial layer is preferably PMGI, which is characterized in that the S3 process can be isotropically etched by tetramethylammonium hydroxide (TMAH) solution, and the process has little effect on the upper photoresist structure. And when acetone is used to remove the photoresist layer in the S5 process, it will not dissolve in acetone. In the process of S6, the mask material pattern is obtained by removing using the reagent N-methylpyrrolidone (NMP).
  • NMP N-methylpyrrolidone
  • the sacrificial layer can also be selected from SiO 2 and SiN sacrificial layers.
  • Their characteristic is that the S3 process can be etched isotropically by BOE (buffered oxide etching solution) or hydrofluoric acid solution, and the process has a greater impact on the upper photoresist structure. Small. And when acetone is used to remove the photoresist layer in the S5 process, it will not dissolve in acetone.
  • the mask material pattern is obtained by using the reagent BOE (buffered oxide etching solution) or hydrofluoric acid solution.
  • the mask hole in S2 is a micro-nano pattern proportionally reduced pattern, and the mask hole is located just above the center of the lower structure pattern.
  • the mask hole is not only used as an isotropic etching mask for the sacrificial layer in the S3 process, but also as a mask hole for ion implantation in the S4 process.
  • a mask hole is prepared on the top layer glue structure according to the shape of the micro-nano structure by a photolithography process, and the photolithography process may be an electron beam photolithography process or an ultraviolet photolithography process.
  • the ion species implanted in S4 is related to the doping defect species, and the ion penetration depth cannot exceed the thickness of the photoresist layer.
  • the types of implanted ions are different, for example, doped NV color center implants nitrogen-containing ions; doped SiV color centers implants silicon-containing ions.
  • the ion penetration depth cannot exceed the thickness of the photoresist layer because after the thickness of the photoresist layer is exceeded, photolithography will not be able to block the ion implantation into the crystal, so the implanted ion position cannot be controlled.
  • the deposition of the mask material in S5 adopts a coating process, including evaporation coating and sputtering coating.
  • the mask material can be metal, metal oxide, non-metal and non-metal oxide.
  • the evaporation coating process includes thermal evaporation coating and electron beam evaporation coating, which has the advantages of low energy and good mask edge after stripping; sputtering coating process has The film layer has the advantages of high density and small particle size.
  • the sacrificial layer is removed in S6 by means of stripping.
  • the selection of reagents in the process of dissolution and stripping is determined according to the type of the underlying structure material.
  • the reagent N-methylpyrrolidone (NMP) is used for the dissolution and stripping of the underlying structure PMGI
  • the reagent containing hydrofluoric acid is used for the dissolution and stripping of the underlying structure SiO 2 and SiN.
  • a dry etching process is used for etching the exposed crystal surface, including plasma etching, reactive ion etching, and inductively coupled plasma etching.
  • Dry etching process including ion beam etching, reactive plasma etching, inductively coupled plasma etching, etc., and by adjusting etching power, gas ratio, etching gas pressure, etching temperature, etching time and other conditions, Realize the control of the etching depth and the inclination angle of the etching sidewall to form a specific micro-nano structure.
  • the removal of the surface mask material in S7 adopts a dry etching or wet etching process.
  • the removal of the mask material can be done by dry etching or wet etching.
  • the dry etching process requires the use of plasma etching equipment, which has the advantages of simple operation, stable process and high precision.
  • the wet etching process has the advantages of low cost and low cost. advantage.
  • the second embodiment of the present invention provides an NV color center sensor, wherein the NV color center in the NV color center sensor is prepared by the aforementioned method.
  • the present invention provides a method for implementing fixed-point doping in micro-nano structures, and the method can be used for point-defect fixed-point doping in diamond, silicon carbide, and h-BN micro-nano structures.
  • the following takes the fixed-point doping of the nitrogen vacancy color center in the positive center of the diamond nanocolumn waveguide end face as an example, and gives a specific implementation:
  • a double-layer thin film structure is formed on the surface of the diamond substrate 3, and a PMGI sacrificial layer 2 and an electron beam photoresist PMMA photoresist layer 1 are formed by a spin coating process, namely S1;
  • Electron beam lithography is carried out to electron beam photoresist PMMA to prepare mask hole, mask hole is circular shape, and diameter is smaller than nano-column waveguide diameter, i.e. S2;
  • TMAH tetramethylammonium hydroxide
  • the in-plane position of the doped defect is controlled by the ion implantation direction.
  • the ion implantation direction is perpendicular to the substrate surface, and the position of the lattice defect 4 will be located in the center of the underlying pattern;
  • the ion implantation ion species is nitrogen-containing group ions, i.e. S4;
  • the mask material 5 uses metal Ti, preferably an evaporation coating process, namely S5;
  • NMP N-methylpyrrolidone
  • a diamond nanocolumn waveguide structure with high fluorescence collection efficiency is formed; Ti metal 5 is removed by wet etching with BOE solution; NV color centers 6 are formed by annealing in a vacuum environment at 600-1200 °C The center of the end face of the column waveguide is S7.
  • an NV color center sensor can be obtained through the embodiment, which is characterized in that the NV color centers are all located in the center of the end face of the diamond nano-column waveguide structure, which can achieve the expected optimal fluorescence collection efficiency and have a high yield.
  • the working principle of the NV color center sensor is to convert the external magnetic, electrical, temperature and other information into the information of the fluorescence intensity of the NV color center for readout.
  • the NV color center sensor obtained in this example has higher fluorescence signal collection efficiency and therefore better detection sensitivity.
  • the senor obtained in this patent can be combined with scanning microscopy imaging technology to form a scanning test NV color center sensor.
  • it can replace the nano-column waveguide structure manufacturing method in the patent CN202010100070.X to improve the yield of the sensor.

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Abstract

一种基于自对准工艺的微纳米结构定点缺陷掺杂的方法，包括：S1，在晶体衬底表面依次形成牺牲层、光刻胶层；S2，根据微纳米图形在光刻胶层光刻出掩模孔；S3，通过掩模孔对牺牲层各向同性刻蚀，将掩模孔图形放大至牺牲层；S4，对掩模孔下方裸露的晶体表面进行离子注入掺杂；S5，去除光刻胶层，沉积掩模材料；S6，去除牺牲层，牺牲层中微纳米放大图形转移为掩模材料图形；S7，对裸露晶体表面进行刻蚀，去除表面掩模材料并退火形成特定缺陷。本方法基于自对准工艺，不需要对准的操作，精度高过程简单，不存在对准的误差。

Description

一种微纳米结构定点缺陷掺杂的方法及NV色心传感器 技术领域
本发明涉及微纳加工技术与量子信息技术领域，具体涉及一种基于自对准工艺的微纳米结构定点缺陷掺杂的方法及应用。
背景技术
固态量子系统因其可集成化、器件化，在量子信息领域被广泛的应用和研究。其中固体中的点缺陷因受到固体材料的保护，通常拥有良好的自旋性质和光学性质，因此成为目前固态量子计算、量子精密测量等方向研究和应用的热点，例如金刚石中的氮-空位色心(NV)、硅-空位色心(SiV)、镍-氮色心(NE8)、碳化硅中的点缺陷等。其中金刚石中的NV色心凭借室温下优越的自旋相干时间、光学初始化读出手段、成熟微波控制方法，成为量子信息领域主要研究的固态体系之一。尤其是在微观磁测量领域，NV色心作为单自旋量子传感器展示出了纳米空间分辨率、单自旋探测灵敏度、宽松工作条件、无破坏性和无需磁屏蔽等突出优势
以NV色心为代表的光学缺陷通常发光较弱，受晶体材料本身高折射率的限制(比如金刚石(n＝2.4)、碳化硅(n＝2.6)等)点缺陷发出的荧光绝大部分在界面发生全反射效应，需要制备微纳米结构来提高光学荧光收集效率。例如制备固体浸没透镜[Applied Physics Letters，2010，97(24)：241901、Journal of Applied Physics，2015，118(14)：144501]、纳米柱波导[Nano letters，2015，15(1)：165-169]、超薄金刚石“牛眼”[Nano letters，2015，15(3)：1493-1497]以及抛物面[Nano letters，2018，18(5)：2787-2793]等微纳米光学结构。
而光学荧光收集效率的提升效果与微纳米光学结构中缺陷的空间位置密切相关，通常要求缺陷在结构中心空间定位精度达到50nm才会有较强的效果。传统方法通过无掩膜离子注入进行掺杂，难以控制缺陷 在结构中的空间位置，通常只有不到10％的光学结构达到预期增强效果。
由工艺缺陷引起的空间位置不确定性是制约光学结构效果以及成品率的关键。为提升微纳光学结构的良率，需要将微纳结构和缺陷掺杂对准，实现微纳结构定点缺陷掺杂。
目前已有的技术方案主要有：
1.电子束光刻套刻，利用电子束成像实现对准[Nano Lett.2010，10，3168-3172]
2.AFM针尖制备小孔掩模结合，利用AFM成像实现对准[Applied Physics A，2008，91(4)：567-571、专利：US7126139B2]。
3.聚焦离子束注入，利用离子束成像实现对准[Nature communications，2017，8(1)：1-7、physica status solidi(a)，2013，210(10)：2055-2059]
这些方法，均存在复杂的对准过程，且对准过程会有对准误差的存在，设备工艺要求较高且成本昂贵。
发明内容
(一)要解决的技术问题
针对上述问题，本发明提供了一种基于自对准工艺的微纳米结构定点缺陷掺杂的方法及应用，用于至少部分解决传统无掩膜缺陷掺杂工艺难以控制缺陷在微纳米结构中的空间位置的等技术问题。
(二)技术方案
本发明一方面提供了一种基于自对准工艺的微纳米结构定点缺陷掺杂的方法，包括：S1，在晶体衬底表面依次形成牺牲层、光刻胶层；S2，根据微纳米图形在光刻胶层光刻出掩模孔；S3，通过掩模孔对牺牲层各向同性刻蚀，将微纳米图形放大至牺牲层；S4，对掩模孔下方裸露的晶体表面进行离子注入掺杂；S5，去除光刻胶层，沉积掩模材料；S6，去除牺牲层，牺牲层中微纳米放大图形转移为掩模材料图形；S7，对裸露晶体表面进行刻蚀，去除表面掩模材料并退火形成特定缺陷。
进一步地，S1中牺牲层、光刻胶层形成双层薄膜结构，形成方式包括涂覆和气相沉积。
进一步地，S1中牺牲层材料包括PMGI(聚二甲基戊二酰亚胺)、SiO 2、SiN。
进一步地，S2中掩模孔为微纳米图形等比例缩小的图形，掩模孔位于下层结构图形中心正上方位置。
进一步地，S4中离子注入的离子种类与掺杂缺陷种类相关，离子穿透深度不能超过光刻胶层的厚度。
进一步地，S5中沉积掩模材料采用镀膜工艺，包括蒸发镀膜、溅射镀膜。
进一步地，S6中去除牺牲层采用溶脱剥离的方式。
进一步地，S7中对裸露晶体表面刻蚀采用干法刻蚀工艺，包括等离子体刻蚀、反应离子刻蚀、感应耦合等离子体刻蚀。
进一步地，S7中去除表面掩模材料采用干法刻蚀或湿法刻蚀工艺。
本发明另一方面提供了一种NV色心传感器，NV色心传感器中的NV色心通过如前述的方法制备。
(三)有益效果
本发明实施例提供的一种基于自对准工艺的微纳米结构定点缺陷掺杂的方法及应用，实现了微纳米结构中的定点掺杂，有效的提升缺陷在微纳结构中位置的精确性；去除空间位置不确定性对光学结构效果以及成品率的影响；并可获得利用该方法所制备的高品质NV色心传感器。
附图说明
图1示意性示出了根据本发明实施例基于自对准工艺的微纳米结构定点缺陷掺杂的方法的流程图；
图2示意性示出了根据本发明实施例基于自对准工艺的微纳米结构定点缺陷掺杂示意图；
附图标记
1-PMMA；
2-PMGI；
3-金刚石样品；
4-晶格缺陷；
5-金属掩模；
6-NV色心。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚明白，以下结合具体实施例，并参照附图，对本发明进一步详细说明。
本发明的第一实施例提供一种基于自对准工艺的微纳米结构定点缺陷掺杂的方法，请参见图1，包括：S1，在晶体衬底表面依次形成牺牲层、光刻胶层；S2，根据微纳米图形在光刻胶层光刻出掩模孔；S3，通过掩模孔对牺牲层各向同性刻蚀，将微纳米图形放大至牺牲层；S4，对掩模孔下方裸露的晶体表面进行离子注入掺杂；S5，去除光刻胶层，沉积掩模材料；S6，去除牺牲层，牺牲层中微纳米放大图形转移为掩模材料图形；S7，对裸露晶体表面进行刻蚀，去除表面掩模材料并退火形成特定缺陷。
提供晶体衬底，在表面形成双层薄膜结构，下层结构为牺牲层能够被各向同性腐蚀，顶层结构为光刻胶；通过光刻工艺根据微纳米结构形状在顶层胶结构上制备出掩模孔；利用刻蚀液通过掩模孔，对下层结构进行各向同性刻蚀。将掩模孔图形放大至下层结构，实现下层结构的图形化；将顶层结构作为掩模，通过离子注入对掩模孔下方裸露的晶体表面进行掺杂；去除顶层光刻胶，利用镀膜工艺沉积掩模材料；通过溶脱剥离的方式去除下层结构材料，实现下层结构的图形转移为掩模材料图形；将掩模材料图形作为抗刻蚀的掩模，利用干法刻蚀工艺对裸露晶体表面进行刻蚀形成微纳米结构。后去除表面剩余掩模材料并退火形成特定缺陷。
在上述实施例的基础上，S1中牺牲层、光刻胶层形成双层薄膜结构，形成方式包括涂覆和气相沉积。
光刻胶层用于通过S2光刻制备掩模孔用于离子注入，牺牲层用于S3各向同性刻蚀形成图形，并通过S5镀膜和S6去除以形成刻蚀掩模。
涂覆工艺通过旋涂或喷涂形成膜层结构，常用于光刻胶、PMGI、旋涂SiO 2层等材料；气相沉积通过物理气相沉积或化学气相沉积形成膜层结构，常用于SiO 2、SiN材料。光刻胶材料包括紫外光刻胶、电子光刻胶。
在上述实施例的基础上，S1中牺牲层材料包括PMGI、SiO 2、SiN。
牺牲层优选PMGI，其特点在于S3过程可以通过四甲基氢氧化铵(TMAH)溶液进行各向同性刻蚀，过程对上层光刻胶结构影响较小。并且在S5过程去除光刻胶层使用丙酮时，不会溶解于丙酮。S6过程中用使用试剂N-甲基吡咯烷酮(NMP)进行去除得到掩模材料图形。
牺牲层还可以选SiO 2、SiN牺牲层，他们的特点在于S3过程可以通过BOE(缓冲氧化物刻蚀液)或氢氟酸溶液进行各向同性刻蚀，过程对上层光刻胶结构影响较小。并且在S5过程去除光刻胶层使用丙酮时，不会溶解于丙酮。S6过程中用使用试剂BOE(缓冲氧化物刻蚀液)或氢氟酸溶液得到掩模材料图形。
在上述实施例的基础上，S2中掩模孔为微纳米图形等比例缩小的图形，掩模孔位于下层结构图形中心正上方位置。
掩模孔不仅作为S3过程牺牲层各项同性刻蚀掩模，还作为S4过程离子注入的掩模孔。通过光刻工艺根据微纳米结构形状在顶层胶结构上制备出掩模孔，光刻工艺可以是电子束光刻工艺、紫外光刻工艺。
在上述实施例的基础上，S4中离子注入的离子种类与掺杂缺陷种类相关，离子穿透深度不能超过光刻胶层的厚度。
根据掺杂缺陷种类的不同，注入的离子种类不同，例如掺杂NV色心注入含氮离子；掺杂SiV色心注入含硅离子。
离子穿透深度不能超过光刻胶层的厚度是因为超过光刻胶层厚度过后，光刻将无法阻挡离子注入晶体，因此无法控制注入离子位置。
在上述实施例的基础上，S5中沉积掩模材料采用镀膜工艺，包括蒸发镀膜、溅射镀膜。
掩模材料可以是金属、金属氧化物、非金属、非金属氧化物，蒸发镀膜工艺包括热蒸发镀膜和电子束蒸发镀膜，其具有能量低剥离后掩模边缘良好的优点；溅射镀膜工艺具有膜层致密度高粒径小的优点。
在上述实施例的基础上，S6中去除牺牲层采用溶脱剥离的方式。
溶脱剥离过程选用试剂根据下层结构材料种类决定，例如使用试剂N-甲基吡咯烷酮(NMP)进行下层结构PMGI的溶脱剥离、使用含有氢氟酸试剂进行下层结构SiO 2、SiN的溶脱剥离。
在上述实施例的基础上，S7中对裸露晶体表面刻蚀采用干法刻蚀工艺，包括等离子体刻蚀、反应离子刻蚀、感应耦合等离子体刻蚀。
干法刻蚀工艺，包括离子束刻蚀、反应等离子体刻蚀、感应耦合等离子体刻蚀等，并且通过调节刻蚀功率、气体比例、刻蚀气压、刻蚀温度、刻蚀时间等条件，实现刻蚀深度，刻蚀侧壁倾斜角度的控制，形成特定的微纳米结构。
在上述实施例的基础上，S7中去除表面掩模材料采用干法刻蚀或湿法刻蚀工艺。
去除掩模材料采用干法刻蚀或湿法刻蚀工艺均可，干法刻蚀工艺需要使用等离子体刻蚀设备，具有操作简单工艺稳定精度高的优点，湿法刻蚀工艺具有低成本的优点。
本发明的第二实施例提供一种NV色心传感器，NV色心传感器中的NV色心通过前述的方法制备。
请参见图2，本发明提供一种实现微纳米结构中定点掺杂的方法，方法可以用于金刚石、碳化硅、h-BN微纳米结构中的点缺陷定点掺杂。以下以金刚石纳米柱波导端面正中心氮空位色心的定点掺杂为实施例，给出具体的实施方案：
在金刚石衬底3表面形成双层薄膜结构，使用旋涂工艺形成PMGI牺牲层2、电子束光刻胶PMMA光刻胶层1，即S1；
对电子束光刻胶PMMA进行电子束光刻制备出掩模孔，掩模孔为 圆形状，直径小于纳米柱波导直径，即S2；
刻蚀液不能损坏双层薄膜结构顶层，本步骤使用四甲基氢氧化铵(TMAH)溶液进行各向同性刻蚀；实现下层结构的图形化为最终微纳米结构的形状，衬底平面内掩模孔位于下层结构图形中心正上方位置，本实施例中下层结构图形为圆形，掩模孔在正中心位置，即S3；
掺杂的缺陷平面内位置由离子注入方向进行控制，本实施例中，离子注入方向垂直衬底表面，晶格缺陷4位置将位于下层图形正中心；离子注入离子种类为含氮基团离子，即S4；
使用丙酮对顶层光刻胶PMMA进行溶解，同时不会破坏下层结构PMGI牺牲层2；掩模材料5使用金属Ti，优选蒸发镀膜工艺，即S5；
使用试剂N-甲基吡咯烷酮(NMP)进行下层结构PMGI牺牲层2的溶脱剥离，即S6；
通过感应耦合等离子体刻蚀，形成高荧光收集效率的金刚石纳米柱波导结构；使用BOE溶液湿法刻蚀去除Ti金属5；使用600-1200℃真空环境进行退火形成NV色心6，其位于纳米柱波导端面正中心即S7。
以上实施例完成微纳米结构的自对准定点掺杂。最终通过实施例可获得一种NV色心传感器，其特点在于NV色心均处于金刚石纳米柱波导结构端面正中心位置，均能达到预期的最优荧光收集效率，具有较高的良率。NV色心传感器的工作原理是，将外界的磁、电、温度等信息转化为NV色心荧光强度的信息进行读出。本实施例获得的NV色心传感器具有更高的荧光信号收集效率，因此具有更好的探测灵敏度。
需要说明的是本专利所获得的传感器可以与扫描显微成像技术相结合，形成扫描试NV色心传感器。例如替代专利CN202010100070.X中纳米柱波导结构制作方法，提升传感器的良率。
以上所述的具体实施例，对本发明的目的、技术方案和有益效果进行了进一步详细说明，所应理解的是，以上所述仅为本发明的具体实施例而已，并不用于限制本发明，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种基于自对准工艺的微纳米结构定点缺陷掺杂的方法，包括：
    S1，在晶体衬底表面依次形成牺牲层、光刻胶层；
    S2，根据微纳米图形在所述光刻胶层光刻出掩模孔；
    S3，通过所述掩模孔对所述牺牲层各向同性刻蚀，将所述微纳米图形放大至所述牺牲层；
    S4，对所述掩模孔下方裸露的晶体表面进行离子注入掺杂；
    S5，去除所述光刻胶层，沉积掩模材料；
    S6，去除所述牺牲层，所述牺牲层中微纳米放大图形转移为掩模材料图形；
    S7，对裸露晶体表面进行刻蚀，去除表面所述掩模材料并退火形成特定缺陷。
  2. 根据权利要求1所述的基于自对准工艺的微纳米结构定点缺陷掺杂的方法，其特征在于，所述S1中牺牲层、光刻胶层形成双层薄膜结构，形成方式包括涂覆、气相沉积。
  3. 根据权利要求1所述的基于自对准工艺的微纳米结构定点缺陷掺杂的方法，其特征在于，所述S1中牺牲层材料包括PMGI、SiO 2、SiN。
  4. 根据权利要求1所述的基于自对准工艺的微纳米结构定点缺陷掺杂的方法，其特征在于，所述S2中掩模孔为微纳米图形等比例缩小的图形，所述掩模孔位于下层结构图形中心正上方位置。
  5. 根据权利要求1所述的基于自对准工艺的微纳米结构定点缺陷掺杂的方法，其特征在于，所述S4中离子注入的离子种类与掺杂缺陷种类相关，离子穿透深度不能超过所述光刻胶层的厚度。
  6. 根据权利要求1所述的基于自对准工艺的微纳米结构定点缺陷 掺杂的方法，其特征在于，所述S5中沉积掩模材料采用镀膜工艺，包括蒸发镀膜、溅射镀膜。
  7. 根据权利要求1所述的基于自对准工艺的微纳米结构定点缺陷掺杂的方法，其特征在于，所述S6中去除所述牺牲层采用溶脱剥离的方式。
  8. 根据权利要求1所述的基于自对准工艺的微纳米结构定点缺陷掺杂的方法，其特征在于，所述S7中对裸露晶体表面刻蚀采用干法刻蚀工艺，包括等离子体刻蚀、反应离子刻蚀、感应耦合等离子体刻蚀。
  9. 根据权利要求1所述的基于自对准工艺的微纳米结构定点缺陷掺杂的方法，其特征在于，所述S7中去除表面所述掩模材料采用干法刻蚀或湿法刻蚀工艺。
  10. 一种NV色心传感器，其特征在于，所述NV色心传感器中的NV色心通过权利要求1-9中任一所述的方法制备。
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CN106229256A (zh) * 2016-07-29 2016-12-14 东莞华南设计创新院 一种硅锗纳米线的制作方法
CN109904062A (zh) * 2019-02-03 2019-06-18 中国科学院微电子研究所 纳米结构的制备方法

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