WO2022088080A1 - 信息传输方法、控制装置、电磁信号收发装置及信号处理设备 - Google Patents

信息传输方法、控制装置、电磁信号收发装置及信号处理设备 Download PDF

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Publication number
WO2022088080A1
WO2022088080A1 PCT/CN2020/125435 CN2020125435W WO2022088080A1 WO 2022088080 A1 WO2022088080 A1 WO 2022088080A1 CN 2020125435 W CN2020125435 W CN 2020125435W WO 2022088080 A1 WO2022088080 A1 WO 2022088080A1
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Prior art keywords
fault
processor
channel
electromagnetic signal
information
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PCT/CN2020/125435
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English (en)
French (fr)
Inventor
阮红超
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华为技术有限公司
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Priority to JP2023526334A priority Critical patent/JP2023547484A/ja
Priority to EP20959242.7A priority patent/EP4228225A4/en
Priority to PCT/CN2020/125435 priority patent/WO2022088080A1/zh
Priority to CN202080015075.0A priority patent/CN113454613B/zh
Priority to CA3197021A priority patent/CA3197021A1/en
Publication of WO2022088080A1 publication Critical patent/WO2022088080A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/87—Combinations of radar systems, e.g. primary radar and secondary radar
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/02—Systems using reflection of radio waves, e.g. primary radar systems; Analogous systems
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
    • G01S13/88—Radar or analogous systems specially adapted for specific applications
    • G01S13/93—Radar or analogous systems specially adapted for specific applications for anti-collision purposes
    • G01S13/931—Radar or analogous systems specially adapted for specific applications for anti-collision purposes of land vehicles
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/003—Transmission of data between radar, sonar or lidar systems and remote stations
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
    • G01S7/40—Means for monitoring or calibrating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4072—Drivers or receivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

Definitions

  • the present application relates to the technical field of information transmission, and in particular, to an information transmission method, a control device, an electromagnetic signal transceiver device, and a signal processing device.
  • Millimeter-wave radar systems are attracting more and more attention due to their low cost and mature technology. Millimeter-wave radar systems have but are not limited to the following advantages: large bandwidth, abundant frequency domain resources, low antenna sidelobes, which is conducive to imaging or quasi-imaging; short wavelengths, the size of radar equipment and antenna aperture can be reduced, and weight; narrow beam , under the same antenna size, the millimeter wave beam is much narrower than the microwave beam, and the radar resolution is high; Working around the clock, etc. Based on the advantages of the millimeter wave radar system, the millimeter wave radar system has been widely used in many fields, such as the automotive field. Since the wavelength of the millimeter wave is between 1 and 10 millimeters (mm), the corresponding frequency range is 30 to 200 GHz. Hertz (GHz), in this frequency band, the millimeter-wave-related characteristics are very suitable for application in the automotive field. Generally, the frequencies of the automotive millimeter-wave radar system are 24GHz and 77GHz.
  • the present application provides an information transmission method, a control device, an electromagnetic signal transceiver device, and a signal processing device, which are used to handle each fault in a double-point fault in time.
  • the present application provides an information transmission method, which can be applied to a control device, and the control device can include a first processor and a second processor.
  • the method may include: the first processor acquires first fault information of the electromagnetic signal transceiving device through the first channel, the second processor acquires the second fault information from the electromagnetic signal transceiving device and transmitted via the second channel, wherein the first The fault information corresponds to the first fault, and the second fault information corresponds to the second fault.
  • the first processor can obtain the first fault information through the first channel, and the second processor can obtain the second fault information through the second channel.
  • the first processor can obtain the information corresponding to the first fault information.
  • the first fault is processed in time, and the second processor can process the second fault corresponding to the second fault information in time.
  • the processing of the second fault by the second processor can be performed in parallel with the processing of the first fault by the first processor, so that each fault in the double-point fault can be processed in time.
  • the first channel may be a serial peripheral interface (SPI), and/or the second channel may be a low voltage differential signaling (LVDS) channel.
  • SPI serial peripheral interface
  • LVDS low voltage differential signaling
  • the first channel may be an SPI
  • the second channel may be an LVDS channel.
  • the method of sending the second fault information by multiplexing the LVDS channel belongs to the method of heterogeneous redundancy, which helps to avoid the situation that all communication channels fail due to the single communication method of SPI.
  • control device may further include a first memory, and the second fault information is stored in the first memory; the second processor may acquire the second fault information from the first memory.
  • the second processor may obtain the second fault information from the first memory in the following two possible implementation manners.
  • Implementation manner 1 The second processor periodically queries the first memory, and acquires the second fault information from the first memory.
  • the second processor detects a second fault indication (FI) hard-wired flag, acquires second fault information from the first memory, and the second FI hard-wired flag is used to indicate the second fault.
  • FI fault indication
  • the second processor After the second processor detects the second FI hard-wired flag, it indicates that the second fault has occurred. At this time, the second processor obtains the second fault information from the first memory, which is helpful for saving Power consumption of the second processor.
  • the second processor processes the second fault in response to at least one of the first fault not being processed, the first instruction, or the detection of the second FI hardwire flag, wherein the first fault is
  • the instructions are for instructing the second processor to handle the second fault.
  • the second processor determines that the processing of the first fault is not completed, and detects the second FI hardwire flag, and processes the second fault.
  • the first processor detects the first FI hard-wired flag, and sends a first instruction to the second processor, where the first instruction is used to instruct the second processor to handle the second fault, the first The FI hardwire flag is used to indicate the first fault.
  • the second processor can process the generated second fault in time, which helps to avoid the inability to process the second fault in time due to the second processor processing other tasks. , thereby helping to further improve the processing efficiency of double-point faults.
  • the second processor sends a second instruction to the electromagnetic signal transceiving apparatus, where the second instruction is used to instruct the electromagnetic signal transceiving apparatus to clear the second FI hard wire flag and/or the second fault information.
  • the second FI hardwire flag corresponding to the second fault and the second fault information are cleared in time, so that the newly generated fault can be processed in time in the next task cycle .
  • the first processor receives the first FI hard-line flag from the electromagnetic signal transceiving device, and the first FI hard-line flag is used to indicate the first fault, when the first processor receives the first FI The hard-wired mark indicates that the first fault has occurred in the electromagnetic signal transceiver; the first processor sends a first request message to the electromagnetic signal transceiver, and the first request message is used to request the first fault information; the first processor passes the first channel Receive the first fault information from the electromagnetic signal transceiving device.
  • the present application provides an information transmission method.
  • the method includes that an electromagnetic signal transceiver detects a first fault, and transmits first fault information to a control device through a first channel, where the first fault information corresponds to the first fault;
  • the signal transceiving device detects the second fault, and transmits the second fault information to the control device through the second channel, and the second fault information corresponds to the second fault.
  • the electromagnetic signal transceiver device can transmit different fault information (ie, the first fault information and the second fault information) to the control device through two different channels (ie, the first channel and the second channel).
  • the purpose is to improve the timeliness of the electromagnetic signal transceiver device transmitting fault information to the control device, thereby helping to further improve the timeliness of processing each fault in the double-point fault.
  • the first channel may be an SPI; and/or the second channel may be an LVDS channel.
  • the first channel may be an SPI
  • the second channel may be an LVDS channel.
  • the method of sending the second fault information by multiplexing the LVDS channel belongs to the method of heterogeneous redundancy, which helps to avoid the situation that all communication channels fail due to the single communication method of SPI.
  • the electromagnetic signal transceiver device may transmit the second fault information to the first memory in the control device through the second channel.
  • the second fault information can be transmitted to the first memory through the second channel.
  • the electromagnetic signal transceiver does not need to wait for an instruction from the processor, and can directly transmit the second fault to the first memory.
  • the second fault information helps to improve the efficiency of the electromagnetic signal transceiver device for transmitting the second fault information, thereby helping to improve the timeliness of the second fault processing.
  • the electromagnetic signal transceiving device may send a second FI hard-wire flag to the second processor in the control device, where the second FI hard-line flag is used to indicate the second fault.
  • the electromagnetic signal transceiving device detects the second fault, and may send a second FI hard-wire flag for indicating the second fault to the second processor in the control device.
  • the electromagnetic signal transceiving device may send a first FI hard-wire flag to the first processor in the control device, where the first FI hard-line flag is used to indicate that the first fault is generated.
  • the electromagnetic signal transceiving device detects the first fault, and may send a first FI hard-wire flag to the first processor in the control device for indicating the generation of the first fault.
  • the electromagnetic signal transceiver device detects the first fault and triggers the first FI hard-wired mark, and detects the second fault and triggers the second FI hard-wired mark. In this way, the electromagnetic signal transceiver device can notify the control device in time after detecting two faults , so that the control device can deal with the fault in time.
  • the electromagnetic signal transceiving apparatus receives a second instruction from the second processor, and according to the second instruction, clears the second FI hard-wired flag and/or the second fault information.
  • the second FI hard-wired flag and/or the second fault information corresponding to the second fault is cleared in time by the electromagnetic signal transceiving device, which can prevent the influence of the newly generated fault in the next task cycle.
  • the electromagnetic signal transceiving device may receive the first request message from the first processor in the control device, and obtain the first fault information according to the first request message.
  • the electromagnetic signal transceiving device may query the fault register according to the first request message, and obtain the first fault information from the fault register.
  • the present application provides an information transmission device or control device, the information transmission device or control device is used to implement any one of the above-mentioned first aspect or the first aspect method, including corresponding functional modules, respectively used for Implement the steps in the above method.
  • the functions can be implemented by hardware, or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the control device includes a first processor, a second processor, a first interface circuit and a second interface circuit; wherein the first processor is configured to acquire the first fault of the electromagnetic signal transceiver device through the first interface circuit corresponding to the first channel information, the first fault information corresponds to the first fault; the second processor is used to obtain the second fault information of the electromagnetic signal transceiver, and the second fault information corresponds to the second fault; wherein the second fault information comes from the electromagnetic signal transceiver, and transmitted through the second interface circuit corresponding to the second channel.
  • the first channel is an SPI; and/or the second channel is an LVDS channel.
  • control device further includes a first memory, and the second fault information is stored in the first memory; the second processor is configured to acquire the second fault information from the first memory.
  • the second processor is configured to query the first memory regularly; and obtain the second fault information from the first memory.
  • the second processor is configured to detect the second FI hard-wired flag, obtain the second fault information from the first memory, and the second FI hard-wired flag is used to indicate the second fault.
  • the second processor is further configured to process the second fault in response to the first fault not being processed, the first instruction, or the detection of the second FI hardwire flag, wherein the first instruction uses for instructing the second processor to handle the second fault.
  • control device further includes a third interface circuit; the first processor is further configured to detect the first FI hard-wired flag, and send the first instruction to the second processor through the third interface circuit, the first An instruction is used to instruct the second processor to handle the second fault, and the first FI hardwire flag is used to indicate the first fault.
  • the second processor is further configured to send a second instruction to the electromagnetic signal transceiving apparatus through the first interface circuit corresponding to the first channel, where the second instruction is used to instruct the electromagnetic signal transceiving apparatus to clear the second FI Hardwired flags and/or secondary fault messages.
  • the first processor is configured to receive the first FI hard-wired flag from the electromagnetic signal transceiver device through the first FI hard-wired pin, and the first FI hard-wired flag is used to indicate the first fault;
  • the first interface circuit corresponding to the first channel sends a first request message to the electromagnetic signal transceiver, where the first request message is used to request the first fault information.
  • the first processor may be configured to receive the first fault information from the electromagnetic signal transceiver through the interface circuit corresponding to the first channel.
  • the present application provides an information transmission device or an electromagnetic signal transceiver device, the information transmission device or electromagnetic signal transceiver device is used to implement any one of the above second aspect or the second aspect method, including corresponding functional modules , which are respectively used to implement the steps in the above method.
  • the functions can be implemented by hardware, or by executing corresponding software by hardware.
  • the hardware or software includes one or more modules corresponding to the above functions.
  • the electromagnetic signal transceiving device includes a controller, a fourth interface circuit and a fifth interface circuit.
  • the controller is used to detect the first fault, and transmit the first fault information to the control device through the fourth interface circuit corresponding to the first channel, where the first fault information corresponds to the first fault; the controller is also used to detect the second fault , and transmit the second fault information to the control device through the fifth interface circuit corresponding to the second channel, where the second fault information corresponds to the second fault.
  • the first channel may be an SPI; and/or the second channel may be an LVDS channel.
  • the first channel may be an SPI; and/or the second channel may be an LVDS channel.
  • the controller is configured to: transmit the second fault information to the first memory of the control device through the fifth interface circuit corresponding to the second channel.
  • the controller is further configured to: send a second FI hard-wired flag to the second processor of the control device through the second FI hard-wired pin, where the second FI hard-wired flag is used to indicate the second FI hard-wired flag Fault.
  • the controller is configured to: detect the second fault, and send a second FI hard-wired flag for indicating the second fault to the second processor of the control device through the second FI hard-wired pin.
  • the controller is further configured to: clear the second FI hardwire flag and/or the second fault information according to a second instruction from the second processor of the control device.
  • the controller may be configured to receive the second instruction from the second processor of the control device through the fourth interface circuit corresponding to the first channel.
  • the controller is further configured to: send the first FI hard-wired flag to the first processor of the control device through the first FI hard-wired pin, where the first FI hard-wired flag is used to instruct the generation of the first FI hard-wired flag a failure.
  • the controller is configured to: when the first fault is detected, send a first FI hard-wired flag for indicating the generation of the first fault to the first processor of the control device through the first FI hard-wired pin.
  • the controller is configured to: obtain the first fault information in the fault register according to the first request message from the first processor of the control device.
  • the controller may be configured to receive the first request message from the first processor of the control device through the fourth interface circuit corresponding to the first channel.
  • the present application provides a signal processing device, where the signal processing device includes the control device described in the third aspect or any possible implementation manner of the third aspect and/or the fourth aspect or the fourth aspect.
  • the control device may be used to perform any one of the above first aspect or the first aspect method
  • the electromagnetic signal transceiving device may be used to perform any one of the above second aspect or the second aspect method.
  • the present application provides a terminal device, where the terminal device may include the signal processing device of the fifth aspect.
  • the terminal device may be an intelligent transportation device (vehicle or drone), a smart home device, an intelligent manufacturing device, or a robot, and the like.
  • the intelligent transportation device may be, for example, an automated guided vehicle (AGV), or an unmanned transportation vehicle.
  • AGV automated guided vehicle
  • unmanned transportation vehicle for example, an unmanned transportation vehicle.
  • the present application provides a computer-readable storage medium, in which a computer program or instruction is stored, and when the computer program or instruction is executed by a control device, the control device is made to execute the above-mentioned first aspect or the first aspect.
  • the method in any possible implementation of one aspect; or, when the computer program or instruction is executed by the electromagnetic signal transceiving device, the electromagnetic signal transceiving device is made to perform the above-mentioned second aspect or any possible implementation of the second aspect. method.
  • the present application provides a computer program product
  • the computer program product includes a computer program or an instruction
  • the control device is made to perform the above-mentioned first aspect or any possibility of the first aspect or, when the computer program or instructions are executed by the electromagnetic signal transceiving apparatus, the electromagnetic signal transceiving apparatus is caused to execute the method in the second aspect or any possible implementation manner of the second aspect.
  • the technical effects that can be achieved in the third aspect please refer to the description of the beneficial effects in the first aspect
  • the technical effects that can be achieved in the fourth aspect may refer to the description of the beneficial effects in the second aspect
  • the fifth to eighth aspects for technical effects that can be achieved, reference may be made to the descriptions of the beneficial effects in the first aspect and the second aspect, which will not be repeated here.
  • FIG. 3 is a schematic diagram of a millimeter-wave radar system provided by the application.
  • FIG. 5 is a schematic flowchart of another information transmission method provided by the present application.
  • FIG. 6 is a schematic flowchart of another information transmission method provided by the present application.
  • FIG. 7 is a schematic flowchart of another information transmission method provided by the present application.
  • FIG. 8 is a schematic structural diagram of a control device provided by the application.
  • FIG. 9 is a schematic structural diagram of an electromagnetic signal transceiver provided by the application.
  • FIG. 10 is a schematic structural diagram of a signal processing device provided by the present application.
  • the rising edge in digital circuits, represents the level of the voltage with a logic level.
  • Logic levels include both high and low levels.
  • Digital circuits formed by different components have different logic levels corresponding to voltages. It can be specified as a logic high level, represented by a number 1; a logic low level, represented by a number 0.
  • the moment (moment) when the digital level changes from a low level (digital "0") to a high level (digital "1”) is called a rising edge.
  • the moment when the digital level changes from a high level (digital "1") to a low level (digital "0") is called a falling edge.
  • random access memory random access memory
  • Random access memory also called main memory
  • main memory is the internal memory that exchanges data directly with the CPU. It can be read and written at any time (except when flushing), is fast, and is often used as a temporary data storage medium for the operating system or other running programs.
  • RAM When RAM is working, information can be written (stored in) or read out (extracted) from any specified address at any time. After the RAM is powered on, the data information can be accessed at any location at any time, and the internal information will disappear after the power is turned off.
  • Registers are some small storage areas used to store data inside the CPU, which are used to temporarily store the data involved in the operation and the operation results. It can also be understood that a register is usually a sequential logic circuit, but this sequential logic circuit only includes a storage circuit.
  • the storage circuit of the register is composed of latches or flip-flops. Because a latch or flip-flop can store 1-bit binary numbers, N latches or flip-flops can form an N-bit register.
  • Registers are components within the central processing unit. Registers are high-speed storage elements with limited storage capacity that can be used to temporarily store instructions, data, and addresses.
  • the flip-flops in the register are only required to have the function of setting 1 and setting 0, so whether it is a level-triggered flip-flop, or a pulse-triggered or edge-triggered flip-flop, a register can be formed.
  • serial peripheral interface serial peripheral interface
  • the serial peripheral interface is a synchronous peripheral interface, which enables a single-chip microcomputer (or a single-chip microwave integrated circuit) to communicate with various peripheral devices in a serial manner to exchange information.
  • Peripherals include but are not limited to a microprocessor unit (microcontroller unit, MCU) and the like.
  • SPI can be applied to various systems under software control.
  • a master controller and several slave controllers, several slave controllers are connected to each other to form a multi-master system (distributed system), various systems formed by a master controller and one or several slave I/O devices, etc. .
  • a master controller can be used as the master to control data and transmit the data to one or several slave peripheral devices.
  • the slave controller can receive or send data only when the master controller issues a command, and the data transmission format is high-order (MSB) first and low-order (LSB) last.
  • MSB high-order
  • LSB low-order
  • Hard-wired pins refer to hard-wired connections between two pins to transmit high and low levels.
  • FIG. 1 is a schematic flowchart of an information processing method in the prior art.
  • the CPU in the method is the CPU in the MCU, and the control unit is the control unit included in the MMIC.
  • the method includes the following steps:
  • Step 101 the control unit in the MMIC detects that the MMIC is faulty, and sends the FI hard-wired flag to the MCU.
  • control unit detects that the MMIC has failed, triggering the FI hardwire flag.
  • Step 102 the CPU detects the FI hard-wired flag, and sends the instruction b to the control unit through the SPI.
  • the instruction b is used to instruct the MMIC to stop sending and receiving service data (that is, stop the collection of normal service data of the millimeter-wave radar system), and discard the service data obtained in this task period.
  • Step 103 the control unit in the MMIC stops sending and receiving service data according to the instruction b, stops transmitting service data to the RAM in the MCU, and discards (clears) the service data acquired by the RAM in the MMIC in this task cycle.
  • Step 104 the control unit in the MMIC periodically sends the execution process of the instruction b to the CPU through the SPI. Accordingly, the CPU receives the execution progress of the instruction b from the control unit.
  • the execution process of the instruction b can be represented by a first process flag, and the first process flag can be represented by 0 and 1, where 0 represents that the instruction b has not been executed, and 1 represents that the instruction b has been executed.
  • step 105 the CPU can determine whether the MMIC has completed the execution of instruction b according to the first process flag; if completed, execute step 106; Here, when the CPU receives that the first process flag is 0, it can be determined that the execution of the instruction b is not completed; when the CPU receives that the first process flag is 1, it can be determined that the execution of the instruction b is completed.
  • Step 106 the CPU clears (or is called discarding) the service data received in the current task cycle in the RAM in the MCU.
  • clearing the service data received in the current task cycle in the RAM in the MCU refers to clearing all data stored in the RAM in the MCU.
  • Step 107 the CPU sends the command c to the control unit through the SPI.
  • the control unit receives the instruction c from the CPU through the SPI.
  • the instruction c is used to instruct the control unit to query the fault register.
  • Step 108 the control unit in the MMIC queries the fault register according to the instruction c, and obtains the information of the fault register.
  • Step 109 the control unit in the MMIC sends the queried information of the fault register to the CPU through the SPI. Accordingly, the CPU can receive information from the fault register of the control unit through the SPI.
  • Step 110 the CPU identifies the first fault according to the information in the fault register.
  • the information of the fault register received by the CPU is 01000000000000000000000000, and the second bit can be identified as a fault.
  • Step 111 the CPU processes the identified first fault.
  • Step 112 the CPU sends the instruction d to the control unit through the SPI.
  • the control unit receives the instruction d from the CPU through the SPI.
  • the instruction d is used to instruct the control unit to clear the FI hard-wired flag bit and the fault information corresponding to the first fault.
  • Step 113 according to the instruction d, the control unit in the MMIC clears the fault information corresponding to the first fault, and clears the FI hard wire flag.
  • Step 114 the control unit in the MMIC periodically sends a response d to the CPU through the SPI. Accordingly, the CPU receives the response d from the control unit.
  • the response d includes the execution process of the instruction d, 0 indicates that the instruction d has not been executed, and 1 indicates that the instruction d has been executed.
  • Step 115 the CPU determines that the MMIC executes the completion instruction d according to the received response d, and exits the fault handling task.
  • single point of failure handling can be implemented.
  • the CPU actively inquires whether the second fault occurs, and handles it.
  • FIG. 2 it is an information processing method in the prior art.
  • the information processing method can solve the double-point failure problem.
  • the first fault (referred to as the first fault) generated by the MMIC is processed first.
  • the specific processing process please refer to steps 101 to 114 in the aforementioned FIG. 1.
  • the CPU determines After the MMIC executes the completion instruction d, the following steps 201 to 207 are performed.
  • Step 201 the CPU sends an instruction e to the control unit through the SPI.
  • the control unit receives the command e from the SPI through the SPI.
  • the instruction e is used to instruct the control unit to inquire about the fault information.
  • Step 202 the control unit in the MMIC may query the fault register according to the instruction e to obtain the information of the fault register.
  • the information inquired into the fault register by the control unit includes fault information of two faults.
  • the information of the queried fault register is 0100100000000000000000000, which means that a fault occurs in the second bit and a fault occurs in the fifth bit.
  • Step 203 the control unit in the MMIC sends the queried information of the fault register to the CPU through the SPI. Accordingly, the CPU can receive information from the fault register of the control unit through the SPI.
  • step 203 reference may be made to the introduction of the above-mentioned step 109, and details are not repeated here.
  • Step 204 the CPU detects whether the second fault in the information in the fault register is a valid fault; if yes, executes step 205 ; if not, executes step 206 .
  • the CPU Since the CPU actively checks whether there is a fault at regular intervals, the MMIC may not be faulty when the CPU queries. Therefore, it is necessary to determine whether the second fault is a valid fault.
  • the CPU needs to identify the second fault from the information in the fault register. For example, if the information in the fault register queried is 0100000000000000000000000, and it can be determined that the second fault has been processed, it means that the second fault has not occurred , or an invalid fault; if the queried fault register information is 0100100000000000000000000, and it can be determined that the second fault has been processed, it means that the fifth fault is a valid fault, that is, the second fault.
  • Step 205 the CPU can process the second fault.
  • Step 206 the CPU exits the fault handling task.
  • the MMIC After the MMIC has a fault, it will trigger the FI hard-wired flag bit, and send the FI hard-wired flag to a CPU in the MCU.
  • the CPU detects the FI hard-wired flag, it will send the query fault register to the MMIC.
  • the MMIC sends the queried fault register information to the CPU, and the CPU identifies the fault register information. After identifying the first fault, it processes the first fault until the first fault is detected.
  • the FI hardwire flag is cleared only after the fault has been handled.
  • the present application proposes an information transmission method, please refer to the following FIG. 4 .
  • the information transmission method can make each fault in the double-point fault be dealt with in time as much as possible.
  • FIG. 3 is a schematic structural diagram of a possible millimeter-wave radar system of the present application.
  • the millimeter-wave radar system may include a microcontroller unit (MCU) 301 and a monolithic microwave integrated circuit (MMIC) 302 .
  • the MCU 301 may include at least two central processing units (CPUs) (in FIG. 3 , the CPU 3011 and the CPU 3012 are taken as an example), a RAM 3013 , an SPI module 3014 and an LVDS module 3015 .
  • the MMIC 302 may include a control unit 3021, an LVDS module 3022, an SPI module 3023, a fault register 3024, a fault register 3025, and the like.
  • the SPI module 3014 corresponds to the SPI module 3023, and the SPI module 3014, the SPI module 3023, and the physical connection (such as a cable or PCB trace) between the SPI module 3014 and the SPI module 3023 can form a connection between the MCU301 and the MMIC302.
  • the channel for example, is called SPI;
  • the LVDS module 3015 corresponds to the LVDS module 3022, and the LVDS module 3015, the LVDS module 3022, and the physical connection (such as a cable or PCB trace) between the LVDS module 3015 and the LVDS module 3022 can also form an MCU301 A channel between the MMIC302, for example, can be called an LVDS channel.
  • the LVDS module 3015 can be called a differential signal transmitter, which can be used to convert the TTL signal of unbalanced transmission into the LVDS signal of balanced transmission; the LVDS module 3022 can be called a differential signal receiver, which can be used to convert the LVDS signal of balanced transmission. TTL signal for unbalanced transmission.
  • the SPI module may be an interface circuit, or referred to as an input and output interface; the LVDS module may be an interface circuit, or referred to as an input and output interface.
  • CPU3011 (or CPU3012) and control unit 3021 can communicate through SPI
  • RAM3013 and control unit 3021 can communicate through LVDS channel, for example, electromagnetic waves received by MMIC302 can be transmitted to RAM3013 through LVDS channel.
  • the MCU can also include multiple pins, and the function of each pin can be controlled by software to achieve a certain function.
  • the interrupt pin of MCU this pin can realize the interrupt function through software control.
  • the MMIC302 is a passive device and requires the MCU301 to control its execution tasks.
  • the various components included in the architecture are only an exemplary description. For example, the CPU, fault register, etc. can be replaced by other components with equivalent functions. This application does not make specific component types. Specific restrictions.
  • the control unit 3021 is used to control the work of the MMIC302.
  • the MMIC 302 can be controlled to perform service data detection, MMIC fault detection, and the like.
  • the control unit 3021 can generate radar signals (ie, electromagnetic waves), and then transmit the radar signals through the transmitter.
  • a radar signal consists of one or more burst packets, each burst including multiple chirp signals. After the radar signal is sent, it is reflected by one or more targets to form an echo signal, and the echo signal is received by the receiver.
  • the MMIC302 is also used to transform and sample the echo signal received by the receiver, and transmit the processed echo signal to the MCU301.
  • Both the CPU 3011 and the CPU 3012 are configured for fault processing, eg, processing faults generated by the MMIC 302 .
  • the RAM 3013 is used to temporarily store the data (for example, electromagnetic waves) and/or fault information transmitted from the MMIC 302 .
  • the millimeter wave radar system may further include a transmitter 1031, a receiver 1032, and the like.
  • the transmitter may be composed of a transmit antenna and a transmit channel in the MMIC.
  • the receiver can be composed of a receive antenna and a receive channel in the MMIC.
  • the transmitting antenna and the receiving antenna may be located on a printed circuit board (print circuit board, PCB), and the transmitting channel and the receiving channel may be located in the chip, that is, AOB (antenna on PCB); or, the transmitting antenna and the receiving antenna may be located in the chip package Inside, the transmit channel and receive channel can be located in the chip, that is, AIP (antenna in package).
  • AOB antienna on PCB
  • the millimeter-wave radar system shown in Figure 3 above can be used in various fields, such as vehicle-mounted radar (that is, the millimeter-wave radar system is installed on the car), roadside traffic radar (that is, the millimeter-wave radar system is installed on the roadside traffic radar. equipment), UAV radar (that is, the millimeter wave radar system is installed on the UAV), etc.
  • vehicle-mounted radar that is, the millimeter-wave radar system is installed on the car
  • roadside traffic radar that is, the millimeter-wave radar system is installed on the roadside traffic radar. equipment
  • UAV radar that is, the millimeter wave radar system is installed on the UAV
  • the above-mentioned millimeter-wave radar system shown in FIG. 3 can also be applied to terminal equipment, or arranged in components of terminal equipment; for example, the terminal equipment can be smart home equipment, smart manufacturing equipment, robots, or smart transportation
  • the transportation device may be, for example, an automated guided vehicle (AGV) or an unmanned transportation vehicle.
  • AGV
  • the millimeter-wave radar system may further include a connector, a controller area network (CAN), an electromagnetic compatibility (EMC) Protection and power management modules (power management ICs, PMICs).
  • the connector can be used to connect the millimeter-wave radar system with the electronic and electrical system of the vehicle.
  • the control area network can be used for the exchange of information between the electronic and electrical systems of the vehicle. For example, fault information can be reported to the electronic and electrical systems of the vehicle through CAN.
  • the control area network is an ISO international standardized serial communication protocol, which can be used to communicate directly with the external control terminal.
  • Electromagnetic compatibility protection can be used for electromagnetic compatibility protection of power supply.
  • the power management module can be used to convert the power input of the vehicle into 3.3V and 1.25V, and supply it to CAN, MCU and MMIC.
  • the vehicle-mounted millimeter-wave radar system can measure the distance, angle, and relative velocity from the millimeter-wave radar system to the measured object. Specifically, the vehicle-mounted millimeter-wave radar system can transmit millimeter waves through the transmitter 1031, and receive the target reflected signal through the receiver 1032. After processing, the physical environment information around the vehicle body (such as the relationship between the vehicle and other objects) can be quickly and accurately obtained. The relative distance, relative speed, angle, movement direction, etc.), and then target tracking, recognition and classification are carried out according to the detected object information, and then data fusion is carried out in combination with vehicle body dynamic information.
  • the vehicle can realize adaptive cruise control (adaptive cruise control), forward collision warning (forward collision warning), blind spot detection (blind spot detection), assisted parking (parking aid), assisted lane change (lane change assistant), and other advanced driving assistance system (advanced driving assistant system, ADAS) functions.
  • adaptive cruise control adaptive cruise control
  • forward collision warning forward collision warning
  • blind spot detection blind spot detection
  • assisted parking parking aid
  • assisted lane change lane change assistant
  • ADAS advanced driving assistance system
  • the fault behavior of electronic and electrical systems is mainly caused by random hardware failures and systematic failures, and random hardware failures are divided into single-point failure, double-point failure (or double-point failure), and three-point and more multi-point failures (also called double-point failures). known as failsafe).
  • the single point of failure refers to a failure occurring in the same task cycle, wherein the task cycle refers to the time period from when a failure occurs to when the failure is processed.
  • a two-point failure refers to two failures that occur in the same task cycle; a three-point failure refers to three failures that occur in the same task cycle. Since the probability of multi-point failure is very small, it can basically be ignored.
  • an information transmission method is provided in the present application.
  • the method can be applied to the millimeter-wave radar system shown in FIG. 3 , or a related device in the millimeter-wave radar system.
  • the method can be applied to an electromagnetic signal transceiving device and a control device, where the control device includes a first processor and a second processor; optionally, it can also include at least one memory.
  • the electromagnetic signal transceiving device includes a controller; optionally, it may also include at least one register. The method includes the following steps:
  • Step 401 the electromagnetic signal transceiving device detects the first fault, and can transmit the first fault information corresponding to the first fault to the control device through the first channel.
  • the control device acquires the first fault information of the electromagnetic signal transceiver through the first channel.
  • the first fault information is transmitted to the first processor of the control device through the first channel. And/or, the first processor of the control device acquires the first fault information through the first channel.
  • the first channel may be a control channel, for example, SPI, or an integrated circuit (inter integrated circuit, IIC) interface, or a serial communication interface (serial communication interface, SCI), or all
  • the control device is a micro-control unit, such as MCU301;
  • the electromagnetic signal transceiver is a single-chip microwave integrated circuit, such as MMIC302.
  • the electromagnetic signal transceiving device may, upon detecting the first fault, send a first FI hard-wire flag for indicating the generation of the first fault to the first processor of the control device.
  • the electromagnetic signal transceiving device may, upon detecting the first fault, set the FI hardwire flag to a high level (eg, 1), and send the FI hardwire flag set to a high level to the control device, which is set to a high level.
  • the high-level FI hard line flag is the first FI hard line flag.
  • the FI hardwire flag is represented by 1 after being triggered. It should be understood that the FI hard line flag can also be a rising edge or a falling edge.
  • the first processor of the control device receives the first FI hardwire flag from the electromagnetic signal transceiving device. Further, the first processor sends a first request message to the electromagnetic signal transceiving device, wherein the first request message is used to request the first fault information.
  • the electromagnetic signal transceiver may obtain the first fault information in the fault register according to the first request message. Specifically, the electromagnetic signal transceiver device can query the fault registers in the order of the fault registers according to the first request message, and then obtain information of the fault registers, where the information of the fault registers includes the first fault information.
  • the information of the fault register can be 32-bit or 64-bit. The following takes the information of the fault register as 32-bit as an example.
  • the information of the fault register is 00000000000000000000000000; if a fault occurs, one of the 32 bits is set by 0 becomes 1, for example, 0000010000000000000000000000; if two faults occur, two of the 32 bits are changed from 0 to 1, for example, 0010010000000000000000000000. That is, 1 means a failure occurred and 0 means no failure occurred.
  • the electromagnetic signal transceiving device may send information of the fault register to the control device, where the information of the fault register includes the first fault information.
  • the control device can receive information from the fault register of the electromagnetic signal transceiving device.
  • the first processor in the control device may identify the first fault information in the information of the fault register.
  • the information of the fault register received by the first processor is 0000010000000000000000000000, and it can be recognized that the sixth bit is the first fault information, that is, the first fault information is in the sixth bit.
  • the information of the fault register received by the first processor is 0010010000000000000000000000000, and the first processor identifies in sequence and identifies that the third bit is the first fault information, that is, the first fault information is in the third bit.
  • Step 402 the electromagnetic signal transceiving device detects the second fault, and can transmit the second fault information corresponding to the second fault to the control device through the second channel.
  • the control device acquires the second fault information through the second channel.
  • the second fault information is transmitted to the second processor of the control device through the second channel. And/or, the second processor in the control device acquires the second fault information transmitted through the second channel.
  • the second channel may be a data channel, for example, an LVDS channel, or a mobile industry processor interface (MIPI).
  • MIPI mobile industry processor interface
  • the first channel is SPI and the second channel is LVDS channel.
  • the solution when applied to a millimeter-wave radar, it is compatible with the SPI and LVDS channels in the existing millimeter-wave radar.
  • the second fault information may be stored in the first memory in the control device.
  • the electromagnetic signal transceiving device transmits the second fault information to the first memory in the control device through the second channel.
  • Implementation manner 1 The second processor detects the second FI hard-wired flag, and the second FI hard-wired flag is used to indicate that a second fault occurs in the electromagnetic signal transceiving device. The second processor obtains the second fault information from the first memory.
  • Implementation manner 2 The second processor periodically queries the first memory, and acquires the second fault information from the first memory.
  • the second processor may periodically query the first memory and identify the second fault information.
  • identification methods please refer to the related description of step 509 in FIG. 5 below. At this time, the triggering of the FI hardwire flag is not required.
  • the electromagnetic signal transceiver device detects the second fault, and can send the information of the fault register to the control device through the LVDS channel.
  • the control device can receive the information from the fault register of the electromagnetic signal transceiving device through the LVDS channel.
  • the second processor in the control device may acquire (or identify) the information of the fault register, and identify the second fault information from the information of the fault register.
  • the information of the fault register obtained by the second processor from the first memory of the control device is 001001000000000000000000000
  • the sixth bit of the fault register information ie the first fault information
  • the second processor identifies the information in the fault register as 0010010000000000000000000000
  • it will mask the sixth bit, that is, the first fault information in the sixth bit will not be identified, and the second processor will identify the third bit and determine For the second fault information.
  • the second processor reads the information of the fault register from the first memory of the control device as 00000100010000000000000000000000, and reads the fault of the sixth bit of the fault register information from the cache of the first processor (that is, the first fault). information) has been processed by the first processor.
  • the second processor recognizes the information of the fault register as 0000010001000000000000000000, it will mask the sixth bit, that is, it will not identify the fault information of the sixth bit, and will continue to identify the bits after the sixth bit. Until the 10th digit is identified, it is determined as the second fault information.
  • the processing of the second fault by the second processor can be performed in parallel with the processing of the first fault by the first processor, so that each fault in the double-point fault can be processed in time as much as possible.
  • the first fault information and the second fault information are sent through two channels, which helps to avoid the situation that a single channel is used and the communication channel fails.
  • control device may process the second fault corresponding to the second fault information, and the following exemplarily shows three possible ways to trigger the second processor to handle the second fault.
  • Manner 1 The second processor receives the first instruction from the first processor.
  • the first processor may further send a first instruction to the second processor, where the first instruction is used to instruct the second processing
  • the controller handles the second fault.
  • the second processor may receive the first instruction from the first processor and, in response to the first instruction, handle the second fault.
  • the first processor in the control device detects the FI hard-wired flag, it indicates that a fault (called the first fault) has occurred in the electromagnetic signal transceiver, and at this time, the first processor needs to deal with the first fault.
  • the second processor needs to start the fault processing interrupt task and process the electromagnetic signal transceiver device in time. new fault (called the second fault).
  • the first instruction may be used to instruct the second processor to handle the second fault.
  • the first instruction may directly instruct the second processor to handle the second fault; or, the first instruction may indirectly instruct the second processor to handle the second fault.
  • the first instruction indicates that the first processor is occupied to handle the second fault. A fault, or the second processor is notified to start the fault processing task, so that when the second fault occurs, the second processor can handle the second fault.
  • the first instruction may trigger a software flag bit in the second processor, and the second processor reads the fault processing task corresponding to the software flag bit in the storage area corresponding to the software flag bit.
  • the second processor detects the second FI hard-wired flag.
  • the second processor may process the second fault in response to detecting the second FI hardwire flag. It should be understood that the second processor detects the second FI hard-wired flag, indicating that the second fault has occurred, and the second processor can be triggered to process the second fault here.
  • Manner 3 The second processor determines that the first fault has not been processed.
  • the second processor may process the second fault in response to the first fault not being processed. It should be understood that the first processor does not complete the first fault, and at this time, the first processor needs to handle the first fault. In order to prevent the first processor from generating a new fault in the electromagnetic signal transceiver device during the task period of processing the first fault and failing to handle it in time, the second processor is required to process the task of starting the fault processing.
  • any combination of the above three manners may also trigger the second processor to process the second fault.
  • the second processor determines that the first fault is unhandled and the second FI hardwire flag is detected (ie, a combination of the second and third modes), in response to the first fault unhandled and the second FI hardwire flag detected , the second processor handles the second fault.
  • the second processor detects the second FI hard-wired flag, indicating that the second fault has occurred; moreover, the first processor has not completed the processing of the first fault, in order to make the first fault and the second fault be detected as soon as possible. processing, a second processor is required to handle the second fault.
  • the first FI hard line flag as an FI hard line flag as an example
  • the second FI hard line flag as a second fault indication (FSI) hard line flag as an example
  • the first memory as an MCU
  • the electromagnetic signal transceiver device is an MMIC as an example
  • the control device is an MCU
  • the first processor is the first CPU
  • the second processor is the second CPU
  • the first channel is SPI.
  • the second channel is an LVDS channel as an example for introduction.
  • the RAM described later in this application can be replaced by the first memory
  • the MMIC can be replaced by an electromagnetic signal transceiver device
  • the MCU can be replaced by a control device
  • the first CPU can be replaced by a first processor
  • the first CPU can be replaced by a first processor.
  • Both the two CPUs can be replaced with the second processor
  • the FI hard-wire flags can be replaced with the first FI hard-line flags
  • the FSI hard-line flags can be replaced with the second FI hard-line flags
  • the SPI can be replaced with the first channel.
  • Either LVDS channel can be replaced with a second channel.
  • FIG. 5 another information transmission method is provided in the present application, and the information transmission method can be applied to the millimeter-wave radar system shown in the above-mentioned FIG. 3 .
  • the method may include the following steps:
  • Step 501 the MMIC detects the first fault, and sends the FI hardwire flag to the first CPU.
  • control unit 3021 in the MMIC 302 detects the first fault, and sends the FI hard wire flag to the CPU 3011 through the FI hard wire pin connected to the pin of the MCU 301 .
  • the MMIC can start to perform fault detection based on the instruction a sent by the first CPU.
  • Step 502 the first CPU in the MCU detects the FI hard-wired flag, and sends a first instruction to the second CPU in the MCU. Accordingly, the second CPU receives the first instruction from the first CPU.
  • each pin of the MCU has a corresponding flag
  • the flag corresponding to the pin can be stored in the register of the MCU, wherein a pin on the MCU is connected to the FI hard-wired pin, and the register stores the The flag bit of the pin connected to the FI hard-wired pin (called the FI hard-wired flag bit)
  • the first CPU can regularly detect the FI hard-wired flag bit in the register on the MCU to determine whether the MMIC is faulty. For example, if the CPU detects that the FI hardwire flag is 1, it means that a fault has occurred in the MMIC.
  • the first instruction reference may be made to the above-mentioned related content, which will not be repeated here.
  • Step 503 the first CPU in the MCU sends a first request message to the MMIC. Accordingly, the MMIC receives the first request message from the first CPU of the MCUs.
  • the first request message is used to request the first fault information. Or the first request message is used to request the MMIC to query the fault register to obtain the first fault information.
  • Step 504 the MMIC queries the fault register according to the first request message.
  • the MMIC may query the information of the fault register according to the first request message. It should be noted that the MMIC is a passive device, which can only determine that a fault has occurred, and cannot identify which bit in the fault register is faulty.
  • Step 505 the MMIC may send the information of the fault register to the first CPU. Accordingly, the first CPU may receive and buffer the information from the fault register of the MMIC.
  • the information in the fault register includes the first fault information.
  • the MMIC may send the information of the fault register to the first CPU through the SPI.
  • the first CPU can receive and buffer the information from the fault register of the MMIC through the SPI.
  • the MMIC may need to send the fault register information to the first CPU in multiple times.
  • the fault register information please refer to the foregoing related description, which will not be repeated here.
  • Step 506 the first CPU in the MCU determines (or is referred to as identifying) the first fault information in the information of the fault register.
  • step 507 For the process of identifying the first fault information in the information of the fault register by the first CPU, reference may be made to the above-mentioned related description, which will not be repeated here. It should be noted that, after the first CPU recognizes the first fault information, it will not continue to recognize subsequent bits, and the following step 507 can be executed.
  • Step 507 the first CPU in the MCU processes the first fault.
  • the fault processing software deployed in the first CPU includes a fault processing strategy, and the fault processing strategy includes but is not limited to the corresponding relationship between the fault level and the processing method.
  • the fault processing strategy includes but is not limited to the corresponding relationship between the fault level and the processing method. For example, if the fault level is a general fault, the MMIC will be reset, and if it fails to return to normal three times, the MMIC will be powered off; if the fault level is a fatal fault, the MMIC will be powered off directly.
  • the first CPU may first determine the level of the first fault, and perform corresponding processing on the first fault according to the level of the first fault.
  • Step 508 the MMIC detects the second fault, and can send the information of the fault register to the MCU through the LVDS channel. Accordingly, the MCU can receive information from the fault register of the MMIC through the LVDS channel.
  • the information of the fault register can be stored in the RAM of the MCU, and the information of the fault register includes the second fault information.
  • the MMIC302 detects the second fault, and can send the information of the fault register to the RAM3013 in the MCU301 through the LVDS channel. Accordingly, the RAM 3013 in the MCU 301 stores the information of the fault register. In other words, when the MMIC 302 detects the second fault, the LVDS channel is no longer used to transmit normal service data to the RAM 3013 in the MCU 301, but transmits the information of the fault register to the RAM 3013 in the MCU 301 by multiplexing the LVDS channel.
  • the MMIC detects the second fault and can only determine that two faults have occurred, but cannot determine which two bits in the fault register are faulty.
  • the information of the fault register is 001001000000000000000000000, and the MMIC sends the information of the fault register 001001000000000000000000000000 to the RAM of the MCU through the LVDS channel. Accordingly, the RAM in the MCU can store 0010010000000000000000000000.
  • the information of the fault register is 00000100010000000000000000000000, and the MMIC sends the information of the fault register 000001000100000000000000000000000 to the RAM of the MCU through the LVDS channel. Accordingly, the RAM in the MCU can store 00000100010000000000000000000000.
  • the MMIC continues to detect faults after the first fault is detected, and the second fault may be after the first fault is detected and at any time during the first fault's duty cycle detected.
  • step 508 may be any step after the above step 501 and before the following step 509 .
  • Step 509 the second CPU in the MCU acquires (or is referred to as identifying) the second fault information in the information of the fault register.
  • the second CPU detects the FSI hard-wired flag, and acquires the second fault information from the RAM in the MCU.
  • the CPU 3011 and the control unit 3021 are connected by FI hard-wire pins, and the CPU 3012 and the control unit 3021 are connected by FSI hard-wire pins. That is, an FSI hardwired flag for fault indication is set between MMIC302 and MCU301.
  • the control unit 3021 in the MMIC 302 detects the second fault, and sends the FSI hard wire flag to the CPU 3012 through the FSI hard wire pin connected to the pin of the MCU 301 .
  • the firmware deployed in the MMIC is preconfigured with two hard-wired flag bits (that is, the FI hard-wired flag bit and the FSI hard-wired flag bit), and the functions of the FSI hard-wired pins and the FI hard-wired pins are controlled by software. function of the feet. That is, the deployed firmware of the MMIC detects a fault for the first time and triggers the FI hard-wired flag bit; and detects a fault for the second time, triggers the FSI hard-wired flag bit.
  • the MMIC triggers the FSI hard-wired flag bit, for example, sets the FSI hard-wired flag bit to a high level (eg, 1).
  • the second CPU will serially execute tasks, and detect the FSI hard-wired flag as one of the tasks.
  • the task that handles the FSI hardwired flag interrupt has the highest priority. For example, if the second CPU needs to execute task 1 (that is, the FSI hardwire flag is detected), task 2 and task 3, the second CPU can run these three tasks serially in priority order, with task 1 having a higher priority than task 1 2, the priority of task 2 is higher than that of task 3.
  • the first CPU runs task 1, task 2 and task 3 in series.
  • the second CPU detects the occurrence of task 1, it can enter task 1, that is, execute the task. 1 process.
  • the second CPU in the MCU detects the FSI hard-wired flag, it reads the information of the fault register from the RAM in the MCU, and reads the first fault in the information of the fault register from the cache of the first CPU. information, and it is determined that the first fault has been processed by the first CPU, the second CPU shields the first fault information, and identifies the second fault information from the information in the fault register.
  • the second CPU periodically queries the RAM in the MCU, and acquires the second fault information from the RAM in the MCU.
  • the second CPU periodically reads the information of the fault register from the RAM in the MCU, reads the first fault information in the information of the fault register from the cache of the first CPU, and determines the first fault Having been processed by the first CPU, the second CPU shields the first fault information, and identifies the second fault information from the information in the fault register.
  • the second CPU identifies the second fault information from the information of the fault register read
  • the second CPU may periodically query the RAM in the MCU, for example, once every 1 ms.
  • Step 510 the second CPU in the MCU processes the second fault.
  • step 510 reference may be made to the above-mentioned step 507, which will not be repeated here.
  • the method of multiplexing the LVDS channel to send the information of the fault register belongs to the method of heterogeneous redundancy, which helps to avoid the situation that all communication channels are invalid due to the single communication method of SPI.
  • the second CPU receives the first instruction, and in response to the first instruction, can start the fault processing task.
  • FIG. 6 is a schematic flowchart of another information transmission method provided by the present application.
  • the FI hard line flag bit is 1 to indicate that the FI hard line flag is interrupted (that is, the FI hard line flag is triggered)
  • the FSI hard line flag bit is 1 to indicate that the FSI hard line flag is interrupted (that is, the FSI hard line flag is triggered).
  • the FI hard line flag bit is 1 to indicate that the FI hard line flag is interrupted (that is, the FI hard line flag is triggered)
  • the FSI hard line flag bit is 1 to indicate that the FSI hard line flag is interrupted (that is, the FSI hard line flag is triggered).
  • Step 601 the second CPU clears the data in the RAM in the MCU.
  • the second CPU may send a data clearing instruction to the RAM in the MCU, and the RAM in the MCU clears the stored data according to the data clearing instruction. In this way, the original data in the RAM in the MCU can be prevented from interfering with the fault interrupt processing task.
  • the RAM in the MCU has not yet received the information from the fault register of the MMIC. That is to say, before receiving the information of the fault register, the data in the RAM in the MCU is cleared first, so that the RAM in the MCU can only store the information of the fault register after receiving the information of the fault register.
  • Step 602 the second CPU determines whether the FI hard line flag is 1; if yes, executes step 603; if not, executes step 604.
  • the FI hard line flag is 1, it means that the first CPU has not finished processing the first fault. If the second fault occurs in the MMIC, the first CPU cannot handle the second fault in time, so the second CPU is required to handle the second fault. If it is determined that the FI hard line flag is 0, it means that the first CPU has finished processing the first fault. At this time, if a second fault occurs in the MMIC, the first CPU can directly handle the second fault, and the second CPU does not need to handle the second fault. Failure, here, the second CPU can perform the following steps 604 and 605 .
  • Step 603 the second CPU determines whether the FSI hard line flag is 1; if so, execute the following step 606;
  • step 606 is executed; if the FSI hard line flag is 0, it means that the second fault is After the fault has been processed, return to step 602 to wait for a new fault processing task.
  • Step 604 the second CPU clears the RAM in the MCU.
  • Step 605 is executed after this step 604 .
  • Step 605 the second CPU exits the fault handling task.
  • Step 606 the second CPU processes the second fault.
  • the second CPU obtains the second fault information based on the above-mentioned first implementation, after the second CPU completes the processing of the second fault, it is also necessary to process the FSI hard-wired flag and/or the information in the fault memory corresponding to the second fault.
  • the second fault information please refer to the introduction in FIG. 7 .
  • Step 701 the second CPU may send a second instruction to the MMIC. Accordingly, the MMIC receives the second instruction from the second CPU through the SPI.
  • the second CPU may send the second instruction to the MMIC through the SPI.
  • the second instruction is used to instruct the MMIC to clear the FSI hard wire flag and/or the second fault information.
  • the CPU 1302 can send the second instruction to the control unit 3021 in the MMIC 302 .
  • the second instruction is used to instruct the control unit 3021 to clear the second fault information and/or clear the FSI hard line flag.
  • the control unit 3021 may restore the second fault information 1 to 0, and set the FSI hard line flag to a low level (eg, 0).
  • the MMIC may clear the second fault information included in the information of the fault register and/or clear the FSI hard wire flag according to the second instruction.
  • the information of the fault register is 001001000000000000000000000
  • the second fault information is the third bit in the information of the fault register.
  • the MMIC can restore the 1 of the third bit to 0 according to the second instruction.
  • the information in the fault register is 0000010001000000000000000000
  • the second fault information is the 10th bit in the information in the fault register
  • the MMIC can restore the 1 in the 10th bit to 0 according to the second instruction.
  • the MMIC can restore the FI hard line flag to 0 according to the second instruction.
  • Step 703 the MMIC may send a third response to the second CPU.
  • the MMIC may send the third response to the second CPU through the SPI.
  • the third response includes the execution progress of the second instruction.
  • the execution process of the second instruction may be identified by 0 and 1, where 0 indicates that the second instruction has not been executed, and 1 indicates that the second instruction has been executed. It should be noted that, the execution of the second instruction may also be represented by other identifiers, and an identifier that can distinguish whether the second instruction is completed or not completed may be used, which is not limited in this application.
  • the MMIC needs to determine the process of executing the second instruction by the MMIC. Therefore, the MMIC will periodically feed back the process of executing the second instruction to the second CPU. For example, the MMIC may feed back the execution process of the second instruction to the second CPU every 10us.
  • Step 704 the second CPU determines whether the MMIC has completed the second instruction according to the received third response; if completed, executes step 705;
  • the second CPU sends the second instruction at time t1, and checks the third response at time t2, where time t1 and time t2 may be preset. That is, the CPU typically sends commands and receives responses for a fixed duration.
  • Step 705 the second CPU exits the fault handling task.
  • the execution process of each step in the first CPU is serial
  • the execution process of each step in the second CPU is serial
  • the first CPU and the second CPU are executed serially.
  • the execution process between CPUs can be serial or parallel. It should be noted that the execution process of the above steps is described for the purpose of clearly explaining the solution. According to the needs of the actual scenario, one or more of the above steps may not need to be executed, or there may be multiple steps that can be executed in combination. , subject to the specific implementation in the actual scene.
  • control apparatus includes corresponding hardware structures and/or software modules for executing each function.
  • modules and method steps of each example described in conjunction with the embodiments disclosed in the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is performed by hardware or computer software-driven hardware depends on the specific application scenarios and design constraints of the technical solution.
  • FIG. 8 is a schematic structural diagram of a possible control device provided by the present application.
  • These control apparatuses can be used to implement the functions of the control apparatuses in the above method embodiments, and thus can also achieve the beneficial effects possessed by the above method embodiments.
  • the control device may be the MCU 301 shown in FIG. 3 .
  • the control device 800 includes a first processor 801 and a second processor 802 . Further, the control device 800 may further include a first interface circuit 803 and a second interface circuit 804 . Optionally, the control device 800 may further include a first memory 805 and/or a second memory 806, the first memory 805 may be used to store instructions executed by the first processor 801 and the second processor 802; the second memory 806 may be used for The second fault information received by the control device 800 is stored.
  • the control apparatus 800 may be used to implement the functions of the control apparatus or the MCU in the method embodiments shown in FIG. 4 , FIG. 5 , FIG. 6 or the above-mentioned figures.
  • first interface circuit 803 may also be referred to as a first input/output interface 803
  • second interface circuit 804 may also be referred to as a second input/output interface 804 .
  • the introduction of the interface circuit here is to better describe the hardware structure of the product, and those skilled in the art can understand that the interface circuit may be a hardware circuit or a logic circuit that implements a corresponding channel.
  • the "interface circuit corresponding to the channel” that appears in the following can also be directly understood or replaced as "through the channel”.
  • the first processor 801 is configured to acquire the first fault information of the electromagnetic signal transceiver through the first interface circuit 803 corresponding to the first channel , the first fault information corresponds to the first fault;
  • the second processor 802 is configured to acquire the second fault information of the electromagnetic signal transceiver, and the second fault information corresponds to the second fault; wherein the second fault information comes from the electromagnetic signal transceiver , and is transmitted through the second interface circuit 804 corresponding to the second channel.
  • first processor 801 and the second processor 802 can be obtained directly by referring to the relevant descriptions in the method embodiment shown in FIG. 4 , and details are not repeated here.
  • FIG. 9 is a schematic structural diagram of a possible electromagnetic signal transceiver provided by the present application.
  • These electromagnetic signal transceivers can be used to implement the functions of the electromagnetic signal transceivers in the above method embodiments, and thus can also achieve the beneficial effects of the above method embodiments.
  • the electromagnetic signal transceiving device may be the MMIC 302 as shown in FIG. 3 .
  • the electromagnetic signal transceiver 900 includes a controller 901 . Further, a fourth interface circuit 902 and a fifth interface circuit 903 are also included. Optionally, the control device 900 may further include a memory 904, and the memory 904 may be used to store fault information. It should be noted that the instructions executed by the controller 901 are usually firmware programs, that is, the instructions executed by the controller 901 are usually solidified in the electromagnetic signal transceiving device 900 .
  • the electromagnetic signal transceiver 900 is configured to implement the functions of the electromagnetic signal transceiver module or the MMIC in the method embodiments shown in FIG. 4 , FIG. 5 , FIG. 6 or the above-mentioned method.
  • fourth interface circuit 902 may also be referred to as the fourth input/output interface 902
  • fifth interface circuit 903 may also be referred to as the fifth input/output interface 903 .
  • the explanation of the interface circuit here refers to the above.
  • memory 904 may include registers.
  • the controller 901 is used to detect the first fault, and sends the information to the control through the fourth interface circuit 902 corresponding to the first channel.
  • the device transmits the first fault information, the first fault information corresponds to the first fault;
  • the controller 901 is further configured to detect the second fault, and transmit the second fault information to the control device through the fifth interface circuit 903 corresponding to the second channel, and the first fault information is The second fault information corresponds to the second fault.
  • controller 901 can be obtained directly by referring to the relevant descriptions in the method embodiment shown in FIG. 4 , and details are not repeated here.
  • the present application further provides a signal processing device 1000 .
  • the signal processing apparatus 1000 may include at least one of a control device 800 or an electromagnetic signal transceiving device 900 .
  • a control device 800 reference may be made to the above-mentioned description in FIG. 8, and for the electromagnetic signal transceiving device 900, reference may be made to the above-mentioned description of FIG. 9.
  • FIG. 8 For the control device 800, reference may be made to the above-mentioned description in FIG. 8, and for the electromagnetic signal transceiving device 900, reference may be made to the above-mentioned description of FIG. 9.
  • the control device 800 is used to perform the functions of the above-mentioned control device
  • the electromagnetic signal transceiving device 900 is used to perform the functions of the above-mentioned electromagnetic signal transceiving device.
  • the processor in the embodiments of the present application may be a central processing unit (central processing unit, CPU), and may also be other general-purpose processors, digital signal processors (digital signal processors, DSP), application-specific integrated circuits (application specific integrated circuit, ASIC), field programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • a general-purpose processor may be a microprocessor or any conventional processor.
  • the controller may be, for example, a control unit (control unit), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device in a millimeter wave radar system, Transistor logic devices, hardware components, or any combination thereof.
  • the method steps in the embodiments of the present application may be implemented in a hardware manner, or may be implemented in a manner in which a processor executes software instructions.
  • Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (programmable ROM) , PROM), erasable programmable read-only memory (erasable PROM, EPROM), electrically erasable programmable read-only memory (electrically EPROM, EEPROM), registers, hard disks, removable hard disks, CD-ROMs or known in the art in any other form of storage medium.
  • An exemplary storage medium is coupled to the processor, such that the processor can read information from, and write information to, the storage medium.
  • the storage medium can also be an integral part of the processor.
  • the processor and storage medium may reside in an ASIC.
  • the ASIC may be located in the control device or the electromagnetic signal transceiving device.
  • the processor and the storage medium may also exist in the network device or the terminal device as discrete components.
  • a computer program product includes one or more computer programs or instructions.
  • a computer may be a general purpose computer, a special purpose computer, a computer network, network equipment, user equipment, or other programmable apparatus.
  • Computer programs or instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer program or instructions may be downloaded from a website site, computer, server or data center Transmission by wire or wireless to another website site, computer, server or data center.
  • a computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server, data center, or the like that integrates one or more available media.
  • Usable media can be magnetic media, such as floppy disks, hard disks, magnetic tapes; optical media, such as digital video discs (DVD); and semiconductor media, such as solid state drives (SSDs) ).
  • the word "exemplary” is used to mean serving as an example, illustration, or illustration. Any embodiment or design described in this application as “exemplary” should not be construed as preferred or advantageous over other embodiments or designs. Alternatively, it can be understood that the use of the word example is intended to present concepts in a specific manner, and not to limit the application.

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Abstract

一种信息传输方法、控制装置、电磁信号收发装置及信号处理设备，用于解决现有技术中例如毫米波雷达中双点故障的处理问题。该方法可应用于微处理单元MCU，MCU包括第一CPU和第二CPU，第一CPU通过第一通道获取单片微波集成电路MMIC的第一故障信息，第二CPU获取来自MMIC且经第二通道传输的第二故障信息，第一故障信息对应于第一故障，第二故障信息对应于第二故障。如此，第一CPU可对第一故障信息对应的第一故障进行及时处理，第二CPU可对第二故障信息对应的第二故障进行及时处理，从而可使得双点故障中的每个故障均被及时处理。该方案进一步可用于提升自动驾驶或高级驾驶辅助系统ADAS能力，可应用于车联网等。

Description

信息传输方法、控制装置、电磁信号收发装置及信号处理设备 技术领域
本申请涉及信息传输技术领域，尤其涉及一种信息传输方法、控制装置、电磁信号收发装置及信号处理设备。
背景技术
毫米波雷达系统由于成本较低、技术比较成熟，越来越受关注。毫米波雷达系统具有但不限于以下优势：带宽大，频域资源丰富，天线副瓣低，有利于实现成像或准成像；波长短，雷达设备体积和天线口径得以减小，重量减轻；波束窄，在相同天线尺寸下毫米波的波束要比微波的波束窄得多，雷达分辨率高；穿透强，相比于激光雷达和光学系统，更加具有穿透烟、灰尘和雾的能力，可全天候工作等。基于毫米波雷达系统的优势，毫米波雷达系统已被广泛应用于多个领域，例如车载领域，由于毫米波的波长介于1～10毫米(mm)，所对应的频率范围为30～200吉赫(GHz)，在这个频段，毫米波相关的特性非常适合应用于车载领域，通常，车载毫米波雷达系统的频率为24GHz和77GHz。
车载毫米波雷达系统中的电子电器系统中的故障处理是必不可少。电子电器系统的故障行为主要由随机硬件失效和系统性失效引起，而随机硬件失效又分为单点失效、双点失效(或称为双点故障)、三点及以上的多点失效(又称为安全失效)。其中，双点失效是指在同一任务周期内发生的两个故障；三点失效是指在同一任务周期内发生三个故障。由于三及以上的多点失效发生的几率非常小，基本可以忽略。对于双点失效，新的故障会得不到及时处理，可能会造成系统短路、或产生错误的数据等等。
发明内容
本申请提供一种信息传输方法、控制装置、电磁信号收发装置及信号处理设备，用于实现及时处理双点故障中的每个故障。
第一方面，本申请提供一种信息传输方法，该方法可应用于控制装置，该控制装置可包括第一处理器和第二处理器。该方法可包括：第一处理器通过第一通道获取电磁信号收发装置的第一故障信息，第二处理器获取来自电磁信号收发装置且经由第二通道传输的第二故障信息，其中，第一故障信息对应于第一故障，第二故障信息对应于第二故障。
基于该方案，第一处理器可通过第一通道获取到第一故障信息，第二处理器可通过第二通道获取到第二故障信息，如此，第一处理器可对第一故障信息对应的第一故障进行及时处理，第二处理器可对第二故障信息对应的第二故障进行及时处理。换言之，第二处理器处理第二故障可与第一处理器处理第一故障并行执行，从而可实现及时处理双点故障中的每个故障。
在一种可能的实现方式中，第一通道可为串行外设接口(serial peripheral interface，SPI)，和/或，第二通道可为低电压差分信号(low voltage differential signaling，LVDS)通道。
进一步，可选地，第一通道可为SPI、且第二通道可为LVDS通道。
通过复用LVDS通道发送第二故障信息的方式属于异质冗余的方式，有助于避免都使用SPI单一的通信方式而导致通信通道都失效的情况。
在一种可能的实现方式中，控制装置还可包括第一存储器，第二故障信息存储于第一存储器；第二处理器可获取来自第一存储器的第二故障信息。
示例性地，第二处理器获取来自第一存储器的第二故障信息可通过如下两种可能的实现方式。
实现方式一，第二处理器定时查询第一存储器，从第一存储器中获取第二故障信息。
实现方式二，第二处理器检测到第二故障指示(fault indication，FI)硬线标志，从第一存储器中获取第二故障信息，第二FI硬线标志用于指示第二故障。
通过上述实现方式二，第二处理器检测到第二FI硬线标志后，说明第二故障已经发生，此时，第二处理器再从第一存储器中获取第二故障信息，有助于节省第二处理器的功耗。
在一种可能的实现方式中，第二处理器响应于第一故障未处理完成、第一指令或者检测到第二FI硬线标志中的至少一个，对第二故障进行处理，其中，第一指令用于指示第二处理器处理第二故障。
例如，第二处理器确定第一故障未处理完成、且检测到第二FI硬线标志，对第二故障进行处理。
在一种可能的实现方式中，第一处理器检测到第一FI硬线标志，并向第二处理器发送第一指令，第一指令用于指示第二处理器处理第二故障，第一FI硬线标志用于指示第一故障。
通过第一处理器向第二处理器发送第一指令，可使得第二处理器可以及时处理产生的第二故障，有助于避免因第二处理器处理其它任务而导致不能及时处理第二故障，从而有助于进一步提高双点故障的处理效率。
在一种可能的实现方式中，第二处理器向电磁信号收发装置发送第二指令，第二指令用于指示电磁信号收发装置清除第二FI硬线标志和/或第二故障信息。
通过在第二处理器对第二故障处理完成后，及时对第二故障对应的第二FI硬线标志以及第二故障信息进行了清除，以便于在下一个任务周期中可以及时处理新产生的故障。
在一种可能的实现方式中，第一处理器接收来自电磁信号收发装置的第一FI硬线标志，第一FI硬线标志用于指示第一故障，当第一处理器接收到第一FI硬线标志，说明电磁信号收发装置发生了第一故障；第一处理器向电磁信号收发装置发送第一请求消息，第一请求消息用于请求第一故障信息；第一处理器通过第一通道接收来自电磁信号收发装置的第一故障信息。
第二方面，本申请提供一种信息传输方法，该方法包括电磁信号收发装置检测到第一故障，通过第一通道向控制装置传输第一故障信息，第一故障信息对应于第一故障；电磁信号收发装置检测到第二故障，通过第二通道向控制装置传输第二故障信息，第二故障信息对应于第二故障。
基于该方案，电磁信号收发装置可通过两个不同的通道(即第一通道和第二通道)向控制装置传输不同的故障信息(即第一故障信息和第二故障信息)，如此，有助于提高电磁信号收发装置向控制装置传输故障信息的及时性，从而有助于进一步提高双点故障中每个故障的处理的及时性。
在一种可能的实现方式中，第一通道可为SPI；和/或，第二通道可为LVDS通道。
进一步，可选地，第一通道可为SPI、且第二通道可为LVDS通道。
通过复用LVDS通道发送第二故障信息的方式属于异质冗余的方式，有助于避免都使 用SPI单一的通信方式而导致通信通道都失效的情况。
在一种可能的实现方式中，电磁信号收发装置可通过第二通道，向控制装置中的第一存储器传输第二故障信息。
当电磁信号收发装置发生第二故障时，可通过第二通道向第一存储器传输第二故障信息，此处，电磁信号收发装置不需要再等处理器的指令，可以直接向第一存储器传输第二故障信息，有助于提高电磁信号收发装置传输第二故障信息的效率，从而有助于提高第二故障处理的及时性。
在一种可能的实现方式中，电磁信号收发装置可向控制装置中的第二处理器发送第二FI硬线标志，第二FI硬线标志用于指示第二故障。
进一步，可选地，电磁信号收发装置检测到第二故障，可向控制装置中的第二处理器发送用于指示第二故障的第二FI硬线标志。
在一种可能的实现方式中，电磁信号收发装置可向控制装置中的第一处理器发送第一FI硬线标志，第一FI硬线标志用于指示产生第一故障。
进一步，可选地，电磁信号收发装置检测到第一故障，可向控制装置中的第一处理器发送用于指示产生第一故障第一FI硬线标志。
电磁信号收发装置检测到第一故障触发第一FI硬线标志，检测到第二故障触发第二FI硬线标志，如此，电磁信号收发装置在检测到两个故障后，均可及时通知控制装置，以便于控制装置可以及时处理故障。
在一种可能的实现方式中，电磁信号收发装置接收来自第二处理器的第二指令，并根据第二指令，清除第二FI硬线标志和/或第二故障信息。
通过电磁信号收发装置及时对第二故障对应的第二FI硬线标志和/或第二故障信息进行了清除，可以防止该对下一个任务周期中新产生的故障的影响。
在一种可能的实现方式中，电磁信号收发装置可接收来自控制装置中的第一处理器的第一请求消息，并根据第一请求消息，获得第一故障信息。示例性地，电磁信号收发装置可根据第一请求消息，查询故障寄存器，从故障寄存器中获得第一故障信息。
第三方面，本申请提供一种信息传输装置或者控制装置，该信息传输装置或者控制装置用于实现上述第一方面或第一方面中的任意一种方法，包括相应的功能模块，分别用于实现以上方法中的步骤。功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的模块。
该控制装置包括第一处理器、第二处理器、第一接口电路和第二接口电路；其中，第一处理器用于通过第一通道对应的第一接口电路获取电磁信号收发装置的第一故障信息，第一故障信息对应于第一故障；第二处理器用于获取电磁信号收发装置的第二故障信息，第二故障信息对应于第二故障；其中，第二故障信息来自电磁信号收发装置，且经由第二通道对应的第二接口电路传输。
在一种可能的实现方式中，第一通道为SPI；和/或，第二通道为LVDS通道。
在一种可能的实现方式中，控制装置还包括第一存储器，第二故障信息存储于第一存储器；第二处理器用于获取来自第一存储器的第二故障信息。
在一种可能的实现方式中，第二处理器用于定时查询第一存储器；从第一存储器中获取第二故障信息。
在一种可能的实现方式中，第二处理器用于检测到第二FI硬线标志，从第一存储器中 获取第二故障信息，第二FI硬线标志用于指示第二故障。
在一种可能的实现方式中，第二处理器还用于响应于第一故障未处理完成、第一指令、或者检测到第二FI硬线标志，处理第二故障，其中，第一指令用于指示第二处理器处理第二故障。
在一种可能的实现方式中，控制装置还包括第三接口电路；第一处理器还用于检测到第一FI硬线标志，通过第三接口电路向第二处理器发送第一指令，第一指令用于指示第二处理器处理第二故障，第一FI硬线标志用于指示第一故障。
在一种可能的实现方式中，第二处理器还用于通过第一通道对应的第一接口电路向电磁信号收发装置发送第二指令，第二指令用于指示电磁信号收发装置清除第二FI硬线标志和/或第二故障信息。
在一种可能的实现方式中，第一处理器用于通过第一FI硬线引脚接收来自电磁信号收发装置的第一FI硬线标志，第一FI硬线标志用于指示第一故障；通过第一通道对应的第一接口电路向电磁信号收发装置发送第一请求消息，第一请求消息用于请求第一故障信息。
进一步，可选地，第一处理器可用于通过第一通道对应的接口电路接收来自电磁信号收发装置的第一故障信息。
第四方面，本申请提供一种信息传输装置或者电磁信号收发装置，该信息传输装置或电磁信号收发装置用于实现上述第二方面或第二方面中的任意一种方法，包括相应的功能模块，分别用于实现以上方法中的步骤。功能可以通过硬件实现，也可以通过硬件执行相应的软件实现。硬件或软件包括一个或多个与上述功能相对应的模块。
该电磁信号收发装置包括控制器、第四接口电路和第五接口电路。其中，控制器用于检测到第一故障，通过第一通道对应的第四接口电路向控制装置传输第一故障信息，第一故障信息对应于第一故障；控制器还用于检测到第二故障，通过第二通道对应的第五接口电路向控制装置传输第二故障信息，第二故障信息对应于第二故障。
在一种可能的实现方式中，第一通道可为SPI；和/或，第二通道可为LVDS通道。
进一步，可选地，第一通道可为SPI；和/或，第二通道可为LVDS通道。
在一种可能的实现方式中，控制器用于：通过第二通道对应的第五接口电路向控制装置的第一存储器传输第二故障信息。
在一种可能的实现方式中，控制器还用于：通过第二FI硬线引脚向控制装置的第二处理器发送第二FI硬线标志，第二FI硬线标志用于指示第二故障。
进一步，可选地，控制器用于：检测到第二故障，通过第二FI硬线引脚向控制装置的第二处理器发送用于指示第二故障的第二FI硬线标志。
在一种可能的实现方式中，控制器还用于：根据来自控制装置的第二处理器的第二指令，清除第二FI硬线标志和/或第二故障信息。
进一步，可选地，控制器可用于通过第一通道对应的第四接口电路接收来自控制装置的第二处理器的第二指令。
在一种可能的实现方式中，控制器还用于：通过第一FI硬线引脚向控制装置的第一处理器发送第一FI硬线标志，第一FI硬线标志用于指示产生第一故障。
进一步，可选地，控制器用于：在检测到第一故障，通过第一FI硬线引脚向控制装置的第一处理器发送用于指示产生第一故障的第一FI硬线标志。
在一种可能的实现方式中，控制器用于：根据来自控制装置的第一处理器的第一请求 消息，获得故障寄存器中的第一故障信息。
进一步，可选地，控制器可用于通过第一通道对应的第四接口电路接收来自控制装置的第一处理器的第一请求消息。
第五方面，本申请提供一种信号处理设备，该信号处理设备包括上述第三方面或者上述第三方面任一可能的实现方式中所述的控制装置和/或上述第四方面或者上述第四方面任一可能的实现方式中所述的电磁信号收发装置。其中，控制装置可以用于执行上述第一方面或第一方面中的任意一种方法，电磁信号收发装置可以用于执行上述第二方面或第二方面中的任意一种方法。
第六方面，本申请提供一种终端设备，该终端设备可包括上述第五方面的信号处理设备。
在一种可能的实现方式中，该终端设备可以为智能运输设备(车辆或者无人机)、智能家居设备、智能制造设备或者机器人等。
该智能运输设备例如可以是自动导引运输车(automated guided vehicle，AGV)、或无人运输车。
第七方面，本申请提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机程序或指令，当计算机程序或指令被控制装置执行时，使得该控制装置执行上述第一方面或第一方面的任意可能的实现方式中的方法；或者，当计算机程序或指令被电磁信号收发装置执行时，使得该电磁信号收发装置执行上述第二方面或第二方面的任意可能的实现方式中的方法。
第八方面，本申请提供一种计算机程序产品，该计算机程序产品包括计算机程序或指令，当计算机程序或指令被控制装置执行时，使得该控制装置执行上述第一方面或第一方面的任意可能的实现方式中的方法；或者，当计算机程序或指令被电磁信号收发装置执行时，使得该电磁信号收发装置执行上述第二方面或第二方面的任意可能的实现方式中的方法。
上述第三方面可以达到的技术效果可以参照上述第一方面中有益效果的描述，上述第四方面可以达到的技术效果可以参照上述第二方面中有益效果的描述，上述第五方面至第八方面可以达到的技术效果可以参见上述第一方面和第二方面中的有益效果的描述，此处不再重复赘述。
附图说明
图1为现有技术中的一种信息传输方法流程示意图；
图2为现有技术中的另一种信息传输方法流程示意图；
图3为本申请提供的一种毫米波雷达系统的示意图；
图4为本申请提供的一种信息传输方法流程示意图；
图5为本申请提供的另一种信息传输方法流程示意图；
图6为本申请提供的又一种信息传输方法流程示意图；
图7为本申请提供的又一种信息传输方法流程示意图；
图8为本申请提供的一种控制装置的结构示意图；
图9为本申请提供的一种电磁信号收发装置的结构示意图；
图10为本申请提供的一种信号处理设备的结构示意图。
具体实施方式
下面将结合附图，对本申请实施例进行详细描述。
以下，对本申请中的部分用语进行解释说明。需要说明的是，这些解释是为了便于本领域技术人员理解，并不是对本申请所要求的保护范围构成限定。
一、上升沿和下降沿
上升沿，数字电路中，把电压的高低用逻辑电平来表示。逻辑电平包括高电平和低电平这两种。不同的元器件形成的数字电路，电压对应的逻辑电平也不同。可规定为逻辑高电平，用数字1表示；逻辑低电平，用数字0表示。数字电平从低电平(数字“0”)变为高电平(数字“1”)的那一瞬间(时刻)叫作上升沿。数字电平从高电平(数字“1”)变为低电平(数字“0”)的那一瞬间叫作下降沿。
二、随机存取存储器(random access memory，RAM)
随机存取存储器也叫主存，是与CPU直接交换数据的内部存储器。它可以随时读写(刷新时除外)，而且速度很快，通常作为操作系统或其他正在运行中的程序的临时数据存储介质。RAM工作时可以随时从任何一个指定的地址写入(存入)或读出(取出)信息。RAM通电后，随时可在任意位置单元存取数据信息，断电后内部信息也随之消失。
三、寄存器
寄存器是CPU内部用来存放数据的一些小型存储区域，用来暂时存放参与运算的数据和运算结果。也可以理解为，寄存器通常是一种时序逻辑电路，但这种时序逻辑电路只包含存储电路。寄存器的存储电路是由锁存器或触发器构成的，因为一个锁存器或触发器能存储1位二进制数，所以由N个锁存器或触发器可以构成N位寄存器。寄存器是中央处理单元内的组成部分。寄存器是有限存储容量的高速存储部件，它们可用来暂存指令、数据和位址。对寄存器中的触发器只要求它们具有置1，置0的功能即可，因而无论是用电平触发的触发器，还是用脉冲触发或边沿触发的触发器，都可以组成寄存器。
四、串行外设接口(serial peripheral interface，SPI)
串行外设接口是一种同步外设接口，它可以使单片机(或单片微波集成电路)与各种外围设备以串行方式进行通信以交换信息。外围设备包括但不限于微处理单元(microcontroller unit，MCU)等。
SPI可以在软件的控制下应用于各种系统。如一个主控制器和几个从控制器、几个从控制器相互连接构成多主机系统(分布式系统)、一个主控制器和一个或几个从I/O设备所构成的各种系统等。在一些应用场景中，可以使用一个主控制器作为主控机来控制数据，并向一个或几个从外围器件传送该数据。从控制器只有在主控制器发命令时才能接收或发送数据，其数据的传输格式是高位(MSB)在前，低位(LSB)在后。
五、硬线引脚
硬线引脚是指两个引脚之间通过硬线连接，以用于传输高低电平。
请参阅图1，为现有技术中的一种信息处理方法流程示意图。该方法中的CPU为MCU中的CPU，控制单元为MMIC中包括的控制单元。该方法包括以下步骤：
步骤101，MMIC中的控制单元检测到MMIC发生故障，向MCU发送FI硬线标志。
此处，控制单元检测到MMIC发生故障，触发FI硬线标志。
步骤102，CPU检测到FI硬线标志，通过SPI向控制单元发送指令b。其中，指令b用于指示MMIC停止收发业务数据(即停止毫米波雷达系统的正常业务数据的采集)，并丢弃本 任务周期内获得的业务数据。
步骤103，MMIC中的控制单元根据指令b，停止收发业务数据，并停止向MCU中的RAM传输业务数据，并丢弃(清除)MMIC中的RAM在本任务周期内获取到的业务数据。
步骤104，MMIC中的控制单元定时通过SPI向CPU发送指令b的执行进程。相应地，CPU接收来自控制单元的指令b的执行进程。此处，可用第一进程标志表示指令b的执行进程，第一进程标志可用0和1标识，0表示指令b未执行完成，1表示指令b已执行完成。
步骤105，CPU可根据第一进程标志，确定MMIC是否执行完成指令b；若完成，执行步骤106；若未完成，继续检测指令b的执行进程，即循环该步骤105。此处，当CPU接收到第一进程标志为0，则可确定指令b未执行完成；当CPU接收到第一进程标志为1，则可确定指令b执行完成。
步骤106，CPU清除(或称为丢弃)MCU中的RAM中本任务周期接收到的业务数据。
此处，清除MCU中的RAM中本任务周期接收到的业务数据指清空MCU中的RAM中存储的全部数据。
步骤107，CPU通过SPI向控制单元发送指令c。相应地，控制单元通过SPI接收来自CPU的指令c。其中，指令c用于指示控制单元查询故障寄存器。
步骤108，MMIC中的控制单元根据指令c，查询故障寄存器，得到故障寄存器的信息。
步骤109，MMIC中的控制单元通过SPI向CPU发送查询到的故障寄存器的信息。相应地，CPU可通过SPI接收来自控制单元的故障寄存器的信息。
步骤110，CPU根据故障寄存器的信息，识别出第一故障。例如，CPU接收到的故障寄存器的信息为0100000000000000000000000000000000，可识别出第2位为故障。
步骤111，CPU对识别出的第一故障进行处理。
通过该步骤111，CPU对该第一故障处理完成后，需要清除该第一故障对应的FI硬线标志以及该第一故障对应的故障信息。
步骤112，CPU通过SPI向控制单元发送指令d。相应地，控制单元通过SPI接收来自CPU的指令d。其中，指令d用于指示控制单元清除FI硬线标志位、以及该第一故障对应的故障信息。
步骤113，MMIC中的控制单元根据指令d，清除第一故障对应的故障信息，以及清除FI硬线标志。
步骤114，MMIC中的控制单元定时通过SPI向CPU发送响应d。相应地，CPU接收来自控制单元的响应d。此处，响应d包括指令d的执行进程，0表示指令d未执行完成，1表示指令d已执行完成。
步骤115，CPU根据接收到的响应d，确定MMIC执行完成指令d，退出故障处理任务。
基于上述图1，可实现单点故障处理。为了对双点故障进行处理，在现有技术中，CPU在处理完成第一故障后，主动查询第二个故障是否产生，并进行处理。如图2所示，为现有技术中的一种信息处理方法。该信息处理方法可以解决双点故障问题。
现有技术中，在双点故障处理中，先处理MMIC产生的第一个故障(称为第一故障)，具体的处理过程可参见前述图1的步骤101至步骤114，在上述步骤115CPU确定MMIC执行完成指令d之后，执行下述步骤201至步骤207。
步骤201，CPU通过SPI向控制单元发送指令e。相应地，控制单元通过SPI接收来自SPI的指令e。其中，指令e用于指示控制单元查询故障信息。
步骤202，MMIC中的控制单元可根据指令e，查询故障寄存器，得到故障寄存器的信息。此处，控制单元查询到故障寄存器的信息中包括两个故障的故障信息。例如，查询到的故障寄存器的信息为0100100000000000000000000000000000，表示第2位发生一个故障，第5位发生一个故障。
步骤203，MMIC中的控制单元通过SPI向CPU发送查询到的故障寄存器的信息。相应地，CPU可通过SPI接收来自控制单元的故障寄存器的信息。该步骤203可参见上述步骤109的介绍，此处不再重复赘述。
步骤204，CPU检测故障寄存器的信息中的第二故障是否为有效故障；若是，执行步骤205；若否，执行步骤206。
由于是CPU主动定时查询是否有故障，因此，CPU查询的时候MMIC可能未发生故障。因此，需要确定第二故障是否有效故障。此处，CPU需从故障寄存器的信息中识别出第二故障，例如，若查询到的故障寄存器的信息为0100000000000000000000000000000000，且可确定出第2位的故障已被处理完成，说明第二故障未发生，或者为无效故障；若查询到的故障寄存器的信息为0100100000000000000000000000000000，且可确定第2位的故障已被处理完成，说明第5位的故障为有效故障，即第二故障。
步骤205，CPU可对第二故障进行处理。
步骤206，CPU退出故障处理任务。
基于现有信息处理方法，MMIC产生故障后，会触发FI硬线标志位，并向MCU中的一个CPU发送FI硬线标志，当该CPU检测到FI硬线标志后，向MMIC发送查询故障寄存器的指令，MMIC将查询到的故障寄存器的信息发送至该CPU，该CPU对故障寄存器的信息进行识别，当识别到第一个故障后，对该第一个故障进行处理，直到该第一个故障被处理后才清除FI硬线标志。基于此，若在第一个故障处理的任务周期内MMIC又产生了一个新的故障，此时，第一个故障的FI硬线标志未被清除，该CPU无法获知新的故障，不会对新的故障进行处理，造成新的故障得不到及时处理，造成系统短路或产生错误的数据等。
鉴于上述问题，本申请提出一种信息传输方法，请参阅下述图4。该信息传输方法可使得双点故障中的每个故障尽量得到及时处理。
下面对本申请提出的信息传输方法可应用的系统架构进行介绍。
图3为本申请的一种可能的毫米波雷达系统的架构示意图。如图3所示，该毫米波雷达系统可包括微控制单元(microcontroller unit，MCU)301和单片微波集成电路(monolithic microwave integrated circuit，MMIC)302。MCU301可包括至少两个中央处理单元(central processing unit，CPU)(图3以包括CPU3011和CPU3012为例)、RAM3013、SPI模块3014和LVDS模块3015。MMIC302可包括控制单元(control unit)3021、LVDS模块3022、SPI模块3023、故障寄存器3024和故障寄存器3025等。其中，SPI模块3014与SPI模块3023对应，SPI模块3014、SPI模块3023、以及SPI模块3014和SPI模块3023间的物理连线(如电缆或PCB走线)可形成一个MCU301与MMIC302之间的一个通道，例如称为SPI；LVDS模块3015与LVDS模块3022对应，LVDS模块3015、LVDS模块3022、以及LVDS模块3015与LVDS模块3022间的物理连线(如电缆或PCB走线)也可形成一个MCU301与MMIC302之间的一个通道，例如可称为LVDS通道。其中，LVDS模块3015可以称为差分信号发送器，可用于将非平衡传输的TTL信号转换成平衡传输的LVDS信号；LVDS模块3022可称为差分信号接收器，可用于将平衡传输的LVDS信号转换为非平衡传输的TTL信号。应理解，SPI模块可以是接 口电路，或称为输入输出接口；LVDS模块可以是接口电路，或称为输入输出接口。CPU3011(或者CPU3012)与控制单元3021可通过SPI通信，RAM3013与控制单元3021可通过LVDS通道通信，例如，可通过LVDS通道向RAM3013传输MMIC302接收到的电磁波等。MCU上可还可包括多个引脚，每个引脚的功能可通过软件控制实现某一功能。例如MCU的中断引脚，该引脚可通过软件控制实现中断功能。需要说明的是，MMIC302为被动器件，需要MCU301控制其执行任务。这里需要说明的是，该架构中包含的各种元器件仅是一种示例性说明，例如CPU、故障寄存器等均可以用其他具有等同功能的元器件替代，本申请不对具体的元器件类型做具体限定。
控制单元3021，用于控制MMIC302的工作。例如可控制MMIC302进行业务数据的检测、MMIC的故障检测等。控制单元3021可产生雷达信号(即电磁波)，进而通过发射器将雷达信号发出。雷达信号由一个或多个突发(burst)包组成，每个突发包括多个啁啾信号。雷达信号发出后，经一个或多个目标反射后形成回波信号，回波信号被接收器接收。MMIC302还用于对接收器接收到的回波信号进行变换和采样等处理，并将处理后的回波信号传输至MCU301。
CPU3011和CPU3012均配置用于故障处理，例如，对MMIC302的产生的故障进行处理。
RAM3013，用于暂时存储MMIC302传输过来的数据(例如电磁波)、和/或故障信息等。
进一步，可选地，该毫米波雷达系统还可包括发射器1031和接收器1032等。其中，发射器可以由发射天线与MMIC中的发射通道构成。接收器可以由接收天线与MMIC中的接收通道构成。其中，发射天线和接收天线可以位于印刷电路板(print circuit board，PCB)上，发射通道和接收通道可以位于芯片内，即AOB(antenna on PCB)；或者，发射天线和接收天线可以位于芯片封装内，发射通道和接收通道可以位于芯片内，即AIP(antenna in package)。本申请实施例中对于组合形式不做具体限定。
上述图3所示的毫米波雷达系统可以应用于多种领域，例如：车载雷达(即把毫米波雷达系统安装在汽车上)、路边交通雷达(即把毫米波雷达系统安装在路边交通设备上)、无人机雷达(即把毫米波雷达系统安装在无人机上)等。或者，上述图3所示的毫米波雷达系统也可以应用于终端设备、或设置于终端设备的部件中；该终端设备例如可以是智能家居设备、智能制造设备、机器人，或者智能运输设备，智能运输设备例如可以是自动导引运输车(automated guided vehicle，AGV)或者无人运输车等。
当该毫米波雷达系统应用车辆上，即车载毫米波雷达，该毫米波雷达系统还可包括连接器(connector)、控制区域网络(controller area network，CAN)、电磁兼容性(electromagnetic compatibility，EMC)保护和电源管理模块(power management ICs，PMIC)。其中，连接器可用于毫米波雷达系统与整车电子电器系统连接。控制区域网络可用于整车电子电器系统交互信息，例如，通过CAN可把故障信息上报给整车电子电器系统。控制区域网络是ISO国际标准化的串行通信协议，可用于直接与外部控制端通讯。电磁兼容保护可用于电源的电磁兼容保护。电源管理模块可用于将整车输入的电源转换为3.3V及1.25V，并供给CAN、MCU和MMIC等。
车载毫米波雷达系统可以测量从毫米波雷达系统到被测物体之间的距离、角度和相对速度等。具体地，车载毫米波雷达系统可通过发射器1031向外发射毫米波，通过接收器1032接收目标反射信号，经处理后可快速准确地获取车辆车身周围的物理环境信息(如车辆与其他物体之间的相对距离、相对速度、角度、运动方向等)，然后根据所探知的物体信息 进行目标追踪和识别分类，进而结合车身动态信息进行数据融合。经合理决策后，以声、光及触觉等多种方式告知或警告驾驶员，或及时对汽车做出主动干预，从而保证驾驶过程的安全性和舒适性，减少事故发生几率。目前，车辆利用毫米波雷达系统可以实现自适应巡航控制(adaptive cruise control)，前向防撞报警(forward collision warning)，盲点检测(blind spot detection)，辅助停车(parking aid)，辅助变道(lane change assistant)，等高级驾驶辅助系统(advanced driving assistant system，ADAS)功能。
需要说明的是，本申请所描述的系统架构以及可应用场景是为了更加清楚的说明本申请的技术方案，并不构成对本申请提供的技术方案的限定，本领域普通技术人员可知，随着系统架构的演变和新业务场景的出现，本申请提供的技术方案对于类似的下述技术问题，同样适用。
对于毫米波雷达系统中的电子电器的信息传输及处理是必不可少，特别是电子电器系统的故障信息传输及处理。电子电器系统的故障行为主要由随机硬件失效和系统性失效引起，而随机硬件失效又分为单点失效、双点失效(或称为双点故障)、三点及以上的多点失效(又称为安全失效)。其中，单点失效是指在同一个任务周期发生一个故障，其中，任务周期是指从一个故障发生到该故障被处理完成的时长。双点失效是指在同一任务周期内发生的两个故障；三点失效是指在同一任务周期内发生三个故障。由于多点失效发生的几率非常小，基本可以忽略。
为了保证毫米波雷达系统的各部件的功能安全，需要及时处理电子电器系统所产生的故障。如图4所示，为本申请提供的一种信息传输方法。该方法可以应用于图3所示的毫米波雷达系统，或者，所述毫米波雷达系统中相关装置。示例性的，该方法可以应用于电磁信号收发装置以及控制装置，所述控制装置包含第一处理器和第二处理器；可选的，还可以包含至少一个存储器。所述电磁信号收发装置包含控制器；可选的，还可以包含至少一个寄存器。该方法包括以下步骤：
步骤401，电磁信号收发装置检测到第一故障，可通过第一通道向控制装置传输对应第一故障的第一故障信息。相应地，所述控制装置通过第一通道获取电磁信号收发装置的第一故障信息。
上述步骤401进一步可选的设计中，通过第一通道向控制装置的第一处理器传输所述第一故障信息。和/或，控制装置的第一处理器通过第一通道获取所述第一故障信息。
在一种可能的实现方式中，第一通道可为控制通道，例如，SPI、或者集成电路总线(inter integrated circuit，IIC)接口、或者串行通信接口(serial communication interface，SCI)，或者，所述也可以称接口对应的通道为所述通道。可选的，控制装置为微控制单元，例如MCU301；电磁信号收发装置为单片微波集成电路，例如MMIC302。
在一种可能的实现方式中，电磁信号收发装置可在检测到第一故障，向所述控制装置的第一处理器发送用于指示产生所述第一故障的第一FI硬线标志。示例性地，电磁信号收发装置可在检测到第一故障，将FI硬线标志置为高电平(例如1)，并向控制装置发送置为高电平的FI硬线标志，该置为高电平的FI硬线标志即为第一FI硬线标志。可选的，FI硬线标志被触发后用1表示。应理解，FI硬线标志也可以是上升沿或下降沿。
相应地，控制装置的第一处理器接收来自所述电磁信号收发装置的第一FI硬线标志。进一步，所述第一处理器向所述电磁信号收发装置发送第一请求消息，其中，所述第一请求消息用于请求所述第一故障信息。在一种可能的实现方式中，所述电磁信号收发装置可 根据所述第一请求消息，获得故障寄存器中的所述第一故障信息。具体地，电磁信号收发装置可根据第一请求消息，按故障寄存器的顺序，查询故障寄存器，进而得到故障寄存器的信息，故障寄存器的信息中包括第一故障信息。故障寄存器的信息可以为32位或64位，下面以故障寄存器的信息为32位为例，若未发生故障，则故障寄存器的信息为0000000000000000000000000000000000；若发生一个故障，则32位中的一位由0变为1，例如00000100000000000000000000000000；若发生两个故障，则32位中的两位由的0变为1，例如，00100100000000000000000000000000。也就是说，1表示发生故障，0表示未发生故障。
进一步，电磁信号收发装置可向控制装置发送故障寄存器的信息，该故障寄存器的信息中包括第一故障信息。相应地，控制装置可接收来自电磁信号收发装置的故障寄存器的信息。进一步，可选地，控制装置中的第一处理器可识别出故障寄存器的信息中的第一故障信息。例如，第一处理器接收的故障寄存器的信息为00000100000000000000000000000000，可识别出第6位为第一故障信息，即第一故障信息在第6位。再比如，第一处理器接收的故障寄存器的信息为00100100000000000000000000000000，第一处理器按顺序识别，识别出第3位是第一故障信息，即第一故障信息在第3位。
步骤402，电磁信号收发装置检测到第二故障，可通过第二通道向控制装置传输对应于第二故障的第二故障信息。相应地，所述控制装置通过所述第二通道获取第二故障信息。
上述步骤402进一步可选的设计中，通过第二通道向控制装置的第二处理器传输所述第二故障信息。和/或，控制装置中的第二处理器获取通过所述第二通道传输的第二故障信息。
此处，第二通道可为数据通道，例如，LVDS通道、或者移动行业处理器接口(mobile industry processor interface，MIPI)。
一种可选的设计中，第一通道为SPI，第二通道为LVDS通道。如此，当该方案应用于毫米波雷达时，可兼容现有的毫米波雷达中的SPI和LVDS通道。
在一种可能的实现方式中，第二故障信息可存储于控制装置中的第一存储器中。或者说，电磁信号收发装置通过第二通道向控制装置中的第一存储器传输第二故障信息。
如下，示例性地的示出了第二处理器获取第二故障信息的两种可能的实现方式。
实现方式一，第二处理器检测到第二FI硬线标志，第二FI硬线标志用于指示电磁信号收发装置发生第二故障。第二处理器从第一存储器中获取第二故障信息。
实现方式二，第二处理器定时查询第一存储器，从第一存储器中获取第二故障信息。例如，第二处理器可以周期性查询第一存储器，并识别第二故障信息，可能的识别方式可参见下述图5中的步骤509的相关描述。此时，不需要FI硬线标志的触发。
基于上述实现方式一或实现方式二，电磁信号收发装置检测到第二故障，可通过LVDS通道向控制装置发送故障寄存器的信息。相应地，控制装置可通过LVDS通道接收来自电磁信号收发装置的故障寄存器的信息。进一步，控制装置中的第二处理器可获取(或称为识别)故障寄存器的信息，并从故障寄存器的信息中识别出第二故障信息。
例如，第二处理器从控制装置的第一存储器中获取的故障寄存器的信息为00100100000000000000000000000000，并向第一处理器的缓存中读取到故障寄存器信息的第6位(即第一故障信息)已被第一处理器处理，第二处理器在识别故障寄存器的信息00100100000000000000000000000000时，会屏蔽第6位，即不对第6位的第一故障信息进 行识别，第二处理器识别到第3位，确定为第二故障信息。
再比如，第二处理器从控制装置的第一存储器中读取故障寄存器的信息为00000100010000000000000000000000，并向第一处理器的缓存中读取到故障寄存器信息的第6位的故障(即第一故障信息)已被第一处理器处理，第二处理器在识别故障寄存器的信息00000100010000000000000000000000时，会屏蔽第6位，即不对第6位的故障信息进行识别，会继续识别第6位以后的位，直到识别到第10位，确定为第二故障信息。
通过上述步骤401至步骤402可以看出，第二处理器处理第二故障可与第一处理器处理第一故障并行执行，从而可以尽可能的及时处理双点故障中的每个故障。而且，第一故障信息和第二故障信息是通过两个通道发送的，有助于避免都使用单一的通道而导致通信通道失效的情况。
控制装置获取到第二故障信息后，可对第二故障信息对应的第二故障进行处理，如下示例性示出了触发第二处理器处理第二故障的三种可能的方式。
方式一，第二处理器接收来自第一处理器的第一指令。
在一种可能的实现方式中，第一处理器在检测到第一FI硬线标志，还可向所述第二处理器发送第一指令，所述第一指令用于指示所述第二处理器处理所述第二故障。相应地，第二处理器可接收来自第一处理器的第一指令，响应于第一指令，处理第二故障。
应理解，控制装置中的第一处理器检测到FI硬线标志，说明电磁信号收发装置已经发生了一个故障(称为第一故障)，此时，第一处理器需要处理该第一故障。为了防止第一处理器在处理第一故障的任务周期中电磁信号收发装置产生新的故障得不到及时处理，因此，需要第二处理器启动故障处理中断任务，以及时处理电磁信号收发装置产生的新故障(称为第二故障)。基于此，第一指令可用于指示第二处理器处理第二故障。具体地，第一指令可以直接指示第二处理器处理第二故障；或者，第一指令间接的指示第二处理器处理第二故障，例如，第一指令指示出第一处理器被占用处理第一故障，或者，通知第二处理器启动故障处理任务，以便于产生第二故障时，第二处理器可以处理第二故障。
在一种可能的实现方式中，第一指令可以触发第二处理器中的一个软件标志位，第二处理器在该软件标志位对应的存储区域读取该软件标志位对应的故障处理任务。
方式二，第二处理器检测到第二FI硬线标志。
基于该方式二，第二处理器可以响应于检测到第二FI硬线标志，处理第二故障。应理解，第二处理器检测到第二FI硬线标志，说明第二故障已发生，此处可触发第二处理器处理第二故障。
方式三，第二处理器确定第一故障未处理完成。
基于该方式三，第二处理器可响应于第一故障未处理完成，处理第二故障。应理解，第一处理器未处理完成第一故障，此时，第一处理器需要处理该第一故障。为了防止第一处理器在处理第一故障的任务周期中电磁信号收发装置产生新的故障得不到及时处理，因此，需要第二处理器处理启动故障处理任务。
需要说明的是，也可以是上述三种方式的任意组合触发第二处理器处理第二故障。例如，第二处理器确定第一故障未处理完成且检测到第二FI硬线标志(即方式二和方式三的组合)，响应于第一故障未处理完成且检测到第二FI硬线标志，第二处理器处理第二故障。应理解，第二处理器检测到第二FI硬线标志，说明第二故障已发生；而且，第一处理器未处理完成第一故障，为了使得第一故障和第二故障尽可能的及时被处理，需要第二处理器 处理第二故障。
在下文的介绍中，以第一FI硬线标志为FI硬线标志为例、第二FI硬线标志为第二故障指示(fault second indication，FSI)硬线标志为例、第一存储器为MCU中的RAM为例、电磁信号收发装置为MMIC为例、控制装置以MCU为例、第一处理器为第一CPU为例、第二处理器为第二CPU为例，第一通道为SPI为例，第二通道为LVDS通道为例进行介绍。也就是说，本申请后续所描述的RAM均可以替换为第一存储器，MMIC均可以替换为电磁信号收发装置，MCU均可以替换为控制装置，第一CPU均可以替换为第一处理器，第二CPU均可以替换为第二处理器，FI硬线标志均可以替换为第一FI硬线标志，FSI硬线标志均可以替换为第二FI硬线标志，SPI均可替换为第一通道，LVDS通道均可替换为第二通道。下文仅是为了阐述方便而进行的示例性说明。
如图5所示，为本申请提供的另一种信息传输方法，该信息传输方法可应用于上述图3所示的毫米波雷达系统。该方法可包括以下步骤：
步骤501，MMIC检测到第一故障，向第一CPU发送FI硬线标志。
结合上述图3，可以是MMIC302中的控制单元3021检测到第一故障，并通过与MCU301的引脚连接的FI硬线引脚，向CPU3011发送FI硬线标志。
应理解，MMIC可基于第一CPU发送的指令a开始进行故障检测。
步骤502，MCU中的第一CPU检测到FI硬线标志，向MCU中的第二CPU发送第一指令。相应地，第二CPU接收来自第一CPU的第一指令。
此处，MCU的每个引脚均有对应的标志，可将引脚对应的标志存储在MCU的寄存器中，其中，MCU上的一个引脚与FI硬线引脚连接，在寄存器中存储有与FI硬线引脚连接的引脚的标志位(称为FI硬线标志位)，第一CPU可定时检测MCU上的寄存器中FI硬线标志位，以确定MMIC是否发生了故障。例如，若CPU检测到FI硬线标志为1，说明MMIC发生了一个故障。关于第一指令的介绍可参见上述相关内容，此处不再重复赘述。
步骤503，MCU中的第一CPU向MMIC发送第一请求消息。相应地，MMIC接收来自MCU中的第一CPU的第一请求消息。
其中，第一请求消息用于请求第一故障信息。或者第一请求消息用于请求MMIC查询故障寄存器，以获得第一故障信息。
步骤504，MMIC根据第一请求消息，查询故障寄存器。
此处，MMIC可根据第一请求消息，查询故障寄存器的信息。需要说明的是，MMIC是被动器件，仅能确定出发生了故障，不能识别出故障寄存器中哪一位有故障。
步骤505，MMIC可向第一CPU发送故障寄存器的信息。相应地，第一CPU可接收来自MMIC的故障寄存器的信息并缓存。
此处，故障寄存器的信息中包括第一故障信息。
在一种可能的实现方式中，MMIC可通过SPI向第一CPU发送故障寄存器的信息。相应地，第一CPU可通过SPI接收来自MMIC的故障寄存器的信息并缓存。
当查询到的故障寄存器的信息的数据量较大时，MMIC可能需要分多次向第一CPU发送故障寄存器的信息，关于故障寄存器的信息可参见前述相关描述，此处不再重复赘述。
步骤506，MCU中的第一CPU确定(或称为识别)故障寄存器的信息中的第一故障信息。
此处，第一CPU识别故障寄存器的信息中的第一故障信息的过程可参见上述相关描述， 此处不再重复赘述。需要说明的是，第一CPU识别到第一故障信息后，不会再继续识别后面的位，可执行下述步骤507。
步骤507，MCU中的第一CPU对第一故障进行处理。
在一种可能的实现方式中，第一CPU中部署的故障处理软件中包括故障处理策略，故障处理策略包括但不限于故障等级与处理方法的对应的关系。例如，若故障等级为一般故障，则对MMIC复位，若三次无法恢复正常，对MMIC断电；若故障等级为致命故障，则直接对MMIC断电。示例性地，第一CPU可先确定第一故障的等级，并根据第一故障的等级，对第一故障进行相应的处理。
步骤508，MMIC检测到第二故障，可通过LVDS通道向MCU发送故障寄存器的信息。相应地，MCU可通过LVDS通道接收来自MMIC的故障寄存器的信息。
此处，故障寄存器的信息可存储于MCU的RAM中，该故障寄存器的信息中包括第二故障信息。
结合上述图3，MMIC302检测到第二故障，可通过LVDS通道向MCU301中的RAM3013发送故障寄存器的信息。相应地，MCU301中的RAM3013存储有故障寄存器的信息。换言之，当MMIC302检测到第二故障，LVDS通道不再用于向MCU301中的RAM3013传输正常的业务数据，而是通过复用LVDS通道，向MCU301中的RAM3013传输故障寄存器的信息。
此处，MMIC检测到第二故障，仅能确定出发生了两个故障，不能确定出故障寄存器中哪两位有故障。例如，故障寄存器的信息为00100100000000000000000000000000，MMIC通过LVDS通道将故障寄存器的信息00100100000000000000000000000000发送给MCU的RAM中。相应地，MCU中的RAM可将00100100000000000000000000000000存储。再比如，故障寄存器的信息为00000100010000000000000000000000，MMIC通过LVDS通道将故障寄存器的信息00000100010000000000000000000000发送给MCU的RAM中。相应地，MCU中的RAM可将00000100010000000000000000000000存储。
在一种可能的实现方式中，MMIC检测到第一个故障后，一直在持续检测故障，第二个故障可能是在检测到第一个故障之后且在第一个故障的任务周期的任意时间检测的。
需要说明的是，上述步骤508可以在上述步骤501之后，下述步骤509之前的任意步骤。
步骤509，MCU中的第二CPU获取(或称为识别)故障寄存器的信息中的第二故障信息。
如下，示例性地的示出了MCU中的第二CPU获取故障寄存器的信息中的第二故障信息的两种可能的实现方式。
实现方式1，第二CPU检测到FSI硬线标志，从MCU中的RAM获取第二故障信息。
结合上述图3，CPU3011与控制单元3021通过FI硬线引脚连接，CPU3012与控制单元3021通过FSI硬线引脚连接。也就是说，在MMIC302和MCU301之间设置一个用于故障指示的FSI硬线标志。MMIC302中的控制单元3021检测到第二故障，通过与MCU301的引脚连接的FSI硬线引脚，向CPU3012发送FSI硬线标志。示例性地，MMIC中部署的固件中预先配置两个硬线标志位(即FI硬线标志位和FSI硬线标志位)，并通过软件控制FSI硬线引脚的功能、以及FI硬线引脚的功能。即，MMIC的部署的固件第一次检测到故障，触发FI硬线标志位；第二次检测到故障，触发FSI硬线标志位。
基于该实现方式1，MMIC检测到第二个故障后，触发FSI硬线标志位，例如，将FSI硬线标志位置为高电平(如1)。
此处，第二CPU会串行执行任务，检测FSI硬线标志为其中的一个任务。通常，处理FSI硬线标志中断的任务的优先级最高。例如，第二CPU需要执行任务1(即检测到FSI硬线标志)、任务2和任务3，第二CPU可按优先级顺序串行运行这三个任务，以任务1的优先级高于任务2的，任务2的优先级高于任务3的为例，第一CPU串行运行任务1、任务2和任务3，当第二CPU检测到任务1发生，则可进入任务1，即执行任务1的流程。
当MCU中的第二CPU检测到FSI硬线标志，从MCU中的RAM中读取故障寄存器的信息，并向第一CPU的缓存(cache)中读取到故障寄存器的信息中的第一故障信息，且确定第一故障已被第一CPU处理，第二CPU屏蔽该第一故障信息，并从该故障寄存器的信息中识别第二故障信息。
第二CPU从故障寄存器的信息中识别出第二故障信息的可能的实现可参见上述相关描述，此处不再重复赘述。
实现方式2，第二CPU定时查询MCU中的RAM，并从MCU中的RAM中获取第二故障信息。
基于该实现方式2，第二CPU定时从MCU中的RAM中读取故障寄存器的信息，并向第一CPU的缓存中读取到故障寄存器的信息中的第一故障信息，且确定第一故障已被第一CPU处理，第二CPU屏蔽该第一故障信息，从该故障寄存器的信息中识别出第二故障信息。
其中，第二CPU从读取到的故障寄存器的信息中识别第二故障信息的示例可参见上述实现方式1相关描述，此处不再重复赘述。
在一种可能的实现方式中，第二CPU可周期性查询MCU中的RAM，例如，每隔1ms查询一次。
步骤510，MCU中的第二CPU对第二故障进行处理。
该步骤510可参见上述步骤507，此处不再重复赘述。
通过上述步骤501至步骤510可以看出，第一CPU处理第一故障，第二CPU处理第二故障，可使得第一故障和第二故障可以得到及时处理。而且，复用LVDS通道发送故障寄存器的信息的方式属于异质冗余的方式，有助于避免都使用SPI单一的通信方式而导致通信通道都失效的情况。
在上述步骤502之后，即第二CPU接收到第一指令，响应于第一指令，可启动故障处理任务。请参阅图6，为本申请提供的另一种信息传输方法流程示意图。在该方法中，以FI硬线标志位为1表示FI硬线标志中断(即触发FI硬线标志)，以FSI硬线标志位为1表示FSI硬线标志中断(即触发FSI硬线标志)为例。
步骤601，第二CPU清除MCU中的RAM中的数据。
此处，可以是第二CPU向MCU中的RAM发送清除数据指令，MCU中的RAM根据清除数据的指令清除存储的数据。如此，可防止MCU中的RAM中原有数据干扰故障中断处理任务。
需要说明的是，第二CPU接收到第一指令后，MCU中的RAM中还未接收到来自MMIC的故障寄存器的信息。也就是说，在接收到故障寄存器的信息之前，先对MCU中的RAM中的数据进行清除，可使得MCU中的RAM接收到故障寄存器的信息后，只存储 有故障寄存器的信息。
步骤602，第二CPU确定FI硬线标志是否为1；若是，执行步骤603；若否，执行步骤604。
此处，若FI硬线标志为1，说明第一CPU未处理完第一故障，如果MMIC发生第二故障，第一CPU不能及时处理第二故障，故需要第二CPU来处理第二故障。若确定FI硬线标志为0，说明第一CPU已经处理完第一故障，此时，如果MMIC发生第二故障，可以直接由第一CPU处理第二故障，不需要第二CPU来处理第二故障，此处，第二CPU可执行后续步骤604和步骤605。
步骤603，第二CPU确定FSI硬线标志是否为1；若是，执行下述步骤606；若否，返回执行步骤602。
此处，若FSI硬线标志为1，说明第二CPU未处理完第二故障，因此第二CPU需要对第二故障进行处理，即执行步骤606；若FSI硬线标志为0，说明第二故障已被处理完成，返回步骤602重新等待新的故障处理任务。
步骤604，第二CPU清除MCU中的RAM。该步骤604之后执行步骤605。
步骤605，第二CPU退出故障处理任务。
步骤606，第二CPU对第二故障进行处理。
若第二CPU是基于上述实现方式一获取的第二故障信息，在第二CPU对第二故障处理完成后，还需要对第二故障对应的FSI硬线标志和/或故障存储器的信息中的第二故障信息进行清除，可参见图7的介绍。
步骤701，第二CPU可向MMIC发送第二指令。相应地，MMIC通过SPI接收来自第二CPU的第二指令。
在一种可能的实现方式中，第二CPU可通过SPI向MMIC发送第二指令。
此处，第二指令用于指示MMIC清除FSI硬线标志和/或第二故障信息。结合上述图3，CPU1302可向MMIC302中的控制单元3021发送第二指令。其中，第二指令用于指示控制单元3021清除第二故障信息和/或清除FSI硬线标志。示例性地，控制单元3021可将第二故障信息1复原为0，将FSI硬线标志位置为低电平(如0)。
步骤702，MMIC可根据第二指令，清除故障寄存器的信息包括的第二故障信息和/或清除FSI硬线标志。
结合上述图5中的步骤509，例如，故障寄存器的信息为00100100000000000000000000000000，第二故障信息为故障寄存器的信息中的第3位，MMIC可根据第二指令，将第3位的1复原为0。再比如，故障寄存器的信息为00000100010000000000000000000000，第二故障信息为故障寄存器的信息中的第10位，MMIC可根据第二指令，将第10位的1复原为0。
此处，若FI硬线标志为1表示中断，MMIC可根据第二指令，将FI硬线标志恢复为0。
步骤703，MMIC可向第二CPU发送第三响应。
在一种可能的实现方式中，MMIC可通过SPI向第二CPU发送第三响应。
此处，第三响应包括第二指令的执行进程。示例性地，第二指令的执行进程可用0和1标识，0表示第二指令未执行完成，1表示第二指令已执行完成。需要说明的是，第二指令的执行也可以用其它标识表示，可以区分出第二指令完成或未完成的标识均可以，本申请对此不做限定。
应理解，第二CPU需要确定MMIC执行第二指令的进程，因此，MMIC会定时向第二 CPU反馈第二指令执行的进程。例如，MMIC可每隔10us向第二CPU反馈一次第二指令的执行进程。
步骤704，第二CPU根据接收到的第三响应，确定MMIC是否执行完成第二指令；若完成，执行步骤705；若未完成，继续检测第二指令的执行进行，即循环指令该步骤704。
示例性地，第二CPU在t1时刻发送第二指令，在第t2时刻查看第三响应，t1时刻和t2时刻可以是预先设置的。也就是说，CPU通常按固定时长发送指令和接收响应。
步骤705，第二CPU退出故障处理任务。
通过上述步骤701至步骤705可以看出，在第二CPU对第二故障处理完成后，及时对第二故障对应的FSI硬线标志和/或第二故障信息进行了清除，以便于在下一个任务周期中可以及时处理新产生的故障。
需要说明的是，上述实施例中，第一CPU中的各步骤之间的执行过程是串行的，第二CPU中的各步骤之间的执行过程是串行的，第一CPU与第二CPU之间执行过程可以是串行的，也可以是并行的。需要说明的是，上述各个步骤的执行过程是为了清楚解释方案而阐述的，根据实际场景的需要，上述各个步骤中的某一个或者多个步骤可能无需执行，或者可能存在多个步骤可以合并执行，以实际场景中的具体执行为准。
可以理解的是，为了实现上述实施例中功能，控制装置包括了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本申请中所公开的实施例描述的各示例的模块及方法步骤，本申请能够以硬件或硬件和计算机软件相结合的形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用场景和设计约束条件。
基于上述内容和相同构思，图8为本申请的提供的可能的控制装置的结构示意图。这些控制装置可以用于实现上述方法实施例中控制装置的功能，因此也能实现上述方法实施例所具备的有益效果。在本申请中，该控制装置可以是如图3所示MCU301。
如图8所示，该控制装置800包括第一处理器801、第二处理器802。进一步，所述控制装置800还可以包括第一接口电路803和第二接口电路804。可选地，控制装置800还可包括第一存储器805和/或第二存储器806，第一存储器805可用于存储第一处理器801和第二处理器802执行的指令；第二存储器806可用于存储控制装置800接收到的第二故障信息。控制装置800可用于实现上述图4、图5、图6或图中所示的方法实施例中控制装置或者MCU的功能。需要说明的是，第一接口电路803也可以称为第一输入输出接口803，第二接口电路804也可以称为第二输入输出接口804。这里的接口电路的引入是为了更好的阐述产品的硬件结构，本领域技术人员可以理解，接口电路可以为实现相应通道的硬件电路或者逻辑电路。下文中所出现的“通过通道对应的接口电路”也可以直接理解或替换为“通过通道”。
当控制装置800用于实现图4所示的方法实施例的控制装置的功能时：第一处理器801用于通过第一通道对应的第一接口电路803获取电磁信号收发装置的第一故障信息，第一故障信息对应于第一故障；第二处理器802用于获取电磁信号收发装置的第二故障信息，第二故障信息对应于第二故障；其中，第二故障信息来自电磁信号收发装置，且经由第二通道对应的第二接口电路804传输。
有关上述第一处理器801和第二处理器802更详细的描述可以参考图4所示的方法实施例中相关描述直接得到，此处不再一一赘述。
基于上述内容和相同构思，图9为本申请的提供的可能的电磁信号收发装置的结构示意图。这些电磁信号收发装置可以用于实现上述方法实施例中电磁信号收发装置的功能，因此也能实现上述方法实施例所具备的有益效果。在本申请中，该电磁信号收发装置可以是如图3所示MMIC302。
如图9所示，该电磁信号收发装置900包括控制器901。进一步，还包括第四接口电路902和第五接口电路903。可选地，控制装置900还可包括存储器904，存储器904可用于存储故障信息。需要说明的是，控制器901执行的指令通常是固件(firmware)程序，即控制器901执行的指令通常固化于电磁信号收发装置900中。电磁信号收发装置900用于实现上述图4、图5、图6或图中所示的方法实施例中电磁信号收发模块或者MMIC的功能。需要说明的是，第四接口电路902也可以称为第四输入输出接口902，第五接口电路903也可以称为第五输入输出接口903。这里接口电路的解释参考上文。进一步，可选地，存储器904可包括寄存器。
当电磁信号收发装置900用于实现图4所示的方法实施例的电磁信号收发装置的功能时：控制器901用于检测到第一故障，通过第一通道对应的第四接口电路902向控制装置传输第一故障信息，第一故障信息对应于第一故障；控制器901还用于检测到第二故障，通过第二通道对应的第五接口电路903向控制装置传输第二故障信息，第二故障信息对应于第二故障。
有关上述控制器901更详细的描述可以参考图4所示的方法实施例中相关描述直接得到，此处不再一一赘述。
基于上述内容和相同构思，如图10所示，本申请还提供一种信号处理设备1000。该信号处理设备1000包括可包括控制装置800或电磁信号收发装置900中的至少一个。控制装置800可参见上述图8相关描述，电磁信号收发装置900可参见上述图9相关描述。
当该信号处理设备1000用于实现图4所示的方法时，控制装置800用于执行上述控制装置的功能，电磁信号收发装置900用于执行上述电磁信号收发装置的功能。
可以理解的是，本申请的实施例中的处理器可以是中央处理单元(central processing unit，CPU)，还可以是其它通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field programmable gate array，FPGA)或者其它可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。通用处理器可以是微处理器，也可以是任何常规的处理器。控制器例如可以是毫米波雷达系统中的控制单元(control unit)、专用集成电路(application specific integrated circuits，ASIC)，现场可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、晶体管逻辑器件、硬件部件或者其任意组合。
本申请的实施例中的方法步骤可以通过硬件的方式来实现，也可以由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器(random access memory，RAM)、闪存、只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC 中。另外，该ASIC可以位于控制装置或电磁信号收发装置中。当然，处理器和存储介质也可以作为分立组件存在于网络设备或终端设备中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机程序或指令。在计算机上加载和执行计算机程序或指令时，全部或部分地执行本申请实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、网络设备、用户设备或者其它可编程装置。计算机程序或指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机程序或指令可以从一个网站站点、计算机、服务器或数据中心通过有线或无线方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是集成一个或多个可用介质的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，例如，软盘、硬盘、磁带；也可以是光介质，例如，数字视频光盘(digital video disc，DVD)；还可以是半导体介质，例如，固态硬盘(solid state drive，SSD)。
在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，不同的实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
本申请中，“示例的”一词用于表示作例子、例证或说明。本申请中被描述为“示例”的任何实施例或设计方案不应被解释为比其它实施例或设计方案更优选或更具优势。或者可理解为，使用示例的一词旨在以具体方式呈现概念，并不对本申请构成限定。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定。术语“第一”、“第二”等类似表述，是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。此外，术语“包括”和“具有”以及他们的任何变形，意图在于覆盖不排他的包含，例如，包含了一系列步骤或模块。方法、系统、产品或设备不必限于清楚地列出的那些步骤或模块，而是可包括没有清楚地列出的或对于这些过程、方法、产品或设备固有的其它步骤或模块。
显然，本领域的技术人员可以对本申请进行各种改动和变型而不脱离本申请的保护范围。这样，倘若本申请的这些修改和变型属于本申请权利要求及其等同技术的范围之内，则本申请也意图包含这些改动和变型在内。

Claims (34)

  1. 一种信息传输方法，其特征在于，应用于控制装置，所述控制装置包括第一处理器和第二处理器；所述方法包括：
    所述第一处理器通过第一通道获取电磁信号收发装置的第一故障信息，所述第一故障信息对应于第一故障；
    所述第二处理器获取所述电磁信号收发装置的第二故障信息，所述第二故障信息对应于第二故障；
    其中，所述第二故障信息来自所述电磁信号收发装置，且经由第二通道传输。
  2. 如权利要求1所述的方法，其特征在于，所述第一通道为串行外设接口SPI；和/或，所述第二通道为低电压差分信号LVDS通道。
  3. 如权利要求1或2所述的方法，其特征在于，所述控制装置还包括第一存储器，所述第二故障信息存储于所述第一存储器；
    所述第二处理器获取所述电磁信号收发装置的第二故障信息，包括：
    所述第二处理器获取来自所述第一存储器的所述第二故障信息。
  4. 如权利要求3所述的方法，其特征在于，所述第二处理器获取来自所述第一存储器的所述第二故障信息，包括：
    所述第二处理器定时查询所述第一存储器；
    所述第二处理器从所述第一存储器中获取所述第二故障信息。
  5. 如权利要求3所述的方法，其特征在于，所述第二处理器获取来自所述第一存储器的所述第二故障信息，包括：
    所述第二处理器检测到第二FI硬线标志，从所述第一存储器中获取所述第二故障信息，所述第二FI硬线标志用于指示所述第二故障。
  6. 如权利要求5所述的方法，其特征在于，所述方法还包括：
    所述第二处理器响应于所述第一故障未处理完成、第一指令或者检测到所述第二FI硬线标志中的至少一个，处理所述第二故障，所述第一指令用于指示所述第二处理器处理所述第二故障。
  7. 如权利要求1至6任一项所述的方法，其特征在于，所述方法还包括：
    所述第一处理器检测到第一FI硬线标志，所述第一FI硬线标志用于指示所述第一故障；
    所述第一处理器向所述第二处理器发送第一指令，所述第一指令用于指示所述第二处理器处理所述第二故障。
  8. 如权利要求1至7任一项所述的方法，其特征在于，所述方法还包括：
    所述第二处理器向所述电磁信号收发装置发送第二指令，所述第二指令用于指示所述电磁信号收发装置清除所述第二FI硬线标志和/或所述第二故障信息。
  9. 如权利要求1至8任一项所述的方法，其特征在于，所述第一处理器通过第一通道获取电磁信号收发装置的第一故障信息，包括：
    所述第一处理器接收来自所述电磁信号收发装置的第一FI硬线标志，所述第一FI硬线标志用于指示所述第一故障；
    所述第一处理器向所述电磁信号收发装置发送第一请求消息，所述第一请求消息用于 请求所述第一故障信息；
    所述第一处理器通过所述第一通道接收来自所述电磁信号收发装置的所述第一故障信息。
  10. 一种信息传输方法，其特征在于，包括：
    电磁信号收发装置检测到第一故障，通过第一通道向控制装置传输第一故障信息，所述第一故障信息对应于所述第一故障；
    所述电磁信号收发装置检测到第二故障，通过第二通道向所述控制装置传输第二故障信息，所述第二故障信息对应于所述第二故障。
  11. 如权利要求10所述的方法，其特征在于，所述第一通道为串行外设接口SPI；和/或所述第二通道为低电压差分信号LVDS通道。
  12. 如权利要求10或11所述的方法，其特征在于，所述电磁信号收发装置通过第二通道向所述控制装置传输第二故障信息，包括：
    所述电磁信号收发装置通过所述第二通道，向所述控制装置的第一存储器传输所述第二故障信息。
  13. 如权利要求10至12任一项所述的方法，其特征在于，所述方法还包括：
    所述电磁信号收发装置向所述控制装置中的第二处理器发送第二FI硬线标志，所述第二FI硬线标志用于指示所述第二故障。
  14. 如权利要求13所述的方法，其特征在于，所述方法还包括：
    所述电磁信号收发装置接收来自所述第二处理器的第二指令；
    所述电磁信号收发装置根据所述第二指令，清除所述第二FI硬线标志和/或所述第二故障信息。
  15. 如权利要求10至14任一项所述的方法，其特征在于，所述方法还包括：
    所述电磁信号收发装置向所述控制装置的第一处理器发送第一FI硬线标志，所述第一FI硬线标志用于指示产生所述第一故障。
  16. 如权利要求10至15任一项所述的方法，其特征在于，所述电磁信号收发装置检测到第一故障，通过第一通道向控制装置传输第一故障信息，包括：
    所述电磁信号收发装置接收来自所述第一处理器的第一请求消息；
    所述电磁信号收发装置根据所述第一请求消息，获得故障寄存器中的所述第一故障信息。
  17. 一种控制装置，其特征在于，包括第一处理器、第二处理器、第一接口电路和第二接口电路；
    所述第一处理器，用于通过所述第一通道对应的第一接口电路获取电磁信号收发装置的第一故障信息，所述第一故障信息对应于第一故障；
    所述第二处理器，用于获取所述电磁信号收发装置的第二故障信息，所述第二故障信息对应于第二故障；
    其中，所述第二故障信息来自所述电磁信号收发装置，且经由所述第二通道对应的第二接口电路传输。
  18. 如权利要求17所述的装置，其特征在于，所述第一通道为串行外设接口SPI；和/或，所述第二通道为低电压差分信号LVDS通道。
  19. 如权利要求17或18所述的装置，其特征在于，所述控制装置还包括第一存储器， 所述第二故障信息存储于所述第一存储器；
    所述第二处理器，用于：
    获取来自所述第一存储器的所述第二故障信息。
  20. 如权利要求19所述的装置，其特征在于，所述第二处理器，用于：
    定时查询所述第一存储器；
    从所述第一存储器中获取所述第二故障信息。
  21. 如权利要求19所述的装置，其特征在于，所述第二处理器，用于：
    检测到第二FI硬线标志，从所述第一存储器中获取所述第二故障信息，所述第二FI硬线标志用于指示所述第二故障。
  22. 如权利要求21所述的装置，其特征在于，所述第二处理器，还用于：
    响应于所述第一故障未处理完成、第一指令或者检测到所述第二FI硬线标志中的至少一个，处理所述第二故障，所述第一指令用于指示所述第二处理器处理所述第二故障。
  23. 如权利要求17至22任一项所述的装置，其特征在于，所述控制装置还包括第三接口电路；
    所述第一处理器，还用于：
    检测到第一FI硬线标志，通过所述第三接口电路向所述第二处理器发送第一指令，所述第一指令用于指示所述第二处理器处理所述第二故障，所述第一FI硬线标志用于指示所述第一故障。
  24. 如权利要求17至23任一项所述的装置，其特征在于，所述第二处理器，还用于：
    通过所述第一通道对应的第一接口电路向所述电磁信号收发装置发送第二指令，所述第二指令用于指示所述电磁信号收发装置清除所述第二FI硬线标志和/或所述第二故障信息。
  25. 如权利要求17至24任一项所述的装置，其特征在于，所述第一处理器，用于：
    通过第一FI硬线引脚接收来自所述电磁信号收发装置的第一FI硬线标志，所述第一FI硬线标志用于指示所述第一故障；
    通过所述第一通道对应的第一接口电路向所述电磁信号收发装置发送第一请求消息，所述第一请求消息用于请求第一故障信息。
  26. 一种电磁信号收发装置，其特征在于，包括控制器、第四接口电路和第五接口电路；
    所述控制器，用于检测到第一故障，通过第一通道对应的第四接口电路向控制装置传输第一故障信息，所述第一故障信息对应于所述第一故障；
    所述控制器，还用于检测到第二故障，通过第二通道对应的第五接口电路向所述控制装置传输第二故障信息，所述第二故障信息对应于所述第二故障。
  27. 如权利要求26所述的装置，其特征在于，所述第一通道为串行外设接口SPI；和/或所述第二通道为低电压差分信号LVDS通道。
  28. 如权利要求26或27所述的装置，其特征在于，所述控制器，用于：
    通过所述第二通道对应的第五接口电路向所述控制装置的第一存储器传输所述第二故障信息。
  29. 如权利要求26至28任一项所述的装置，其特征在于，所述控制器，还用于：
    通过第二FI硬线引脚向所述控制装置的第二处理器发送第二FI硬线标志，所述第二 FI硬线标志用于指示所述第二故障。
  30. 如权利要求29所述的装置，其特征在于，所述控制器，还用于：
    根据来自所述控制装置的第二处理器的第二指令，清除所述第二FI硬线标志和/或所述第二故障信息。
  31. 如权利要求26至30任一项所述的装置，其特征在于，所述控制器，还用于：
    通过第一FI硬线引脚向所述控制装置的第一处理器发送第一FI硬线标志，所述第一FI硬线标志用于指示产生所述第一故障。
  32. 如权利要求26至31任一项所述的装置，其特征在于，所述控制器，用于：
    根据来自所述控制装置的第一处理器的第一请求消息，获得故障寄存器中的所述第一故障信息。
  33. 一种信号处理设备，其特征在于，包括权利要求17至25任一项的控制装置，和/或，权利要求26至32任一项的电磁信号收发装置。
  34. 如权利要求33所述的设备，其特征在于，所述设备为毫米波雷达。
PCT/CN2020/125435 2020-10-30 2020-10-30 信息传输方法、控制装置、电磁信号收发装置及信号处理设备 WO2022088080A1 (zh)

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