WO2022082735A1 - 显示基板及其驱动方法、显示装置 - Google Patents

显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2022082735A1
WO2022082735A1 PCT/CN2020/123261 CN2020123261W WO2022082735A1 WO 2022082735 A1 WO2022082735 A1 WO 2022082735A1 CN 2020123261 W CN2020123261 W CN 2020123261W WO 2022082735 A1 WO2022082735 A1 WO 2022082735A1
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Prior art keywords
shift register
register unit
signal
shift
gate line
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PCT/CN2020/123261
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English (en)
French (fr)
Inventor
丁腾飞
王洋
王世君
冯博
樊君
穆文凯
刘屹
杨心澜
田丽
Original Assignee
京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方显示技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to PCT/CN2020/123261 priority Critical patent/WO2022082735A1/zh
Priority to US17/429,919 priority patent/US11804196B2/en
Priority to CN202080002442.3A priority patent/CN114667556A/zh
Publication of WO2022082735A1 publication Critical patent/WO2022082735A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0404—Matrix technologies
    • G09G2300/0408—Integration of the drivers onto the display substrate
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202—Addressing of scan or signal lines
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/021—Power management, e.g. power saving
    • G09G2330/023—Power management, e.g. power saving using energy recovery or conservation

Definitions

  • the present application relates to the field of display technology, and in particular, to a display substrate, a driving method thereof, and a display device.
  • LCD Liquid crystal display
  • the related art proposes an LCD device with a dual gate design.
  • the dual gate LCD device includes: a plurality of gate lines, a plurality of data lines, and a plurality of pixels arranged in an array.
  • multiple pixels located in the same row can be divided into multiple groups, each group can include two adjacent pixels with different colors, and the two pixels can be connected to different gate lines respectively, and can be connected to the same data line. connect. That is, each row of pixels may be connected to two gate lines, respectively.
  • the current scanning driving mode of the dual-gate LCD device is progressive scanning, that is, a plurality of gate lines are turned on in sequence according to the arrangement sequence, so as to drive the pixels in each row to emit light in sequence.
  • the present application provides a display substrate, a driving method thereof, and a display device, and the technical solutions are as follows:
  • a display substrate comprising: a base substrate;
  • two pixels, and the two pixels are connected to different gate lines and the same data line;
  • each of the shift circuits is respectively connected to an on-signal terminal and at least two gate lines of the plurality of gate lines, each of the shift circuits for providing a gate drive signal to each of the connected gate lines in response to the turn-on signal provided by the turn-on signal terminal;
  • the pixels connected to the same data line have the same color.
  • each of the shift circuits includes: at least four shift register units, each of the shift register units is connected to a gate line, and at least four shift registers in each of the shift circuits
  • the register unit can be divided into two shift register groups;
  • each of the shift register groups includes a plurality of the shift register units that are cascaded, and one of the shift register units in each of the shift register groups is connected to the enable signal terminal.
  • each of the shift register groups includes a plurality of shift register subgroups, each of the shift register subgroups includes two adjacent and cascaded shift register units, and each of the shift register subgroups includes two adjacent shift register units.
  • Two of the shift register units in the shift register subgroup are respectively connected to the adjacent i-th gate line and the i+s-th gate line, where i is a positive integer, and s is 1 or 2.
  • the number d of clock signal terminals connected to the plurality of shift circuits in the display substrate is an integer multiple of 4.
  • the number d of clock signal terminals connected to the plurality of shift circuits in the display substrate is 16.
  • the plurality of shift circuits include: a first shift circuit, a second shift circuit, a third shift circuit and a fourth shift circuit, a total of four shift circuits;
  • first shift circuit and the second shift circuit are located on one side of the multiple rows of pixels
  • third shift circuit and the fourth shift circuit are located on the other side of the multiple rows of pixels. side.
  • the 2n-1th shift register subset located on one side of the multi-row pixels belongs to the first shift circuit
  • the 2n-th subgroup located on one side of the multi-row pixels belongs to the first shift circuit.
  • the shift register subgroup belongs to the second shift circuit, and n is a positive integer;
  • the 2n-1th said shift register subgroup located on the other side of the multi-row pixels belongs to the third shift circuit, and the 2n-th said shift register located on the other side of the multi-row pixels A subgroup of registers belongs to the fourth shift circuit.
  • the 4n-3th shift register subgroup located on one side of the multi-row pixels belongs to a shift register group in the first shift circuit, and the 4n-3th shift register subgroup located on one side of the multi-row pixels
  • the 4n-1th shift register subgroup belongs to another shift register group in the first shift circuit
  • the 4n-2th shift register subgroup located on one side of the multi-line pixels belongs to one shift register group in the second shift circuit; the 4n-th shift register group located on one side of the multi-line pixels The bit register subgroup belongs to another shift register group in the second shift circuit;
  • the 4n-3th shift register subgroup located on the other side of the multi-line pixels belongs to one shift register group in the third shift circuit, and the 4n-th shift register group located on the other side of the multi-line pixels - 1 shift register subgroup belongs to another shift register group in the third shift circuit;
  • the 4n-2th shift register subgroup located on the zero side of the multi-line pixels belongs to one shift register group in the fourth shift circuit; the 4n-th shift register subgroup located on the other side of the multi-line pixels
  • the shift register subsets belong to another shift register group in the fourth shift circuit.
  • s is 2, and the shift register unit connected to the ith gate line is the ith shift register unit;
  • first shift register unit and the third shift register unit are cascaded with each other, and the first shift register unit is used to provide a carry signal to the third shift register unit;
  • the third shift register unit is used to provide a reset signal to the first shift register unit;
  • the third shift register unit is also cascaded with the 1+d-th shift register unit, and the third shift register unit is used to provide the 1+d-th shift register unit a carry signal; the 1st+d shift register unit is used to provide a reset signal to the 3rd shift register unit;
  • the fifth shift register unit and the seventh shift register unit are cascaded with each other, and the fifth shift register unit is used to provide a carry signal to the seventh shift register unit; the seventh shift register unit each of the shift register units is used to provide a reset signal to the fifth of the shift register units;
  • the seventh shift register unit is also cascaded with the fifth+dth shift register unit, and the seventh shift register unit is used to provide the fifth+dth shift register unit a carry signal; the 5th+d shift register unit is used to provide a reset signal to the 7th shift register unit;
  • the ninth shift register unit and the eleventh shift register unit are cascaded with each other, and the ninth shift register unit is used to provide a carry signal to the eleventh shift register unit; the eleventh shift register unit the shift register units are used to provide a reset signal to the ninth shift register unit;
  • the 11th shift register unit is also cascaded with the 9+dth shift register unit, and the 11th shift register unit is used to provide the 9+dth shift register unit a carry signal; the 9th+d shift register unit is used to provide a reset signal to the 11th shift register unit;
  • the 13th said shift register unit and the 15th said shift register unit are cascaded with each other, and the 13th said shift register unit is used to provide a carry signal to the 15th said shift register unit; each of the shift register units is used to provide a reset signal to the thirteenth of the shift register units;
  • the 15th shift register unit is also cascaded with the 13th+dth shift register unit, and the 15th shift register unit is used to provide the 13th+dth shift register unit a carry signal; the 13th+d shift register unit is used to provide a reset signal to the 15th shift register unit;
  • the second shift register unit and the fourth shift register unit are cascaded with each other, and the second shift register unit is used to provide a carry signal to the fourth shift register unit; the fourth shift register unit one of the shift register units is used to provide a reset signal to the second of the shift register units;
  • the fourth shift register unit is also cascaded with the 2+dth shift register unit, and the fourth shift register unit is used to provide the 2+dth shift register unit a carry signal; the 2+d shift register unit is used to provide a reset signal to the 4th shift register unit;
  • the sixth shift register unit and the eighth shift register unit are cascaded with each other, and the sixth shift register unit is used to provide a carry signal to the eighth shift register unit; each of the shift register units is used to provide a reset signal to the sixth of the shift register units;
  • the 8th shift register unit is also cascaded with the 6+dth shift register unit, and the 8th shift register unit is used to provide the 6+dth shift register unit a carry signal; the 6th+d shift register unit is used to provide a reset signal to the 8th shift register unit;
  • the tenth shift register unit and the twelfth shift register unit are cascaded with each other, and the tenth shift register unit is used to provide a carry signal to the twelfth shift register unit; the twelfth shift register unit the shift register units are used for providing a reset signal to the tenth shift register unit;
  • the 12th shift register unit is also cascaded with the 10+dth shift register unit, and the 12th shift register unit is used to provide the 10+dth shift register unit a carry signal; the 10+d shift register unit is used to provide a reset signal to the 12th shift register unit;
  • the 14th said shift register unit and the 16th said shift register unit are cascaded with each other, and the 14th said shift register unit is used to provide a carry signal to the 16th said shift register unit; each of the shift register units is used to provide a reset signal to the 14th of the shift register units;
  • the 16th shift register unit is also cascaded with the 14+dth shift register unit, and the 16th shift register unit is used to provide the 14+dth shift register unit Carry signal; the 14th+dth shift register unit is used to provide a reset signal to the 16th said shift register unit.
  • s is 1, and the shift register unit connected to the ith gate line is the ith shift register unit;
  • first shift register unit and the second shift register unit are cascaded with each other, and the first shift register unit is used to provide a carry signal to the second shift register unit;
  • the second shift register unit is used to provide a reset signal to the first shift register unit;
  • the second shift register unit is also cascaded with the 1+d-th shift register unit, and the second shift register unit is used to provide the 1+d-th shift register unit a carry signal; the 1st+d shift register unit is used to provide a reset signal to the 2nd said shift register unit;
  • the third shift register unit and the fourth shift register unit are cascaded with each other, and the third shift register unit is used to provide a carry signal to the fourth shift register unit; the fourth shift register unit each of the shift register units is used to provide a reset signal to the third of the shift register units;
  • the fourth shift register unit is also cascaded with the third+dth shift register unit, and the fourth shift register unit is used to provide the third+dth shift register unit a carry signal; the 3rd+d shift register unit is used to provide a reset signal to the 4th shift register unit;
  • the fifth shift register unit and the sixth shift register unit are cascaded with each other, and the fifth shift register unit is used to provide a carry signal to the sixth shift register unit; the sixth shift register unit each of the shift register units is used to provide a reset signal to the fifth of the shift register units;
  • the sixth shift register unit is also cascaded with the fifth+dth shift register unit, and the sixth shift register unit is used to provide the fifth+dth shift register unit a carry signal; the 5th+d shift register unit is used to provide a reset signal to the 6th shift register unit;
  • the seventh shift register unit and the eighth shift register unit are cascaded with each other, and the seventh shift register unit is used to provide a carry signal to the eighth shift register unit; each of the shift register units is used to provide a reset signal to the seventh of the shift register units;
  • the 8th shift register unit is also cascaded with the 7th+dth shift register unit, and the 8th shift register unit is used to provide the 7th+dth shift register unit a carry signal; the 7th+d shift register unit is used to provide a reset signal to the 8th shift register unit;
  • the ninth shift register unit and the tenth shift register unit are cascaded with each other, and the ninth shift register unit is used to provide a carry signal to the tenth shift register unit; the tenth shift register unit the shift register units are used to provide a reset signal to the ninth shift register unit;
  • the tenth shift register unit is also cascaded with the 9+dth shift register unit, and the tenth shift register unit is used to provide the 9+dth shift register unit a carry signal; the 9th+d shift register unit is used to provide a reset signal to the 10th shift register unit;
  • the eleventh shift register unit and the twelfth shift register unit are cascaded with each other, and the eleventh shift register unit is used to provide a carry signal to the twelfth shift register unit; the twelfth shift register unit the shift register units are used to provide a reset signal to the eleventh shift register unit;
  • the twelfth shift register unit is also cascaded with the 11+dth shift register unit, and the twelfth shift register unit is used to provide the 11+dth shift register unit a carry signal; the 11+d shift register unit is used to provide a reset signal to the 12th shift register unit;
  • the 13th said shift register unit and the 14th said shift register unit are cascaded with each other, and the 13th said shift register unit is used to provide a carry signal to the 14th said shift register unit; each of the shift register units is used to provide a reset signal to the thirteenth of the shift register units;
  • the 14th shift register unit is also cascaded with the 13+dth shift register unit, and the 14th shift register unit is used to provide the 13+dth shift register unit a carry signal; the 13th+d shift register unit is used to provide a reset signal to the 14th shift register unit;
  • the 15th said shift register unit and the 16th said shift register unit are cascaded with each other, and the 15th said shift register unit is used to provide a carry signal to the 16th said shift register unit; the shift register units are used to provide a reset signal to the fifteenth shift register unit;
  • the 16th shift register unit is also cascaded with the 15th+dth shift register unit, and the 16th shift register unit is used to provide the 15th+dth shift register unit Carry signal; the 15th+dth shift register unit is used to provide a reset signal to the 16th said shift register unit.
  • the display substrate includes a total of four turn-on signal terminals: a first turn-on signal terminal, a second turn-on signal terminal, a third turn-on signal terminal and a fourth turn-on signal terminal;
  • the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup.
  • the bit register unit is connected to the first open signal terminal;
  • the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup.
  • the bit register unit is connected to the third open signal terminal;
  • the bit register unit is connected to the second open signal terminal;
  • the first shift register unit in the first shift register subgroup and the first shift register unit in the second shift register subgroup.
  • the bit register unit is connected to the fourth enable signal terminal.
  • the pixels located in the same row are arranged in sequence according to the first color, the second color and the third color, and the colors of the pixels located in the same column are the same.
  • each pixel is located in a different column.
  • each of the data lines includes: a plurality of data line segments and a plurality of connection line segments;
  • each of the connecting line segments are respectively connected with two adjacent data line segments; each of the pixel groups corresponds to one of the data line segments, and any two adjacent data line segments are respectively It is located between two pixels included in pixel groups of adjacent rows and different columns.
  • At least two pixels are located in the same column.
  • a method for driving a display substrate for driving the display substrate according to the above aspect, the method comprising:
  • each of the shift circuits provides a gate driving signal to each of the connected gate lines in response to the turn-on signal
  • a data signal is provided to each data line in the display substrate, and each pixel in the display substrate is responsive to a gate driving signal provided by the connected gate line and data provided by the connected data line Signal glows.
  • the display substrate includes: a first shift circuit, a second shift circuit, a third shift circuit and a fourth shift circuit, a total of four shift circuits, and a first turn-on signal terminal, a second turn-on signal terminal
  • the signal terminal, the third switch-on signal terminal and the fourth switch-on signal terminal have a total of four switch-on signal terminals; wherein, the first switch-on signal terminal is connected to the first shift circuit, and the third switch-on signal terminal is connected to the first shift circuit.
  • a second shift circuit is connected, the second turn-on signal terminal is connected to the third shift circuit, and the fourth turn-on signal terminal is connected to the fourth shift circuit;
  • the step of sequentially providing turn-on signals to each turn-on signal terminal in the display substrate includes:
  • a turn-on signal is sequentially provided to the first turn-on signal terminal, the third turn-on signal terminal, the second turn-on signal terminal and the fourth turn-on signal terminal.
  • each of the shift circuits includes at least four shift register units, each of the shift register units is connected to a gate line, and at least four shift registers in each of the shift circuits
  • the unit can be divided into two shift register groups; each of the shift register groups includes a cascade of a plurality of the shift register units, and one of the shift register units in each of the shift register groups connected with the open signal terminal; each of the shift register groups includes a plurality of shift register subgroups, and each of the shift register subgroups includes two adjacent and cascaded shift register units, And two of the shift register units in each of the shift register subgroups are respectively connected with the adjacent i-th gate line and the i+2-th gate line, where i is a positive integer;
  • Each of the shift circuits provides a gate driving signal to each of the connected gate lines in response to the turn-on signal, including the following steps performed in sequence:
  • the shift register unit connected to the first gate line provides a gate driving signal to the first gate line in response to the turn-on signal provided by the first turn-on signal terminal, and providing a carry signal to the shift register unit connected to the third gate line;
  • the shift register unit connected to the fifth gate line provides a gate driving signal to the fifth gate line in response to the turn-on signal provided by the third turn-on signal terminal, and providing a carry signal to the shift register unit connected to the seventh gate line;
  • the shift register unit connected to the ninth gate line provides a gate drive signal to the ninth gate line in response to the turn-on signal provided by the first turn-on signal terminal, and providing a carry signal to the shift register unit connected to the eleventh gate line;
  • the shift register unit connected to the thirteenth gate line provides a gate driving signal to the thirteenth gate line in response to the turn-on signal provided by the third turn-on signal terminal , and provide a carry signal to the shift register unit connected with the fifteenth gate line;
  • the shift register unit connected to the third gate line provides a gate driving signal to the third gate line in response to the received carry signal
  • the shift register unit connected to the seventh gate line provides a gate driving signal to the seventh gate line in response to the received carry signal
  • the shift register unit connected to the eleventh gate line provides a gate drive signal to the eleventh gate line in response to the received carry signal;
  • the shift register unit connected to the fifteenth gate line provides a gate driving signal to the fifteenth gate line in response to the received carry signal
  • the shift register unit connected to the second gate line provides a gate driving signal to the second gate line in response to the turn-on signal provided by the second turn-on signal terminal, and providing a carry signal to the shift register unit connected to the fourth gate line;
  • the shift register unit connected to the sixth gate line provides a gate driving signal to the sixth gate line in response to the turn-on signal provided by the fourth turn-on signal terminal, and providing a carry signal to the shift register unit connected to the eighth gate line;
  • the shift register unit connected to the tenth gate line provides a gate driving signal to the tenth gate line in response to the turn-on signal provided by the second turn-on signal terminal, and providing a carry signal to the shift register unit connected to the twelfth gate line;
  • the shift register unit connected to the fourteenth gate line provides a gate driving signal to the fourteenth gate line in response to the turn-on signal provided by the fourth turn-on signal terminal , and provide a carry signal to the shift register unit connected with the sixteenth gate line;
  • the shift register unit connected to the fourth gate line provides a gate driving signal to the fourth gate line in response to the received carry signal
  • the shift register unit connected to the eighth gate line provides a gate driving signal to the eighth gate line in response to the received carry signal
  • the shift register unit connected to the twelfth gate line provides a gate driving signal to the twelfth gate line in response to the received carry signal;
  • the shift register unit connected to the sixteenth gate line provides a gate driving signal to the sixteenth gate line in response to the received carry signal.
  • each of the shift circuits includes at least four shift register units, each of the shift register units is connected to a gate line, and at least four shift registers in each of the shift circuits
  • the unit can be divided into two shift register groups; each of the shift register groups includes a cascade of a plurality of the shift register units, and one of the shift register units in each of the shift register groups connected with the open signal terminal; each of the shift register groups includes a plurality of shift register subgroups, and each of the shift register subgroups includes two adjacent and cascaded shift register units, And two of the shift register units in each of the shift register subgroups are respectively connected with the adjacent i-th gate line and the i+1-th gate line, where i is a positive integer;
  • Each of the shift circuits provides a gate driving signal to each of the connected gate lines in response to the turn-on signal, including the following steps performed in sequence:
  • the shift register unit connected to the first gate line provides a gate driving signal to the first gate line in response to the turn-on signal provided by the first turn-on signal terminal, and providing a carry signal to the shift register unit connected to the second gate line;
  • the shift register unit connected to the fifth gate line provides a gate driving signal to the fifth gate line in response to the turn-on signal provided by the third turn-on signal terminal, and providing a carry signal to the shift register unit connected to the sixth gate line;
  • the shift register unit connected to the ninth gate line provides a gate drive signal to the ninth gate line in response to the turn-on signal provided by the first turn-on signal terminal, and providing a carry signal to the shift register unit connected to the tenth gate line;
  • the shift register unit connected to the thirteenth gate line provides a gate driving signal to the thirteenth gate line in response to the turn-on signal provided by the third turn-on signal terminal , and provide a carry signal to the shift register unit connected with the fourteenth gate line;
  • the shift register unit connected to the third gate line provides a gate driving signal to the third gate line in response to the turn-on signal provided by the second turn-on signal terminal, and providing a carry signal to the shift register unit connected to the fourth gate line;
  • the shift register unit connected to the seventh gate line provides a gate driving signal to the seventh gate line in response to the turn-on signal provided by the fourth turn-on signal terminal, and providing a carry signal to the shift register unit connected to the eighth gate line;
  • the shift register unit connected to the eleventh gate line provides a gate driving signal to the eleventh gate line in response to the turn-on signal provided by the second turn-on signal terminal , and provide a carry signal to the shift register unit connected with the twelfth gate line;
  • the shift register unit connected to the fifteenth gate line provides a gate driving signal to the fifteenth gate line in response to the turn-on signal provided by the fourth turn-on signal terminal , and provide a carry signal to the shift register unit connected with the sixteenth gate line;
  • the shift register unit connected to the second gate line provides a gate driving signal to the second gate line in response to the received carry signal
  • the shift register unit connected to the sixth gate line provides a gate driving signal to the sixth gate line in response to the received carry signal
  • the shift register unit connected to the tenth gate line provides a gate driving signal to the tenth gate line in response to the received carry signal;
  • the shift register unit connected to the fourteenth gate line provides a gate driving signal to the fourteenth gate line in response to the received carry signal
  • the shift register unit connected to the fourth gate line provides a gate driving signal to the fourth gate line in response to the received carry signal
  • the shift register unit connected to the eighth gate line provides a gate driving signal to the eighth gate line in response to the received carry signal
  • the shift register unit connected to the twelfth gate line provides a gate driving signal to the twelfth gate line in response to the received carry signal;
  • the shift register unit connected to the sixteenth gate line provides a gate driving signal to the sixteenth gate line in response to the received carry signal.
  • a display device comprising: a signal providing circuit, and the display substrate according to the above aspect;
  • the signal providing circuit is connected with the turn-on signal terminal in the display substrate, and is used for providing the turn-on signal terminal with the turn-on signal.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • FIG. 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of still another display substrate provided by an embodiment of the present application.
  • FIG. 9 is a signal timing diagram of a display substrate provided by an embodiment of the present application.
  • FIG. 10 is a signal timing diagram of another display substrate provided by an embodiment of the present application.
  • FIG. 11 is a waveform diagram of a data signal provided by a data line provided by an embodiment of the present application.
  • FIG. 13 is a flowchart of a method for driving a display substrate provided by an embodiment of the present application.
  • FIG. 14 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present application.
  • the display substrate may include: a base substrate 01, a plurality of gate lines G1 to Gm on the base substrate 01, a plurality of data lines D1 to Dk, and a plurality of rows of pixels arranged in an array (Fig. not identified in ), m and k are both integers greater than 0.
  • each row of pixels may include multiple pixel groups 02
  • each pixel group 02 may include two adjacent pixels 021 with different colors
  • the two pixels 021 may be respectively connected to different gate lines and the same data line . That is, referring to FIG. 1 , a plurality of pixels 021 located in the same row may be connected to two gate lines, and two pixels 021 connected to the same data line may be connected to different gate lines, respectively.
  • the first pixel 021 and the second pixel 021 located in the first row and adjacent to each other the first pixel 021 is connected to the first gate line G1, and the second pixel 021 is connected to the second gate line G2 is connected, and both the first pixel 021 and the second pixel 021 are connected to the first data line D1.
  • the number k of data lines required in the display substrate is only 1/2 of the number of pixel columns.
  • the number of leads in the binding area is also relatively reduced, which is beneficial to the realization of a narrow frame.
  • the display substrate described in the embodiment of the present application is a display substrate with a zigzag structure.
  • the display substrate provided in this embodiment of the present application may further include: a plurality of shift circuits located on the base substrate 01, each shift circuit may be respectively connected to at least two of an on-signal terminal and a plurality of gate lines. Grid line connection.
  • Each shift circuit may be configured to provide a gate driving signal to each of the connected gate lines in response to the turn-on signal provided by the turn-on signal terminal. That is, each shift circuit may provide a gate driving signal to each connected gate line when the connected turn-on signal terminal provides the turn-on signal.
  • each pixel 021 connected to the same data line has the same color.
  • the display substrate shown in FIG. 1 includes a total of four shift circuits 03a, 03b, 03c and 03d, wherein the two shift circuits 03a and 03c are located on one side of the gate line extending direction, and the two shift circuits 03b and 03c 03d is located on the other side of the grid line extending direction.
  • the shift circuit 03a is respectively connected to the turn-on signal terminal STV1, the first gate line G1, the third gate line G3 and the m-1 th gate line Gm-1, and the first gate line G1 and the third gate line G3 and each pixel 021 connected to the m-1th gate line Gm-1, that is, each pixel 021 connected to the shift circuit 03a, each pixel 021 connected to the first data line D1 (that is, located in the first row of the first row).
  • the color of the pixel 021 in the column, the pixel 021 in the second row and the first column, and the pixel 021 in the mth row and the first column) may all be red (red, R).
  • the shift circuit 03b is respectively connected with the turn-on signal terminal STV2, the second gate line G2, the fourth gate line G4 and the mth gate line Gm, and the second gate line G2, the fourth gate line G4 and the mth gate line Gm are respectively connected.
  • Each pixel 021 connected to the gate line Gm that is, each pixel 021 connected to the shift circuit 03b, each pixel 021 connected to the first data line D1 (that is, the pixel 021 located in the first row and the second column, the second row
  • the color of the pixel 021 in the second column and the pixel 021 in the m-th row and the second column may both be green (green, G).
  • the shift circuit 03c is respectively connected to the turn-on signal terminal STV3, the fifth gate line G5 and the seventh gate line G7, and each pixel 021 connected to the fifth gate line G5 and the seventh gate line G7, namely the shift circuit Among the pixels 021 connected to 03c, the colors of the pixels 021 connected to the second data line D2 (that is, the pixels 021 in the third row and the third column and the pixels 021 in the fourth row and the third column) may all be blue ( blue, B) color.
  • the shift circuit 03d is respectively connected to the turn-on signal terminal STV4, the sixth gate line G6 and the eighth gate line G8, and each pixel 021 connected to the sixth gate line G6 and the eighth gate line G8, namely the shift circuit
  • the color of each pixel 021 connected to the second data line D2 ie the pixel 021 in the third row and the fourth column and the pixel 021 in the fourth row and the fourth column
  • each of the above-mentioned four shift circuits 03a to 03d is not only connected to several gate lines shown in FIG. 1 , but also connected to other gate lines not shown in FIG. 1 , which will not be repeated here.
  • the shift circuit 03a can sequentially provide gate driving to the gate line G1, the gate line G3 and the gate line Gm-1
  • the first data line D1 can sequentially provide data signals to the pixels 021 in the first row and the first column, the pixels 021 in the second row and the first column, and the pixels 021 in the mth row and the first column.
  • the first data line D1 can be continuously directed to the Pixels of the same color provide data signals. In this way, when displaying a pure color picture, the potential of the data signal provided by the first data line D1 does not need to be constantly flipped, which effectively reduces power consumption. The same is true for other data lines, and will not be repeated here.
  • the embodiment of the present application adopts a display substrate, because in the display substrate, among a plurality of pixels connected to each shift circuit, each pixel sharing the same data line has the same color, and each pixel has the same color.
  • the shift circuit is connected to a turn-on signal terminal, so the turn-on signal provided by the turn-on signal terminal can be flexibly controlled, so that each data line can continuously provide data signals to pixels of the same color. In this way, when displaying a pure color picture, the number of potential inversions on each data line is less, which effectively reduces the power consumption of the display device.
  • FIG. 2 is a schematic structural diagram of another display substrate provided by an embodiment of the present application. It can be seen in combination with FIG. 1 and FIG. 2 that each pixel 021 in the same row may be arranged in sequence according to the first color, the second color and the third color.
  • the first color may be red R
  • the second color may be green G
  • the third color may be blue B. That is, as shown in FIG. 2 , each row of pixels 021 in the display substrate can be arranged in sequence according to the RGB colors.
  • the pixels in the display substrate are not limited to three colors of RGB, and may also include other colors such as yellow (yello, Y) and white (white, W).
  • each of the pixels 021 may be located in different columns.
  • at least two pixels 021 may be located in the same column.
  • the second data line D2 is connected to the data line D2 and is located in the pixel group 02 of the first row and the second row, and is located in a pixel B in the pixel group 02 of the first row Located in the third column, another pixel R is located in the fourth column; one pixel R in the pixel group 02 located in the second row is located in the first column, and the other pixel G is located in the second column. That is, all in different columns.
  • each data line may be arranged on the base substrate 01 in an arcuate shape. That is, each data line may include: a plurality of data line segments and a plurality of connection line segments, wherein both ends of each connection line segment are respectively connected with two adjacent data line segments; each pixel group corresponds to a data line segment, And any two adjacent data line segments are respectively located between two pixels included in pixel groups in different columns of adjacent rows.
  • the embodiment of the present application does not limit the directions of the two adjacent openings of each data line in the arcuate arrangement. The following embodiments are described by taking the display substrate shown in FIG. 2 as an example.
  • FIG. 3 shows a schematic structural diagram of another display substrate.
  • each shift circuit may include at least four shift register units, and each shift register unit may be connected to one gate line.
  • the display substrate may include m shift register units GOA1 to GOAm in total, wherein the first shift register unit GOA1 may Connect to the first gate line G1, and so on.
  • the number d of clock signal terminals connected to the plurality of shift circuits in the display substrate may be an integer multiple of 4. That is, multiple rows of pixels in the display substrate can be driven by an integer multiple of 4 phase clocks.
  • the number of clock signal terminals connected to the plurality of shift circuits may also be an integer multiple of 2.
  • the pixels in the multiple rows of the display substrate are driven by a 16-phase clock.
  • 16-phase clock driving is adopted, that is, starting from the first shift register unit GOA1, every adjacent 16 shift register units are connected with 16 clock signal terminals CLK1 to CLK1 in turn. CLK16 connection.
  • the following embodiments of the present application all use a 16-phase clock as an example to describe the display substrate.
  • the display substrate may include: a first shift circuit 03a, a second shift circuit 03b, a third shift circuit 03c, and a fourth shift circuit 03c.
  • Circuit 03d has a total of 4 shift circuits.
  • the first shift circuit 03a and the second shift circuit 03b may be located on one side of the rows of pixels 0, and the third shift circuit 03c and the fourth shift circuit 03d may be located on the other side of the rows of pixels.
  • the first shift circuit 03a is connected to the turn-on signal terminal STV1
  • the second shift circuit 03b is connected to the turn-on signal terminal STV3
  • the third shift circuit 03c is connected to the turn-on signal terminal STV2 connection
  • the dead low shift circuit 03d is connected to the open signal terminal STV4.
  • each shift register group 031 can be divided into two shift register groups 031, and each shift register group 031 can A number of shift register subgroups 0311 are included.
  • each shift register group 031 may include a plurality of shift register units cascaded with each other, and each shift register sub-group 0311 may include two adjacent and cascaded shift register units.
  • the turn-on signal terminal is only connected to one shift register unit in one shift register group 031 .
  • each shift register group 031 is the first shift register unit (eg, GOA1, GOA9, GOA5 and GOA13) are connected to the open signal terminal.
  • the plurality of shift register subgroups 0311 in each shift register group 031 are arranged in sequence, and each shift register group 031 is arranged in sequence.
  • the two shift register units in the shift register subgroup 0311 are arranged in sequence.
  • the first shift register subgroup 0311 in each shift register group 031 may refer to a shift register subgroup at the starting position of the target direction.
  • the first shift register subgroup 0311 included in the shift circuit 03a refers to the shift register subgroup including GOA1 and GOA3.
  • the first shift register unit included in each shift register subgroup 0311 may refer to the shift register unit located at the starting position of the target direction.
  • the first shift register unit included is GOA1.
  • the 2n-1th shift register subgroup 0311 located on one side of the multi-row pixels may belong to the first shift circuit 03a, and the 2n-th shift register located on one side of the multi-row pixels
  • the subgroup 0311 may belong to the second shift circuit 03b.
  • the 2n-1th shift register subgroup 0311 located on the other side of the multi-row pixels may belong to the third shift circuit 03c, and the 2n-th shift register subgroup 0311 located on the other side of the multi-row pixels may belong to the 3rd shift circuit 03c.
  • Four-shift circuit 03d, n may be a positive integer. That is, the shift register subgroups 0311 located on the same side with odd numbers may belong to the same shift circuit, and the shift register subgroups 0311 located on the same side with even numbers may belong to the same shift circuit.
  • the 4n-3th shift register subgroup 0311 located on the side thereof may belong to one of the first shift circuits 03a
  • the shift register group 031, the 4n-1th shift register subgroup 0311 may belong to another shift register group 031 in the first shift circuit 03a.
  • the 4n-2th shift register subgroup 0311 may belong to one shift register group 031 in the second shift circuit 03b, and the 4nth shift register subgroup 0311 may belong to the other shift register group 031 in the second shift circuit 03b Bit register bank 031.
  • the 4n-3th shift register subgroup 0311 on the side where they are located may belong to one shift register group 031 in the third shift circuit 03c
  • the 4n-1th shift register subgroup 0311 may belong to another shift register group 031 in the third shift circuit 03c.
  • the 4n-2th shift register subgroup 0311 may belong to one shift register group 031 in the fourth shift circuit 03d.
  • the 4nth shift register subgroup 0311 may belong to another shift register group 031 in the fourth shift circuit 03d.
  • the first shift register subgroup 0311 and the fifth shift register subgroup 0311 belongs to one shift register group 031 in the first shift circuit 03a.
  • the second shift register subgroup 0311 and the sixth shift register subgroup 0311 belong to one shift register group 031 in the second shift circuit 03b.
  • the third shift register subgroup 0311 and the seventh shift register subgroup 0311 belong to another shift register group 031 in the first shift circuit 03a.
  • the fourth shift register subgroup 0311 and the eighth shift register subgroup 0311 belong to another shift register group 031 in the second shift circuit 03b.
  • the first shift register subgroup 0311 and the fifth shift register subgroup 0311 belong to one shift register in the third shift circuit 03c Group 031.
  • the second shift register subgroup 0311 and the sixth shift register subgroup 0311 belong to one shift register group 031 in the fourth shift circuit 03d.
  • the third shift register subgroup 0311 and the seventh shift register subgroup 0311 belong to another shift register group 031 in the third shift circuit 03c.
  • the fourth shift register subgroup 0311 and the eighth shift register subgroup 0311 belong to another shift register group 031 in the fourth shift circuit 03d.
  • the shift register The shift register units GOA1 and GOA3 included in the first shift register sub-group 0311 in the group 031 are cascaded with each other, and the shift register unit GOA3 and the shift register unit GOA17 in the second shift register sub-group 0311 are mutually connected.
  • the shift register unit GOA17 is also cascaded with the shift register unit GOA19 in the second shift register subgroup 0311.
  • the first shift register unit GOA1 of the first shift register sub-group 0311 is connected to the start signal terminal STV1. And so on.
  • the two shift register units in each shift register subgroup 0311 may be respectively connected to the i-th gate line and the i+s-th gate line, where i is a positive integer, s can be 1 or 2.
  • s is 2. That is, the shift register units with odd numbers are located on the same side, and the shift register units with even numbers are located on the same side. In this way, the pixels in the same row can be simultaneously driven by the shift register units located on both sides. That is, the pixels of the same line are driven bilaterally.
  • the first shift register unit GOA1 and the third shift register unit GOA3 are cascaded with each other, and the first shift register unit GOA1 can be used to provide a carry signal to the third shift register unit GOA3.
  • the third shift register unit may be used to provide a reset signal to the first shift register unit GOA1.
  • the third shift register unit GOA3 is also cascaded with the 1+16th, that is, the 17th shift register unit (not shown in the figure), and the third shift register unit GOA3 can be used to shift to the 17th shift register unit.
  • the bit register unit provides the carry signal.
  • the 17th shift register unit is used to provide a reset signal to the 3rd shift register unit GOA3.
  • the fifth shift register unit GOA5 and the seventh shift register unit GOA7 are cascaded with each other, and the fifth shift register unit GOA5 can be used to provide a carry signal to the seventh shift register unit GOA7.
  • the seventh shift register unit GOA7 may be used to provide a reset signal to the fifth shift register unit GOA5.
  • the 7th shift register unit GOA7 is also cascaded with the 5th+16th, that is, the 21st shift register unit (not shown in the figure), and the 7th shift register unit GOA7 can be used to shift to the 21st shift register unit.
  • the bit register unit provides the carry signal.
  • the 21st shift register unit may be used to provide a reset signal to the 7th shift register unit GOA7.
  • the ninth shift register unit GOA9 and the eleventh shift register unit GOA11 are cascaded with each other, and the ninth shift register unit GOA9 is used to provide a carry signal to the eleventh shift register unit GOA11.
  • the eleventh shift register unit GOA11 is used to provide a reset signal to the ninth shift register unit GOA9.
  • the 11th shift register unit GOA11 is also cascaded with the 9th+16th, that is, the 25th shift register unit (not shown in the figure), and the 11th shift register unit GOA11 is used to shift to the 25th shift register unit.
  • the register unit provides the carry signal.
  • the 25th shift register unit is used to provide a reset signal to the 11th shift register unit GOA11.
  • the 13th shift register unit GOA13 and the 15th shift register unit GOA15 are cascaded with each other, and the 13th shift register unit GOA13 is used to provide a carry signal to the 15th shift register unit GOA15.
  • the 15th shift register unit GOA15 is used to provide a reset signal to the 13th shift register unit GOA13.
  • the 15th shift register unit GOA15 is also cascaded with the 13th+16th, that is, the 29th shift register unit (not shown in the figure), and the 15th shift register unit GOA15 is used to shift to the 29th shift register unit.
  • the register unit provides the carry signal.
  • the 29th shift register unit is used to provide a reset signal to the 15th shift register unit GOA15.
  • the second shift register unit GOA2 can be cascaded with the fourth shift register unit GOA4, and the second shift register unit GOA2 is used to provide a carry signal to the fourth shift register unit GOA4.
  • the fourth shift register unit GOA4 is used to provide a reset signal to the second shift register unit GOA2.
  • the 4th shift register unit GOA4 is also cascaded with the 2nd+16th, that is, the 18th shift register unit (not shown in the figure), and the 4th shift register unit GOA4 is used for shifting to the 18th shift register unit.
  • the register unit provides the carry signal.
  • the 18th shift register unit is used to provide a reset signal to the 4th shift register unit GOA4.
  • the sixth shift register unit GOA6 and the eighth shift register unit GOA8 are cascaded with each other, and the sixth shift register unit GOA6 is used to provide a carry signal to the eighth shift register unit GOA8.
  • the 8th shift register unit GOA8 is used to provide a reset signal to the 6th shift register unit GOA6.
  • the 8th shift register unit GOA8 is also cascaded with the 6th+16th, that is, the 22nd shift register unit (not shown in the figure), and the 8th shift register unit GOA8 can be used to shift to the 22nd shift register unit.
  • the bit register unit provides the carry signal.
  • the 22nd shift register unit is used to provide a reset signal to the 8th shift register unit GOA8.
  • the tenth shift register unit GOA10 and the twelfth shift register unit GOA12 are cascaded with each other, and the tenth shift register unit GOA10 is used to provide a carry signal to the twelfth shift register unit GOA12.
  • the twelfth shift register unit GOA12 is used to provide a reset signal to the tenth shift register unit GOA10.
  • the 12th shift register unit GOA12 is also cascaded with the 10th+16th, that is, the 26th shift register unit (not shown in the figure), and the 12th shift register unit GOA12 is used to shift to the 26th shift register unit.
  • the register unit provides the carry signal.
  • the 26th shift register unit is used to provide a reset signal to the 12th shift register unit GOA12.
  • the 14th shift register unit GOA14 and the 16th shift register unit GOA16 are cascaded with each other, and the 14th shift register unit GOA14 is used to provide a carry signal to the 16th shift register unit GOA16.
  • the 16th shift register unit GOA16 is used to provide a reset signal to the 14th shift register unit GOA14.
  • the 16th shift register unit GOA16 is also cascaded with the 14th+16th, that is, the 30th shift register unit (not shown in the figure), and the 16th shift register unit GOA16 is used to shift to the 30th shift register unit.
  • the register unit provides the carry signal.
  • the 30th shift register unit is used to provide a reset signal to the 16th shift register unit GOA16.
  • s is 1.
  • the pixels in the same row can be simultaneously driven by the shift register units located on the same side. That is, the pixels in the same row are driven on the same side.
  • the first shift register unit GOA1 and the second shift register unit GOA2 are cascaded with each other, and the first shift register unit GOA1 can be used to provide a carry signal to the second shift register unit GOA2.
  • the second shift register unit GOA2 may be used to provide a reset signal to the first shift register unit GOA1.
  • the second shift register unit GOA2 is also cascaded with the 1+16th, that is, the 17th shift register unit (not shown in the figure), and the second shift register unit GOA2 can be used to shift to the 17th shift register unit.
  • the bit register unit provides the carry signal.
  • the 17th shift register unit may be used to provide a reset signal to the 2nd shift register unit GOA2.
  • the third shift register unit GOA3 and the fourth shift register unit GOA4 are cascaded with each other, and the third shift register unit GOA3 can be used to provide a carry signal to the fourth shift register unit GOA4.
  • the fourth shift register unit GOA4 may be used to provide a reset signal to the third shift register unit GOA3.
  • the 4th shift register unit GOA4 is also cascaded with the 3rd+16th, that is, the 19th shift register unit (not shown in the figure), and the 4th shift register unit GOA4 can be used to shift to the 19th shift register unit.
  • the bit register unit provides the carry signal.
  • the 19th shift register unit may be used to provide a reset signal to the 4th shift register unit GOA4.
  • the fifth shift register unit GOA5 and the sixth shift register unit GOA6 are cascaded with each other, and the fifth shift register unit GOA5 can be used to provide a carry signal to the sixth shift register unit GOA6.
  • the sixth shift register unit GOA6 may be used to provide a reset signal to the fifth shift register unit GOA5.
  • the 6th shift register unit GOA6 is also cascaded with the 5th+16th, that is, the 21st shift register unit (not shown in the figure), and the 6th shift register unit GOA6 can be used to shift to the 21st shift register unit.
  • the bit register unit provides the carry signal.
  • the 21st shift register unit may be used to provide a reset signal to the 6th shift register unit GOA6.
  • the seventh shift register unit GOA7 and the eighth shift register unit GOA8 are cascaded with each other, and the seventh shift register unit GOA7 can be used to provide a carry signal to the eighth shift register unit GOA8.
  • the 8th shift register unit GOA8 may be used to provide a reset signal to the 7th shift register unit GOA7.
  • the 8th shift register unit GOA8 is also cascaded with the 7th+16th, that is, the 23rd shift register unit (not shown in the figure), and the 8th shift register unit GOA8 can be used to shift to the 23rd shift register unit.
  • the bit register unit provides the carry signal.
  • the 23rd shift register unit may be used to provide a reset signal to the 8th shift register unit GOA8.
  • the ninth shift register unit GOA9 and the tenth shift register unit GOA10 are cascaded with each other, and the ninth shift register unit GOA9 can be used to provide a carry signal to the tenth shift register unit GOA10.
  • the tenth shift register unit GOA10 may be used to provide a reset signal to the ninth shift register unit GOA9.
  • the 10th shift register unit GOA10 is also cascaded with the 9th+16th, that is, the 25th shift register unit (not shown in the figure), and the 10th shift register unit GOA10 can be used to shift to the 25th shift register unit.
  • the bit register unit provides the carry signal.
  • the 25th shift register unit may be used to provide a reset signal to the 10th shift register unit GOA10.
  • the 11th shift register unit GOA11 and the 12th shift register unit GOA12 are cascaded with each other, and the 11th shift register unit GOA11 can be used to provide a carry signal to the 12th shift register unit GOA12.
  • the 12th shift register unit GOA12 may be used to provide a reset signal to the 11th shift register unit GOA11.
  • the 12th shift register unit GOA12 is also cascaded with the 11th+16th, that is, the 28th shift register unit (not shown in the figure), and the 12th shift register unit GOA12 can be used to shift to the 28th shift register unit.
  • the bit register unit provides the carry signal.
  • the 28th shift register unit may be used to provide a reset signal to the 12th shift register unit GOA12.
  • the 13th shift register unit GOA13 and the 14th shift register unit GOA14 are cascaded with each other, and the 13th shift register unit GOA13 can be used to provide a carry signal to the 14th shift register unit GOA14.
  • the 14th shift register unit GOA14 may be used to provide a reset signal to the 13th shift register unit GOA13.
  • the 14th shift register unit GOA14 is also cascaded with the 13th+16th, that is, the 29th shift register unit (not shown in the figure), and the 14th shift register unit GOA14 can be used to shift to the 29th shift register unit.
  • the bit register unit provides the carry signal.
  • the 29th shift register unit may be used to provide a reset signal to the 14th shift register unit GOA14.
  • the 15th shift register unit GOA15 and the 16th shift register unit GOA16 are cascaded with each other, and the 15th shift register unit GOA15 can be used to provide a carry signal to the 16th shift register unit GOA16.
  • the 16th shift register unit GOA16 may be used to provide a reset signal to the 15th shift register unit GOA15.
  • the 16th shift register unit GOA16 is also cascaded with the 15th+16th, that is, the 31st shift register unit (not shown in the figure), and the 16th shift register unit GOA16 can be used to shift to the 31st shift register unit.
  • the bit register unit provides the carry signal.
  • the 31st shift register unit may be used to provide a reset signal to the 16th shift register unit GOA16.
  • cascade means that during scanning, the previous bit register unit provides a carry signal to the next bit register unit, and the latter bit register unit provides a reset signal to the previous bit register unit. That is, the output terminal of the previous shift register unit is connected to the input terminal of the latter shift register unit, and the output terminal of the latter shift register unit is connected to the reset terminal of the previous shift register unit. In this way, when the potential of the output terminal of the previous shift register unit is an effective potential, the latter shift register unit can be turned on, so the signal provided by the previous bit register unit for the latter bit register unit is called a carry signal.
  • the reset end of the former shift register unit starts to denoise the former shift register unit, so the latter bit register unit provides the former bit register unit
  • the signal is called the carry signal and is called the reset signal.
  • the third shift register unit GOA3 supplies the first shift register unit GOA3 with a carry signal.
  • Cell GOA1 provides the reset signal and at the same time provides the carry signal to the seventeenth shift register cell GOA17, and so on.
  • the second shift register unit GOA2 supplies the first shift register unit GOA1 A reset signal is provided, and a carry signal is simultaneously provided to the seventeenth shift register unit GOA17, and so on.
  • the display substrate shown in FIG. 8 is compared with the display substrate shown in FIG. 7. Because GOA1 and GOA2 are cascaded with each other, it can be determined that the potentials of the clock signals provided by every two adjacent clock signal terminals are complementary, so that the pixel can be further determined.
  • the charging time can be adjusted in a wide range.
  • FIG. 9 shows a timing diagram.
  • FIG. 10 shows another timing diagram.
  • the turn-on signal terminals STV1, STV3, STV2 and STV4 provide turn-on signals in sequence
  • CLK1, CLK5, CLK9, CLK13, CLK3, CLK7, CLK11, CLK15, CLK2, CLK6, CLK10, CLK14, CLK4, CLK8, CLK12, and CLK16 are clock signals that sequentially start supplying effective potentials.
  • the GOA1 when the turn-on signal terminal STV1 provides the turn-on signal of the effective potential, the GOA1 can be turned on first, until the clock signal terminal CLK1 connected to the GOA1 provides the signal.
  • the clock signal becomes an active potential, and GOA1 outputs a gate drive signal having an active potential to the first gate line G1.
  • GOA1 also provides a carry signal to GOA3, and GOA3 is turned on.
  • the clock signal provided by the clock signal terminal CLK3 connected to GOA3 is kept at an inactive potential.
  • the effective potential may be a high potential relative to the inactive potential.
  • the GOA1 can be turned on first until the clock signal provided by the clock signal terminal CLK1 connected to the GOA1. When it becomes an effective potential, GOA1 outputs a gate drive signal of an effective potential to the first gate line G1. At the same time, GOA1 also provides a carry signal to GOA2, GOA2 is turned on, and in order to prevent GOA2 from providing a gate drive signal with an effective potential to the connected second gate line G2 first, the clock signal provided by the clock signal terminal CLK2 remains invalid. potential. And so on.
  • the gate line scanning sequence is: G1—>G5—>G9 —>G13—>G3—>G7—>G11—>G15—>G2—>G6—>G10—>G14—>G4—>G8—>G12—>G16. That is, for every four shift register cells one cycle, the gate line jumps on scanning instead of sequentially turning on scanning.
  • the second data line D2, the third data line D3 and the fourth data line D4 in the display substrate shown in FIG. 3 can be made to sequentially provide data signals to the pixels of the following colors in one cycle:
  • FIG. 11 shows a timing diagram of the data line D2 in one cycle.
  • the potential of the data signal provided by the data line D2 is only inverted twice. The same is true for other data lines.
  • the gate lines are controlled to be turned on in sequence, when the display substrate displays a solid color picture, the second data line D2, the third data line D3 and the third data line D3 and the third data line D2 and the third data line D3 and the third data line D2 and the third data line D3 and the third data line D2 and the third data line D3 and the third data line D2 and the third data line D3 and the third data line D2 and the third data line D3 and the third data line D3 and the third data line D3 and the second data line D3 and the third data line D3 and the third data line D3 and the third data line D3 and the third data line D3 and the third data line D3 and the third data line D3 and the third data line D3 and the third data line D3 and the third data line D3 and the third data line D3 and the third data line D3 in the display substrate shown in FIG.
  • the four data lines D4 sequentially provide data signals to the pixels of the following colors in one cycle:
  • FIG. 12 shows a timing diagram of the data line D2 in one cycle in the related art.
  • the potential of the data signal provided by the data line D2 is flipped 16 times in one cycle.
  • the potential of the data signal provided by the data line D3 is inverted 8 times in a cycle
  • the potential of the data signal provided by the data line D4 is inverted 8 times in a cycle. Its three data lines are flipped 32 times in total.
  • one flip may refer to: flipping from an effective potential to an inactive potential, or flipping from an inactive potential to an effective potential.
  • the inactive potential is 0 volts (V) and the active potential is 5V
  • FIGS. 11 and 12 it can be seen that the potential of each data line in the related art needs to be converted from 0V to 5V multiple times.
  • the switching frequency of the potentials between 0V and 5V is lower, and the power consumption is reduced.
  • G1 is only 4 cycles from turning on to the cascaded G3; while for the display substrate shown in Figure 8, G1 is turned on from the start to the cascaded G3.
  • G2 is turned on, it takes 8 cycles. Therefore, compared with the arrangement in FIG. 8 , the on-time duration of G1 is shorter, and accordingly, the power consumption is also lower.
  • the embodiment of the present application adopts a display substrate, because in the display substrate, among a plurality of pixels connected to each shift circuit, each pixel sharing the same data line has the same color, and each pixel has the same color.
  • the shift circuit is connected to a turn-on signal terminal, so the turn-on signal provided by the turn-on signal terminal can be flexibly controlled, so that each data line can continuously provide data signals to pixels of the same color. In this way, when a pure color picture is displayed, the number of potential flips on each data line is less, which effectively reduces the power consumption of the display device.
  • FIG. 13 is a flowchart of a method for driving a display substrate provided by an embodiment of the present application, and the method can be used to drive the display substrate as shown in any one of FIGS. 1 to 8 .
  • the method may include:
  • Step 1301 Provide turn-on signals to each turn-on signal terminal in the display substrate in sequence, and each shift circuit provides a gate drive signal to each connected gate line in response to the turn-on signal.
  • Step 1302 Provide a data signal to each data line, and each pixel emits light in response to the gate driving signal provided by the connected gate line and the data signal provided by the connected data line.
  • the display substrate includes: a first shift circuit, a second shift circuit, a third shift circuit and a fourth shift circuit, a total of four shift circuits, wherein, The first shift circuit and the second shift circuit are located on one side of the rows of pixels, and the third shift circuit and the fourth shift circuit are located on the other side of the rows of pixels.
  • providing the turn-on signal to each turn-on signal terminal in the display substrate in turn may include: firstly supplying the first shift circuit and the second shift circuit to the two terminals connected to the shift circuit. The turn-on signal terminals provide turn-on signals in sequence; then turn-on signals are sequentially supplied to the two turn-on signal terminals connected to the third shift circuit and the fourth shift circuit.
  • Step 1301 may include the following methods performed in sequence:
  • the shift register unit GOA1 connected to the first gate line G1 provides a gate drive signal to the first gate line G1 in response to the turn-on signal provided by the first turn-on signal terminal STV1, and sends a gate drive signal to the first gate line G1.
  • the shift register unit GOA3 connected to the third gate line G3 provides a carry signal.
  • the shift register unit GOA5 connected to the fifth gate line G5 provides a gate driving signal to the fifth gate line G5 in response to the turn-on signal provided by the third turn-on signal terminal STV3, and provides a gate drive signal to the fifth gate line G5
  • the shift register unit GOA7 connected to the seventh gate line G7 provides a carry signal.
  • the shift register unit GOA9 connected to the ninth gate line G9 provides a gate drive signal to the ninth gate line G9 in response to the turn-on signal provided by the first turn-on signal terminal STV1, and provides a gate drive signal to the ninth gate line G9.
  • the shift register unit GOA11 connected to the eleventh gate line G11 provides a carry signal.
  • the shift register unit GOA13 connected to the thirteenth gate line G13 provides a gate driving signal to the thirteenth gate line G13 in response to the turn-on signal provided by the third turn-on signal terminal STV3, and A carry signal is supplied to the shift register unit GOA15 connected to the fifteenth gate line G15.
  • the shift register unit GOA3 connected to the third gate line G3 provides a gate driving signal to the third gate line G3 in response to the received carry signal.
  • the shift register unit GOA7 connected to the seventh gate line G7 provides a gate driving signal to the seventh gate line G7 in response to the received carry signal.
  • the shift register unit GOA11 connected to the eleventh gate line G11 provides a gate driving signal to the eleventh gate line G11 in response to the received carry signal.
  • the shift register unit GOA15 connected to the fifteenth gate line G15 provides a gate driving signal to the fifteenth gate line G15 in response to the received carry signal.
  • the shift register unit GOA2 connected to the second gate line G2 provides a gate driving signal to the second gate line G2 in response to the turn-on signal provided by the second turn-on signal terminal STV2, and sends a gate driving signal to the second gate line G2.
  • the shift register unit GOA4 connected to the fourth gate line G4 provides a carry signal.
  • the shift register unit GOA6 connected to the sixth gate line G6 provides a gate drive signal to the sixth gate line G6 in response to the turn-on signal provided by the fourth turn-on signal terminal STV4, and to The shift register unit GOA8 connected to the eighth gate line G8 provides a carry signal.
  • the shift register unit GOA10 connected to the tenth gate line G10 provides a gate driving signal to the tenth gate line G10 in response to the turn-on signal provided by the second turn-on signal terminal STV2, and sends a gate driving signal to
  • the shift register unit GOA12 connected to the twelfth gate line G12 provides a carry signal.
  • the shift register unit GOA14 connected to the fourteenth gate line G14 provides a gate drive signal to the fourteenth gate line G14 in response to the turn-on signal provided by the fourth turn-on signal terminal STV4, and A carry signal is supplied to the shift register unit GOA16 connected to the sixteenth gate line G16.
  • the shift register unit GOA4 connected to the fourth gate line G4 provides a gate driving signal to the fourth gate line G4 in response to the received carry signal.
  • the shift register unit GOA8 connected to the eighth gate line G8 provides a gate driving signal to the eighth gate line G8 in response to the received carry signal.
  • the shift register unit GOA12 connected to the twelfth gate line G12 provides a gate driving signal to the twelfth gate line G12 in response to the received carry signal.
  • the shift register unit GOA16 connected to the sixteenth gate line G16 provides a gate driving signal to the sixteenth gate line G16 in response to the received carry signal.
  • Step 1301 may include the following methods performed in sequence:
  • the shift register unit GOA1 connected to the first gate line G1 provides a gate drive signal to the first gate line G1 in response to the turn-on signal provided by the first turn-on signal terminal STV1, and sends a gate drive signal to the first gate line G1.
  • the shift register unit GOA2 connected to the second gate line G2 provides a carry signal.
  • the shift register unit GOA5 connected to the fifth gate line G5 provides a gate driving signal to the fifth gate line G5 in response to the turn-on signal provided by the third turn-on signal terminal STV3, and provides a gate drive signal to the fifth gate line G5
  • the shift register unit GOA6 connected to the sixth gate line G6 provides a carry signal.
  • the shift register unit GOA9 connected to the ninth gate line G9 provides a gate drive signal to the ninth gate line G9 in response to the turn-on signal provided by the first turn-on signal terminal STV1, and provides a gate drive signal to the ninth gate line G9.
  • the shift register unit GOA10 connected to the tenth gate line G10 provides a carry signal.
  • the shift register unit GOA13 connected to the thirteenth gate line G13 provides a gate driving signal to the thirteenth gate line G13 in response to the turn-on signal provided by the third turn-on signal terminal STV3, and A carry signal is supplied to the shift register unit GOA14 connected to the fourteenth gate line G14.
  • the shift register unit GOA3 connected to the third gate line G3 provides a gate driving signal to the third gate line G3 in response to the turn-on signal provided by the second turn-on signal terminal STV2, and sends a gate driving signal to the third gate line G3.
  • the shift register unit GOA4 connected to the fourth gate line G4 provides a carry signal.
  • the shift register unit GOA7 connected to the seventh gate line G7 provides a gate drive signal to the seventh gate line G7 in response to the turn-on signal provided by the fourth turn-on signal terminal STV4, and provides a gate drive signal to the seventh gate line G7.
  • the shift register unit GOA8 connected to the eighth gate line G8 provides a carry signal.
  • the shift register unit GOA11 connected to the eleventh gate line G11 provides a gate driving signal to the eleventh gate line G11 in response to the turn-on signal provided by the second turn-on signal terminal STV2, and A carry signal is supplied to the shift register unit GOA12 connected to the twelfth gate line G12.
  • the shift register unit GOA15 connected to the fifteenth gate line G15 provides a gate drive signal to the fifteenth gate line G15 in response to the turn-on signal provided by the fourth turn-on signal terminal STV4, and A carry signal is supplied to the shift register unit GOA16 connected to the sixteenth gate line G16.
  • the shift register unit GOA2 connected to the second gate line G2 provides a gate driving signal to the second gate line G2 in response to the received carry signal.
  • the shift register unit GOA6 connected to the sixth gate line G6 provides a gate driving signal to the sixth gate line G6 in response to the received carry signal.
  • the shift register unit GOA10 connected to the tenth gate line G10 provides a gate driving signal to the tenth gate line G10 in response to the received carry signal.
  • the shift register unit GOA14 connected to the fourteenth gate line G14 supplies a gate driving signal to the fourteenth gate line G14 in response to the received carry signal.
  • the shift register unit GOA4 connected to the fourth gate line G4 provides a gate driving signal to the fourth gate line G4 in response to the received carry signal.
  • the shift register unit GOA8 connected to the eighth gate line G8 provides a gate driving signal to the eighth gate line G8 in response to the received carry signal.
  • the shift register unit GOA12 connected to the twelfth gate line G12 provides a gate driving signal to the twelfth gate line G12 in response to the received carry signal.
  • the shift register unit GOA16 connected to the sixteenth gate line G16 provides a gate driving signal to the sixteenth gate line G16 in response to the received carry signal.
  • step 1301 it can be seen that whether it is the display substrate shown in FIG. 7 (ie, the timing shown in FIG. 9 ) or the display substrate shown in FIG. 8 (ie, the timing shown in FIG. 10 ), it can be achieved within one cycle.
  • the raster scan order is:
  • the embodiment of the present application adopts a driving method for a display substrate, since each shift circuit can provide a gate driving signal to each connected gate line in response to the turn-on signal, and the display substrate , among the multiple pixels connected to each shift circuit, the pixels sharing the same data line have the same color, and each shift circuit is connected to an open signal terminal, so the open signal provided by the open signal terminal can be flexibly controlled signal, so that each data line can continuously provide data signals to pixels of the same color. In this way, when a pure color picture is displayed, the number of potential inversions on each data line is less, which effectively reduces the power consumption of the display device.
  • FIG. 14 is a schematic structural diagram of a display device provided by an embodiment of the present application.
  • the display device may include: a signal providing circuit 100 and a display substrate 200 as shown in any one of FIGS. 1 to 8 .
  • the signal providing circuit 100 may be connected to the turn-on signal terminal in the display substrate 200, and may be used to provide the turn-on signal terminal for the turn-on signal terminal.
  • the display device may be: an organic light-emitting diode (organic light-emitting diode, OLED) display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer or a navigator, and any other product or component with a display function.
  • OLED organic light-emitting diode

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Abstract

本申请提供了一种显示基板及其驱动方法、显示装置，属于显示技术领域。由于该显示基板中，每个移位电路所连接的多个像素中，共用同一条数据线的各个像素的颜色相同，且每个移位电路与一个开启信号端连接，因此可以通过灵活控制开启信号端提供的开启信号，使得每条数据线可以连续向相同颜色的像素提供数据信号。如此，在显示纯色画面时，每条数据线上的电位翻转次数较少，有效降低了显示装置的功耗。

Description

显示基板及其驱动方法、显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示基板及其驱动方法、显示装置。
背景技术
液晶显示(liquid crystal display，LCD)装置因其分辨率高、重量轻和低能耗等优点被广泛应用于显示领域中。
相关技术提出一种双栅(dual gate)设计的LCD装置，该双栅LCD装置包括：多条栅线、多条数据线和阵列排布的多个像素。其中，位于同一行的多个像素可以划分为多组，每组可以包括相邻且颜色不同的两个像素，且该两个像素可以分别与不同的栅线连接，以及可以与同一条数据线连接。即，每行像素可以与两条栅线分别连接。且，目前该双栅LCD装置的扫描驱动方式为逐行扫描，即多条栅线按照排布顺序依次开启，从而驱动各行像素依次发光。
但是，若需显示纯色画面，相关技术中，每条数据线上的电位需要不断变化(也可称为翻转)，如此导致功耗较大。
发明内容
本申请提供了一种显示基板及其驱动方法、显示装置，所述技术方案如下：
一方面，提供了一种显示基板，所述显示基板包括：衬底基板；
位于所述衬底基板上的多条栅线、多条数据线和阵列排布的多行像素，每行所述像素包括多个像素组，每个所述像素组包括相邻且颜色不同的两个像素，且所述两个像素与不同条所述栅线和同一条所述数据线连接；
位于所述衬底基板上的多个移位电路，每个所述移位电路分别与一个开启信号端和所述多条栅线中的至少两条栅线连接，每个所述移位电路用于响应于所述开启信号端提供的开启信号，向所连接的每条所述栅线提供栅极驱动信号；
其中，每个所述移位电路连接的多个像素中，与同一条所述数据线连接的 像素的颜色相同。
可选的，每个所述移位电路包括：至少四个移位寄存器单元，每个所述移位寄存器单元与一条栅线连接，且每个所述移位电路中的至少四个移位寄存器单元能够划分为两个移位寄存器组；
其中，每个所述移位寄存器组包括级联的多个所述移位寄存器单元，且每个所述移位寄存器组中的一个所述移位寄存器单元与所述开启信号端连接。
可选的，每个所述移位寄存器组包括多个移位寄存器子组，每个所述移位寄存器子组包括相邻且级联的两个所述移位寄存器单元，且每个所述移位寄存器子组中的两个所述移位寄存器单元分别与相邻的第i条栅线和第i+s条栅线连接，i为正整数，且s为1或2。
可选的，所述显示基板中的多个移位电路所连接的时钟信号端的数量d为4的整数倍。
可选的，所述显示基板中的多个移位电路所连接的时钟信号端的数量d为16。
可选的，所述多个移位电路包括：第一移位电路、第二移位电路、第三移位电路和第四移位电路共四个移位电路；
其中，所述第一移位电路和所述第二移位电路位于所述多行像素的一侧，所述第三移位电路和所述第四移位电路位于所述多行像素的另一侧。
可选的，位于所述多行像素的一侧的第2n-1个所述移位寄存器子组属于所述第一移位电路，位于所述多行像素的一侧的第2n个所述移位寄存器子组属于所述第二移位电路，n为正整数；
位于所述多行像素的另一侧的第2n-1个所述移位寄存器子组属于所述第三移位电路，位于所述多行像素的另一侧的第2n个所述移位寄存器子组属于所述第四移位电路。
可选的，位于所述多行像素的一侧的第4n-3个移位寄存器子组属于所述第一移位电路中的一个移位寄存器组，位于所述多行像素的一侧的第4n-1个移位寄存器子组属于所述第一移位电路中的另一个移位寄存器组；
位于所述多行像素的一侧的第4n-2个移位寄存器子组属于所述第二移位电路中的一个移位寄存器组；位于所述多行像素的一侧的第4n个移位寄存器子组属于所述第二移位电路中的另一个移位寄存器组；
位于所述多行像素的另一侧的第4n-3个移位寄存器子组属于所述第三移位电路中的一个移位寄存器组，位于所述多行像素的另一侧的第4n-1个移位寄存器子组属于所述第三移位电路中的另一个移位寄存器组；
位于所述多行像素的零一侧的第4n-2个移位寄存器子组属于所述第四移位电路中的一个移位寄存器组；位于所述多行像素的另一侧的第4n个移位寄存器子组属于所述第四移位电路中的另一个移位寄存器组。
可选的，s为2，连接至第i条栅线的所述移位寄存器单元为第i个所述移位寄存器单元；
其中，第1个所述移位寄存器单元与第3个所述移位寄存器单元相互级联，第1个所述移位寄存器单元用于向第3个所述移位寄存器单元提供进位信号；第3个所述移位寄存器单元用于向第1个所述移位寄存器单元提供复位信号；
第3个所述移位寄存器单元还与第1+d个所述移位寄存器单元相互级联，第3个所述移位寄存器单元用于向第1+d个所述移位寄存器单元提供进位信号；第1+d个所述移位寄存器单元用于向第3个所述移位寄存器单元提供复位信号；
第5个所述移位寄存器单元与第7个所述移位寄存器单元相互级联，第5个所述移位寄存器单元用于向第7个所述移位寄存器单元提供进位信号；第7个所述移位寄存器单元用于向第5个所述移位寄存器单元提供复位信号；
第7个所述移位寄存器单元还与第5+d个所述移位寄存器单元相互级联，第7个所述移位寄存器单元用于向第5+d个所述移位寄存器单元提供进位信号；第5+d个所述移位寄存器单元用于向第7个所述移位寄存器单元提供复位信号；
第9个所述移位寄存器单元与第11个所述移位寄存器单元相互级联，第9个所述移位寄存器单元用于向第11个所述移位寄存器单元提供进位信号；第11个所述移位寄存器单元用于向第9个所述移位寄存器单元提供复位信号；
第11个所述移位寄存器单元还与第9+d个所述移位寄存器单元相互级联，第11个所述移位寄存器单元用于向第9+d个所述移位寄存器单元提供进位信号；第9+d个所述移位寄存器单元用于向第11个所述移位寄存器单元提供复位信号；
第13个所述移位寄存器单元与第15个所述移位寄存器单元相互级联，第13个所述移位寄存器单元用于向第15个所述移位寄存器单元提供进位信号；第15个所述移位寄存器单元用于向第13个所述移位寄存器单元提供复位信号；
第15个所述移位寄存器单元还与第13+d个所述移位寄存器单元相互级联，第15个所述移位寄存器单元用于向第13+d个所述移位寄存器单元提供进位信号；第13+d个所述移位寄存器单元用于向第15个所述移位寄存器单元提供复位信号；
第2个所述移位寄存器单元与第4个所述移位寄存器单元相互级联，第2个所述移位寄存器单元用于向第4个所述移位寄存器单元提供进位信号；第4个所述移位寄存器单元用于向第2个所述移位寄存器单元提供复位信号；
第4个所述移位寄存器单元还与第2+d个所述移位寄存器单元相互级联，第4个所述移位寄存器单元用于向第2+d个所述移位寄存器单元提供进位信号；第2+d个所述移位寄存器单元用于向第4个所述移位寄存器单元提供复位信号；
第6个所述移位寄存器单元与第8个所述移位寄存器单元相互级联，第6个所述移位寄存器单元用于向第8个所述移位寄存器单元提供进位信号；第8个所述移位寄存器单元用于向第6个所述移位寄存器单元提供复位信号；
第8个所述移位寄存器单元还与第6+d个所述移位寄存器单元相互级联，第8个所述移位寄存器单元用于向第6+d个所述移位寄存器单元提供进位信号；第6+d个所述移位寄存器单元用于向第8个所述移位寄存器单元提供复位信号；
第10个所述移位寄存器单元与第12个所述移位寄存器单元相互级联，第10个所述移位寄存器单元用于向第12个所述移位寄存器单元提供进位信号；第12个所述移位寄存器单元用于向第10个所述移位寄存器单元提供复位信号；
第12个所述移位寄存器单元还与第10+d个所述移位寄存器单元相互级联，第12个所述移位寄存器单元用于向第10+d个所述移位寄存器单元提供进位信号；第10+d个所述移位寄存器单元用于向第12个所述移位寄存器单元提供复位信号；
第14个所述移位寄存器单元与第16个所述移位寄存器单元相互级联，第14个所述移位寄存器单元用于向第16个所述移位寄存器单元提供进位信号；第16个所述移位寄存器单元用于向第14个所述移位寄存器单元提供复位信号；
第16个所述移位寄存器单元还与第14+d个所述移位寄存器单元相互级联，第16个所述移位寄存器单元用于向第14+d个所述移位寄存器单元提供进位信号；第14+d个所述移位寄存器单元用于向第16个所述移位寄存器单元提供复位信号。
可选的，s为1，连接至第i条栅线的所述移位寄存器单元为第i个所述移位寄存器单元；
其中，第1个所述移位寄存器单元与第2个所述移位寄存器单元相互级联，第1个所述移位寄存器单元用于向第2个所述移位寄存器单元提供进位信号；第2个所述移位寄存器单元用于向第1个所述移位寄存器单元提供复位信号；
第2个所述移位寄存器单元还与第1+d个所述移位寄存器单元相互级联，第2个所述移位寄存器单元用于向第1+d个所述移位寄存器单元提供进位信号；第1+d个所述移位寄存器单元用于向第2个所述移位寄存器单元提供复位信号；
第3个所述移位寄存器单元与第4个所述移位寄存器单元相互级联，第3个所述移位寄存器单元用于向第4个所述移位寄存器单元提供进位信号；第4个所述移位寄存器单元用于向第3个所述移位寄存器单元提供复位信号；
第4个所述移位寄存器单元还与第3+d个所述移位寄存器单元相互级联，第4个所述移位寄存器单元用于向第3+d个所述移位寄存器单元提供进位信号；第3+d个所述移位寄存器单元用于向第4个所述移位寄存器单元提供复位信号；
第5个所述移位寄存器单元与第6个所述移位寄存器单元相互级联，第5个所述移位寄存器单元用于向第6个所述移位寄存器单元提供进位信号；第6个所述移位寄存器单元用于向第5个所述移位寄存器单元提供复位信号；
第6个所述移位寄存器单元还与第5+d个所述移位寄存器单元相互级联，第6个所述移位寄存器单元用于向第5+d个所述移位寄存器单元提供进位信号；第5+d个所述移位寄存器单元用于向第6个所述移位寄存器单元提供复位信号；
第7个所述移位寄存器单元与第8个所述移位寄存器单元相互级联，第7个所述移位寄存器单元用于向第8个所述移位寄存器单元提供进位信号；第8个所述移位寄存器单元用于向第7个所述移位寄存器单元提供复位信号；
第8个所述移位寄存器单元还与第7+d个所述移位寄存器单元相互级联，第8个所述移位寄存器单元用于向第7+d个所述移位寄存器单元提供进位信号；第7+d个所述移位寄存器单元用于向第8个所述移位寄存器单元提供复位信号；
第9个所述移位寄存器单元与第10个所述移位寄存器单元相互级联，第9个所述移位寄存器单元用于向第10个所述移位寄存器单元提供进位信号；第10个所述移位寄存器单元用于向第9个所述移位寄存器单元提供复位信号；
第10个所述移位寄存器单元还与第9+d个所述移位寄存器单元相互级联， 第10个所述移位寄存器单元用于向第9+d个所述移位寄存器单元提供进位信号；第9+d个所述移位寄存器单元用于向第10个所述移位寄存器单元提供复位信号；
第11个所述移位寄存器单元与第12个所述移位寄存器单元相互级联，第11个所述移位寄存器单元用于向第12个所述移位寄存器单元提供进位信号；第12个所述移位寄存器单元用于向第11个所述移位寄存器单元提供复位信号；
第12个所述移位寄存器单元还与第11+d个所述移位寄存器单元相互级联，第12个所述移位寄存器单元用于向第11+d个所述移位寄存器单元提供进位信号；第11+d个所述移位寄存器单元用于向第12个所述移位寄存器单元提供复位信号；
第13个所述移位寄存器单元与第14个所述移位寄存器单元相互级联，第13个所述移位寄存器单元用于向第14个所述移位寄存器单元提供进位信号；第14个所述移位寄存器单元用于向第13个所述移位寄存器单元提供复位信号；
第14个所述移位寄存器单元还与第13+d个所述移位寄存器单元相互级联，第14个所述移位寄存器单元用于向第13+d个所述移位寄存器单元提供进位信号；第13+d个所述移位寄存器单元用于向第14个所述移位寄存器单元提供复位信号；
第15个所述移位寄存器单元与第16个所述移位寄存器单元相互级联，第15个所述移位寄存器单元用于向第16个所述移位寄存器单元提供进位信号；第16个所述移位寄存器单元用于向第15个所述移位寄存器单元提供复位信号；
第16个所述移位寄存器单元还与第15+d个所述移位寄存器单元相互级联，第16个所述移位寄存器单元用于向第15+d个所述移位寄存器单元提供进位信号；第15+d个所述移位寄存器单元用于向第16个所述移位寄存器单元提供复位信号。
可选的，所述显示基板共包括：第一开启信号端、第二开启信号端、第三开启信号端和第四开启信号端共四个开启信号端；
所述第一移位电路中，第一个所述移位寄存器子组中的第一个所述移位寄存器单元，以及第二个所述移位寄存器子组中的第一个所述移位寄存器单元与所述第一开启信号端连接；
所述第二移位电路中，第一个所述移位寄存器子组中的第一个所述移位寄 存器单元，以及第二个所述移位寄存器子组中的第一个所述移位寄存器单元与所述第三开启信号端连接；
所述第三移位电路中，第一个所述移位寄存器子组中的第一个所述移位寄存器单元，以及第二个所述移位寄存器子组中的第一个所述移位寄存器单元与所述第二开启信号端连接；
所述第四移位电路中，第一个所述移位寄存器子组中的第一个所述移位寄存器单元，以及第二个所述移位寄存器子组中的第一个所述移位寄存器单元与所述第四开启信号端连接。
可选的，位于同一行的各个像素均按第一颜色、第二颜色和第三颜色依次排布，位于同一列的各个像素的颜色相同。
可选的，与同一条所述数据线连接的两个相邻的所述像素组中，各个像素均位于不同列。
可选的，每条所述数据线均包括：多条数据线段和多条连接线段；
其中，每条所述连接线段的两端分别与相邻的两条所述数据线段连接；每个所述像素组与一条所述数据线段对应，且任意相邻的两条所述数据线段分别位于相邻行不同列像素组包括的两个像素之间。
可选的，与同一条所述数据线连接的两个相邻的所述像素组中，至少两个像素位于同一列。
另一方面，提供了一种显示基板的驱动方法，用于驱动如上述方面所述的显示基板，所述方法包括：
向所述显示基板中的各个开启信号端依次提供开启信号，每个所述移位电路响应于所述开启信号，向所连接的每条所述栅线提供栅极驱动信号；
向所述显示基板中的每条数据线提供数据信号，所述显示基板中的每个像素响应于所连接的所述栅线提供的栅极驱动信号和所连接的所述数据线提供的数据信号发光。
可选的，所述显示基板包括：第一移位电路、第二移位电路、第三移位电路和第四移位电路共四个移位电路，以及第一开启信号端、第二开启信号端、第三开启信号端和第四开启信号端共四个开启信号端；其中，所述第一开启信号端与所述第一移位电路连接，所述第三开启信号端与所述第二移位电路连接，所述第二开启信号端与所述第三移位电路连接，所述第四开启信号端与所述第 四移位电路连接；
所述向所述显示基板中的各个开启信号端依次提供开启信号，包括：
依次向所述第一开启信号端、所述第三开启信号端、所述第二开启信号端和所述第四开启信号端提供开启信号。
可选的，每个所述移位电路包括至少四个移位寄存器单元，每个所述移位寄存器单元与一条栅线连接，且每个所述移位电路中的至少四个移位寄存器单元能够划分为两个移位寄存器组；每个所述移位寄存器组包括级联的多个所述移位寄存器单元，且每个所述移位寄存器组中的一个所述移位寄存器单元与所述开启信号端连接；每个所述移位寄存器组包括多个移位寄存器子组，每个所述移位寄存器子组包括相邻且级联的两个所述移位寄存器单元，且每个所述移位寄存器子组中的两个所述移位寄存器单元分别与相邻的第i条栅线和第i+2条栅线连接，i为正整数；
所述每个所述移位电路响应于所述开启信号，向所连接的每条所述栅线提供栅极驱动信号，包括依次执行的以下步骤：
所述第一移位电路中，与第一条栅线连接的移位寄存器单元响应于所述第一开启信号端提供的开启信号，向所述第一条栅线提供栅极驱动信号，并向与第三条栅线连接的移位寄存器单元提供进位信号；
所述第二移位电路中，与第五条栅线连接的移位寄存器单元响应于所述第三开启信号端提供的开启信号，向所述第五条栅线提供栅极驱动信号，并向与第七条栅线连接的移位寄存器单元提供进位信号；
所述第一移位电路中，与第九条栅线连接的移位寄存器单元响应于所述第一开启信号端提供的开启信号，向所述第九条栅线提供栅极驱动信号，并向与第十一条栅线连接的移位寄存器单元提供进位信号；
所述第二移位电路中，与第十三条栅线连接的移位寄存器单元响应于所述第三开启信号端提供的开启信号，向所述第十三条栅线提供栅极驱动信号，并向与第十五条栅线连接的移位寄存器单元提供进位信号；
所述第一移位电路中，与所述第三条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第三条栅线提供栅极驱动信号；
所述第二移位电路中，与所述第七条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第七条栅线提供栅极驱动信号；
所述第一移位电路中，与所述第十一条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十一条栅线提供栅极驱动信号；
所述第二移位电路中，与所述第十五条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十五条栅线提供栅极驱动信号；
所述第三移位电路中，与第二条栅线连接的移位寄存器单元响应于所述第二开启信号端提供的开启信号，向所述第二条栅线提供栅极驱动信号，并向与第四条栅线连接的移位寄存器单元提供进位信号；
所述第四移位电路中，与第六条栅线连接的移位寄存器单元响应于所述第四开启信号端提供的开启信号，向所述第六条栅线提供栅极驱动信号，并向与第八条栅线连接的移位寄存器单元提供进位信号；
所述第三移位电路中，与第十条栅线连接的移位寄存器单元响应于所述第二开启信号端提供的开启信号，向所述第十条栅线提供栅极驱动信号，并向与第十二条栅线连接的移位寄存器单元提供进位信号；
所述第四移位电路中，与第十四条栅线连接的移位寄存器单元响应于所述第四开启信号端提供的开启信号，向所述第十四条栅线提供栅极驱动信号，并向与第十六条栅线连接的移位寄存器单元提供进位信号；
所述第三移位电路中，与所述第四条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第四条栅线提供栅极驱动信号；
所述第四移位电路中，与所述第八条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第八条栅线提供栅极驱动信号；
所述第三移位电路中，与所述第十二条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十二条栅线提供栅极驱动信号；
所述第四移位电路中，与所述第十六条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十六条栅线提供栅极驱动信号。
可选的，每个所述移位电路包括至少四个移位寄存器单元，每个所述移位寄存器单元与一条栅线连接，且每个所述移位电路中的至少四个移位寄存器单元能够划分为两个移位寄存器组；每个所述移位寄存器组包括级联的多个所述移位寄存器单元，且每个所述移位寄存器组中的一个所述移位寄存器单元与所述开启信号端连接；每个所述移位寄存器组包括多个移位寄存器子组，每个所述移位寄存器子组包括相邻且级联的两个所述移位寄存器单元，且每个所述移 位寄存器子组中的两个所述移位寄存器单元分别与相邻的第i条栅线和第i+1条栅线连接，i为正整数；
所述每个所述移位电路响应于所述开启信号，向所连接的每条所述栅线提供栅极驱动信号，包括依次执行的以下步骤：
所述第一移位电路中，与第一条栅线连接的移位寄存器单元响应于所述第一开启信号端提供的开启信号，向所述第一条栅线提供栅极驱动信号，并向与第二条栅线连接的移位寄存器单元提供进位信号；
所述第二移位电路中，与第五条栅线连接的移位寄存器单元响应于所述第三开启信号端提供的开启信号，向所述第五条栅线提供栅极驱动信号，并向与第六条栅线连接的移位寄存器单元提供进位信号；
所述第一移位电路中，与第九条栅线连接的移位寄存器单元响应于所述第一开启信号端提供的开启信号，向所述第九条栅线提供栅极驱动信号，并向与第十条栅线连接的移位寄存器单元提供进位信号；
所述第二移位电路中，与第十三条栅线连接的移位寄存器单元响应于所述第三开启信号端提供的开启信号，向所述第十三条栅线提供栅极驱动信号，并向与第十四条栅线连接的移位寄存器单元提供进位信号；
所述第三移位电路中，与第三条栅线连接的移位寄存器单元响应于所述第二开启信号端提供的开启信号，向所述第三条栅线提供栅极驱动信号，并向与第四条栅线连接的移位寄存器单元提供进位信号；
所述第四移位电路中，与第七条栅线连接的移位寄存器单元响应于所述第四开启信号端提供的开启信号，向所述第七条栅线提供栅极驱动信号，并向与第八条栅线连接的移位寄存器单元提供进位信号；
所述第三移位电路中，与第十一条栅线连接的移位寄存器单元响应于所述第二开启信号端提供的开启信号，向所述第十一条栅线提供栅极驱动信号，并向与第十二条栅线连接的移位寄存器单元提供进位信号；
所述第四移位电路中，与第十五条栅线连接的移位寄存器单元响应于所述第四开启信号端提供的开启信号，向所述第十五条栅线提供栅极驱动信号，并向与第十六条栅线连接的移位寄存器单元提供进位信号；
所述第一移位电路中，与所述第二条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第二条栅线提供栅极驱动信号；
所述第二移位电路中，与所述第六条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第六条栅线提供栅极驱动信号；
所述第一移位电路中，与所述第十条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十条栅线提供栅极驱动信号；
所述第二移位电路中，与所述第十四条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十四条栅线提供栅极驱动信号；
所述第三移位电路中，与所述第四条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第四条栅线提供栅极驱动信号；
所述第四移位电路中，与所述第八条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第八条栅线提供栅极驱动信号；
所述第三移位电路中，与所述第十二条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十二条栅线提供栅极驱动信号；
所述第四移位电路中，与所述第十六条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十六条栅线提供栅极驱动信号。
又一方面，提供了一种显示装置，所述显示装置包括：信号提供电路，以及如上述方面所述的显示基板；
所述信号提供电路与所述显示基板中的开启信号端连接，用于为所述开启信号端提供开启信号。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示基板的结构示意图；
图2是本申请实施例提供的另一种显示基板的结构示意图；
图3是本申请实施例提供的又一种显示基板的结构示意图；
图4是本申请实施例提供的再一种显示基板的结构示意图；
图5是本申请实施例提供的再一种显示基板的结构示意图；
图6是本申请实施例提供的再一种显示基板的结构示意图；
图7是本申请实施例提供的再一种显示基板的结构示意图；
图8是本申请实施例提供的再一种显示基板的结构示意图；
图9是本申请实施例提供的一种显示基板的信号时序图；
图10是本申请实施例提供的另一种显示基板的信号时序图；
图11是本申请实施例提供的一种数据线提供的数据信号波形图；
图12是相关技术中的一种数据线提供的数据信号波形图；
图13是本申请实施例提供的一种显示基板的驱动方法流程图；
图14是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
图1是本申请实施例提供的一种显示基板的结构示意图。如图1所示，该显示基板可以包括：衬底基板01，位于衬底基板01上的多条栅线G1至Gm，多条数据线D1至Dk，以及阵列排布的多行像素(图中未标识)，m和k均为大于0的整数。其中，每行像素可以包括多个像素组02，每个像素组02可以包括相邻且颜色不同的两个像素021，且该两个像素021可以分别与不同条栅线和同一条数据线连接。即，参考图1，位于同一行的多个像素021可以与两条栅线连接，且与同一条数据线连接的两个像素021可以分别连接至不同的栅线。
例如，对于位于第一行且相邻的第一个像素021和第二个像素021而言，第一个像素021与第一条栅线G1连接，第二个像素021与第二条栅线G2连接，且第一个像素021和第二个像素021均与第一条数据线D1连接。如此可以看出，显示基板中所需设置的数据线的数量k仅为像素列数的1/2，相应的，绑定区中引线数量也相对减少，有利于窄边框的实现。基于图1所示连接方式可知，本申请实施例记载的显示基板为之字形(zigzag)架构的显示基板。
可选的，本申请实施例提供的显示基板还可以包括：位于衬底基板01上的多个移位电路，每个移位电路可以分别与一个开启信号端和多条栅线中的至少两条栅线连接。每个移位电路可以用于响应于开启信号端提供的开启信号，向所连接的每条栅线提供栅极驱动信号。即，每个移位电路可以在所连接的开启信号端提供开启信号时，向所连接的每条栅线提供栅极驱动信号。此外，在本 申请实施例中，每个移位电路所连接的多个像素021中，与同一条数据线连接的各个像素021的颜色相同。
例如，图1示出的显示基板共包括4个移位电路03a、03b、03c和03d，其中，两个移位电路03a和03c位于栅线延伸方向的一侧，两个移位电路03b和03d位于栅线延伸方向的另一侧。移位电路03a分别与开启信号端STV1、第一条栅线G1、第三条栅线G3以及第m-1条栅线Gm-1连接，且第一条栅线G1、第三条栅线G3以及第m-1条栅线Gm-1连接的各个像素021，即移位电路03a连接的各个像素021中，与第一条数据线D1连接的各个像素021(即位于第一行第一列的像素021，第二行第一列的像素021和第m行第一列的像素021)颜色可以均为红色(red，R)。
移位电路03b分别与开启信号端STV2、第二条栅线G2、第四条栅线G4以及第m条栅线Gm连接，且第二条栅线G2、第四条栅线G4以及第m条栅线Gm连接的各个像素021，即移位电路03b连接的各个像素021中，与第一条数据线D1连接的各个像素021(即位于第一行第二列的像素021，第二行第二列的像素021和第m行第二列的像素021)颜色可以均为绿色(green，G)。
移位电路03c分别与开启信号端STV3、第五条栅线G5和第七条栅线G7连接，且第五条栅线G5和第七条栅线G7连接的各个像素021，即移位电路03c连接的各个像素021中，与第二条数据线D2连接的各个像素021(即位于第三行第三列的像素021和第四行第三列的像素021)的颜色可以均为蓝(blue，B)色。
移位电路03d分别与开启信号端STV4、第六条栅线G6和第八条栅线G8连接，且第六条栅线G6和第八条栅线G8连接的各个像素021，即移位电路03d连接的各个像素021中，与第二条数据线D2连接的各个像素021(即位于第三行第四列的像素021和第四行第四列的像素021)的颜色可以均为红色R。
当然，上述四个移位电路03a至03d中的每个移位电路不仅与图1示出的几条栅线连接，还与其他图1未示出的栅线连接，在此不再赘述。
以连接至开启信号端STV1的移位电路03a为例，当开启信号端STV1提供开启信号时，该移位电路03a可以依次向栅线G1、栅线G3和栅线Gm-1提供栅极驱动信号，然后，第一条数据线D1即可以依次向位于第一行第一列的像素021，第二行第一列的像素021和第m行第一列的像素021提供数据信号。基于 上述记载，由于第一行第一列的像素021，第二行第一列的像素021和第m行第一列的像素021的颜色相同，因此即使得第一条数据线D1可以连续向相同颜色像素提供数据信号。如此，在显示纯色画面时，第一条数据线D1提供的数据信号的电位无需不断翻转，有效降低了功耗。其他数据线同理，在此不再赘述。
综上所述，本申请实施例通过了一种显示基板，由于该显示基板中，每个移位电路所连接的多个像素中，共用同一条数据线的各个像素的颜色相同，且每个移位电路与一个开启信号端连接，因此可以通过灵活控制开启信号端提供的开启信号，使得每条数据线可以连续向相同颜色的像素提供数据信号。如此，在显示纯色画面时，每条数据线上的电位翻转次数较少，有效降低了显示装置的功耗。
图2是本申请实施例提供的另一种显示基板的结构示意图。结合图1和图2可以看出，位于同一行的各个像素021可以均按第一颜色、第二颜色和第三颜色依次排布。可选的，第一颜色可以为红色R，第二颜色可以为绿色G，第三颜色可以为蓝色B。即，如图2所示，显示基板中的每行像素021均可以按照RGB的颜色依次排布。当然，显示基板中的像素也不限于RGB三个颜色，也可以包括黄色(yello，Y)和白色(white，W)等其他颜色。
此外，与同一条数据线连接的两个相邻的像素组02中。各个像素021可以均位于不同列。或者，与同一条数据线连接的两个相邻的像素组02中，至少两个像素021可以位于同一列。
例如，参考图2，以第二条数据线D2为例，与该数据线D2连接且位于第一行和第二行的像素组02中，位于第一行的像素组02中的一个像素B位于第三列，另一个像素R位于第四列；位于第二行的像素组02中的一个像素R位于第一列，另一个像素G位于第二列。即，均位于不同列。
对于上述记载的排布方式，每条数据线均可以呈弓形排布于衬底基板01上。即，每条数据线均可以包括：多条数据线段和多条连接线段，其中，每条连接线段的两端分别与相邻的两条数据线段连接；每个像素组与一条数据线段对应，且任意相邻的两条数据线段分别位于相邻行不同列像素组包括的两个像素之间。此外，本申请实施例对弓形排布的每条数据线的相邻两个开口的方向不做限定。下述实施例均以图2所示显示基板为例进行说明。
结合图1，以移位电路03a和03b为例，图3示出了另一种显示基板的结构示意图。参考图3可以看出，每个移位电路可以包括：至少四个移位寄存器单元，每个移位寄存器单元可以与一条栅线连接。进而可知，由于显示基板共包括m条栅线G1至Gm，因此结合图1和图3，显示基板可以共包括m个移位寄存器单元GOA1至GOAm，其中，第一个移位寄存器单元GOA1可以与第一条栅线G1连接，以此类推。
可选的，显示基板中的多个移位电路所连接的时钟信号端的数量d可以为4的整数倍。即，显示基板中的多行像素可以采用4的整数倍相时钟驱动。或者，多个移位电路所连接的时钟信号端的数量也可以为2的整数倍。
例如，假设多个移位电路所连接的时钟信号端d的数量为16，则显示基板中的多行像素即是采用16相时钟驱动。结合图4和图5所示显示基板，采用16相时钟驱动也即是：从第一个移位寄存器单元GOA1开始，每相邻的16个移位寄存器单元依次与16个时钟信号端CLK1至CLK16连接。本申请下述实施例均以采用16相时钟为例，对显示基板进行说明。
可选的，结合图1以及下述图6至图8可以看出：显示基板可以共包括：第一移位电路03a、第二移位电路03b、第三移位电路03c和第四移位电路03d共4个移位电路。且，第一移位电路03a和第二移位电路03b可以位于多行像素0的一侧，第三移位电路03c和第四移位电路03d可以位于多行像素的另一侧。进而，共包括四个开启信号端STV1至STV4，第一移位电路03a与开启信号端STV1连接，第二移位电路03b与开启信号端STV3连接，第三移位电路03c与开启信号端STV2连接，死低移位电路03d与开启信号端STV4连接。
再者，参考图6和图8还可以看出：每个移位电路中的至少四个移位寄存器单元能够被划分为两个移位寄存器组031，且每个移位寄存器组031又可以包括多个移位寄存器子组0311。其中，每个移位寄存器组031可以包括相互级联的多个移位寄存器单元，每个移位寄存器子组0311可以包括相邻且级联的两个移位寄存器单元。且开启信号端仅与一个移位寄存器组031中的一个移位寄存器单元连接。例如，图7和图8示出的显示基板中，每个移位寄存器组031中，均是第一个移位寄存器子组0311中的第一个移位寄存器单元(如，GOA1、GOA9、GOA5和GOA13)与开启信号端连接。
需要说明的是，结合图6和图7可以看出，沿自第一行至最后一行的目标 方向，每个移位寄存器组031中的多个移位寄存器子组0311依次排布，且每个移位寄存器子组0311中的两个移位寄存器单元依次排布。相应的，每个移位寄存器组031中的第一个移位寄存器子组0311即可以是指目标方向起始位置处的一个移位寄存器子组。例如，对于移位电路03a包括的第一个移位寄存器组031而言，其包括的第一个移位寄存器子组0311是指包括GOA1和GOA3的移位寄存器子组。每个移位寄存器子组0311包括的第一个移位寄存器单元即可以是指位于目标方向起始位置处的移位寄存器单元。例如，对于包括GOA1和GOA3的移位寄存器子组0311，其包括的第一个移位寄存器单元即是指GOA1。
再结合图6至图8，位于多行像素的一侧的第2n-1个移位寄存器子组0311可以属于第一移位电路03a，位于多行像素的一侧的第2n个移位寄存器子组0311可以属于第二移位电路03b。位于多行像素的另一侧的第2n-1个移位寄存器子组0311可以属于第三移位电路03c，位于多行像素的另一侧的第2n个移位寄存器子组0311可以属于第四移位电路03d，n可以为正整数。即位于同一侧且序号为奇数的移位寄存器子组0311可以属于同一个移位电路，位于同一侧序号为偶数的移位寄存器子组0311可以属于同一个移位电路。
在该实现方式下，对于第一移位电路03a和第二移位电路03b而言，位于其所在侧的第4n-3个移位寄存器子组0311可以属于第一移位电路03a中的一个移位寄存器组031，第4n-1个移位寄存器子组0311可以属于第一移位电路03a中的另一个移位寄存器组031。第4n-2个移位寄存器子组0311可以属于第二移位电路03b中的一个移位寄存器组031，第4n个移位寄存器子组0311可以属于第二移位电路03b中的另一个移位寄存器组031。对于第三移位电路03c和第四移位电路03d而言，位于其所在侧的第4n-3个移位寄存器子组0311可以属于第三移位电路03c中的一个移位寄存器组031，第4n-1个移位寄存器子组0311可以属于第三移位电路03c中的另一个移位寄存器组031。第4n-2个移位寄存器子组0311可以属于第四移位电路03d中的一个移位寄存器组031。第4n个移位寄存器子组0311可以属于第四移位电路03d中的另一个移位寄存器组031。
例如，参考图6至图8，第一移位电路03a和第二移位电路03b所在侧，沿第一行像素至最后一行像素的方向，第1个移位寄存器子组0311和第5个移位寄存器子组0311属于第一移位电路03a中的一个移位寄存器组031。第2个移位寄存器子组0311和第6个移位寄存器子组0311属于第二移位电路03b中的 一个移位寄存器组031。第3个移位寄存器子组0311和第7个移位寄存器子组0311属于第一移位电路03a中的另一个移位寄存器组031。第4个移位寄存器子组0311和第8个移位寄存器子组0311属于第二移位电路03b中的另一个移位寄存器组031。第三移位电路03c和第四移位电路03d所在侧同理，第1个移位寄存器子组0311和第5个移位寄存器子组0311属于第三移位电路03c中的一个移位寄存器组031。第2个移位寄存器子组0311和第6个移位寄存器子组0311属于第四移位电路03d中的一个移位寄存器组031。第3个移位寄存器子组0311和第7个移位寄存器子组0311属于第三移位电路03c中的另一个移位寄存器组031。第4个移位寄存器子组0311和第8个移位寄存器子组0311属于第四移位电路03d中的另一个移位寄存器组031。
再例如，结合图6和图7所示显示基板，沿第一行像素至最后一行像素的方向，以第一移位电路03a中的第一个移位寄存器组031为例，该移位寄存器组031中的第一个移位寄存器子组0311包括的移位寄存器单元GOA1和GOA3相互级联，且移位寄存器单元GOA3与第二个移位寄存器子组0311中的移位寄存器单元GOA17相互级联，移位寄存器单元GOA17还与第二个移位寄存器子组0311中的移位寄存器单元GOA19互级联。且该移位寄存器组031中，第一个移位寄存器子组0311的第一个移位寄存器单元GOA1与开启信号端STV1连接。以此类推。
可选的，在本申请实施例中，每个移位寄存器子组0311中的两个移位寄存器单元可以分别与第i条栅线和第i+s条栅线连接，i为正整数，s可以为1或2。
例如，图4、图6和图7示出的显示基板中，s为2。即序号为奇数的移位寄存器单元位于同一侧，序号为偶数的移位寄存器单元位于同一侧。如此，可以实现同行像素被位于两侧的移位寄存器单元同时驱动。即同行像素双边驱动。
假设连接至第i条栅线的移位寄存器单元为第i个移位寄存器单元，时钟信号数量d为16。则结合图4、图6和图7，对显示基板的级联关系进行下述说明：
其中，第1个移位寄存器单元GOA1与第3个移位寄存器单元GOA3相互级联，第1个移位寄存器单元GOA1可以用于向第3个移位寄存器单元GOA3提供进位信号。第3个移位寄存器单元可以用于向第1个移位寄存器单元GOA1提供复位信号。
第3个移位寄存器单元GOA3还与第1+16，即第17个移位寄存器单元相 互级联(图中未示出)，第3个移位寄存器单元GOA3可以用于向第17个移位寄存器单元提供进位信号。第17个移位寄存器单元用于向第3个移位寄存器单元GOA3提供复位信号。
第5个移位寄存器单元GOA5与第7个移位寄存器单元GOA7相互级联，第5个移位寄存器单元GOA5可以用于向第7个移位寄存器单元GOA7提供进位信号。第7个移位寄存器单元GOA7可以用于向第5个移位寄存器单元GOA5提供复位信号。
第7个移位寄存器单元GOA7还与第5+16，即第21个移位寄存器单元相互级联(图中未示出)，第7个移位寄存器单元GOA7可以用于向第21个移位寄存器单元提供进位信号。第21个移位寄存器单元可以用于向第7个移位寄存器单元GOA7提供复位信号。
第9个移位寄存器单元GOA9与第11个移位寄存器单元GOA11相互级联，第9个移位寄存器单元GOA9用于向第11个移位寄存器单元GOA11提供进位信号。第11个移位寄存器单元GOA11用于向第9个移位寄存器单元GOA9提供复位信号。
第11个移位寄存器单元GOA11还与第9+16，即第25个移位寄存器单元相互级联(图中未示出)，第11个移位寄存器单元GOA11用于向第25个移位寄存器单元提供进位信号。第25个移位寄存器单元用于向第11个移位寄存器单元GOA11提供复位信号。
第13个移位寄存器单元GOA13与第15个移位寄存器单元GOA15相互级联，第13个移位寄存器单元GOA13用于向第15个移位寄存器单元GOA15提供进位信号。第15个移位寄存器单元GOA15用于向第13个移位寄存器单元GOA13提供复位信号。
第15个移位寄存器单元GOA15还与第13+16，即第29个移位寄存器单元相互级联(图中未示出)，第15个移位寄存器单元GOA15用于向第29个移位寄存器单元提供进位信号。第29个移位寄存器单元用于向第15个移位寄存器单元GOA15提供复位信号。
第2个移位寄存器单元GOA2可以与第4个移位寄存器单元GOA4相互级联，第2个移位寄存器单元GOA2用于向第4个移位寄存器单元GOA4提供进位信号。第4个移位寄存器单元GOA4用于向第2个移位寄存器单元GOA2提 供复位信号。
第4个移位寄存器单元GOA4还与第2+16，即第18个移位寄存器单元相互级联(图中未示出)，第4个移位寄存器单元GOA4用于向第18个移位寄存器单元提供进位信号。第18个移位寄存器单元用于向第4个移位寄存器单元GOA4提供复位信号。
第6个移位寄存器单元GOA6与第8个移位寄存器单元GOA8相互级联，第6个移位寄存器单元GOA6用于向第8个移位寄存器单元GOA8提供进位信号。第8个移位寄存器单元GOA8用于向第6个移位寄存器单元GOA6提供复位信号。
第8个移位寄存器单元GOA8还与第6+16，即第22个移位寄存器单元相互级联(图中未示出)，第8个移位寄存器单元GOA8可以用于向第22个移位寄存器单元提供进位信号。第22个移位寄存器单元用于向第8个移位寄存器单元GOA8提供复位信号。
第10个移位寄存器单元GOA10与第12个移位寄存器单元GOA12相互级联，第10个移位寄存器单元GOA10用于向第12个移位寄存器单元GOA12提供进位信号。第12个移位寄存器单元GOA12用于向第10个移位寄存器单元GOA10提供复位信号。
第12个移位寄存器单元GOA12还与第10+16，即第26个移位寄存器单元相互级联(图中未示出)，第12个移位寄存器单元GOA12用于向第26个移位寄存器单元提供进位信号。第26个移位寄存器单元用于向第12个移位寄存器单元GOA12提供复位信号。
第14个移位寄存器单元GOA14与第16个移位寄存器单元GOA16相互级联，第14个移位寄存器单元GOA14用于向第16个移位寄存器单元GOA16提供进位信号。第16个移位寄存器单元GOA16用于向第14个移位寄存器单元GOA14提供复位信号。
第16个移位寄存器单元GOA16还与第14+16，即第30个移位寄存器单元相互级联(图中未示出)，第16个移位寄存器单元GOA16用于向第30个移位寄存器单元提供进位信号。第30个移位寄存器单元用于向第16个移位寄存器单元GOA16提供复位信号。
例如，图5和图8示出的显示基板中，s为1。如此，可以实现同行像素被 位于同一侧的移位寄存器单元同时驱动。即，同行像素同边驱动。
假设连接至第i条栅线的移位寄存器单元为第i个移位寄存器单元，时钟信号数量d为16。则结合图5和图8，对显示基板的级联关系进行下述说明：
其中，第1个移位寄存器单元GOA1与第2个移位寄存器单元GOA2相互级联，第1个移位寄存器单元GOA1可以用于向第2个移位寄存器单元GOA2提供进位信号。第2个移位寄存器单元GOA2可以用于向第1个移位寄存器单元GOA1提供复位信号。
第2个移位寄存器单元GOA2还与第1+16，即第17个移位寄存器单元相互级联(图中未示出)，第2个移位寄存器单元GOA2可以用于向第17个移位寄存器单元提供进位信号。第17个移位寄存器单元可以用于向第2个移位寄存器单元GOA2提供复位信号。
第3个移位寄存器单元GOA3与第4个移位寄存器单元GOA4相互级联，第3个移位寄存器单元GOA3可以用于向第4个移位寄存器单元GOA4提供进位信号。第4个移位寄存器单元GOA4可以用于向第3个移位寄存器单元GOA3提供复位信号。
第4个移位寄存器单元GOA4还与第3+16，即第19个移位寄存器单元相互级联(图中未示出)，第4个移位寄存器单元GOA4可以用于向第19个移位寄存器单元提供进位信号。第19个移位寄存器单元可以用于向第4个移位寄存器单元GOA4提供复位信号。
第5个移位寄存器单元GOA5与第6个移位寄存器单元GOA6相互级联，第5个移位寄存器单元GOA5可以用于向第6个移位寄存器单元GOA6提供进位信号。第6个移位寄存器单元GOA6可以用于向第5个移位寄存器单元GOA5提供复位信号。
第6个移位寄存器单元GOA6还与第5+16，即第21个移位寄存器单元相互级联(图中未示出)，第6个移位寄存器单元GOA6可以用于向第21个移位寄存器单元提供进位信号。第21个移位寄存器单元可以用于向第6个移位寄存器单元GOA6提供复位信号。
第7个移位寄存器单元GOA7与第8个移位寄存器单元GOA8相互级联，第7个移位寄存器单元GOA7可以用于向第8个移位寄存器单元GOA8提供进位信号。第8个移位寄存器单元GOA8可以用于向第7个移位寄存器单元GOA 7提供复位信号。
第8个移位寄存器单元GOA8还与第7+16，即第23个移位寄存器单元相互级联(图中未示出)，第8个移位寄存器单元GOA8可以用于向第23个移位寄存器单元提供进位信号。第23个移位寄存器单元可以用于向第8个移位寄存器单元GOA8提供复位信号。
第9个移位寄存器单元GOA9与第10个移位寄存器单元GOA10相互级联，第9个移位寄存器单元GOA9可以用于向第10个移位寄存器单元GOA10提供进位信号。第10个移位寄存器单元GOA10可以用于向第9个移位寄存器单元GOA9提供复位信号。
第10个移位寄存器单元GOA10还与第9+16，即第25个移位寄存器单元相互级联(图中未示出)，第10个移位寄存器单元GOA10可以用于向第25个移位寄存器单元提供进位信号。第25个移位寄存器单元可以用于向第10个移位寄存器单元GOA10提供复位信号。
第11个移位寄存器单元GOA11与第12个移位寄存器单元GOA12相互级联，第11个移位寄存器单元GOA11可以用于向第12个移位寄存器单元GOA12提供进位信号。第12个移位寄存器单元GOA12可以用于向第11个移位寄存器单元GOA11提供复位信号。
第12个移位寄存器单元GOA12还与第11+16，即第28个移位寄存器单元相互级联(图中未示出)，第12个移位寄存器单元GOA12可以用于向第28个移位寄存器单元提供进位信号。第28个移位寄存器单元可以用于向第12个移位寄存器单元GOA12提供复位信号。
第13个移位寄存器单元GOA13与第14个移位寄存器单元GOA14相互级联，第13个移位寄存器单元GOA13可以用于向第14个移位寄存器单元GOA14提供进位信号。第14个移位寄存器单元GOA14可以用于向第13个移位寄存器单元GOA13提供复位信号。
第14个移位寄存器单元GOA14还与第13+16，即第29个移位寄存器单元相互级联(图中未示出)，第14个移位寄存器单元GOA14可以用于向第29个移位寄存器单元提供进位信号。第29个移位寄存器单元可以用于向第14个移位寄存器单元GOA14提供复位信号。
第15个移位寄存器单元GOA15与第16个移位寄存器单元GOA16相互级 联，第15个移位寄存器单元GOA15可以用于向第16个移位寄存器单元GOA16提供进位信号。第16个移位寄存器单元GOA16可以用于向第15个移位寄存器单元GOA15提供复位信号。
第16个移位寄存器单元GOA16还与第15+16，即第31个移位寄存器单元相互级联(图中未示出)，第16个移位寄存器单元GOA16可以用于向第31个移位寄存器单元提供进位信号。第31个移位寄存器单元可以用于向第16个移位寄存器单元GOA16提供复位信号。
结合上述实施例记载可知，级联是指在扫描时，前一个位寄存器单元为后一个位寄存器单元提供进位信号，后一个位寄存器单元为前一个位寄存器单元提供复位信号。即，前一个移位寄存器单元的输出端与后一个移位寄存器单元的输入端连接，后一个移位寄存器的单元的输出端与前一个移位寄存器单元的复位端连接。如此，在前一个移位寄存器单元的输出端的电位为有效电位时，后一个移位寄存器单元即可以开启，故前一个位寄存器单元为后一个位寄存器单元提供的信号称为进位信号。在后一个移位寄存器单元的输出端的电位为有效电位时，前一个移位寄存器单元的复位端开始对前一个移位寄存器单元进行降噪，故后一个位寄存器单元为前一个位寄存器单元提供的信号称为进位信号称为复位信号。
如此，对于图7所示显示基板而言，在第一个移位寄存器单元GOA1向第三个移位寄存器单元GOA3提供进位信号时，第三个移位寄存器单元GOA3向第一个移位寄存器单元GOA1提供复位信号，且同时向第十七个移位寄存器单元GOA17提供进位信号，以此类推。
对于图8所示显示基板同理，在第一个移位寄存器单元GOA1向第二个移位寄存器单元GOA2提供进位信号时，第二个移位寄存器单元GOA2向第一个移位寄存器单元GOA1提供复位信号，且同时向第十七个移位寄存器单元GOA17提供进位信号，以此类推。
此外，图8所示显示基板相对于图7所示显示基板，因GOA1和GOA2相互级联，故可以确定是每相邻两个时钟信号端提供的时钟信号电位互补，由此可以进一步确定像素充电的时间可调范围较大。
基于图7所示显示基板，图9示出了一种时序图。基于图8所示显示基板，图10示出了另一种时序图。参考图9和图10所示时序图均可以看出，开启信 号端STV1、STV3、STV2和STV4是依次提供开启信号，且CLK1、CLK5、CLK9、CLK13、CLK3、CLK7、CLK11、CLK15、CLK2、CLK6、CLK10、CLK14、CLK4、CLK8、CLK12和CLK16是依次开始提供有效电位的时钟信号。
如此，对于图7所示显示基板，结合图9所示时序图可以看出，当开启信号端STV1提供有效电位的开启信号时，GOA1可以先开启，直至GOA1所连接的时钟信号端CLK1提供的时钟信号变为有效电位，GOA1向第一条栅线G1输出有效电位的栅极驱动信号。与此同时，GOA1还向GOA3提供进位信号，GOA3开启。且为了避免GOA3先向所连接的第三条栅线G3提供有效电位的栅极驱动信号，GOA3所连接的时钟信号端CLK3提供的时钟信号保持为无效电位。以此类推。可选的，有效电位相对于无效电位可以为高电位。
对于图8所示显示基板，结合图10所示时序图可以看出，当开启信号端STV1提供有效电位的开启信号时，GOA1可以先开启，直至GOA1所连接的时钟信号端CLK1提供的时钟信号变为有效电位，GOA1向第一条栅线G1输出有效电位的栅极驱动信号。与此同时，GOA1还向GOA2提供进位信号，GOA2开启，且为避免GOA2先向所连接的第二条栅线G2提供有效电位的栅极驱动信号，时钟信号端CLK2提供的时钟信号保持为无效电位。以此类推。
结合CLK1至CLK16提供有效点位的顺序可知，不论是图9还是图10时序驱动对应显示基板，其在扫描时，均可以实现一个周期内，栅线扫描顺序为：G1—>G5—>G9—>G13—>G3—>G7—>G11—>G15—>G2—>G6—>G10—>G14—>G4—>G8—>G12—>G16。即，每四个移位寄存器单元一个循环，栅线跳跃式开启扫描，而不是顺序开启扫描。基于该栅线扫描顺序，可以使得图3所示显示基板中第二条数据线D2、第三条数据线D3和第四条数据线D4在一个周期内向以下颜色的像素依次提供数据信号：
D2：R->R->R->R->R->R->R->R->B->B->B->B->G->G->G->G；
D3：R->R->R->R->B->B->B->B->G->G->G->G->G->G->G->G；
D4：B->B->B->B->R->R->R->R->G->G->G->G->B->B->B->B。
以显示红色画面为例，图11示出了数据线D2在一个周期内的时序图。结合图11可以确定：在显示纯色画面时，数据线D2所提供的数据信号的电位均仅发生了两次翻转。其他数据线同理。
而，若采用相关技术的扫描方式，即控制各条栅线顺序开启，则在显示基 板显示纯色画面时，图3所示显示基板中第二条数据线D2、第三条数据线D3和第四条数据线D4在一个周期内向以下颜色的像素依次提供数据信号：
D2：R->B->R->G->R->B->R->G->R->B->R->G->R->B->R->G；
D3：B->G->R->B->B->G->R->B->B->G->R->B->B->G->R->B；
D4：R->G->B->G->R->G->B->G->R->G->B->G->R->G->B->G。
依然以显示红色画面为例，图12示出了相关技术中数据线D2在一个周期内的时序图。参考图12可以确定：数据线D2提供的数据信号的电位在一个周期里翻转了16次。此外，结合上述提供数据信号的顺序可以确定，数据线D3提供的数据信号的电位在一个周期里翻转了8次，数据线D4提供的数据信号的电位在一个周期里翻转了8次。其三条数据线一共翻转了32次。
其中，一次翻转可以是指：由有效电位翻转为无效电位，或，由无效电位翻转为有效电位。假设无效电位为0伏特(V)，有效电位为5V，则对比图11和图12可以看出，相关技术中的每条数据线上的电位需要多次在0V至5V转换。而由于本申请实施例提供的数据线提供的数据信号的电位翻转次数减少，故相应的，电位在0V至5V之间切换频率较低，功耗降低。
并且，若采用常规依次级联的方式来实现本申请实施例记载的扫描顺序，需要设置GOA1连接第一条栅线G1，GOA2连接第五条栅线G5，GOA3连接第九条栅线G9，以此类推。该连线方式较为复杂，难以实现。故，本申请实施例通过设置图7或图8所示移位寄存器单元排布方式，既减小了布线难度较大，不易于实现的问题，又可靠实现了上述图11所示的扫描方式，降低了功耗。
再者，结合最终确定的扫描顺序“G1—>G5—>G9—>G13—>G3—>G7—>G11—>G15—>G2—>G6—>G10—>G14—>G4—>G8—>G12—>G16”可知，因图7所示显示基板中，G1自开启至所级联的G3开启，仅4个周期；而对于图8所示显示基板，G1自开启至所级联的G2开启，需经8个周期。故，图7相对于图8排布方式而言，G1的开启时长较短，相应的，功耗也较低。
综上所述，本申请实施例通过了一种显示基板，由于该显示基板中，每个移位电路所连接的多个像素中，共用同一条数据线的各个像素的颜色相同，且每个移位电路与一个开启信号端连接，因此可以通过灵活控制开启信号端提供的开启信号，使得每条数据线可以连续向相同颜色的像素提供数据信号。如此，在显示纯色画面时，每条数据线上的电位翻转次数较少，有效降低了显示装置 的功耗。
图13是本申请实施例提供的一种显示基板的驱动方法流程图，该方法可以用于驱动如图1至图8任一所示的显示基板。如图13所示，该方法可以包括：
步骤1301、向显示基板中的各个开启信号端依次提供开启信号，每个移位电路响应于开启信号，向所连接的每条栅线提供栅极驱动信号。
步骤1302、向每条数据线提供数据信号，每个像素响应于所连接的栅线提供的栅极驱动信号和所连接的数据线提供的数据信号发光。
可选的，假设如图7和图8所示，显示基板包括：第一移位电路、第二移位电路、第三移位电路和第四移位电路共四个移位电路，其中，第一移位电路和第二移位电路位于多行像素的一侧，第三移位电路和第四移位电路位于多行像素的另一侧。相应的，参考图9和图10所示时序图可知，向显示基板中的各个开启信号端依次提供开启信号，可以包括：先向第一移位电路和第二移位电路所连接的两个开启信号端依次提供开启信号；然后再向第三移位电路和第四移位电路所连接的两个开启信号端依次提供开启信号。
作为一种可选的实现方式，结合图7所示显示基板，以及图9对应的时序图，对步骤1301进行下述描述，步骤1301可以包括依次执行的下述方法：
第一移位电路中，与第一条栅线G1连接的移位寄存器单元GOA1响应于第一开启信号端STV1提供的开启信号，向第一条栅线G1提供栅极驱动信号，并向与第三条栅线G3连接的移位寄存器单元GOA3提供进位信号。
第二移位电路中，与第五条栅线G5连接的移位寄存器单元GOA5响应于第三开启信号端STV3提供的开启信号，向第五条栅线G5提供栅极驱动信号，并向与第七条栅线G7连接的移位寄存器单元GOA7提供进位信号。
第一移位电路中，与第九条栅线G9连接的移位寄存器单元GOA9响应于第一开启信号端STV1提供的开启信号，向第九条栅线G9提供栅极驱动信号，并向与第十一条栅线G11连接的移位寄存器单元GOA11提供进位信号。
第二移位电路中，与第十三条栅线G13连接的移位寄存器单元GOA13响应于第三开启信号端STV3提供的开启信号，向第十三条栅线G13提供栅极驱动信号，并向与第十五条栅线G15连接的移位寄存器单元GOA15提供进位信号。
第一移位电路中，与第三条栅线G3连接的移位寄存器单元GOA3响应于接 收到的进位信号，向第三条栅线G3提供栅极驱动信号。
第二移位电路中，与第七条栅线G7连接的移位寄存器单元GOA7响应于接收到的进位信号，向第七条栅线G7提供栅极驱动信号。
第一移位电路中，与第十一条栅线G11连接的移位寄存器单元GOA11响应于接收到的进位信号，向第十一条栅线G11提供栅极驱动信号。
第二移位电路中，与第十五条栅线G15连接的移位寄存器单元GOA15响应于接收到的进位信号，向第十五条栅线G15提供栅极驱动信号。
第三移位电路中，与第二条栅线G2连接的移位寄存器单元GOA2响应于第二开启信号端STV2提供的开启信号，向第二条栅线G2提供栅极驱动信号，并向与第四条栅线G4连接的移位寄存器单元GOA4提供进位信号。
第四移位电路中，与第六条栅线G6连接的移位寄存器单元GOA6响应于第四开启信号端STV4提供的开启信号，向第六条栅线G6提供栅极驱动信号，并向与第八条栅线G8连接的移位寄存器单元GOA8提供进位信号。
第三移位电路中，与第十条栅线G10连接的移位寄存器单元GOA10响应于第二开启信号端STV2提供的开启信号，向第十条栅线G10提供栅极驱动信号，并向与第十二条栅线G12连接的移位寄存器单元GOA12提供进位信号。
第四移位电路中，与第十四条栅线G14连接的移位寄存器单元GOA14响应于第四开启信号端STV4提供的开启信号，向第十四条栅线G14提供栅极驱动信号，并向与第十六条栅线G16连接的移位寄存器单元GOA16提供进位信号。
第三移位电路中，与第四条栅线G4连接的移位寄存器单元GOA4响应于接收到的进位信号，向第四条栅线G4提供栅极驱动信号。
第四移位电路中，与第八条栅线G8连接的移位寄存器单元GOA8响应于接收到的进位信号，向第八条栅线G8提供栅极驱动信号。
第三移位电路中，与第十二条栅线G12连接的移位寄存器单元GOA12响应于接收到的进位信号，向第十二条栅线G12提供栅极驱动信号。
第四移位电路中，与第十六条栅线G16连接的移位寄存器单元GOA16响应于接收到的进位信号，向第十六条栅线G16提供栅极驱动信号。
作为另一种可选的实现方式，结合图9所示显示基板，以及图10对应的时序图，对步骤1301进行下述描述，步骤1301可以包括依次执行的下述方法：
第一移位电路中，与第一条栅线G1连接的移位寄存器单元GOA1响应于第 一开启信号端STV1提供的开启信号，向第一条栅线G1提供栅极驱动信号，并向与第二条栅线G2连接的移位寄存器单元GOA2提供进位信号。
第二移位电路中，与第五条栅线G5连接的移位寄存器单元GOA5响应于第三开启信号端STV3提供的开启信号，向第五条栅线G5提供栅极驱动信号，并向与第六条栅线G6连接的移位寄存器单元GOA6提供进位信号。
第一移位电路中，与第九条栅线G9连接的移位寄存器单元GOA9响应于第一开启信号端STV1提供的开启信号，向第九条栅线G9提供栅极驱动信号，并向与第十条栅线G10连接的移位寄存器单元GOA10提供进位信号。
第二移位电路中，与第十三条栅线G13连接的移位寄存器单元GOA13响应于第三开启信号端STV3提供的开启信号，向第十三条栅线G13提供栅极驱动信号，并向与第十四条栅线G14连接的移位寄存器单元GOA14提供进位信号。
第三移位电路中，与第三条栅线G3连接的移位寄存器单元GOA3响应于第二开启信号端STV2提供的开启信号，向第三条栅线G3提供栅极驱动信号，并向与第四条栅线G4连接的移位寄存器单元GOA4提供进位信号。
第四移位电路中，与第七条栅线G7连接的移位寄存器单元GOA7响应于第四开启信号端STV4提供的开启信号，向第七条栅线G7提供栅极驱动信号，并向与第八条栅线G8连接的移位寄存器单元GOA8提供进位信号。
第三移位电路中，与第十一条栅线G11连接的移位寄存器单元GOA11响应于第二开启信号端STV2提供的开启信号，向第十一条栅线G11提供栅极驱动信号，并向与第十二条栅线G12连接的移位寄存器单元GOA12提供进位信号。
第四移位电路中，与第十五条栅线G15连接的移位寄存器单元GOA15响应于第四开启信号端STV4提供的开启信号，向第十五条栅线G15提供栅极驱动信号，并向与第十六条栅线G16连接的移位寄存器单元GOA16提供进位信号。
第一移位电路中，与第二条栅线G2连接的移位寄存器单元GOA2响应于接收到的进位信号，向第二条栅线G2提供栅极驱动信号。
第二移位电路中，与第六条栅线G6连接的移位寄存器单元GOA6响应于接收到的进位信号，向第六条栅线G6提供栅极驱动信号。
第一移位电路中，与第十条栅线G10连接的移位寄存器单元GOA10响应于接收到的进位信号，向第十条栅线G10提供栅极驱动信号。
第二移位电路中，与第十四条栅线G14连接的移位寄存器单元GOA14响应 于接收到的进位信号，向第十四条栅线G14提供栅极驱动信号。
第三移位电路中，与第四条栅线G4连接的移位寄存器单元GOA4响应于接收到的进位信号，向第四条栅线G4提供栅极驱动信号。
第四移位电路中，与第八条栅线G8连接的移位寄存器单元GOA8响应于接收到的进位信号，向第八条栅线G8提供栅极驱动信号。
第三移位电路中，与第十二条栅线G12连接的移位寄存器单元GOA12响应于接收到的进位信号，向第十二条栅线G12提供栅极驱动信号。
第四移位电路中，与第十六条栅线G16连接的移位寄存器单元GOA16响应于接收到的进位信号，向第十六条栅线G16提供栅极驱动信号。
结合上述对步骤1301的记载可知，无论是图7所示显示基板(即，图9所示时序)，还是图8所示显示基板(即，图10所示时序)，均可以实现一个周期内，栅线扫描顺序为：
G1—>G5—>G9—>G13—>G3—>G7—>G11—>G15—>G2—>G6—>G10—>G14—>G4—>G8—>G12—>G16。
综上所述，本申请实施例通过了一种显示基板的驱动方法，由于每个移位电路可以响应于开启信号，向所连接的每条栅线提供栅极驱动信号，且该显示基板中，每个移位电路所连接的多个像素中，共用同一条数据线的各个像素的颜色相同，且每个移位电路与一个开启信号端连接，因此可以通过灵活控制开启信号端提供的开启信号，使得每条数据线可以连续向相同颜色的像素提供数据信号。如此，在显示纯色画面时，每条数据线上的电位翻转次数较少，有效降低了显示装置的功耗。
图14是本申请实施例提供的一种显示装置的结构示意图。如图14所示，该显示装置可以包括：信号提供电路100，以及如图1至图8任一所示的显示基板200。其中，信号提供电路100可以与显示基板200中的开启信号端连接，且可以用于为所述开启信号端提供开启信号。
可选的，该显示装置可以为：有机发光二极管(organic light-emitting diode，OLED)显示装置、手机、平板电脑、电视机、显示器、笔记本电脑或导航仪等任何具有显示功能的产品或部件。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的 精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种显示基板，其中，所述显示基板包括：
    衬底基板；
    位于所述衬底基板上的多条栅线、多条数据线和阵列排布的多行像素，每行所述像素包括多个像素组，每个所述像素组包括相邻且颜色不同的两个像素，且所述两个像素与不同条所述栅线和同一条所述数据线连接；
    位于所述衬底基板上的多个移位电路，每个所述移位电路分别与一个开启信号端和所述多条栅线中的至少两条栅线连接，每个所述移位电路用于响应于所述开启信号端提供的开启信号，向所连接的每条所述栅线提供栅极驱动信号；
    其中，每个所述移位电路连接的多个像素中，与同一条所述数据线连接的像素的颜色相同。
  2. 根据权利要求1所述的显示基板，其中，每个所述移位电路包括：至少四个移位寄存器单元，每个所述移位寄存器单元与一条栅线连接，且每个所述移位电路中的至少四个移位寄存器单元能够划分为两个移位寄存器组；
    其中，每个所述移位寄存器组包括级联的多个所述移位寄存器单元，且每个所述移位寄存器组中的一个所述移位寄存器单元与所述开启信号端连接。
  3. 根据权利要求2所述的显示基板，其中，每个所述移位寄存器组包括多个移位寄存器子组，每个所述移位寄存器子组包括相邻且级联的两个所述移位寄存器单元，且每个所述移位寄存器子组中的两个所述移位寄存器单元分别与相邻的第i条栅线和第i+s条栅线连接，i为正整数，且s为1或2。
  4. 根据权利要求3所述的显示基板，其中，所述显示基板中的多个移位电路所连接的时钟信号端的数量d为4的整数倍。
  5. 根据权利要求4所述的显示基板，其中，所述显示基板中的多个移位电路所连接的时钟信号端的数量d为16。
  6. 根据权利要求5所述的显示基板，其中，所述多个移位电路包括：第一 移位电路、第二移位电路、第三移位电路和第四移位电路共四个移位电路；
    其中，所述第一移位电路和所述第二移位电路位于所述多行像素的一侧，所述第三移位电路和所述第四移位电路位于所述多行像素的另一侧。
  7. 根据权利要求6所述的显示基板，其中，位于所述多行像素的一侧的第2n-1个所述移位寄存器子组属于所述第一移位电路，位于所述多行像素的一侧的第2n个所述移位寄存器子组属于所述第二移位电路，n为正整数；
    位于所述多行像素的另一侧的第2n-1个所述移位寄存器子组属于所述第三移位电路，位于所述多行像素的另一侧的第2n个所述移位寄存器子组属于所述第四移位电路。
  8. 根据权利要求7所述的显示基板，其中，位于所述多行像素的一侧的第4n-3个移位寄存器子组属于所述第一移位电路中的一个移位寄存器组，位于所述多行像素的一侧的第4n-1个移位寄存器子组属于所述第一移位电路中的另一个移位寄存器组；
    位于所述多行像素的一侧的第4n-2个移位寄存器子组属于所述第二移位电路中的一个移位寄存器组；位于所述多行像素的一侧的第4n个移位寄存器子组属于所述第二移位电路中的另一个移位寄存器组；
    位于所述多行像素的另一侧的第4n-3个移位寄存器子组属于所述第三移位电路中的一个移位寄存器组，位于所述多行像素的另一侧的第4n-1个移位寄存器子组属于所述第三移位电路中的另一个移位寄存器组；
    位于所述多行像素的零一侧的第4n-2个移位寄存器子组属于所述第四移位电路中的一个移位寄存器组；位于所述多行像素的另一侧的第4n个移位寄存器子组属于所述第四移位电路中的另一个移位寄存器组。
  9. 根据权利要求5至8任一所述的显示基板，其中，s为2，连接至第i条栅线的所述移位寄存器单元为第i个所述移位寄存器单元；
    其中，第1个所述移位寄存器单元与第3个所述移位寄存器单元相互级联，第1个所述移位寄存器单元用于向第3个所述移位寄存器单元提供进位信号；第3个所述移位寄存器单元用于向第1个所述移位寄存器单元提供复位信号；
    第3个所述移位寄存器单元还与第1+d个所述移位寄存器单元相互级联， 第3个所述移位寄存器单元用于向第1+d个所述移位寄存器单元提供进位信号；第1+d个所述移位寄存器单元用于向第3个所述移位寄存器单元提供复位信号；
    第5个所述移位寄存器单元与第7个所述移位寄存器单元相互级联，第5个所述移位寄存器单元用于向第7个所述移位寄存器单元提供进位信号；第7个所述移位寄存器单元用于向第5个所述移位寄存器单元提供复位信号；
    第7个所述移位寄存器单元还与第5+d个所述移位寄存器单元相互级联，第7个所述移位寄存器单元用于向第5+d个所述移位寄存器单元提供进位信号；第5+d个所述移位寄存器单元用于向第7个所述移位寄存器单元提供复位信号；
    第9个所述移位寄存器单元与第11个所述移位寄存器单元相互级联，第9个所述移位寄存器单元用于向第11个所述移位寄存器单元提供进位信号；第11个所述移位寄存器单元用于向第9个所述移位寄存器单元提供复位信号；
    第11个所述移位寄存器单元还与第9+d个所述移位寄存器单元相互级联，第11个所述移位寄存器单元用于向第9+d个所述移位寄存器单元提供进位信号；第9+d个所述移位寄存器单元用于向第11个所述移位寄存器单元提供复位信号；
    第13个所述移位寄存器单元与第15个所述移位寄存器单元相互级联，第13个所述移位寄存器单元用于向第15个所述移位寄存器单元提供进位信号；第15个所述移位寄存器单元用于向第13个所述移位寄存器单元提供复位信号；
    第15个所述移位寄存器单元还与第13+d个所述移位寄存器单元相互级联，第15个所述移位寄存器单元用于向第13+d个所述移位寄存器单元提供进位信号；第13+d个所述移位寄存器单元用于向第15个所述移位寄存器单元提供复位信号；
    第2个所述移位寄存器单元与第4个所述移位寄存器单元相互级联，第2个所述移位寄存器单元用于向第4个所述移位寄存器单元提供进位信号；第4个所述移位寄存器单元用于向第2个所述移位寄存器单元提供复位信号；
    第4个所述移位寄存器单元还与第2+d个所述移位寄存器单元相互级联，第4个所述移位寄存器单元用于向第2+d个所述移位寄存器单元提供进位信号；第2+d个所述移位寄存器单元用于向第4个所述移位寄存器单元提供复位信号；
    第6个所述移位寄存器单元与第8个所述移位寄存器单元相互级联，第6个所述移位寄存器单元用于向第8个所述移位寄存器单元提供进位信号；第8 个所述移位寄存器单元用于向第6个所述移位寄存器单元提供复位信号；
    第8个所述移位寄存器单元还与第6+d个所述移位寄存器单元相互级联，第8个所述移位寄存器单元用于向第6+d个所述移位寄存器单元提供进位信号；第6+d个所述移位寄存器单元用于向第8个所述移位寄存器单元提供复位信号；
    第10个所述移位寄存器单元与第12个所述移位寄存器单元相互级联，第10个所述移位寄存器单元用于向第12个所述移位寄存器单元提供进位信号；第12个所述移位寄存器单元用于向第10个所述移位寄存器单元提供复位信号；
    第12个所述移位寄存器单元还与第10+d个所述移位寄存器单元相互级联，第12个所述移位寄存器单元用于向第10+d个所述移位寄存器单元提供进位信号；第10+d个所述移位寄存器单元用于向第12个所述移位寄存器单元提供复位信号；
    第14个所述移位寄存器单元与第16个所述移位寄存器单元相互级联，第14个所述移位寄存器单元用于向第16个所述移位寄存器单元提供进位信号；第16个所述移位寄存器单元用于向第14个所述移位寄存器单元提供复位信号；
    第16个所述移位寄存器单元还与第14+d个所述移位寄存器单元相互级联，第16个所述移位寄存器单元用于向第14+d个所述移位寄存器单元提供进位信号；第14+d个所述移位寄存器单元用于向第16个所述移位寄存器单元提供复位信号。
  10. 根据权利要求5至8任一所述的显示基板，其中，s为1，连接至第i条栅线的所述移位寄存器单元为第i个所述移位寄存器单元；
    其中，第1个所述移位寄存器单元与第2个所述移位寄存器单元相互级联，第1个所述移位寄存器单元用于向第2个所述移位寄存器单元提供进位信号；第2个所述移位寄存器单元用于向第1个所述移位寄存器单元提供复位信号；
    第2个所述移位寄存器单元还与第1+d个所述移位寄存器单元相互级联，第2个所述移位寄存器单元用于向第1+d个所述移位寄存器单元提供进位信号；第1+d个所述移位寄存器单元用于向第2个所述移位寄存器单元提供复位信号；
    第3个所述移位寄存器单元与第4个所述移位寄存器单元相互级联，第3个所述移位寄存器单元用于向第4个所述移位寄存器单元提供进位信号；第4个所述移位寄存器单元用于向第3个所述移位寄存器单元提供复位信号；
    第4个所述移位寄存器单元还与第3+d个所述移位寄存器单元相互级联，第4个所述移位寄存器单元用于向第3+d个所述移位寄存器单元提供进位信号；第3+d个所述移位寄存器单元用于向第4个所述移位寄存器单元提供复位信号；
    第5个所述移位寄存器单元与第6个所述移位寄存器单元相互级联，第5个所述移位寄存器单元用于向第6个所述移位寄存器单元提供进位信号；第6个所述移位寄存器单元用于向第5个所述移位寄存器单元提供复位信号；
    第6个所述移位寄存器单元还与第5+d个所述移位寄存器单元相互级联，第6个所述移位寄存器单元用于向第5+d个所述移位寄存器单元提供进位信号；第5+d个所述移位寄存器单元用于向第6个所述移位寄存器单元提供复位信号；
    第7个所述移位寄存器单元与第8个所述移位寄存器单元相互级联，第7个所述移位寄存器单元用于向第8个所述移位寄存器单元提供进位信号；第8个所述移位寄存器单元用于向第7个所述移位寄存器单元提供复位信号；
    第8个所述移位寄存器单元还与第7+d个所述移位寄存器单元相互级联，第8个所述移位寄存器单元用于向第7+d个所述移位寄存器单元提供进位信号；第7+d个所述移位寄存器单元用于向第8个所述移位寄存器单元提供复位信号；
    第9个所述移位寄存器单元与第10个所述移位寄存器单元相互级联，第9个所述移位寄存器单元用于向第10个所述移位寄存器单元提供进位信号；第10个所述移位寄存器单元用于向第9个所述移位寄存器单元提供复位信号；
    第10个所述移位寄存器单元还与第9+d个所述移位寄存器单元相互级联，第10个所述移位寄存器单元用于向第9+d个所述移位寄存器单元提供进位信号；第9+d个所述移位寄存器单元用于向第10个所述移位寄存器单元提供复位信号；
    第11个所述移位寄存器单元与第12个所述移位寄存器单元相互级联，第11个所述移位寄存器单元用于向第12个所述移位寄存器单元提供进位信号；第12个所述移位寄存器单元用于向第11个所述移位寄存器单元提供复位信号；
    第12个所述移位寄存器单元还与第11+d个所述移位寄存器单元相互级联，第12个所述移位寄存器单元用于向第11+d个所述移位寄存器单元提供进位信号；第11+d个所述移位寄存器单元用于向第12个所述移位寄存器单元提供复位信号；
    第13个所述移位寄存器单元与第14个所述移位寄存器单元相互级联，第 13个所述移位寄存器单元用于向第14个所述移位寄存器单元提供进位信号；第14个所述移位寄存器单元用于向第13个所述移位寄存器单元提供复位信号；
    第14个所述移位寄存器单元还与第13+d个所述移位寄存器单元相互级联，第14个所述移位寄存器单元用于向第13+d个所述移位寄存器单元提供进位信号；第13+d个所述移位寄存器单元用于向第14个所述移位寄存器单元提供复位信号；
    第15个所述移位寄存器单元与第16个所述移位寄存器单元相互级联，第15个所述移位寄存器单元用于向第16个所述移位寄存器单元提供进位信号；第16个所述移位寄存器单元用于向第15个所述移位寄存器单元提供复位信号；
    第16个所述移位寄存器单元还与第15+d个所述移位寄存器单元相互级联，第16个所述移位寄存器单元用于向第15+d个所述移位寄存器单元提供进位信号；第15+d个所述移位寄存器单元用于向第16个所述移位寄存器单元提供复位信号。
  11. 根据权利要求5至10任一所述的显示基板，其中，所述显示基板共包括：第一开启信号端、第二开启信号端、第三开启信号端和第四开启信号端共四个开启信号端；
    所述第一移位电路中，第一个所述移位寄存器子组中的第一个所述移位寄存器单元，以及第二个所述移位寄存器子组中的第一个所述移位寄存器单元与所述第一开启信号端连接；
    所述第二移位电路中，第一个所述移位寄存器子组中的第一个所述移位寄存器单元，以及第二个所述移位寄存器子组中的第一个所述移位寄存器单元与所述第三开启信号端连接；
    所述第三移位电路中，第一个所述移位寄存器子组中的第一个所述移位寄存器单元，以及第二个所述移位寄存器子组中的第一个所述移位寄存器单元与所述第二开启信号端连接；
    所述第四移位电路中，第一个所述移位寄存器子组中的第一个所述移位寄存器单元，以及第二个所述移位寄存器子组中的第一个所述移位寄存器单元与所述第四开启信号端连接。
  12. 根据权利要求1至11任一所述的显示基板，其中，位于同一行的各个像素均按第一颜色、第二颜色和第三颜色依次排布，位于同一列的各个像素的颜色相同。
  13. 根据权利要求12所述的显示基板，其中，与同一条所述数据线连接的两个相邻的所述像素组中，各个像素均位于不同列。
  14. 根据权利要求13所述的显示基板，其中，每条所述数据线均包括：多条数据线段和多条连接线段；
    其中，每条所述连接线段的两端分别与相邻的两条所述数据线段连接；每个所述像素组与一条所述数据线段对应，且任意相邻的两条所述数据线段分别位于相邻行不同列像素组包括的两个像素之间。
  15. 根据权利要求12所述的显示基板，其中，与同一条所述数据线连接的两个相邻的所述像素组中，至少两个像素位于同一列。
  16. 一种显示基板的驱动方法，其中，用于驱动如权利要求1至15任一所述的显示基板，所述方法包括：
    向所述显示基板中的各个开启信号端依次提供开启信号，每个所述移位电路响应于所述开启信号，向所连接的每条所述栅线提供栅极驱动信号；
    向所述显示基板中的每条数据线提供数据信号，所述显示基板中的每个像素响应于所连接的所述栅线提供的栅极驱动信号和所连接的所述数据线提供的数据信号发光。
  17. 根据权利要求16所述的方法，其中，所述显示基板包括：第一移位电路、第二移位电路、第三移位电路和第四移位电路共四个移位电路，以及第一开启信号端、第二开启信号端、第三开启信号端和第四开启信号端共四个开启信号端；其中，所述第一开启信号端与所述第一移位电路连接，所述第三开启信号端与所述第二移位电路连接，所述第二开启信号端与所述第三移位电路连接，所述第四开启信号端与所述第四移位电路连接；
    所述向所述显示基板中的各个开启信号端依次提供开启信号，包括：
    依次向所述第一开启信号端、所述第三开启信号端、所述第二开启信号端和所述第四开启信号端提供开启信号。
  18. 根据权利要求17所述的方法，其中，每个所述移位电路包括至少四个移位寄存器单元，每个所述移位寄存器单元与一条栅线连接，且每个所述移位电路中的至少四个移位寄存器单元能够划分为两个移位寄存器组；每个所述移位寄存器组包括级联的多个所述移位寄存器单元，且每个所述移位寄存器组中的一个所述移位寄存器单元与所述开启信号端连接；每个所述移位寄存器组包括多个移位寄存器子组，每个所述移位寄存器子组包括相邻且级联的两个所述移位寄存器单元，且每个所述移位寄存器子组中的两个所述移位寄存器单元分别与相邻的第i条栅线和第i+2条栅线连接，i为正整数；
    所述每个所述移位电路响应于所述开启信号，向所连接的每条所述栅线提供栅极驱动信号，包括依次执行的以下步骤：
    所述第一移位电路中，与第一条栅线连接的移位寄存器单元响应于所述第一开启信号端提供的开启信号，向所述第一条栅线提供栅极驱动信号，并向与第三条栅线连接的移位寄存器单元提供进位信号；
    所述第二移位电路中，与第五条栅线连接的移位寄存器单元响应于所述第三开启信号端提供的开启信号，向所述第五条栅线提供栅极驱动信号，并向与第七条栅线连接的移位寄存器单元提供进位信号；
    所述第一移位电路中，与第九条栅线连接的移位寄存器单元响应于所述第一开启信号端提供的开启信号，向所述第九条栅线提供栅极驱动信号，并向与第十一条栅线连接的移位寄存器单元提供进位信号；
    所述第二移位电路中，与第十三条栅线连接的移位寄存器单元响应于所述第三开启信号端提供的开启信号，向所述第十三条栅线提供栅极驱动信号，并向与第十五条栅线连接的移位寄存器单元提供进位信号；
    所述第一移位电路中，与所述第三条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第三条栅线提供栅极驱动信号；
    所述第二移位电路中，与所述第七条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第七条栅线提供栅极驱动信号；
    所述第一移位电路中，与所述第十一条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十一条栅线提供栅极驱动信号；
    所述第二移位电路中，与所述第十五条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十五条栅线提供栅极驱动信号；
    所述第三移位电路中，与第二条栅线连接的移位寄存器单元响应于所述第二开启信号端提供的开启信号，向所述第二条栅线提供栅极驱动信号，并向与第四条栅线连接的移位寄存器单元提供进位信号；
    所述第四移位电路中，与第六条栅线连接的移位寄存器单元响应于所述第四开启信号端提供的开启信号，向所述第六条栅线提供栅极驱动信号，并向与第八条栅线连接的移位寄存器单元提供进位信号；
    所述第三移位电路中，与第十条栅线连接的移位寄存器单元响应于所述第二开启信号端提供的开启信号，向所述第十条栅线提供栅极驱动信号，并向与第十二条栅线连接的移位寄存器单元提供进位信号；
    所述第四移位电路中，与第十四条栅线连接的移位寄存器单元响应于所述第四开启信号端提供的开启信号，向所述第十四条栅线提供栅极驱动信号，并向与第十六条栅线连接的移位寄存器单元提供进位信号；
    所述第三移位电路中，与所述第四条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第四条栅线提供栅极驱动信号；
    所述第四移位电路中，与所述第八条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第八条栅线提供栅极驱动信号；
    所述第三移位电路中，与所述第十二条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十二条栅线提供栅极驱动信号；
    所述第四移位电路中，与所述第十六条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十六条栅线提供栅极驱动信号。
  19. 根据权利要求17所述的方法，其中，每个所述移位电路包括至少四个移位寄存器单元，每个所述移位寄存器单元与一条栅线连接，且每个所述移位电路中的至少四个移位寄存器单元能够划分为两个移位寄存器组；每个所述移位寄存器组包括级联的多个所述移位寄存器单元，且每个所述移位寄存器组中的一个所述移位寄存器单元与所述开启信号端连接；每个所述移位寄存器组包 括多个移位寄存器子组，每个所述移位寄存器子组包括相邻且级联的两个所述移位寄存器单元，且每个所述移位寄存器子组中的两个所述移位寄存器单元分别与相邻的第i条栅线和第i+1条栅线连接，i为正整数；
    所述每个所述移位电路响应于所述开启信号，向所连接的每条所述栅线提供栅极驱动信号，包括依次执行的以下步骤：
    所述第一移位电路中，与第一条栅线连接的移位寄存器单元响应于所述第一开启信号端提供的开启信号，向所述第一条栅线提供栅极驱动信号，并向与第二条栅线连接的移位寄存器单元提供进位信号；
    所述第二移位电路中，与第五条栅线连接的移位寄存器单元响应于所述第三开启信号端提供的开启信号，向所述第五条栅线提供栅极驱动信号，并向与第六条栅线连接的移位寄存器单元提供进位信号；
    所述第一移位电路中，与第九条栅线连接的移位寄存器单元响应于所述第一开启信号端提供的开启信号，向所述第九条栅线提供栅极驱动信号，并向与第十条栅线连接的移位寄存器单元提供进位信号；
    所述第二移位电路中，与第十三条栅线连接的移位寄存器单元响应于所述第三开启信号端提供的开启信号，向所述第十三条栅线提供栅极驱动信号，并向与第十四条栅线连接的移位寄存器单元提供进位信号；
    所述第三移位电路中，与第三条栅线连接的移位寄存器单元响应于所述第二开启信号端提供的开启信号，向所述第三条栅线提供栅极驱动信号，并向与第四条栅线连接的移位寄存器单元提供进位信号；
    所述第四移位电路中，与第七条栅线连接的移位寄存器单元响应于所述第四开启信号端提供的开启信号，向所述第七条栅线提供栅极驱动信号，并向与第八条栅线连接的移位寄存器单元提供进位信号；
    所述第三移位电路中，与第十一条栅线连接的移位寄存器单元响应于所述第二开启信号端提供的开启信号，向所述第十一条栅线提供栅极驱动信号，并向与第十二条栅线连接的移位寄存器单元提供进位信号；
    所述第四移位电路中，与第十五条栅线连接的移位寄存器单元响应于所述第四开启信号端提供的开启信号，向所述第十五条栅线提供栅极驱动信号，并向与第十六条栅线连接的移位寄存器单元提供进位信号；
    所述第一移位电路中，与所述第二条栅线连接的移位寄存器单元响应于接 收到的进位信号，向所述第二条栅线提供栅极驱动信号；
    所述第二移位电路中，与所述第六条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第六条栅线提供栅极驱动信号；
    所述第一移位电路中，与所述第十条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十条栅线提供栅极驱动信号；
    所述第二移位电路中，与所述第十四条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十四条栅线提供栅极驱动信号；
    所述第三移位电路中，与所述第四条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第四条栅线提供栅极驱动信号；
    所述第四移位电路中，与所述第八条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第八条栅线提供栅极驱动信号；
    所述第三移位电路中，与所述第十二条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十二条栅线提供栅极驱动信号；
    所述第四移位电路中，与所述第十六条栅线连接的移位寄存器单元响应于接收到的进位信号，向所述第十六条栅线提供栅极驱动信号。
  20. 一种显示装置，其中，所述显示装置包括：信号提供电路，以及如权利要求1至15任一所述的显示基板；
    所述信号提供电路与所述显示基板中的开启信号端连接，用于为所述开启信号端提供开启信号。
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