WO2022077178A1 - Structure d'encapsulation de puce, dispositif électronique et procédé de fabrication de structure d'encapsulation de puce - Google Patents

Structure d'encapsulation de puce, dispositif électronique et procédé de fabrication de structure d'encapsulation de puce Download PDF

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Publication number
WO2022077178A1
WO2022077178A1 PCT/CN2020/120470 CN2020120470W WO2022077178A1 WO 2022077178 A1 WO2022077178 A1 WO 2022077178A1 CN 2020120470 W CN2020120470 W CN 2020120470W WO 2022077178 A1 WO2022077178 A1 WO 2022077178A1
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WIPO (PCT)
Prior art keywords
chip
package substrate
package
packaging
pads
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PCT/CN2020/120470
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English (en)
Chinese (zh)
Inventor
胡骁
赵南
郑见涛
蒋尚轩
吴维哲
朱泽
江宇
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/120470 priority Critical patent/WO2022077178A1/fr
Priority to CN202080104838.9A priority patent/CN116250066A/zh
Publication of WO2022077178A1 publication Critical patent/WO2022077178A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape

Definitions

  • the present application relates to the technical field of chip packaging, and in particular, to a chip packaging structure, an electronic device and a method for preparing the chip packaging structure.
  • chip integration has been further improved.
  • chip size becomes larger, multi-chip packaging technology is also widely used, which makes the size of the entire chip packaging structure within continuously increasing.
  • the structure has a large warpage (Warpage).
  • Warpage the Coefficient of Thermal Expansion
  • the chip package structure has a large degree of warpage, when the chip package structure is electrically connected to the printed circuit board (PCB) 1-1 through the solder balls 1-2, adjacent Solder balls 1-2 are connected in series, resulting in a short circuit, or poor soldering of solder balls 1-2, which affects the surface mount technology (STM) good rate.
  • PCB printed circuit board
  • the size of the heat dissipation lid (Lid) is usually increased.
  • the heat dissipation cover 1-5 is generally connected to the package substrate 1-3 through an adhesive layer 1-4.
  • the heat dissipation cover 1-5 has a larger size, the size of the internal stress of the package, and The degree of warpage is easily affected by the thickness dimension of the adhesive layer 4 .
  • the thickness of the adhesive layer 1-4 that is, before encapsulating the heat dissipation cover 1-5, dispense adhesive on the packaging substrate 1-3, and then cover the heat dissipation cover 1-5 on the uncured adhesive. Then, the force F in the direction shown in FIG. 1 is applied to the heat dissipation cover 1-5, and the thickness of the adhesive layer 1-4 is controlled by the control of the force F (force control). That is to say, the thickness of the adhesive layers 1-4 is determined with the force F value as the process standard.
  • the package substrate 1-3 will be thermally deformed, and may occur in a batch of specifications
  • the thermal deformation amount of the package substrate is different, and some thermal deformation amounts are small, and some thermal deformation amounts are large.
  • the degree of warpage of the chip package structure is different, and the internal stress of the package is different, and it is difficult to standardize the final product.
  • Embodiments of the present application provide a chip package structure, an electronic device and a method for preparing the chip package structure, and the main purpose is to provide a chip package structure that can control the thickness and size of the adhesive layer more accurately.
  • the present application provides a chip packaging structure
  • the chip packaging structure includes: a packaging substrate, a chip, a reinforcement structure, an adhesive layer and a plurality of positioning blocks; wherein the chip and the reinforcement structure are arranged on the same side of the packaging substrate On the surface, and the reinforcement structure surrounds the periphery of the chip, the reinforcement structure is connected to the package substrate through the adhesive layer, the thickness of any one of the positioning blocks is equal to the thickness of the adhesive layer, and the multiple positioning blocks are located in the reinforcement Between the structure and the package substrate, the reinforcement structure is in contact with the surface of the positioning block facing away from the package substrate, and a plurality of positioning blocks are arranged at intervals along the circumferential direction of the package substrate.
  • the thickness of any positioning block of the plurality of positioning blocks is equal to the thickness of the adhesive layer.
  • glue is dispensed, and then the reinforcement structure is packaged, so that the surface of the reinforcement structure facing the packaging substrate will abut on the plurality of positioning blocks, through the The positioning block defines the position of the reinforcement structure, and then precisely controls the thickness of the adhesive layer. If the thickness of the positioning block is equal to or similar to the design value of the thickness of the adhesive layer, the adhesive formed by the final package will The thickness of the layer is equal to or close to the design value. While ensuring that the stress in the package is small, the degree of warpage cannot be too large.
  • the welding quality rate can be improved.
  • the chip package structure of the same specification is packaged in batches, there will be no phenomenon that some adhesive layers are thick and some adhesive layers are thinner, which can realize the unification of product structure.
  • the surface of the package substrate carrying the chip and the reinforcement structure has a plurality of first pads and is covered with a solder resist layer, and the plurality of first pads are covered in the solder resist layer ;
  • a plurality of first openings are opened on the solder mask layer, and the plurality of first openings are all connected to a plurality of first pads;
  • a plurality of positioning blocks are arranged one-to-one on the plurality of first openings, and are connected with the first openings. Pad soldering.
  • the positioning block is set by the same process as the integrated chip, which can simplify the entire chip.
  • the preparation process of the packaging structure improves the packaging efficiency.
  • the positioning block is disposed close to a corner of the package substrate.
  • the positioning blocks are also disposed on the sides of the package substrate.
  • the cross section of the positioning block may be circular or rectangular.
  • the chip packaging structure further includes a cover plate, the cover plate covers the surface of the chip away from the packaging substrate, and is connected with the reinforcement structure to form a heat dissipation cover.
  • an embodiment of the present application further provides a method for preparing a chip packaging structure, the preparation method comprising:
  • a plurality of positioning blocks are arranged on the packaging substrate at the positions for arranging the reinforcement structure, and the plurality of positioning blocks are arranged at intervals along the circumferential direction of the packaging substrate, and the thickness of any positioning block of the plurality of positioning blocks is equal to the thickness used for bonding the reinforcement structure and the thickness of the adhesive layer of the packaging substrate;
  • a reinforcement structure is arranged on the surface of the package substrate integrated with the chip, and the reinforcement structure surrounds the periphery of the chip, and the reinforcement structure is in contact with the surface of the positioning block facing away from the package substrate, so that the reinforcement structure is formed by curing the adhesive layer connected to the package substrate.
  • the thickness of the positioning blocks is equal to the thickness of the adhesive layer.
  • the thickness of the positioning block is equal to or similar to the design value of the thickness of the adhesive layer, so that the thickness of the finally formed adhesive layer is equal to or similar to the design value, so as to accurately control the thickness of the adhesive layer. All, when using this method to prepare chip packaging structures in batches, there will be no phenomenon that some adhesive layers are thicker and some adhesive layers are thinner, but the design value of the thickness and size of the adhesive layer is basically equal to or close to that of the adhesive layer. .
  • the package substrate has a plurality of first bonding pads at a position for carrying the reinforcement structure, and is covered with a solder resist layer, and the plurality of first bonding pads are covered in the solder resist layer ; Arranging a plurality of positioning blocks on the packaging substrate, including: opening a plurality of first openings on the solder resist layer and at the positions where the reinforcement structures are arranged, and the plurality of first openings are spaced along the circumferential direction of the packaging substrate The plurality of first openings are arranged to pass through to the plurality of first pads; the plurality of positioning blocks are passed through the plurality of first openings one-to-one and welded with the first pads.
  • the way of setting the positioning block is the same as the way of setting the controllable collapse chip connection pads in the prior art.
  • the package substrate has a plurality of second pads at the position for carrying the chip, the plurality of second pads are wrapped in the solder resist layer, and a plurality of second pads are opened on the solder resist layer.
  • the preparation method further includes: opening a plurality of second openings on the solder resist layer at the positions where the chips are arranged, and making the plurality of second openings pass through to the plurality of second pads, The second opening is used to connect pads through the controllably collapsed chip for bonding with the second pad to electrically connect the chip and the package substrate. That is, when the second window is opened, the first window is opened by using the same technological means, which can simplify the packaging process and improve the packaging efficiency.
  • the preparation method further includes: connecting the solder joint of the controllable collapsed chip through the second opening to the second pad. Pad soldering.
  • the method when dispensing glue, includes: dispensing glue between two adjacent positioning blocks.
  • the preparation method further includes: spotting a thermally conductive interface material on the surface of the chip integrated on the packaging substrate facing away from the packaging substrate to form a thermally conductive interface on the surface of the chip material layer.
  • the present application further provides an electronic device, comprising a printed circuit board and the chip packaging structure in any implementation manner of the above-mentioned first aspect or the chip packaging structure obtained by any implementation manner of the above-mentioned second aspect.
  • the manufacturing circuit board is electrically connected with the chip packaging structure.
  • the electronic device provided by the embodiment of the present application includes the chip package structure obtained by the embodiment of the first aspect or the embodiment of the second aspect. Therefore, the electronic device provided by the embodiment of the present application and the chip package structure of the above technical solution can solve the same technical problem , and achieve the same expected effect.
  • FIG. 1 is a schematic structural diagram of a chip packaging structure in the prior art
  • Fig. 2 is the partial structure schematic diagram in the electronic equipment
  • FIG. 3 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
  • Fig. 4 is the top view of Fig. 3;
  • FIG. 5 is a schematic structural diagram of a chip packaging structure according to an embodiment of the present application.
  • Fig. 6 is the enlarged view of A place of Fig. 5;
  • FIG. 7 is another perspective view of the chip packaging structure according to the embodiment of the present application.
  • FIG. 8 is another perspective view of the chip packaging structure according to the embodiment of the present application.
  • FIG. 9 is another perspective view of the chip packaging structure according to the embodiment of the present application.
  • FIG. 10 is another perspective view of the chip packaging structure according to the embodiment of the application.
  • FIG. 11a is a schematic structural diagram of a package substrate according to an embodiment of the present application.
  • FIG. 11b is a schematic diagram of a detailed structure of a package substrate according to an embodiment of the present application.
  • 11c is a schematic diagram of a connection relationship between a chip and a package substrate according to an embodiment of the present application.
  • FIG. 12 is a detailed structural schematic diagram of opening a first window on a package substrate according to an embodiment of the present application.
  • FIG. 13 is a schematic diagram of a connection relationship between a positioning block and a package substrate according to an embodiment of the present application.
  • FIG. 14 is a flowchart of a method for fabricating a chip packaging structure according to an embodiment of the present application.
  • FIG. 15 is a flow chart of setting a positioning block on a package substrate according to an embodiment of the present application.
  • 16 is a schematic structural diagram corresponding to each step in the method for preparing a chip packaging structure according to an embodiment of the present application;
  • FIG. 17 is a schematic structural diagram of a chip according to an embodiment of the present application.
  • FIG. 18 is a schematic diagram of the position of the spot adhesive according to the embodiment of the application.
  • FIG. 19 is a schematic structural diagram corresponding to each step in the method for manufacturing a chip package structure according to an embodiment of the present application after completion of each step.
  • 01-PCB 01-electrical connection structure; 03-chip packaging structure;
  • Embodiments of the present application provide an electronic device.
  • the electronic device may include a mobile phone (mobile phone), a tablet computer (pad), a smart wearable product (eg, a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR), It can also be household appliances and other equipment.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • the above electronic device may include a printed circuit board (printed circuit board, PCB) 01 and a chip packaging structure 03 .
  • the chip package structure 03 is electrically connected to the PCB01 through the electrical connection structure 02, so that the chip package structure 03 can be interconnected with other chips or other modules on the PCB01.
  • the electrical connection structure 02 may be a ball grid array (BGA).
  • BGA ball grid array
  • FIG. 3 is a schematic cross-sectional view of a chip package structure 03 provided by an embodiment of the present application.
  • the chip package structure 03 includes a chip 1 and a package substrate 2 for carrying the chip 1 .
  • FIG. 3 is only an embodiment, only one chip 1 is shown, and there may be multiple chips 1 or other passive elements (eg, resistors, inductors, etc.).
  • the structures including the chip 1 and other elements are all fixed on the surface of the package substrate 2 .
  • the chip 1 is electrically connected to the package substrate 2 through a controlled collapsed chip connection (C4) 6, and the package substrate 2 is formed with a metal layer, the The metal layers form wiring structures, establish signal paths between chips, or between chips and other electronic devices, and electrically connect chips and other electronic devices to the electrical connection structures.
  • C4 controlled collapsed chip connection
  • the above-mentioned chip may be a die obtained after wafer dicing, or may be a plurality of stacked dies.
  • a glue dispensing process may be used to fill an underfill layer 9 between the chip 1 and the package substrate 2 .
  • the chip package structure 03 also includes a reinforcement structure 3, as shown in FIG. 3 and FIG. 4, FIG. 4 is a top view of FIG. 3, the reinforcement structure 3 and the chip 1 are integrated on the same surface of the package substrate 2, and The reinforcement structure 3 surrounds the periphery of the chip 1 .
  • the reinforcing structure 3 can suppress the degree of warpage of the package substrate 2 .
  • the above-mentioned reinforcement structure 3 may be a ring-shaped reinforcement ring (Ring) as shown in FIG. 4 , or may be a structure shown in FIG. plate 8, and the cover plate 8 is connected with the reinforcement structure 3 to form a heat dissipation cover (Lid) 15.
  • the cover plate 8 and the reinforcement structure 3 may be an integrally formed structure.
  • the heat dissipation cover 15 of this structure Not only can the chip 1 be dissipated, but also the degree of warpage of the package substrate 2 can be suppressed.
  • the cover plate 8 is connected to the upper surface of the chip 1 through a thermal interface material (thermal interface material, TIM) layer 7 .
  • a thermal interface material thermal interface material, TIM
  • the heat dissipated by the chip 1 will be conducted to the heat dissipation cover 15 through the TIM 7 , and the heat will be dissipated through the heat dissipation cover with a large heat conduction area to cool the chip 1 and ensure the normal operation of the chip 1 .
  • the integration level of the chip is constantly improving.
  • the size of the chip is With the continuous increase in size, the CTE mismatch between the larger-sized chip 1 and the package substrate 2 makes it more difficult to control the thermal deformation of the package, and the degree of warpage continues to increase.
  • the size of the reinforcement structure 3 may be increased to balance the warpage of the package substrate 2 .
  • the size of the reinforcement structure 3 is increased, the contact area of the reinforcement structure 3 with the package substrate 2 may be increased.
  • both the reinforcement structure 3 and the heat dissipation cover 15 are connected to the package substrate 2 through an adhesive layer 4.
  • the material of the adhesive layer 4 may be
  • the silicone material may also be an epoxy material, and the application does not specifically limit the material of the adhesive layer.
  • the thickness of the adhesive layer 4 (dimension d2 as shown in FIG. 6 ) can easily affect the stress and warpage in the package.
  • the thickness of the adhesive layer 4 is smaller than the design value, the deformation of the reinforcement structure 3 and the deformation of the package substrate 2 are coupled to a greater degree, and the deformation of the reinforcement structure 3 is easily transmitted to the package substrate 2, resulting in an increase in the internal stress of the package , the package reliability is reduced.
  • the thickness of the adhesive layer 4 is larger than the design value, the deformation of the reinforcement structure 3 and the deformation of the package substrate 2 are less coupled, and the package warpage degree increases, which seriously affects the welding quality of the chip package structure and the PCB.
  • the chip package structure 03 further includes a plurality of positioning blocks 5 , as shown in FIG. 6 , the thickness d1 of any positioning block 5 is equal to the bonding
  • the thickness d2 of the adhesive layer 4 , a plurality of positioning blocks 5 are arranged on the packaging substrate 2 where the reinforcement structure 3 is connected, and the surface of the positioning blocks 5 facing away from the packaging substrate 2 abuts the reinforcement structure 3 .
  • the thickness d1 of the positioning block 5 refers to the dimension of the positioning block 5 that is perpendicular to the package substrate 2 .
  • the thickness d2 of the adhesive layer 4 refers to the dimension of the adhesive layer 4 perpendicular to the package substrate 2 .
  • a positioning block 5 whose thickness dimension is equal to or similar to the design value of the thickness dimension of the adhesive layer 4 can be set on the encapsulation substrate 2 , and then glue is dispensed, and then the reinforcement The structure 3 is covered on the adhesive layer, so that the reinforcing structure 3 will abut on the positioning block 5, and will not continue to move in the direction of the packaging substrate 2. Due to the thickness of the positioning block 5 and the thickness of the adhesive layer 4 The design value of the adhesive is equal to or similar to, and further, the thickness dimension of the adhesive layer 4 formed by curing the adhesive is equal to or similar to the design value.
  • the thickness of the positioning block 5 it is only necessary to make the thickness of the positioning block 5 equal to or similar to the thickness of the adhesive layer 4, and then the thickness of the adhesive layer can be precisely controlled.
  • the existing method of determining the thickness of the adhesive layer 4 with the force F value as the process standard it is easy to precisely control the thickness of the adhesive layer, so as to ensure that the internal stress of the package is small and the degree of warpage is taken into account. It is also easy to implement on a smaller premise.
  • the adhesive layer 4 relatively fixes the reinforcement structure 3 and the package substrate 2 along the circumferential direction of the package substrate 2 .
  • the surface of the package substrate 2 for carrying the chip is rectangular.
  • at least four positioning can be arranged.
  • one positioning block 5 is arranged at each corner of the package substrate 2 , or as shown in FIG. 8 , multiple positioning blocks 5 may be arranged at each corner.
  • the positioning blocks 5 can also be arranged near the sides to further make the thickness of the adhesive layer 4 uniform.
  • the structure of the positioning block 5 has various situations.
  • the cross-section of the positioning block 5 is a circular structure.
  • the cross section of the positioning block 5 is a rectangular structure. Figures 9 and 10 only show positioning blocks with two different structures. In addition, the cross-section may also be oval, triangular, etc.
  • the structure of the positioning block 5 is not specifically limited in this application.
  • the surface of the package substrate 2 involved in the present application for carrying chips has second pads (Pad) 262 , and the second pads 262 are used to electrically connect the chip and the package substrate.
  • the surface of the package substrate 2 is also covered with a solder resist layer 25 , and the second pad 262 is covered in the solder resist layer 25 .
  • the packaging substrate 2 may be a redistribution layer (RDL), as shown in FIG.
  • the packaging substrate 2 includes: a multi-layer metal layer 22 formed of a metal material and a multi-layer resin layer
  • the dielectric layer 21 made of material, the two adjacent metal layers 22 are separated by the dielectric layer 21 , and the second pad 262 is arranged on the metal layer 22 on the surface of the package substrate 2 and is electrically connected to the metal layer 22 .
  • a conductive channel 23 penetrating the dielectric layer 21 is also included.
  • the above-mentioned solder resist layer 25 can also be made of resin material.
  • a plurality of second openings 242 need to be opened on the solder resist layer 25 on the package substrate 2 to expose a plurality of second pads 262, of which one The second opening 242 corresponds to a second pad 262 .
  • the controllable collapsed chip connection pads 6 can be welded to the corresponding second pads 262 through the second openings 242 to realize the electrical connection between the chip 1 and the package substrate 2 .
  • the bearing method of the positioning block 5 on the package substrate 2 will be introduced below.
  • FIG. 12 and FIG. 13 show a bearing method of the positioning block 5 on the package substrate 2.
  • the package substrate 1 is provided with a first pad 261 at the position where the reinforcement structure is arranged, and the first solder The pad 261 is also wrapped in the solder resist layer 25 , and the solder resist layer 26 on the surface of the package substrate 2 is provided with a plurality of first openings 241 , and the first openings 241 penetrate through to the first bonding pads 261 .
  • one of the first openings 241 corresponds to one of the first pads 261.
  • the positioning block 5 passes through the first openings 241 and is welded to the first pads 261, so that the The positioning block 5 is carried on the package substrate 2 . That is to say, the bearing method of the positioning block 5 shown in FIG. 13 on the packaging substrate 2 is the same as the bearing method of the chip 1 shown in FIG. 11 c on the packaging substrate 2 .
  • the second opening is formed at the position carrying the chip 1 , the same process can be used to open the first opening at the position of the package substrate for carrying the reinforcement structure. In this case, the existing mature process of opening the second window is used to open the first window.
  • the material of the first pad 261 and the second pad 262 may be the same, and the preparation process is also the same.
  • the material of the positioning block 5 can be selected from metals such as copper, nickel, silver, etc., or can be lead-free solder balls, polymer core solder balls, polymer core solder balls, etc. Copper core solder ball (Cu core solder ball), etc.
  • the embodiment of the present application also provides a method for preparing a chip packaging structure.
  • the preparation method includes:
  • Step S1 a plurality of positioning blocks are arranged at the positions of the packaging substrate for setting the reinforcement structure, and the plurality of positioning blocks are arranged at intervals along the circumferential direction of the packaging substrate, and the thickness of any positioning block of the plurality of positioning blocks is equal to the thickness used for bonding The thickness of the adhesive layer connecting the reinforcement structure and the package substrate.
  • the thickness dimension of the positioning block may be equal to or close to the final design value of the thickness dimension of the adhesive layer used to connect the reinforcement structure and the package substrate.
  • Step S2 Dispensing adhesive at the position of the package substrate where the reinforcement structure is arranged.
  • Step S3 disposing a reinforcement structure on the surface of the package substrate integrated with the chip, and the reinforcement structure surrounds the periphery of the chip, and the reinforcement structure is in contact with the surface of the positioning block facing away from the package substrate, so that the reinforcement structure is formed by curing.
  • the adhesive layer is connected with the package substrate.
  • the reinforcement structure when the reinforcement structure is provided, due to the existence of the positioning block, the reinforcement structure will abut on the positioning block. In this case, the position of the reinforcement structure is limited by the positioning block, and the reinforcement structure will not continue to face the direction of the package substrate. move.
  • the actual thickness dimension of the adhesive layer formed after the adhesive adhesive is cured is equal to or equal to the design thickness dimension or near.
  • the thickness and size of the adhesive layer can be accurately controlled by the positioning block, and the internal stress and warpage of the package will not be greatly affected when the adhesive layer is thicker or thinner. .
  • the structure of the package substrate used in the preparation method of the chip package structure of the embodiment of the present application may be the structure shown in FIG. 11a and FIG. 11b . Then, the step of setting the positioning block on the package substrate 2 of the above structure is shown in FIG. 15 . shown, including:
  • Step S1-1 A plurality of first openings are opened on the solder resist layer and at the positions where the reinforcement structures are arranged, the plurality of first openings are arranged at intervals along the circumferential direction of the package substrate, and the plurality of first openings The openings are all penetrated to the plurality of first pads.
  • Step S1-2 Pass the plurality of positioning blocks one-to-one through the plurality of first openings, and weld them with the first pads.
  • the reinforcing structure can be arranged at the position of the package substrate at the same time. Open the first window.
  • FIG. 16 shows a preparation method of the chip package structure, including the process of integrating the chip, setting the positioning block, and packaging the heat dissipation cover including the cover plate.
  • a plurality of first openings 241 are opened on the surface of the package substrate 2 and at the position (Lid footprint) for disposing the heat dissipation cover, and a plurality of first openings 241 are opened at the position (die footprint) for integrating the chip The second fenestration 242 .
  • the number of the shown first openings 241 is the same as the number of positioning blocks to be set, and similarly, the number of the second openings 242 shown is the same as the number of the controllable collapsed chip connection pads to be set.
  • the chip is integrated in the central area of the packaging substrate 2 , then, the second opening 242 is also integrated and opened in the central area close to the packaging substrate 2 .
  • the plurality of first openings 241 are arranged at intervals along the circumferential direction of the package substrate 2 .
  • the first opening 241 and the second opening 242 need to be surface-treated to improve the reliability of the fixed connection between the positioning block and the first pad, and controllable
  • the collapsed chip connection pad and the second pad are electrically connected with reliability.
  • the positioning block 5 is placed on the first window, and reflow soldered to the package substrate together with the controllable-collapse chip connection pads. on the corresponding first and second pads.
  • the chip 1 is mounted, and the passive components 11 (including resistors, capacitors, etc.) are mounted, and reflow soldering is performed.
  • the passive components 11 including resistors, capacitors, etc.
  • a controllable collapsed chip connection pad 6 is also integrated on the surface of the metal layer 102 of the chip 1 .
  • the chip 1 is electrically connected to the package substrate 2 , the The controllable-collapse chip connection pads are reflow soldered to the controllable-collapse chip connection pads on the package substrate 2 .
  • the metal layer 102 of the chip is close to the package substrate 2, and the base 101 is located on the side of the metal layer 102 away from the package substrate 2, so that the interconnection path is short.
  • the base 101 may also be close to the package substrate 2 , and the metal layer 102 may be located on the side of the base 101 away from the package substrate 2 .
  • glue is dispensed between the chip 1 and the package substrate 2 , and cured by heating to form an underfill layer (Underfill) 9 between the chip 1 and the package substrate 2 .
  • an adhesive (adhesive) 12 is applied at the position of the package substrate 2 for disposing the heat dissipation cover, and a thermal interface material 13 is applied on the surface of the chip 1 away from the package substrate 2 .
  • adhesive 12 may be dispensed between two adjacent positioning blocks 5 . Prevent the thickness of the final adhesive layer from being affected after the adhesive glue is dripped on the positioning block 5 .
  • solder balls 14 are implanted on the backside of the package substrate 2 away from the chip 1 so as to be electrically connected to the PCB.
  • the preparation method shown in FIG. 16 that while the second opening is opened on the packaging substrate 2, the first opening can also be opened on the packaging substrate 2, and the same process can be used to adopt this kind of bearing positioning.
  • the block method will simplify the process of the entire chip packaging structure and improve the packaging efficiency.
  • FIG. 19 shows another fabrication method of the chip package structure, which also includes the process of integrating the chip, setting the positioning block, and packaging the heat dissipation cover.
  • a first opening 241 is opened on the surface of the package substrate 2 and at the position (Lid footprint) for disposing the heat dissipation cover, and a second opening 241 is opened at the position (die footprint) for integrating the chip 242.
  • glue is dispensed between the chip 1 and the package substrate 2 , and cured by heating to form an underfill layer (Underfill) between the chip 1 and the package substrate 2 .
  • an adhesive 12 is dispensed at the position of the package substrate 2 for disposing the heat dissipation cover, and a thermal interface material 13 is dispensed on the surface of the chip 1 away from the package substrate 2 .
  • solder balls 14 are implanted on the backside of the package substrate 2 away from the chip 1 so as to be electrically connected to the PCB.

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Abstract

L'invention concerne une structure d'encapsulation de puce, un dispositif électronique et un procédé de fabrication de la structure d'encapsulation de puce, se rapportant au domaine technique de l'encapsulation de puce. L'invention concerne également une structure d'encapsulation de puce (03) qui comprend un substrat d'encapsulation (2), une puce (1), une structure de renforcement (3), une couche adhésive (4) et une pluralité de blocs de positionnement (5). La puce (1) et la structure de renforcement (3) sont disposées sur la même surface du substrat d'encapsulation (2), et la structure de renforcement (3) entoure la périphérie de la puce (1) ; la structure de renforcement (3) est reliée au substrat d'encapsulation (2) au moyen de la couche adhésive (4) ; l'épaisseur d'un bloc de positionnement (5) quelconque de la pluralité de blocs de positionnement (5) est égale à l'épaisseur de la couche adhésive (4) ; la pluralité de blocs de positionnement (5) sont situés entre la structure de renforcement (3) et le substrat d'encapsulation (2) ; la structure de renforcement (3) vient en butée contre des surfaces des blocs de positionnement (5) qui sont orientées à l'opposé du substrat d'encapsulation (2) ; et la pluralité de blocs de positionnement (5) sont disposés à des intervalles dans la direction circonférentielle du substrat d'encapsulation (2).
PCT/CN2020/120470 2020-10-12 2020-10-12 Structure d'encapsulation de puce, dispositif électronique et procédé de fabrication de structure d'encapsulation de puce WO2022077178A1 (fr)

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PCT/CN2020/120470 WO2022077178A1 (fr) 2020-10-12 2020-10-12 Structure d'encapsulation de puce, dispositif électronique et procédé de fabrication de structure d'encapsulation de puce
CN202080104838.9A CN116250066A (zh) 2020-10-12 2020-10-12 芯片封装结构、电子设备及芯片封装结构的制备方法

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