WO2022067739A1 - 上电复位电路 - Google Patents

上电复位电路 Download PDF

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Publication number
WO2022067739A1
WO2022067739A1 PCT/CN2020/119598 CN2020119598W WO2022067739A1 WO 2022067739 A1 WO2022067739 A1 WO 2022067739A1 CN 2020119598 W CN2020119598 W CN 2020119598W WO 2022067739 A1 WO2022067739 A1 WO 2022067739A1
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WIPO (PCT)
Prior art keywords
field effect
effect transistor
voltage
branch
current
Prior art date
Application number
PCT/CN2020/119598
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English (en)
French (fr)
Inventor
杨江
Original Assignee
深圳市汇顶科技股份有限公司
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Filing date
Publication date
Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to EP20923685.0A priority Critical patent/EP4007169A1/en
Priority to PCT/CN2020/119598 priority patent/WO2022067739A1/zh
Priority to US17/473,512 priority patent/US11431335B2/en
Publication of WO2022067739A1 publication Critical patent/WO2022067739A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H03K17/223—Modifications for ensuring a predetermined initial state when the supply voltage has been applied in field-effect transistor switches
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means

Definitions

  • the embodiments of the present application relate to the technical field of sensors, and in particular, to a power-on reset circuit.
  • the power-on reset circuit (English: Power-on Reset Circuit, POR) is used to output a reset signal to other functional circuit modules in the chip after the chip is powered on, so that the chip can start to work.
  • the power supply voltage may be affected by the temperature
  • a bandgap reference circuit connected to the power supply voltage is usually used to provide a stable voltage for the chip. Taking this application scenario as an example, during the power-on process, the power supply voltage starts to increase from 0 potential. Driven by the power supply voltage, the bandgap reference circuit also starts to work.
  • the The electrical reset circuit When the power supply voltage increases to the preset value, the The electrical reset circuit outputs a reset signal, but in reality, the bandgap reference circuit may not be stable, and the voltage provided to the chip is not stable. At this time, the chip starts to work after receiving the reset signal, which is likely to cause errors and cause the chip to fail. start up.
  • one of the technical problems solved by the embodiments of the present invention is to provide a power-on reset circuit to overcome the defect of the prior art that the reset signal is output when the bandgap reference circuit is unstable, resulting in errors.
  • An embodiment of the present application provides a power-on reset circuit, which includes: a bandgap reference circuit, a current comparator, and a voltage comparison circuit, wherein the bandgap reference circuit, the current comparator, and the voltage comparison circuit are all powered by a voltage source;
  • the first output terminal of the bandgap reference circuit is connected to the control terminal of the current comparator, and is used for inputting a first signal to the control terminal of the current comparator to control the operation of the current comparator;
  • the first current input terminal and the second current input terminal of the current comparator are respectively connected to the first current signal and the second current signal, and the output terminal of the current comparator is connected to the control terminal of the voltage comparison circuit, and is used for sending the voltage comparison circuit to the control terminal.
  • the control terminal inputs the second signal to control the operation of the voltage comparison circuit;
  • the first input terminal of the voltage comparison circuit is connected to the first output terminal of the bandgap reference circuit, the second input terminal of the voltage comparison circuit is connected to a signal used to indicate the voltage of the voltage source, and the output terminal of the voltage comparison circuit is used for output reset Signal.
  • the current comparator includes a first switch and a current mirror
  • the first input end of the current mirror is connected to the first current signal
  • the first end of the first switch is the second current input end and output end of the current comparator
  • the second end of the first switch is connected to the second input end of the current mirror
  • the control end of the first switch is the control end of the current comparator end.
  • the first switch includes a first field effect transistor
  • the drain of the first field effect transistor is the first end of the first switch, the source of the first field effect transistor is the second end of the first switch, and the gate of the first field effect transistor is the control end of the first switch;
  • the drain of the first field effect transistor is connected to the second current signal, the source of the first field effect transistor is connected to the second input end of the current mirror, and the gate of the first field effect transistor is connected to the first output of the bandgap reference circuit end connection.
  • the current comparator further includes a voltage limiting element
  • the first end of the voltage limiting element is the first current input end of the current comparator, the second end of the voltage limiting element is connected to the first input end of the current mirror, and the first input end of the current mirror is connected to the first input end of the current mirror through the voltage limiting element. current signal.
  • the voltage limiting element includes a second field effect transistor
  • the source of the second field effect transistor is the first end of the voltage limiting element, and the drain of the second field effect transistor is the second end of the voltage limiting element;
  • the source of the second field effect transistor is connected to the first current signal
  • the drain of the second field effect transistor is connected to the first input end of the current mirror
  • the gate of the second field effect transistor is connected to the drain of the second field effect transistor connect.
  • the current mirror includes a third field effect transistor and a fourth field effect transistor
  • the drain of the third field effect transistor is the first input end of the current mirror, and the drain of the fourth field effect transistor is the second input end of the current mirror;
  • the drain of the third field effect transistor is connected to the gate, and the gate of the third field effect transistor is connected to the gate of the fourth field effect transistor.
  • the current of the first current signal is greater than the current of the second current signal, and the second signal is a high-level signal.
  • the voltage comparison circuit includes a voltage division control branch and a voltage comparator
  • the input end of the voltage dividing control branch is the second input end of the voltage comparison circuit
  • the control end of the voltage dividing control branch is the control end of the voltage comparing circuit
  • the control end of the voltage dividing control branch is connected with the output end of the current comparator
  • the first output terminal of the voltage dividing control branch is connected to the non-inverting input terminal of the voltage comparator
  • the second output terminal of the voltage dividing control branch is grounded;
  • the inverting input end of the voltage comparator is the first input end of the voltage comparison circuit
  • the output end of the voltage comparator is the output end of the voltage comparing circuit
  • the inverting input end of the voltage comparator and the first output end of the bandgap reference circuit connect.
  • the voltage division control branch includes a voltage comparator, a second switch, a first resistor, and a second resistor;
  • the first end of the second switch is the input end of the voltage divider control branch
  • the control end of the second switch is the control end of the voltage divider control branch
  • the output end of the voltage comparator is the output end of the voltage comparison circuit
  • the first end of the second switch is connected to the voltage source, and the second end of the second switch is connected to the first end of the first resistor;
  • the second end of the first resistor is the first output end of the voltage division control branch, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the first resistor is connected to the positive phase of the voltage comparator. input connection;
  • the second end of the second resistor is the second output end of the voltage dividing control branch, and the second end of the second resistor is grounded.
  • the second switch includes a fifth field effect transistor
  • the gate of the fifth field effect transistor is the control terminal of the second switch, the source of the fifth field effect transistor is the first terminal of the second switch, and the drain of the fifth field effect transistor is the second terminal of the second switch;
  • the gate of the fifth field effect transistor is connected to the output end of the current comparator, the source electrode of the fifth field effect transistor is connected to the voltage source, and the drain electrode of the fifth field effect transistor is connected to the first end of the first resistor.
  • the voltage comparison circuit further includes an inverter
  • the input terminal of the inverter is connected to the output terminal of the current comparator, and the output terminal of the inverter is connected to the enabling terminal of the voltage comparator, and is used for inputting an enabling signal to the enabling terminal of the voltage comparator.
  • the first current signal and the second current signal come from a bandgap reference circuit, and the second output end of the bandgap reference circuit is connected to the first current input end of the current comparator, for inputting the first current signal to the current comparator; the third output terminal of the bandgap reference circuit is connected to the second current input terminal of the current comparator for inputting the second current signal to the current comparator.
  • the bandgap reference circuit includes a start-up circuit and a reference generation circuit
  • the first output end of the reference generation circuit is the first output end of the bandgap reference circuit
  • the second output end of the reference generation circuit is the second output end of the bandgap reference circuit
  • the third output end of the reference generation circuit is the bandgap reference circuit the third output of the circuit
  • the input end of the start-up circuit is connected to the first output end of the reference generation circuit, and the first trigger node of the start-up circuit is connected to the second trigger node of the reference generation circuit for inputting a trigger signal to the second trigger node of the reference generation circuit to Trigger the reference generation circuit to work.
  • the reference generating circuit includes an operational amplifier, and a first branch, a second branch, and a third branch connected in parallel with each other;
  • the first branch, the second branch and the third branch are all connected to the voltage source;
  • the output terminal of the first branch and the output terminal of the second branch are respectively connected to the inverting input terminal and the forward input terminal of the operational amplifier, and the correlation between the voltage and temperature of the output terminal of the first branch is different from that of the second branch.
  • the output terminal of the operational amplifier is respectively connected with the control terminal of the first branch, the control terminal of the second branch and the control terminal of the third branch, and the control terminal of the first branch and the control terminal of the second branch are generated based on the reference The trigger node of the circuit;
  • the output end of the third branch is the first output end of the reference generating circuit.
  • the reference generating circuit further includes a fourth branch and a fifth branch connected in parallel with each other;
  • the output end of the fourth branch is the second output end of the reference generating circuit, the input end of the fourth branch is connected to the voltage source, the control end of the fourth branch is connected to the output end of the operational amplifier, and the output of the fourth branch
  • the terminal is connected to the first current input terminal of the current comparator, and is used for inputting the first current signal to the current comparator;
  • the output end of the fifth branch is the third output end of the reference generation circuit, the input end of the fifth branch is connected to the voltage source, the control end of the fifth branch is connected to the output end of the operational amplifier, and the output of the fifth branch
  • the terminal is connected to the second current input terminal of the current comparator, and is used for inputting the second current signal to the current comparator.
  • the fourth branch includes a sixth field effect transistor
  • the gate of the sixth field effect transistor is the control end of the fourth branch, the source of the sixth field effect transistor is the input end of the fourth branch, and the drain of the sixth field effect transistor is the output end of the fourth branch;
  • the source of the sixth field effect transistor is connected to the voltage source, the gate of the sixth field effect transistor is connected to the output terminal of the operational amplifier, and the drain of the sixth field effect transistor is connected to the first current input terminal of the current comparator.
  • the fifth branch includes a seventh field effect transistor
  • the gate of the seventh field effect transistor is the control end of the fifth branch, the source of the seventh field effect transistor is the input end of the fifth branch, and the drain of the seventh field effect transistor is the output end of the fifth branch;
  • the source of the seventh field effect transistor is connected to the voltage source, the gate of the seventh field effect transistor is connected to the output terminal of the operational amplifier, and the drain of the seventh field effect transistor is connected to the second current input terminal of the current comparator.
  • the third branch includes an eighth field effect transistor and a third resistor
  • the drain of the eighth field effect transistor is the output end of the third branch; the source electrode of the eighth field effect transistor is connected to the voltage source, the gate of the eighth field effect transistor is connected to the output end of the operational amplifier, and the eighth field effect transistor is connected to the output end of the operational amplifier.
  • the drain of the third resistor is connected to the first end of the third resistor; the second end of the third resistor is grounded.
  • the first branch includes a first bipolar junction transistor, a ninth field effect transistor, and a fourth resistor;
  • the grid of the ninth field effect transistor is the control terminal of the first branch, and the drain of the ninth field effect transistor is the output terminal of the first branch;
  • the source of the ninth field effect transistor is connected to the voltage source, the gate of the ninth field effect transistor is connected to the output terminal of the operational amplifier, and the drain of the ninth field effect transistor is connected to the non-inverting input terminal of the operational amplifier;
  • One end of the fourth resistor is connected to the drain of the ninth field effect transistor, and the other end is grounded;
  • the emitter of the first bipolar junction transistor is connected to the drain of the ninth field effect transistor, and both the base and the collector of the first bipolar junction transistor are grounded.
  • the second branch includes a second bipolar junction transistor, a tenth field effect transistor, a fifth resistor and a sixth resistor;
  • the grid of the tenth FET is the control terminal of the second branch, and the drain of the tenth FET is the output terminal of the second branch;
  • the source of the tenth FET is connected to the voltage source, the gate of the tenth FET is connected to the output terminal of the operational amplifier, and the drain of the tenth FET is connected to the inverting input terminal of the operational amplifier;
  • One end of the fifth resistor is connected to the drain of the tenth field effect transistor, and the other end is connected to the emitter of the second bipolar junction transistor;
  • One end of the sixth resistor is connected to the drain of the tenth FET, and the other end is grounded;
  • the collector and base of the second bipolar junction transistor are both grounded.
  • the power-on reset circuit further includes a startup circuit
  • the input end of the start-up circuit is connected with the first output end of the reference generation circuit, the first trigger node of the start-up circuit is connected with the second trigger node of the reference generation circuit, and is used for inputting a trigger signal to the second trigger node of the reference generation circuit to Trigger the reference generation circuit to work.
  • the startup circuit includes an eleventh field effect transistor, a twelfth field effect transistor, and a thirteenth field effect transistor;
  • the gate of the eleventh field effect transistor and the gate of the twelfth field effect transistor are the input ends of the start-up circuit, and the drain of the thirteenth field effect transistor is the first trigger node;
  • the source of the eleventh field effect transistor is connected to the voltage source, the gate of the eleventh field effect transistor is connected to the first output end of the reference generating circuit, and the drain of the eleventh field effect transistor is respectively connected to the twelfth field effect tube.
  • the drain of the tube is connected to the gate of the thirteenth FET;
  • the grid of the twelfth FET is connected to the first output end of the reference generating circuit, and the source of the twelfth FET is grounded;
  • the drain of the thirteenth field effect transistor is connected to the second trigger node, and the source of the thirteenth field effect transistor is grounded.
  • the power-on reset circuit includes a bandgap reference circuit, a current comparator and a voltage comparison circuit.
  • the bandgap reference circuit, the current comparator and the voltage comparison circuit are all powered by a voltage source, because the output of the bandgap reference circuit is powered by a voltage source.
  • the first signal can control the current comparator to work, and the current comparator is powered by the voltage source. Therefore, after the power supply voltage and the bandgap reference circuit meet the requirements, the current comparator will work and output the second signal, using the output signal.
  • the second signal controls the voltage comparator to work, and outputs a reset signal, so as to avoid outputting a reset signal when the bandgap reference circuit is unstable, resulting in errors, reducing false triggering during power-on, and increasing power-on reliability.
  • FIG. 1 is a structural diagram of a power-on reset circuit provided in Embodiment 1 of the present application;
  • FIG. 2 is a structural diagram of a power-on reset circuit according to Embodiment 2 of the present application.
  • FIG. 3 is a structural diagram of a current comparator provided in Embodiment 2 of the present application.
  • FIG. 4 is a structural diagram of another current comparator provided in Embodiment 2 of the present application.
  • FIG. 5 is a structural diagram of a power-on reset circuit provided in Embodiment 3 of the present application.
  • FIG. 6 is a structural diagram of a voltage comparison circuit provided in Embodiment 3 of the present application.
  • FIG. 7 is a structural diagram of a power-on reset circuit according to Embodiment 4 of the present application.
  • FIG. 8 is a structural diagram of a reference generation circuit according to Embodiment 4 of the present application.
  • Embodiment 9 is a structural diagram of another reference generation circuit provided in Embodiment 4 of the present application.
  • FIG. 10 is a structural diagram of another reference generation circuit provided by Embodiment 4 of the present application.
  • FIG. 11 is a structural diagram of a startup circuit according to Embodiment 4 of the present application.
  • FIG. 12 is a structural diagram of a power-on reset circuit according to Embodiment 5 of the present application.
  • FIG. 13 is a schematic diagram of a slow power-on signal change according to Embodiment 5 of the present application.
  • FIG. 14 is a schematic diagram of a fast power-on signal change according to Embodiment 5 of the present application.
  • Embodiment 1 of the present application provides a power-on reset circuit.
  • FIG. 1 is a structural diagram of a power-on reset circuit provided by an embodiment of the present application.
  • the power-on reset circuit 10 provided by the embodiment of the present application includes: a bandgap reference circuit 11, a current comparator 12 and a voltage comparison circuit 13, and the bandgap reference circuit 11, the current comparator 12 and the voltage comparison circuit 13 are all powered by a voltage source;
  • the first output terminal of the bandgap reference circuit 11 is connected with the control terminal of the current comparator 12, and is used for inputting the first signal to the control terminal of the current comparator 12 to control the current comparator 12 to work;
  • the first current input terminal and the second current input terminal of the current comparator 12 are respectively connected to the first current signal and the second current signal, and the output terminal of the current comparator 12 is connected to the control terminal of the voltage comparison circuit 13 for sending the voltage
  • the control terminal of the comparison circuit 13 inputs the second signal to control the operation of the voltage comparison circuit 13;
  • the first input terminal of the voltage comparison circuit 13 is connected to the first output terminal of the bandgap reference circuit 11 , the second input terminal of the voltage comparison circuit 13 is used for a signal indicating the voltage of the voltage source, and the output terminal of the voltage comparison circuit 13 is used for Output power-on reset signal (abbreviation: reset signal).
  • the voltage source may include a voltage conversion module in the chip, and the signal output by the voltage source may be a signal output by the voltage conversion module.
  • the voltage of the voltage source has a process of climbing, and the chip can only start to work when the voltage of the voltage source climbs to a stable state.
  • the bandgap reference circuit 11 is used to output a stable voltage.
  • the bandgap reference circuit 11 includes two signals.
  • the voltage of the first signal is positively correlated with temperature, and the voltage of the second signal is negatively correlated with temperature.
  • an output signal that is less affected by temperature or not affected by temperature can be obtained, that is, the first signal output by the first output end of the bandgap reference circuit 11 .
  • the bandgap reference circuit 11 outputs the first signal to the current comparator 12, and the current comparator 12 starts to work after the voltage of the first signal is greater than or equal to the first preset value, and the power supply voltage is greater than or equal to the second preset value,
  • the output terminal of the current comparator 12 outputs a second signal to the control terminal of the voltage comparison circuit 13 .
  • the second preset value is greater than or equal to the working voltage of the current comparator 12 .
  • the voltage source may be directly connected to the current comparator 12 to supply power to the current comparator 12 , or the voltage source may supply power to the current comparator 12 through the bandgap reference circuit 11 .
  • the comparison result of the current comparator 12 can be fixed.
  • the current comparator 12 can output the low-level signal fixedly, that is, the second signal is
  • the current comparator 12 can output the high-level signal fixedly, that is, the second signal is a high-level signal.
  • the current of the first current signal is greater than the current of the second current signal, and the second signal is a high-level signal.
  • the control terminal of the voltage comparison circuit 13 After the control terminal of the voltage comparison circuit 13 receives the second signal, it starts to work, and compares the first signal output by the bandgap reference circuit 11 with the signal used to indicate the voltage of the voltage source, which is used to indicate the voltage of the voltage source. When the signal is greater than the first signal output by the bandgap reference circuit 11 , it means that the power supply voltage meets the requirements, and the voltage comparison circuit 13 outputs a reset signal. It should be noted that, when the signal for indicating the magnitude of the voltage source voltage is greater than the first signal output by the bandgap reference circuit 11 , the power source voltage at this time may be greater than or equal to the second preset value.
  • the current comparator 12 outputs the second signal, the following two conditions need to be met at the same time: 1) the power supply voltage is greater than or equal to the second preset value, that is, the power supply voltage reaches a stable working voltage that can make the current comparator work, 2) ) The first signal output by the bandgap reference circuit 11 to the current comparator 12 is greater than or equal to the first preset value, that is, the first signal output by the bandgap reference circuit 11 is stable, and the voltage output by the current comparator is controlled, while The second signal also controls the voltage comparison circuit to work.
  • the voltage comparison circuit 13 when the voltage comparison circuit 13 starts to work, it must satisfy that the power supply voltage is greater than or equal to the second preset value, and the first signal output by the bandgap reference circuit 11 is greater than or equal to the first preset value. set value. After the above two conditions are satisfied and the operation starts, the voltage comparison circuit compares the signal indicating the voltage of the voltage source and the first signal output by the bandgap reference circuit 11, and outputs the reset signal, so the output of the reset signal.
  • the premise is not only that the signal used to indicate the voltage of the voltage source is large enough, but also to ensure that the power supply voltage and the bandgap reference circuit meet the above two conditions, so as to avoid outputting the reset signal when the bandgap reference circuit 13 is unstable, resulting in errors. Reduce false triggering during power-on and increase power-on reliability.
  • the voltage comparison circuit can output a reset signal when the signal for indicating the magnitude of the voltage source voltage is greater than the voltage of the first signal.
  • the voltage comparison circuit 13 starts to work under the control of the current comparator 12 only when the power supply voltage is greater than or equal to the second threshold value and the first signal output by the bandgap reference circuit is greater than or equal to the first threshold value, and is used for indicating
  • the reset signal will be output only when the voltage of the voltage source voltage is larger than the voltage of the first signal output by the bandgap reference circuit 11 , which avoids outputting the reset signal when the bandgap reference circuit 11 is unstable, which will cause errors and reduce power-on.
  • the false triggering in the process increases the reliability of power-on.
  • FIG. 2 is a structural diagram of a power-on reset circuit according to Embodiment 2 of the present application.
  • the current comparator 12 includes a first switch 121 and a current mirror 122;
  • the first input terminal of the current mirror 122 is connected to the first current signal; the first terminal of the first switch 121 serves as the second current input terminal and output terminal of the current comparator 12 , and the second terminal of the first switch 121 is connected to the current mirror 122 .
  • the second input end of the first switch 121 is connected to the control end of the current comparator 12, and the control end of the first switch 121 is connected to the bandgap reference circuit.
  • the first input terminal of the current mirror 122 inputs the first current signal, and the current mirror 122 can copy the current, so that the second input terminal of the current mirror 122 also inputs the first current signal, and the first terminal of the first switch 121 inputs the second current signal, when the current of the first current signal is greater than the current of the second current signal, the first end of the first switch 121 is at a low level, and when the current of the first current signal is less than the current of the second current signal, the first switch The first terminal of 121 is high.
  • the first input terminal of the current mirror 122 may be the first current input terminal of the current comparator 12; in another implementation manner, the first input terminal of the current mirror 122 is not The first current input terminal of the current comparator 12 and the first input terminal of the current mirror 122 can be connected to the first current signal through the first current input terminal of the current comparator 12 .
  • first switch 121 and the current mirror 122 may have various forms, and two examples are given here to describe the first switch 121 and the current mirror 122 in detail respectively.
  • the first switch 121 is further described. As shown in FIG. 3 , FIG. The structure diagram of the current comparator 12, the first switch 121 includes a first field effect transistor 1211;
  • the drain of the first field effect transistor 1211 is the first terminal of the first switch 121 , the source of the first field effect transistor 1211 is the second terminal of the first switch 121 , and the gate of the first field effect transistor 1211 is the first terminal of the first switch 121 Control terminal; the drain of the first field effect transistor 1211 is connected to the second current signal, the source of the first field effect transistor 1211 is connected to the second input end of the current mirror 122, the gate of the first field effect transistor 1211 is connected to the belt The first output terminal of the gap reference circuit 11 is connected.
  • the first field effect transistor 1211 can be an N-type field effect transistor.
  • the first field effect transistor 1211 When the gate of the first field effect transistor 1211 is at a high level, the first field effect transistor 1211 is turned on, and the current comparator 12 can output a signal.
  • the gate of the first field effect transistor 1211 When the gate of the first field effect transistor 1211 is at a low level, the first field effect transistor 1211 is turned off, and the current comparator 12 does not output a signal.
  • the gate of the first field effect transistor 1211 is connected to the first output terminal of the bandgap reference circuit 11. Therefore, when the voltage of the first signal output by the first output terminal of the bandgap reference circuit 11 is at a high level (that is, the first The voltage of the signal is greater than the first preset value), the current comparator 12 works. This enables more efficient control of the current comparator 12 operation.
  • the current mirror 122 includes a third field effect transistor 1221 and a fourth field effect transistor 1221.
  • Field effect transistor 1222 the drain of the third field effect transistor 1221 is the first input terminal of the current mirror 122, the drain of the fourth field effect transistor 1222 is the second input terminal of the current mirror 122; the drain of the third field effect transistor 1221 Connected to the gate, the gate of the third field effect transistor 1221 is connected to the gate of the fourth field effect transistor 1222 .
  • FIG. 3 shows not only the first field effect transistor 1211, but also the third field effect transistor 1221 and the fourth field effect transistor 1222, which do not represent the first field effect transistor 1211, the third field effect transistor 1221, and the fourth field effect transistor 1222.
  • the fourth field effect transistor 1222 must exist at the same time, and the current mirror 122 can also adopt other designs.
  • FIG. 3 only exemplarily shows the structure of the current comparator 12 , and does not mean that the present application is limited thereto.
  • FIG. 4 is another current comparator 12 provided in Embodiment 2 of the present application.
  • the current comparator 12 also includes a voltage limiting element 123;
  • the first end of the voltage limiting element 123 is the first current input end of the current comparator 12
  • the second end of the voltage limiting element 123 is connected to the first input end of the current mirror 122
  • the first input end of the current mirror 122 passes through the voltage limiting
  • the element 123 is connected to the first current signal.
  • the voltage limiting element 123 includes a second field effect transistor 1231 ; the source of the second field effect transistor 1231 is the first end of the voltage limiting element 123 , The drain of the second field effect transistor 1231 is the second end of the voltage limiting element 123 ; the source of the second field effect transistor 1231 is connected to the first current signal, and the drain of the second field effect transistor 1231 is connected to the first The input terminal is connected, and the gate of the second field effect transistor 1231 is connected to the drain of the second field effect transistor 1231 .
  • the first current signal and the second current signal may come from an independent current source, and in another implementation manner, the first current signal and the second current signal may come from a bandgap
  • the reference circuit 11 is, of course, only an exemplary description here and does not mean that the present application is limited thereto.
  • the voltage across all components on each branch must be greater than or equal to the driving voltage, and the voltage comparator circuit 12 is driven under the voltage provided by the voltage source. Therefore, the power supply voltage must be large enough to drive each. All components on a branch (each branch is in parallel relationship, the voltage is the same), and adding a voltage limiting element 123 to the current comparator 12 makes the power supply voltage not only able to drive all components on each branch in the original circuit, The voltage limiting element 123 is also driven.
  • FIG. 5 is a structural diagram of a power-on reset circuit according to Embodiment 3 of the present application.
  • the voltage comparison circuit 13 includes a voltage comparator 131 and a voltage division control branch 132; the input terminal of the voltage division control branch 132 is the second input terminal of the voltage comparison circuit 13, and the control terminal of the voltage division control branch 132 is the control terminal of the voltage comparison circuit, the control terminal of the voltage division control branch 132 is connected to the output terminal of the current comparator, the first output terminal of the voltage division control branch 132 is connected to the non-inverting input terminal of the voltage comparator 131, The second output terminal of the voltage control branch 132 is grounded; the inverting input terminal of the voltage comparator 131 is the first input terminal of the voltage comparison circuit, the output terminal of the voltage comparator 131 is the output terminal of the voltage comparison circuit, and the voltage comparator 131 The inverting input terminal of the is connected to the first output terminal of the bandgap reference circuit.
  • the voltage division control branch 132 After the voltage division control branch 132 receives the second signal output by the current comparator 12 through the control terminal, the signal indicating the voltage of the voltage source can be connected, and the voltage comparison circuit 13 can start to work.
  • the signal used to indicate the voltage of the voltage source is finally input to the non-inverting input terminal of the voltage comparator 131, but because the voltage division control branch 132 has a voltage dividing effect, the signal input to the non-inverting input terminal of the voltage comparator 131 can be equal to Or not equal to the voltage of the voltage source, by adjusting the voltage dividing element included in the voltage dividing control branch 132 , the magnitude of the signal input to the non-inverting input terminal of the voltage comparator 131 can be controlled.
  • the voltage threshold of the voltage source outputting the reset signal can be adjusted by adjusting the voltage dividing element.
  • the ratio of the voltage of the voltage source to the voltage of the signal input to the non-inverting input terminal of the voltage comparator 131 can be k, where k is an integer greater than or equal to 1, and the voltage The signal at the non-inverting input terminal of the comparator 131 is larger than the voltage of the first signal at the inverting input terminal, and the voltage comparator 131 outputs a reset signal, that is, the voltage of the voltage source is greater than k times the voltage of the first signal.
  • the voltage of the voltage source can only output the reset signal when the voltage reaches a larger value. If k becomes smaller by adjusting the voltage dividing element, the voltage of the voltage source can output the reset signal when it reaches a smaller voltage value, In this way, it is more flexible to adjust the threshold value of the voltage source.
  • the voltage division control branch 132 includes a second switch 1321, a first resistor 1322 and a second resistor 1323;
  • the first end of the second switch 1321 is the input end of the voltage division control branch 132 (ie, the second input end of the voltage comparison circuit 13 ), and the control end of the second switch 1321 is the control end of the voltage division control branch 132 (ie the control terminal of the voltage comparison circuit 13);
  • the first end of the second switch 1321 is connected to the voltage source, and the second end of the second switch 1321 is connected to the first end of the first resistor 1322;
  • the second end of the first resistor 1322 is the first output end of the voltage dividing control branch 132 , the second end of the first resistor 1322 is connected to the first end of the second resistor 1323 , and the second end of the first resistor 1322 is connected to the voltage
  • the non-inverting input end of the comparator 131 is connected; the second end of the second resistor 1323 is the second output end of the voltage dividing control branch 132 , and the second end of the second resistor 1323 is grounded.
  • the voltage divider elements are the first resistor 1322 and the second resistor 1323 , which are only illustrative, and do not mean that the present application is limited thereto, and other elements for voltage division are also possible.
  • the inverting input terminal of the voltage comparator 131 is connected to the first output terminal of the bandgap reference circuit 11 , that is, the inverting input terminal of the voltage comparator 131 inputs the first signal V BG output by the bandgap reference circuit 11 , and the voltage comparator 131
  • the non-inverting input terminal of the voltage comparator 1322 is connected to the middle point of the first resistor 1322 and the second resistor 1323, that is, the second terminal of the first resistor 1322, the first terminal of the second resistor 1323, and the non-inverting input terminal of the voltage comparator 131.
  • the voltage of the signal from the power supply voltage is affected by the resistance values of the first resistor 1322 and the second resistor 1323.
  • the voltage value V DETECT of the signal input from the non-inverting input terminal of the voltage comparator 131 can be expressed by formula 1 , the formula one is as follows:
  • V DETECT V DD ⁇ R 2 /(R 1 +R 2 ); formula 1
  • V DD represents the power supply voltage
  • R 1 represents the resistance value of the first resistor 1322
  • R 2 represents the resistance value of the second resistor 1323 . If the voltage value of the signal input to the non-inverting input terminal of the voltage comparator 131 is greater than the voltage value of the first signal, the voltage comparator 131 outputs a reset signal.
  • the threshold voltage V TH of the reset signal output by the voltage comparator 131 can be obtained, that is, the voltage when the signal input at the non-inverting input terminal is equal to the voltage of the first signal can be expressed by formula 2, and formula 2 is as follows:
  • V TH V BG ⁇ (R 1 +R 2 )/R 2 ; formula 2
  • V BG represents the voltage of the first signal.
  • the voltage comparison circuit 13 further includes an inverter 133;
  • the input terminal of the inverter is connected to the output terminal of the current comparator 12 , and the output terminal of the inverter is connected to the enable terminal of the voltage comparator 131 for inputting an enable signal to the enable terminal of the voltage comparator 131 .
  • the inverter If the second signal output by the current comparator 12 is at a low level, after passing through the inverter, the inverter outputs a high-level enable signal, so that the voltage comparator 131 can work. On the contrary, if the current comparator 12 outputs The signal is high level, after passing through the inverter, the inverter outputs a low level, then the voltage comparator 131 does not work.
  • the second switch 1321 includes a fifth field effect transistor 13211;
  • the gate of the fifth field effect transistor 13211 is the control terminal of the second switch 1321 , the source of the fifth field effect transistor 13211 is the first end of the second switch 1321 , and the drain of the fifth field effect transistor 13211 is the first terminal of the second switch 1321 . two ends;
  • the gate of the fifth field effect transistor 13211 is connected to the output end of the current comparator 12 , the source electrode of the fifth field effect transistor 13211 is connected to the voltage source, and the drain electrode of the fifth field effect transistor 13211 is connected to the first terminal of the first resistor 1322 end connection.
  • the fifth field effect transistor 13211 may be a P-type field effect transistor, and the gate of the fifth field effect transistor 13211 is connected to the second signal output by the current comparator 12. If the second signal is at a low level, then The fifth field effect transistor 13211 is turned on, and if the second signal is at a high level, the fifth field effect transistor 13211 is turned off.
  • FIG. 6 shows the inverter and the fifth field effect transistor 13211 , this does not mean that the inverter and the fifth field effect transistor 13211 must exist at the same time, and FIG. 6 only exemplarily shows the structure of the voltage comparison circuit 13 .
  • the voltage comparison circuit 13 shown in FIG. 6 as an example, if the second signal output by the current ratio comparator is a low level, the fifth field effect transistor is turned on, and the inverter outputs a high level enable signal, The voltage comparator 131 works normally, and uses a second signal to realize two control, and the control effect is better.
  • the fourth embodiment of the present application further describes the structure of the bandgap reference circuit of the power-on reset circuit by way of example. limited to this.
  • the voltage source can supply power to the current comparator 12 through the bandgap reference circuit 11, and the first current signal and the second current signal come from the bandgap reference circuit 11, and the bandgap reference circuit 11
  • the second output terminal of the band gap reference circuit 11 is connected to the first current input terminal of the current comparator 12 for inputting the first current signal to the current comparator 12; the third output terminal of the bandgap reference circuit 11 is connected to the second current of the current comparator 12.
  • FIG. 7 is a structural diagram of a power-on reset circuit according to Embodiment 4 of the present application.
  • the bandgap reference circuit 11 includes a reference generation circuit 111 and a start-up circuit 112;
  • the first output end of the reference generation circuit 111 is the first output end of the bandgap reference circuit 11
  • the first output end of the reference generation circuit is the first output end of the bandgap reference circuit
  • the second output end of the reference generation circuit 111 is
  • the second output terminal of the bandgap reference circuit 11 and the third output terminal of the reference generation circuit 111 are the third output terminal of the bandgap reference circuit 11;
  • the input terminal of the start-up circuit 112 is connected to the first output terminal of the reference generation circuit 111,
  • the first trigger node of the startup circuit is connected to the second trigger node of the reference generation circuit 111 , and is used for inputting a trigger signal to the second trigger node of the reference generation circuit 111 to trigger the reference generation circuit 111 to work.
  • the structures of the reference generation circuit 111 and the start-up circuit 112 are described in detail here by listing two application scenarios respectively.
  • the structure of the reference generation circuit 111 is described with reference to FIGS. 8 to 10 :
  • FIG. 8 is a structural diagram of a reference generation circuit 111 provided in Embodiment 4 of the present application.
  • the reference generating circuit 111 includes an operational amplifier 1111, and a first branch 1112, a second branch 1113 and a third branch 1114 connected in parallel with each other;
  • the first branch 1112, the second branch 1113 and the third branch 1114 are all connected to the voltage source;
  • the output terminal of the first branch 1112 and the output terminal of the second branch 1113 are respectively connected to the inverting input terminal and the non-inverting input terminal of the operational amplifier 1111.
  • the correlation between the voltage and temperature of the output terminal of the first branch 1112 is different from that of the first branch 1112
  • the output end of the operational amplifier 1111 is respectively connected to the control end of the first branch 1112 , the control end of the second branch 1113 and the control end of the third branch 1114 , the control end of the first branch 1112 and the second branch 1113
  • the control terminal of is the trigger node of the reference generating circuit 111;
  • the output end of the third branch 1114 is the first output end of the reference generating circuit 111 .
  • the correlation between the voltage and temperature of the output terminal of the first branch 1112 is different from the correlation between the voltage and temperature of the output terminal of the second branch 1113.
  • the voltage of the output terminal of the first branch 1112 is positively related to temperature
  • the The voltage at the output end of the circuit 1113 is negatively correlated with temperature
  • the voltage at the output end of the second branch circuit 1113 is positively correlated with the temperature
  • the signal output by the first branch circuit 1112 is After the signal output by the second branch 1113 passes through the operational amplifier 1111, the influence of temperature is reduced, so that the voltage of the first signal output by the third branch 1114 is less affected by temperature or not affected by temperature.
  • the reference generating circuit 111 may output the first current signal and the second current signal to the current comparator 12, as shown in FIG. 9 , which is the fourth embodiment of the present application.
  • FIG. 9 A structural diagram of another reference generation circuit 111 is provided, the reference generation circuit 111 further includes a fourth branch 1115 and a fifth branch 1116 that are connected in parallel with each other;
  • the output end of the fourth branch 1115 is the second output end of the reference generating circuit 111, the input end of the fourth branch 1115 is connected to the voltage source, the control end of the fourth branch 1115 is connected to the output end of the operational amplifier 1111, and the first The output terminal of the four branches 1115 is connected to the first current input terminal of the current comparator 12 for inputting the first current signal to the current comparator 12;
  • the output end of the fifth branch 1116 is the third output end of the reference generating circuit 111, the input end of the fifth branch 1116 is connected to the voltage source, the control end of the fifth branch 1116 is connected to the output end of the operational amplifier 1111, the first The output terminal of the five branches 1116 is connected to the second current input terminal of the current comparator 12 for inputting the second current signal to the current comparator 12 .
  • the fourth branch 1115 includes a sixth field effect transistor 11151;
  • the gate of the sixth field effect transistor 11151 is the control end of the fourth branch 1115 , the source of the sixth field effect transistor 11151 is the input end of the fourth branch 1115 , and the drain of the sixth field effect transistor 11151 is the fourth branch 1115 the output terminal;
  • the source of the sixth field effect transistor 11151 is connected to the voltage source, the gate of the sixth field effect transistor 11151 is connected to the output end of the operational amplifier 1111, and the drain of the sixth field effect transistor 11151 is connected to the first current of the current comparator 12 input connection.
  • the fifth branch 1116 includes a seventh field effect transistor 11161;
  • the gate of the seventh field effect transistor 11161 is the control end of the fifth branch 1116 , the source of the seventh field effect transistor 11161 is the input end of the fifth branch 1116 , and the drain of the seventh field effect transistor 11161 is the fifth branch 1116 the output terminal;
  • the source of the seventh field effect transistor 11161 is connected to the voltage source, the gate of the seventh field effect transistor 11161 is connected to the output end of the operational amplifier 1111, and the drain of the seventh field effect transistor 11161 is connected to the second current of the current comparator 12 input connection.
  • the signal output by the first branch 1112 and the signal output by the second branch 1113 are processed by the operational amplifier 1111 to output a control signal, which can satisfy the requirements of the fifth FET and the sixth FET
  • the conduction condition of 11151, the fifth field effect transistor and the sixth field effect transistor 11151 can be P-type field effect transistors, and the control signal output by the operational amplifier 1111 can be a low level signal, but the control signal is not 0 potential
  • the signal is only a signal smaller than the threshold voltage of the P-type field effect transistor.
  • this is only an exemplary illustration, which does not mean that the present application is limited thereto.
  • FIG. 10 is a structural diagram of another reference generation circuit 111 provided in Embodiment 4 of the present application.
  • the first branch of the reference generation circuit 111 is The structures of the road 1112, the second branch 1113, and the third branch 1114 will be described separately.
  • the structure of the third branch 1114 is described, and the third branch 1114 includes an eighth field effect transistor 11141 and a third resistor 11142;
  • the drain of the eighth field effect transistor 11141 is the output end of the third branch 1114; the source electrode of the eighth field effect transistor 11141 is connected to the voltage source, the gate electrode of the eighth field effect transistor 11141 is connected to the output end of the operational amplifier 1111, The drain of the eighth field effect transistor 11141 is connected to the first end of the third resistor 11142; the second end of the third resistor 11142 is grounded.
  • the eighth field effect transistor 11141 may be a P-type field effect transistor, and the control signal output by the operational amplifier 1111 is low level, then the eighth field effect transistor 11141 is turned on, and the drain of the eighth field effect transistor 11141 outputs the second signal.
  • the first branch 1112 includes a first bipolar junction transistor 11121 and a ninth field effect transistor 11122 and the fourth resistor 11123;
  • the gate of the ninth field effect transistor 11122 is the control terminal of the first branch 1112, and the drain of the ninth field effect transistor 11122 is the output terminal of the first branch 1112;
  • the source of the ninth FET 11122 is connected to the voltage source, the gate of the ninth FET 11122 is connected to the output terminal of the operational amplifier 1111, and the drain of the ninth FET 11122 is connected to the non-inverting input terminal of the operational amplifier 1111 connect;
  • One end of the fourth resistor 11123 is connected to the drain of the ninth field effect transistor 11122, and the other end is grounded;
  • the emitter of the first bipolar junction transistor 11121 is connected to the drain of the ninth field effect transistor 11122, and the base and collector of the first bipolar junction transistor 11121 are both grounded.
  • the ninth field effect transistor 11122 may be a P-type field effect transistor, and the voltage at the output end of the first branch 1112 (ie the voltage at the drain of the ninth field effect transistor 11122) is negatively correlated with temperature.
  • the second branch 1113 includes a second bipolar junction transistor 11131 and a tenth field effect transistor 11132 , the fifth resistor 11133 and the sixth resistor 11134;
  • the gate of the tenth FET 11132 is the control terminal of the second branch 1113 , and the drain of the tenth FET 11132 is the output terminal of the second branch 1113 ;
  • the source of the tenth FET 11132 is connected to the voltage source, the gate of the tenth FET 11132 is connected to the output terminal of the operational amplifier 1111, the drain of the tenth FET 11132 is connected to the inverting input terminal of the operational amplifier 1111 connect;
  • One end of the fifth resistor 11133 is connected to the drain of the tenth field effect transistor 11132, and the other end is connected to the emitter of the second bipolar junction transistor 11131;
  • One end of the sixth resistor 11134 is connected to the drain of the tenth field effect transistor 11132, and the other end is grounded;
  • the collector and base of the second bipolar junction transistor 11131 are both grounded.
  • the tenth field effect transistor 11132 may be a P-type field effect transistor, and the voltage at the output end of the second branch 1113 (ie, the voltage at the drain of the tenth field effect transistor 11132 ) is negatively correlated with temperature.
  • FIG. 10 shows the specific structure of each branch, which does not mean that the embodiments of the present application are limited to this.
  • the structure of the reference generation circuit 111 may also be in other forms. This is not limited. Taking the reference generation circuit 111 shown in FIG. 10 as an example, the eighth field effect transistor 11141, the ninth field effect transistor 11122 and the tenth field effect transistor 11132 form the current mirror 122, and the current on the eighth field effect transistor 11141 is based on The structure of the current mirror 122 is replicated. Similarly, the sixth field effect transistor 11151 and the seventh field effect transistor 11161 and the eighth field effect transistor 11141, the ninth field effect transistor 11122 and the tenth field effect transistor are combined with FIG. 9 and FIG. 10.
  • the effect transistor 11132 also forms the current mirror 122, and the currents of the sixth field effect transistor 11151 and the seventh field effect transistor 11161 are also copied according to the current mirror 122.
  • this is only an exemplary illustration, which does not mean that the present application is limited to this. .
  • FIG. 11 provides the fourth embodiment of the present application.
  • the structure diagram of a start-up circuit the start-up circuit 112 includes an eleventh field effect transistor 1121, a twelfth field effect transistor 1122 and a thirteenth field effect transistor 1123;
  • the gate of the eleventh field effect transistor and the gate of the twelfth field effect transistor are the input ends of the start-up circuit, and the drain of the thirteenth field effect transistor is the first trigger node;
  • the source of the eleventh field effect transistor is connected to the voltage source, the gate of the eleventh field effect transistor is connected to the first output terminal of the reference generating circuit 111, and the drain of the eleventh field effect transistor is respectively connected to the twelfth field effect transistor.
  • the drain of the effect transistor is connected to the gate of the thirteenth field effect transistor;
  • the gate of the twelfth FET is connected to the first output end of the reference generating circuit 111, and the source of the twelfth FET is grounded;
  • the drain of the thirteenth field effect transistor is connected to the second trigger node, and the source of the thirteenth field effect transistor is grounded.
  • the eleventh field effect transistor can be a P-type field effect transistor, and the twelfth field effect transistor and the thirteenth field effect transistor can be N-type field effect transistors, because the input end of the start-up circuit is connected to the reference generation circuit.
  • the first output terminal of 111 is connected, therefore, the first signal output by the first output terminal of the reference generating circuit 111 can control the state of the start-up circuit.
  • the eleventh field effect transistor when the first signal is at a low level, the gates of the eleventh and thirteenth field effect transistors are both low level, the eleventh field effect transistor is turned on, and the thirteenth field effect transistor is turned on. The effect transistor is turned off.
  • the drain of the eleventh FET is at a high level, then the gate of the twelfth FET is at a high level, and the first trigger node (the gate of the twelfth FET is at a high level). ) is a high level, the twelfth field effect transistor is turned on, and the voltage of the second trigger node is pulled to a low level, so that the reference generating circuit 111 works.
  • the second signal is at a high level
  • the gates of the eleventh FET and the thirteenth FET are both at a high level, the eleventh FET is turned off, and the thirteenth FET is turned on.
  • the start-up circuit no longer outputs a trigger signal to the reference generating circuit 111 .
  • the second trigger node may be the output end of the operational amplifier 1111, and the trigger signal may be a low-level signal.
  • the voltage of the second trigger node is Pull it to a low level, so that the eighth field effect transistor 11141, the ninth field effect transistor, and the tenth field effect transistor 11132 are turned on, and the sixth field effect transistor 11151 and the seventh field effect transistor 11161 can also be turned on.
  • the reference generation circuit 111 starts to work, the first output terminal of the reference generation circuit 111 outputs a first signal, and the first signal is a high level, then after the reference generation circuit 111 starts to work, the first trigger node (the twelfth FET gate) becomes low level, the twelfth field effect transistor is turned off, and the reference generation circuit 111 relies on the control signal output from the output end of the operational amplifier 1111 to make the eighth field effect transistor 11141, the ninth field effect, and the tenth field effect The transistor 11132 and the sixth FET 11151 and the seventh FET 11161 remain on.
  • the voltage across the reference generation circuit can ensure that each branch can work. Therefore, If the voltage across the bandgap reference circuit is greater than or equal to the driving voltage of the tenth field effect transistor, the fifth resistor, and the second bipolar junction transistor, it can work normally. Therefore, the bandgap reference circuit in the embodiment of the present application can Works at low pressure and consumes less energy.
  • the fifth embodiment of the present application provides a power-on reset circuit, which is a more comprehensive and detailed description of the power-on reset circuit.
  • M represents the field effect transistor
  • M 1 represents the first field effect transistor
  • M 2 represents the second field effect transistor 1231
  • M 13 represents the thirteenth field effect transistor, which needs to be explained.
  • the names of the components are consistent with the names of the components in the first to fifth embodiments.
  • the power-on reset circuit includes a reference generation circuit 111 , a current comparator 12 , a voltage comparator circuit 13 and start-up circuit 112.
  • the current comparator 12 includes a first field effect transistor M 1 , a second field effect transistor M 2 , a third field effect transistor M 3 , and a fourth field effect transistor M 4 , wherein M 2 , M 3 and M 4 The gate is connected at node net 2 , and the gate and drain of M 3 are connected;
  • the voltage comparison circuit 13 includes a voltage comparator 131 , a fifth field effect transistor M 5 , a first resistor 1322 , a second resistor 1323 and an inverter 133 ;
  • the reference generation circuit 111 includes sixth to tenth field effect transistors, namely M 6 to M 10 , and further includes an operational amplifier 1111, a third resistor 11142, a fourth resistor 11123, a fifth resistor 11133, a sixth resistor 11134, The first bipolar junction transistor 11121, and the second bipolar junction transistor 11131;
  • the start-up circuit 112 includes an eleventh field effect transistor M 11 , a twelfth field effect transistor M 12 and a thirteenth field effect transistor M 13 ;
  • the settling time of the power supply voltage is greater than that of the bandgap reference circuit.
  • the power supply voltage V DD starts to rise slowly from 0, because the band gap reference circuit has not yet started to work, at this time, the voltage V BG output by the first output terminal of the band gap reference circuit is a low level signal. Therefore, the band gap reference circuit In the start-up circuit of , M 11 is turned on first, so that the voltage of the drain net 1 node of M 11 is reversed to a high level that rises along with the power supply voltage.
  • the voltage of the drain net 3 of M 7 is the same as the power supply voltage.
  • the rising high level, which makes M 5 off, the non-inverting input terminal net 5 of the voltage comparator 131 is at a low level.
  • the enable terminal net 4 of the voltage comparator 131 is at a low level, the voltage comparator does not work, and the voltage V OUT output by the voltage comparator is 0.
  • the voltage comparator When the power supply voltage rises to be greater than or equal to the threshold voltage of M2 , the sum of the threshold voltage of M3 and the overdrive voltage of M6 (it can also be said that the power supply voltage rises so that the voltage across the current comparator is greater than or equal to its operating voltage, That is, the power supply voltage is greater than or equal to the second preset value), at this time V BG has stably output a high level, M 1 is turned on, the current comparator works, so that net 3 is turned to a low level, and then M 5 is turned on, net 5 toggles to a high level following the rise of the supply voltage. net 4 flips to a high level following the rise of the supply voltage, and the voltage comparator starts to work. However, because the voltage of net 5 at the non-inverting input of the voltage comparator is less than the voltage V BG at the inverting input of the voltage comparator, the voltage comparator output The voltage V OUT remains at 0.
  • the threshold voltage V TH can be calculated by referring to the formula 2 in the third embodiment, which is not repeated here.
  • the output voltage V OUT of the voltage comparator is turned to a high level following the rise of the power supply voltage to generate a reset signal. The process is shown in Figure 13.
  • the power supply voltage settling time is less than the settling time of the bandgap reference, for example, VDD is powered on for 10us, and the establishment of the bandgap reference circuit takes 100us to complete.
  • VDD power supply voltage
  • M 11 in the start-up circuit of the bandgap reference is turned on first, so that the net 1 turns to a high level that rises with the power supply voltage.
  • M 3 is turned on, the V BP voltage is pulled down to a low level, and the bandgap reference starts to start.
  • net 3 is at a high level that rises along with the power supply voltage, so that M 5 is turned off, so net 5 is at a low level.
  • net 4 is low, the voltage comparator does not work, and the voltage comparator output is 0.
  • the bandgap reference circuit has not been established, and at this time, the power supply voltage has been greater than the threshold voltage of M2 , the threshold voltage of M3 and the overdrive of M6 .
  • the sum of the voltages (it can also be said that the power supply voltage rises so that the voltage across the current comparator is greater than or equal to its operating voltage, that is, the power supply voltage is greater than or equal to the second preset value).
  • the voltage of V BG rises slowly, so M 1 is still not conducting, net 4 is low potential, the voltage comparator does not work, and the output is still 0.
  • the power-on reset circuit includes a bandgap reference circuit, a current comparator and a voltage comparison circuit.
  • the bandgap reference circuit, the current comparator and the voltage comparison circuit are all powered by a voltage source, because the output of the bandgap reference circuit is powered by a voltage source.
  • the first signal can control the current comparator to work, and the current comparator is powered by the voltage source. Therefore, after the power supply voltage and the bandgap reference circuit meet the requirements, the current comparator will work and output the second signal, using the output signal.
  • the second signal controls the voltage comparator to work, and outputs a reset signal, so as to avoid outputting a reset signal when the bandgap reference circuit is unstable, resulting in errors, reducing false triggering during power-on, and increasing power-on reliability.

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Abstract

一种上电复位电路，包括：带隙基准电路(11)、电流比较器(12)和电压比较电路(13)，带隙基准电路(11)、电流比较器(12)及电压比较电路(13)均由电压源供电；其中，带隙基准电路(11)的第一输出端与电流比较器(12)的控制端连接；电流比较器(12)的第一电流输入端及第二电流输入端分别接入第一电流信号和第二电流信号，电流比较器(12)的输出端与电压比较电路(13)的控制端连接；电压比较电路(13)的第一输入端与带隙基准电路(11)的第一输出端连接，电压比较电路(13)的第二输入端接入用于指示来自于电压源电压大小的信号，电压比较电路(13)的输出端用于输出复位信号。避免在基准产生电路不稳定时输出复位信号，导致出现错误，减少上电过程中的误触发，增加了上电的可靠性。

Description

上电复位电路 技术领域
本申请实施例涉及传感器技术领域，尤其涉及上电复位电路。
背景技术
上电复位电路(英文：Power-on Reset Circuit，POR)用于在芯片上电完成后输出复位信号至芯片内其他功能电路模块，以便芯片开始工作，在一些应用场景中，电源电压可能受到温度影响，为了减小温度对电压的影响，为芯片提供稳定电压，通常利用接入电源电压的带隙基准电路为芯片提供稳定电压。以这种应用场景为例，在上电过程中，电源电压由0电位开始增大，在电源电压的驱动下，带隙基准电路也开始工作，当电源电压增大到预设值时，上电复位电路输出复位信号，但实际情况下带隙基准电路可能还没有达到稳定，为芯片提供的电压还不稳定，此时芯片在接收到复位信号后开始工作，容易引发错误，导致芯片无法正常启动。
发明内容
有鉴于此，本发明实施例所解决的技术问题之一在于提供一种上电复位电路，用以克服现有技术中在带隙基准电路不稳定时输出复位信号，导致出现错误的缺陷。
本申请实施例提供了一种上电复位电路，其包括：带隙基准电路、电流比较器和电压比较电路，带隙基准电路、电流比较器及电压比较电路均由电压源供电；
其中，带隙基准电路的第一输出端与电流比较器的控制端连接，用于向电流比较器的控制端输入第一信号，以控制电流比较器工作；
电流比较器的第一电流输入端及第二电流输入端分别接入第一电流信号和第二电流信号，电流比较器的输出端与电压比较电路的控制端连接，用于向电压比较电路的控制端输入第二信号，以控制电压比较电路工作；
电压比较电路的第一输入端与带隙基准电路的第一输出端连接，电压比较电路的第二输入端接入用于指示电压源电压大小的信号，电压比较电路的输出端用于输出复位信号。
可选地，在本申请的一种实施例中，电流比较器包括第一开关和电流镜；
电流镜的第一输入端接入第一电流信号；
第一开关的第一端为电流比较器的第二电流输入端和输出端，第一开关的第二端与电流镜的第二输入端连接，第一开关的控制端为电流比较器的控制端。
可选地，在本申请的一种实施例中，第一开关包括第一场效应管；
第一场效应管的漏极为第一开关的第一端，第一场效应管的源极为第一开关 的第二端，第一场效应管的栅极为第一开关的控制端；
第一场效应管的漏极接入第二电流信号，第一场效应管的源极与电流镜的第二输入端连接，第一场效应管的栅极与带隙基准电路的第一输出端连接。
可选地，在本申请的一种实施例中，电流比较器还包括限压元件；
限压元件的第一端为电流比较器的第一电流输入端，限压元件的第二端与电流镜的第一输入端连接，电流镜的第一输入端通过限压元件接入第一电流信号。
可选地，在本申请的一种实施例中，限压元件包括第二场效应管；
第二场效应管的源极为限压元件的第一端，第二场效应管的漏极为限压元件的第二端；
第二场效应管的源极接入第一电流信号，第二场效应管的漏极与电流镜的第一输入端连接，第二场效应管的栅极与第二场效应管的漏极连接。
可选地，在本申请的一种实施例中，电流镜包括第三场效应管和第四场效应管；
第三场效应管的漏极为电流镜的第一输入端，第四场效应管的漏极为电流镜的第二输入端；
第三场效应管的漏极与栅极连接，第三场效应管的栅极与第四场效应管的栅极连接。
可选地，在本申请的一种实施例中，第一电流信号的电流大于第二电流信号的电流，第二信号为高电平信号。
可选地，在本申请的一种实施例中，电压比较电路包括分压控制支路和电压比较器；
分压控制支路的输入端为电压比较电路的第二输入端，分压控制支路的控制端为电压比较电路的控制端，分压控制支路的控制端与电流比较器的输出端连接，分压控制支路的第一输出端与电压比较器的正相输入端连接，分压控制支路的第二输出端接地；
电压比较器的反相输入端为电压比较电路的第一输入端，电压比较器的输出端为电压比较电路的输出端，电压比较器的反相输入端与带隙基准电路的第一输出端连接。
可选地，在本申请的一种实施例中，分压控制支路包括电压比较器、第二开关、第一电阻和第二电阻；
其中，第二开关的第一端为分压控制支路的输入端，第二开关的控制端为分 压控制支路的的控制端，电压比较器的输出端为电压比较电路的输出端；
第二开关的第一端与电压源连接，第二开关的第二端与第一电阻的第一端连接；
第一电阻的第二端为分压控制支路的第一输出端，第一电阻的第二端与第二电阻的第一端连接，第一电阻的第二端与电压比较器的正相输入端连接；
第二电阻的第二端为分压控制支路的第二输出端，第二电阻的第二端接地。
可选地，在本申请的一种实施例中，第二开关包括第五场效应管；
第五场效应管的栅极为第二开关的控制端，第五场效应管的源极为第二开关的第一端，第五场效应管的漏极为第二开关的第二端；
第五场效应管的栅极与电流比较器的输出端连接，第五场效应管的源极与电压源连接，第五场效应管的漏极与第一电阻的第一端连接。
可选地，在本申请的一种实施例中，电压比较电路还包括反相器；
反相器的输入端与电流比较器的输出端连接，反相器的输出端与电压比较器的使能端连接，用于向电压比较器的使能端输入使能信号。
可选地，在本申请的一种实施例中，第一电流信号和第二电流信号来自带隙基准电路，带隙基准电路的第二输出端与电流比较器的第一电流输入端连接，用于向电流比较器输入第一电流信号；带隙基准电路的第三输出端与电流比较器的第二电流输入端连接，用于向电流比较器输入第二电流信号。
可选地，在本申请的一种实施例中，带隙基准电路包括启动电路和基准产生电路；
基准产生电路的第一输出端为带隙基准电路的第一输出端，基准产生电路的第二输出端为带隙基准电路的第二输出端，基准产生电路的第三输出端为带隙基准电路的第三输出端；
启动电路的输入端与基准产生电路的第一输出端连接，启动电路的第一触发节点与基准产生电路的第二触发节点连接，用于向基准产生电路的第二触发节点输入触发信号，以触发基准产生电路工作。
可选地，在本申请的一种实施例中，基准产生电路包括运算放大器，以及相互并联的第一支路、第二支路和第三支路；
第一支路、第二支路和第三支路均与电压源连接；
第一支路的输出端和第二支路的输出端分别与运算放大器的反相输入端和正向输入端连接，第一支路的输出端的电压与温度的相关性不同于第二支路的输出端 的电压与温度的相关性；
运算放大器的输出端分别与第一支路的控制端、第二支路的控制端以及第三支路的控制端连接，第一支路的控制端和第二支路的控制端为基准产生电路的触发节点；
第三支路的输出端为基准产生电路的第一输出端。
可选地，在本申请的一种实施例中，基准产生电路还包括相互并联的第四支路和第五支路；
第四支路的输出端为基准产生电路的第二输出端，第四支路的输入端与电压源连接，第四支路的控制端与运算放大器的输出端连接，第四支路的输出端与电流比较器的第一电流输入端连接，用于向电流比较器输入第一电流信号；
第五支路的输出端为基准产生电路的第三输出端，第五支路的输入端与电压源连接，第五支路的控制端与运算放大器的输出端连接，第五支路的输出端与电流比较器的第二电流输入端连接，用于向电流比较器输入第二电流信号。
可选地，在本申请的一种实施例中，第四支路包括第六场效应管；
第六场效应管的栅极为第四支路的控制端，第六场效应管的源极为第四支路的输入端，第六场效应管的漏极为第四支路的输出端；
第六场效应管的源极与电压源连接，第六场效应管的栅极与运算放大器的输出端连接，第六场效应管的漏极与电流比较器的第一电流输入端连接。
可选地，在本申请的一种实施例中，第五支路包括第七场效应管；
第七场效应管的栅极为第五支路的控制端，第七场效应管的源极为第五支路的输入端，第七场效应管的漏极为第五支路的输出端；
第七场效应管的源极与电压源连接，第七场效应管的栅极与运算放大器的输出端连接，第七场效应管的漏极与电流比较器的第二电流输入端连接。
可选地，在本申请的一种实施例中，第三支路包括第八场效应管和第三电阻；
第八场效应管的漏极为第三支路的输出端；第八场效应管的源极与电压源连接，第八场效应管的栅极与运算放大器的输出端连接，第八场效应管的漏极与第三电阻的第一端连接；第三电阻的第二端接地。
可选地，在本申请的一种实施例中，第一支路包括第一双极性结型晶体管、第九场效应管和第四电阻；
第九场效应管的栅极为第一支路的控制端，第九场效应管的漏极为第一支路的输出端；
第九场效应管的源极与电压源连接，第九场效应管的栅极与运算放大器的输出端连接，第九场效应管的漏极与运算放大器的正相输入端连接；
第四电阻的一端与第九场效应管的漏极连接，另一端接地；
第一双极性结型晶体管的发射极与第九场效应管的漏极连接，第一双极性结型晶体管的基极和集电极均接地。
可选地，在本申请的一种实施例中，第二支路包括第二双极性结型晶体管、第十场效应管、第五电阻和第六电阻；
第十场效应管的栅极为第二支路的控制端，第十场效应管的漏极为第二支路的输出端；
第十场效应管的源极与电压源连接，第十场效应管的栅极与运算放大器的输出端连接，第十场效应管的漏极与运算放大器的反相输入端连接；
第五电阻的一端与第十场效应管的漏极连接，另一端与第二双极性结型晶体管的发射极连接；
第六电阻的一端与第十场效应管的漏极连接，另一端接地；
第二双极性结型晶体管的集电极和基极均接地。
可选地，在本申请的一种实施例中，上电复位电路还包括启动电路；
启动电路的输入端与基准产生电路的第一输出端连接，启动电路的第一触发节点与基准产生电路的第二触发节点连接，用于向基准产生电路的第二触发节点输入触发信号，以触发基准产生电路工作。
可选地，在本申请的一种实施例中，启动电路包括第十一场效应管、第十二场效应管和第十三场效应管；
其中，第十一场效应管的栅极和第十二场效应管的栅极为启动电路的输入端，第十三场效应管的漏极为第一触发节点；
第十一场效应管的源极与电压源连接，第十一场效应管的栅极与基准产生电路的第一输出端连接，第十一场效应管的漏极分别与第十二场效应管的漏极和第十三场效应管的栅极连接；
第十二场效应管的栅极与基准产生电路的第一输出端连接，第十二场效应管的源极接地；
第十三场效应管的漏极与第二触发节点连接，第十三场效应管的源极接地。
本申请实施例提供的上电复位电路，包括带隙基准电路、电流比较器和电压比较电路，带隙基准电路、电流比较器及电压比较电路均由电压源供电，因为带隙 基准电路输出的第一信号可以控制电流比较器工作，而电流比较器由电压源供电，因此，在电源电压和带隙基准电路都达到要求后，电流比较器才会工作，并输出第二信号，利用输出的第二信号控制电压比较器工作，并输出复位信号，避免在带隙基准电路不稳定时输出复位信号，导致出现错误，减少上电过程中的误触发，增加了上电的可靠性。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比值绘制的。附图中：
图1为本申请实施例一提供的一种上电复位电路的结构图；
图2为本申请实施例二提供的一种上电复位电路的结构图；
图3为本申请实施例二提供的一种电流比较器的结构图；
图4为本申请实施例二提供的另一种电流比较器的结构图；
图5为本申请实施例三提供的一种上电复位电路的结构图；
图6为本申请实施例三提供的一种电压比较电路的结构图；
图7为本申请实施例四提供的一种上电复位电路的结构图；
图8为本申请实施例四提供的一种基准产生电路的结构图；
图9为本申请实施例四提供的另一种基准产生电路的结构图；
图10为本申请实施例四提供的又一种基准产生电路的结构图；
图11为本申请实施例四提供的一种启动电路的结构图；
图12为本申请实施例五提供的一种上电复位电路的结构图；
图13为本申请实施例五提供的一种慢上电信号变化示意图；
图14为本申请实施例五提供的一种快上电信号变化示意图。
具体实施方式
下面结合本发明实施例附图进一步说明本发明实施例具体实现。
实施例一
本申请实施例一提供一种上电复位电路，如图1所示，图1为本申请实施例提供的一种上电复位电路的结构图。本申请实施例提供的上电复位电路10包括：带隙基准电路11、电流比较器12和电压比较电路13，带隙基准电路11、电流比较器12及电压比较电路13均由电压源供电；
其中，带隙基准电路11的第一输出端与电流比较器12的控制端连接，用于 向电流比较器12的控制端输入第一信号，以控制电流比较器12工作；
电流比较器12的第一电流输入端及第二电流输入端分别接入第一电流信号和第二电流信号，电流比较器12的输出端与电压比较电路13的控制端连接，用于向电压比较电路13的控制端输入第二信号，以控制电压比较电路13工作；
电压比较电路13的第一输入端与带隙基准电路11的第一输出端连接，电压比较电路13的第二输入端用于指示电压源电压大小的信号，电压比较电路13的输出端用于输出上电复位信号(简称：复位信号)。
需要说明的是，可选地，电压源可以包括芯片中的电压转换模块，电压源输出的信号可以是电压转换模块输出的信号，当然，此处只是示例性说明。因为在对芯片上电过程中，电信号流过芯片中的元件需要一定时间，因此，电压源的电压有一个爬升的过程，等到电压源的电压爬升到稳定状态，芯片才可以开始工作。
可选地，带隙基准电路11用于输出稳定电压，通常，带隙基准电路11包含两路信号，第一路信号的电压与温度正相关，第二路信号的电压与温度负相关，将两路信号进行融合，就可以得到受温度影响较小或者不受温度影响的输出信号，即带隙基准电路11的第一输出端输出的第一信号。
带隙基准电路11向电流比较器12输出第一信号，电流比较器12在第一信号的电压大于或等于第一预设值，且电源电压大于或等于第二预设值后，开始工作，电流比较器12的输出端向电压比较电路13的控制端输出第二信号，需要说明的是，第二预设值大于或等于电流比较器12的工作电压。需要说明的是，电压源可以直接连接到电流比较器12，向电流比较器12供电，也可以是电压源通过带隙基准电路11向电流比较器12供电。电流比较器12的比较结果可以是固定的，例如，电压比较电路13的控制端在接收到低电平信号后开始工作，则电流比较器12可以固定输出低电平信号，即第二信号为低电平信号；又如，电压比较电路13的控制端在接收到高电平信号后开始工作，则电流比较器12可以固定输出高电平信号，即第二信号为高电平信号。可选地，在本申请的一种实施例中，第一电流信号的电流大于第二电流信号的电流，第二信号为高电平信号。
电压比较电路13的控制端接收到第二信号后，开始工作，并将带隙基准电路11输出的第一信号与用于指示电压源电压大小的信号进行比较，用于指示电压源电压大小的信号大于带隙基准电路11输出的第一信号时，说明电源电压满足要求，电压比较电路13输出复位信号。需要说明的是，在用于指示电压源电压大小的信号大于带隙基准电路11输出的第一信号时，此时的电源电压可以大于或等于第二预设值。
因为电流比较器12输出第二信号，需要同时满足以下两个条件：1)电源电压大于或等于第二预设值，也就是电源电压达到稳定的，能够使电流比较器工作的工作电压，2)带隙基准电路11向电流比较器12输出的第一信号大于或等于第一预设值，也就是带隙基准电路11输出的第一信号达到稳定的，控制电流比较器输出的电压，而第二信号又控制电压比较电路工作，因此，电压比较电路13开始工作，就必须满足电源电压大于或等于第二预设值，且带隙基准电路11输出的第一信号大于或等于第一预设值。在满足上述两个条件并开始工作后，电压比较电路才会比较用于指示电压源电压大小的信号以及带隙基准电路11输出的第一信号的大小，并输出复位信号，故而输出复位信号的前提不仅仅是用于指示电压源电压的信号足够大，还需要保证电源电压和带隙基准电路达到上述两个条件，避免了在带隙基准电路13不稳定时输出复位信号，导致出现错误，减少上电过程中的误触发，增加了上电的可靠性。
进一步地，电压比较电路，可以在用于指示电压源电压大小的信号比第一信号的电压大时，输出复位信号。电压比较电路13，在电源电压大于或等于第二阈值，且带隙基准电路输出的第一信号大于或等于第一阈值，才会在电流比较器12的控制下开始工作，并且在用于指示电压源电压大小的信号比带隙基准电路11输出的第一信号的电压大时，才会输出复位信号，避免了在带隙基准电路11不稳定时输出复位信号，导致出现错误，减少上电过程中的误触发，增加了上电的可靠性。
实施例二
本申请实施例二基于实施例一中上电复位电路的结构，示例性地对该上电复位电路的电流比较器12的结构进行进一步说明，当然，此处只是示例性说明，不代表本申请局限于此。如图2所示，图2为本申请实施例二提供的一种上电复位电路的结构图。可选地，在本实施例中，电流比较器12包括第一开关121和电流镜122；
电流镜122的第一输入端接入第一电流信号；第一开关121的第一端作为电流比较器12的第二电流输入端和输出端，第一开关121的第二端与电流镜122的第二输入端连接，第一开关121的控制端为电流比较器12的控制端连接到带隙基准电路。
电流镜122的第一输入端输入第一电流信号，电流镜122可以复制电流，使得电流镜122的第二输入端也输入第一电流信号，而第一开关121的第一端输入第二电流信号，在第一电流信号的电流大于第二电流信号的电流时，第一开关121的第一端为低电平，在第一电流信号的电流小于第二电流信号的电流时，第一开关121 的第一端为高电平。需要说明的是，在一种实现方式中，电流镜122的第一输入端可以是电流比较器12的第一电流输入端；在另一种实现方式中，电流镜122的第一输入端不是电流比较器12的第一电流输入端，电流镜122的第一输入端可以通过电流比较器12的第一电流输入端接入第一电流信号。
需要说明的是，第一开关121和电流镜122的形式可以有多种，此处列举两个示例分别对第一开关121和电流镜122进行详细说明。
可选地，基于上述图2所示的上电复位电路，在第一个示例中，对第一开关121进行进一步说明，如图3所示，图3为本申请实施例二提供的一种电流比较器12的结构图，第一开关121包括第一场效应管1211；
第一场效应管1211的漏极为第一开关121的第一端，第一场效应管1211的源极为第一开关121的第二端，第一场效应管1211的栅极为第一开关121的控制端；第一场效应管1211的漏极接入第二电流信号，第一场效应管1211的源极与电流镜122的第二输入端连接，第一场效应管1211的栅极与带隙基准电路11的第一输出端连接。
需要说明的是，第一场效应管1211可以是N型场效应管，在第一场效应管1211的栅极为高电平时，第一场效应管1211导通，电流比较器12可以输出信号，在第一场效应管1211的栅极为低电平时，第一场效应管1211关断，电流比较器12不输出信号。第一场效应管1211的栅极与带隙基准电路11的第一输出端连接，因此，在带隙基准电路11的第一输出端输出的第一信号的电压是高电平时(即第一信号的电压大于第一预设值)，电流比较器12才工作。这能够更有效地控制电流比较器12工作。
可选地，基于上述图2所示的上电复位电路，在第二个示例中，对电流镜122进行进一步说明，如图3所示，电流镜122包括第三场效应管1221和第四场效应管1222；第三场效应管1221的漏极为电流镜122的第一输入端，第四场效应管1222的漏极为电流镜122的第二输入端；第三场效应管1221的漏极与栅极连接，第三场效应管1221的栅极与第四场效应管1222的栅极连接。
图3中不仅示出了第一场效应管1211，还示出了第三场效应管1221、第四场效应管1222，这并不代表第一场效应管1211和第三场效应管1221、第四场效应管1222必须同时存在，电流镜122也可以采用其他设计，图3只是示例性展示电流比较器12的结构，并不代表本申请局限于此。
基于上述图2所示的电流比较器12，可选地，在本申请的一种实施例中，如 图4所示，图4为本申请实施例二提供的另一种电流比较器12的结构图，电流比较器12还包括限压元件123；
限压元件123的第一端为电流比较器12的第一电流输入端，限压元件123的第二端与电流镜122的第一输入端连接，电流镜122的第一输入端通过限压元件123接入第一电流信号。
可选地，在本申请的一种实施例中，如图4所示，限压元件123包括第二场效应管1231；第二场效应管1231的源极为限压元件123的第一端，第二场效应管1231的漏极为限压元件123的第二端；第二场效应管1231的源极接入第一电流信号，第二场效应管1231的漏极与电流镜122的第一输入端连接，第二场效应管1231的栅极与第二场效应管1231的漏极连接。
需要说明的是，在一种实现方式中，第一电流信号和第二电流信号可以来自一个独立的电流源，在另一种实现方式中，第一电流信号和第二电流信号可以来自带隙基准电路11，当然，此处只是示例性说明并不代表本申请局限于此。
电流比较器12如果要正常工作，每一条支路上的所有元件两端的电压都必须大于或等于驱动电压，电压比较电路12在电压源提供的电压下驱动，因此，电源电压必须大到足够驱动每一条支路上的所有元件(各支路为并联关系，电压相同)，而在电流比较器12中增加限压元件123，就使得电源电压不仅要能够驱动原本电路中每一条支路上的所有元件，还要驱动限压元件123，相比于原电路，这就使得电源电压必须达到更大才能够使得电流比较器12工作，相当于提高了第二预设值，保证了在电源电压更大，更稳定的情况下，使得电流比较器12工作，进一步提高了上电的可靠性。
实施例三
本申请实施例三基于实施例一中上电复位电路的结构，示例性地对该上电复位电路的电压比较电路13的结构进行进一步说明，当然，此处只是示例性说明，不代表本申请局限于此。如图5所示，图5为本申请实施例三提供的一种上电复位电路的结构图。可选地，电压比较电路13包括电压比较器131和分压控制支路132；分压控制支路132的输入端为电压比较电路13的第二输入端，分压控制支路132的控制端为电压比较电路的控制端，分压控制支路132的控制端与电流比较器的输出端连接，分压控制支路132的第一输出端与电压比较器131的正相输入端连接，分压控制支路132的第二输出端接地；电压比较器131的反相输入端为电压比较电路的第一输入端，电压比较器131的输出端为电压比较电路的输出端，电压比较器131 的反相输入端与带隙基准电路的第一输出端连接。
分压控制支路132通过控制端接收到电流比较器12输出的第二信号后，才能够接入用于指示电压源电压大小的信号，电压比较电路13才能开始工作。用于指示电压源电压大小的信号最终输入了电压比较器131的正相输入端，但因为分压控制支路132具有分压作用，因此，输入电压比较器131的正相输入端的信号可以等于或者不等于电压源的电压，通过调整分压控制支路132中包含的分压元件，可以控制输入电压比较器131正相输入端的信号的大小。因此，可以通过调整分压元件，对输出复位信号的电压源的电压阈值进行调整。示例性地，因为分压控制支路132的分压作用，可以使得电压源的电压与输入电压比较器131正相输入端的信号的电压的比值为k，k为大于或等于1的整数，电压比较器131正相输入端的信号比反相输入端的第一信号的电压大，电压比较器131输出复位信号，也就是电压源的电压要大于k倍的第一信号的电压，通过调整分压元件，使得k变大，则电压源的电压达到更大才能输出复位信号，如果通过调整分压元件，使得k变小，则电压源的电压在达到更小的电压值时就可以输出复位信号，这样调整电压源的阈值更加灵活。
可选地，在本实施例中，如图5所示，分压控制支路132包括第二开关1321、第一电阻1322和第二电阻1323；
其中，第二开关1321的第一端为分压控制支路132的输入端(即电压比较电路13的第二输入端)，第二开关1321的控制端为分压控制支路132的控制端(即电压比较电路13的控制端)；
第二开关1321的第一端与电压源连接，第二开关1321的第二端与第一电阻1322的第一端连接；
第一电阻1322的第二端为分压控制支路132的第一输出端，第一电阻1322的第二端与第二电阻1323的第一端连接，第一电阻1322的第二端与电压比较器131的正相输入端连接；第二电阻1323的第二端为分压控制支路132的第二输出端，第二电阻1323的第二端接地。
需要说明的是，图5中，分压元件为第一电阻1322和第二电阻1323，这只是举例示意，并不代表本申请局限于此，用于分压的其他元件也是可以的。电压比较器131的反相输入端与带隙基准电路11的第一输出端连接，即电压比较器131的反相输入端输入带隙基准电路11输出的第一信号V BG，电压比较器131的正相输入端连接在第一电阻1322和第二电阻1323的中间点，即第一电阻1322的第二端，第二电阻1323的第一端，电压比较器131的正相输入端输入的来自于电源电压的信号， 其电压受第一电阻1322和第二电阻1323阻值的影响，示例性的，电压比较器131的正相输入端输入的信号的电压值V DETECT可以用公式一表示，公式一如下：
V DETECT＝V DD×R 2/(R 1+R 2)；公式一
其中，V DD表示电源电压，R 1表示第一电阻1322的电阻值，R 2表示第二电阻1323的电阻值。如果电压比较器131的正相输入端输入的信号的电压值大于第一信号的电压值，则电压比较器131输出复位信号。
根据公式一，可以得到电压比较器131输出复位信号的阈值电压V TH，即正相输入端输入的信号与第一信号的电压相等时的电压，可以用公式二表示，公式二如下：
V TH＝V BG×(R 1+R 2)/R 2；公式二
其中，V BG表示第一信号的电压。当然，此处只是示例性说明，并不代表本申请局限于此。
可选地，基于图5所示的上电复位电路，对电压比较器131的使能信号进行说明，如图6所示，图6为本申请实施例三提供的一种电压比较电路13的结构图，在本申请的一种实施例中，电压比较电路13还包括反相器133；
反相器的输入端与电流比较器12的输出端连接，反相器的输出端与电压比较器131的使能端连接，用于向电压比较器131的使能端输入使能信号。
如果电流比较器12输出的第二信号是低电平，通过反相器后，反相器输出高电平的使能信号，即可使得电压比较器131工作，相反，如果电流比较器12输出的信号是高电平，通过反相器后，反相器输出低电平，则电压比较器131不工作。
可选地，在本申请的一种实施例中，如图6所示，第二开关1321包括第五场效应管13211；
第五场效应管13211的栅极为第二开关1321的控制端，第五场效应管13211的源极为第二开关1321的第一端，第五场效应管13211的漏极为第二开关1321的第二端；
第五场效应管13211的栅极与电流比较器12的输出端连接，第五场效应管13211的源极与电压源连接，第五场效应管13211的漏极与第一电阻1322的第一端连接。
需要说明的是，第五场效应管13211可以是P型场效应管，第五场效应管13211的栅极接入电流比较器12输出的第二信号，如果第二信号是低电平，则第五场效应管13211导通，如果第二信号是高电平，则第五场效应管13211关断。
虽然图6示出了反相器和第五场效应管13211，但这不代表反相器和第五场效应管13211必须同时存在，图6只是示例性展示电压比较电路13的结构。以图6所示的电压比较电路13为例，如果电流比比较器输出的第二信号是低电平，则第五场效应管导通，且反相器输出高电平的使能信号，电压比较器131正常工作，利用一个第二信号，实现了两处控制，控制效果更好。
实施例四
本申请实施例四基于实施例一中上电复位电路的结构，示例性地对该上电复位电路的带隙基准电路的结构进行进一步说明，当然，此处只是示例性说明，不代表本申请局限于此。可选地，在本申请的实施例四中，电压源可以通过带隙基准电路11向电流比较器12供电，第一电流信号和第二电流信号来自带隙基准电路11，带隙基准电路11的第二输出端与电流比较器12的第一电流输入端连接，用于向电流比较器12输入第一电流信号；带隙基准电路11的第三输出端与电流比较器12的第二电流输入端连接，用于向电流比较器12输入第二电流信号。如图7所示，图7为本申请实施例四提供的一种上电复位电路的结构图。带隙基准电路11包括基准产生电路111和启动电路112；
基准产生电路111的第一输出端为带隙基准电路11的第一输出端，基准产生电路的第一输出端为带隙基准电路的第一输出端，基准产生电路111的第二输出端为带隙基准电路11的第二输出端，基准产生电路111的第三输出端为带隙基准电路11的第三输出端；启动电路112的输入端与基准产生电路111的第一输出端连接，启动电路的第一触发节点与基准产生电路111的第二触发节点连接，用于向基准产生电路111的第二触发节点输入触发信号，以触发基准产生电路111工作。
此处分别列举两个应用场景对基准产生电路111和启动电路112的结构进行详细说明。
在第一个应用场景中，结合图8-图10，对基准产生电路111的结构进行说明：
可选地，如图8所示，图8为本申请实施例四提供的一种基准产生电路111的结构图。在本实施例中，基准产生电路111包括运算放大器1111，以及相互并联的第一支路1112、第二支路1113和第三支路1114；
第一支路1112、第二支路1113和第三支路1114均与电压源连接；
第一支路1112的输出端和第二支路1113的输出端分别与运算放大器1111的反相输入端和正向输入端连接，第一支路1112的输出端的电压与温度的相关性不同于第二支路1113的输出端的电压与温度的相关性；
运算放大器1111的输出端分别与第一支路1112的控制端、第二支路1113的控制端以及第三支路1114的控制端连接，第一支路1112的控制端和第二支路1113的控制端为基准产生电路111的触发节点；
第三支路1114的输出端为基准产生电路111的第一输出端。
第一支路1112的输出端的电压与温度的相关性不同于第二支路1113的输出端的电压与温度的相关性，例如，第一支路1112的输出端的电压与温度正相关，第二支路1113的输出端的电压与温度负相关；或者，第一支路1112的输出端的电压与温度负相关，第二支路1113的输出端的电压与温度正相关，第一支路1112输出的信号与第二支路1113输出的信号，经过运算放大器1111后，就减少了温度的影响，使得第三支路1114输出的第一信号的电压受温度影响较小或者不受温度影响。
进一步可选地，在本申请的一种实施例中，基准产生电路111可以向电流比较器12输出第一电流信号和第二电流信号，如图9所示，图9为本申请实施例四提供的另一种基准产生电路111的结构图，基准产生电路111还包括相互并联的第四支路1115和第五支路1116；
第四支路1115的输出端为基准产生电路111的第二输出端，第四支路1115的输入端与电压源连接，第四支路1115的控制端与运算放大器1111的输出端连接，第四支路1115的输出端与电流比较器12的第一电流输入端连接，用于向电流比较器12输入第一电流信号；
第五支路1116的输出端为基准产生电路111的第三输出端，第五支路1116的输入端与电压源连接，第五支路1116的控制端与运算放大器1111的输出端连接，第五支路1116的输出端与电流比较器12的第二电流输入端连接，用于向电流比较器12输入第二电流信号。
可选地，在本申请的一种实施例中，如图9所示，第四支路1115包括第六场效应管11151；
第六场效应管11151的栅极为第四支路1115的控制端，第六场效应管11151的源极为第四支路1115的输入端，第六场效应管11151的漏极为第四支路1115的输出端；
第六场效应管11151的源极与电压源连接，第六场效应管11151的栅极与运算放大器1111的输出端连接，第六场效应管11151的漏极与电流比较器12的第一电流输入端连接。
可选地，在本申请的一种实施例中，如图9所示，第五支路1116包括第七场 效应管11161；
第七场效应管11161的栅极为第五支路1116的控制端，第七场效应管11161的源极为第五支路1116的输入端，第七场效应管11161的漏极为第五支路1116的输出端；
第七场效应管11161的源极与电压源连接，第七场效应管11161的栅极与运算放大器1111的输出端连接，第七场效应管11161的漏极与电流比较器12的第二电流输入端连接。
需要说明的是，第一支路1112输出的信号与第二支路1113输出的信号，经过运算放大器1111处理后输出一个控制信号，该控制信号可以满足第五场效应管和第六场效应管11151的导通条件，第五场效应管和第六场效应管11151可以是P型场效应管，运算放大器1111输出的控制信号可以是一个低电平信号，但该控制信号并不是0电位的信号，只不过是小于P型场效应管的阈值电压的信号，当然，此处只是示例性说明，并不代表本申请局限于此。
可选地，基于图8所示的基准产生电路，图10为本申请实施例四提供的又一种基准产生电路111的结构图，以图10为例，对基准产生电路111的第一支路1112、第二支路1113和第三支路1114的结构分别进行说明。
可选地，在第一个示例中，如图10所示，对第三支路1114的结构进行说明，第三支路1114包括第八场效应管11141和第三电阻11142；
第八场效应管11141的漏极为第三支路1114的输出端；第八场效应管11141的源极与电压源连接，第八场效应管11141的栅极与运算放大器1111的输出端连接，第八场效应管11141的漏极与第三电阻11142的第一端连接；第三电阻11142的第二端接地。
第八场效应管11141可以是P型场效应干，运算放大器1111输出的控制信号是低电平，则第八场效应管11141导通，第八场效应管11141的漏极输出第二信号。
可选地，在第二个示例中，如图10所示，对第一支路1112的结构进行说明，第一支路1112包括第一双极性结型晶体管11121、第九场效应管11122和第四电阻11123；
第九场效应管11122的栅极为第一支路1112的控制端，第九场效应管11122的漏极为第一支路1112的输出端；
第九场效应管11122的源极与电压源连接，第九场效应管11122的栅极与运算放大器1111的输出端连接，第九场效应管11122的漏极与运算放大器1111的正 相输入端连接；
第四电阻11123的一端与第九场效应管11122的漏极连接，另一端接地；
第一双极性结型晶体管11121的发射极与第九场效应管11122的漏极连接，第一双极性结型晶体管11121的基极和集电极均接地。
需要说明的是，第九场效应管11122可以是P型场效应管，第一支路1112输出端的电压(即第九场效应管11122漏极的电压)与温度负相关。
可选地，在第三个示例中，如图10所示，对第二支路1113的结构进行说明，第二支路1113包括第二双极性结型晶体管11131、第十场效应管11132、第五电阻11133和第六电阻11134；
第十场效应管11132的栅极为第二支路1113的控制端，第十场效应管11132的漏极为第二支路1113的输出端；
第十场效应管11132的源极与电压源连接，第十场效应管11132的栅极与运算放大器1111的输出端连接，第十场效应管11132的漏极与运算放大器1111的反相输入端连接；
第五电阻11133的一端与第十场效应管11132的漏极连接，另一端与第二双极性结型晶体管11131的发射极连接；
第六电阻11134的一端与第十场效应管11132的漏极连接，另一端接地；
第二双极性结型晶体管11131的集电极和基极均接地。
需要说明的是，第十场效应管11132可以是P型场效应管，第二支路1113输出端的电压(即第十场效应管11132漏极的电压)与温度负相关。
结合上述三个示例，需要说明的是，图10示出了每个支路的具体结构，并不代表本申请实施例局限于此，基准产生电路111的结构也可以是其他形式，本申请对此不作限制。以图10所示的基准产生电路111为例，第八场效应管11141、第九场效应管11122和第十场效应管11132形成了电流镜122，第八场效应管11141上的电流是根据电流镜122结构复制的，同理，将图9和图10结合起来，第六场效应管11151和第七场效应管11161与第八场效应管11141、第九场效应管11122和第十场效应管11132也形成了电流镜122，第六场效应管11151和第七场效应管11161的电流也是根据电流镜122复制的，当然，此处只是示例性说明，并不代表本申请局限于此。
在第二种应用场景中，结合图11，对启动电路112的结构进行说明，可选地，在本申请的一种实施例中，如图11所示，图11为本申请实施例四提供的一种启动 电路的结构图，启动电路112包括第十一场效应管1121、第十二场效应管1122和第十三场效应管1123；
其中，第十一场效应管的栅极和第十二场效应管的栅极为启动电路的输入端，第十三场效应管的漏极为第一触发节点；
第十一场效应管的源极与电压源连接，第十一场效应管的栅极与基准产生电路111的第一输出端连接，第十一场效应管的漏极分别与第十二场效应管的漏极和第十三场效应管的栅极连接；
第十二场效应管的栅极与基准产生电路111的第一输出端连接，第十二场效应管的源极接地；
第十三场效应管的漏极与第二触发节点连接，第十三场效应管的源极接地。
需要说明的是，第十一场效应管可以是P型场效应管，第十二场效应管和第十三场效应管可以是N型场效应管，因为启动电路的输入端与基准产生电路111的第一输出端连接，因此，基准产生电路111的第一输出端输出的第一信号可以控制启动电路的状态。结合图11所示，在第一信号是低电平时，第十一场效应管和第十三场效应管的栅极均为低电平，第十一场效应管导通，第十三场效应管关断，此时，第十一场效应管的漏极为高电平，则第十二场效应管的栅极为高电平，则第一触发节点(第十二场效应管的栅极)为高电平，第十二场效应管导通，将第二触发节点的电压拉至低电平，使得基准产生电路111工作。在第二信号是高电平时，第十一场效应管和第十三场效应管的栅极均为高电平，第十一场效应管关断，第十三场效应管导通，此时，第一触发节点(第十二场效应管的栅极)为低电平，启动电路不再向基准产生电路111输出触发信号。结合图9所示的基准产生电路111，第二触发节点可以是运算放大器1111的输出端，触发信号可以是低电平信号，在第一触发节点为高电平时，第二触发节点的电压被拉至低电平，使得第八场效应管11141、第九场效应、第十场效应管11132导通，还可以使得第六场效应管11151和第七场效应管11161导通，此时，基准产生电路111开始工作，基准产生电路111的第一输出端输出第一信号，第一信号是高电平，则基准产生电路111开始工作后，第一触发节点(第十二场效应管的栅极)变为低电平，第十二场效应管关断，基准产生电路111依靠运算放大器1111的输出端输出的控制信号使得第八场效应管11141、第九场效应、第十场效应管11132以及第六场效应管11151和第七场效应管11161保持导通。
结合图10所示的基准产生电路，因为第一支路、第二支路和第三支路是并联 的，因此，基准产生电路两端电压保证每一个支路都能工作即可，因此，带隙基准电路两端的电压大于或等于第十场效应管、第五电阻、第二双极性结型晶体管的驱动电压，就可以正常工作，因此，本申请实施例中的带隙基准电路可以在低压下工作，能耗较低。
实施例五
基于实施例一至实施例四中所描述的上电复位电路以及上电复位电路中各个电路的具体结构，本申请实施例五提供一种上电复位电路，对上电复位电路进行更全面详细地说明，本实施例中，以M表示场效应管，M 1表示第一场效应管，M 2表示第二场效应管1231，以此类推，M 13表示第十三场效应管，需要说明的时，本申请实施例五中，各个元件的名称与实施例一至实施例五中的元件名称一致，如图12所示，该上电复位电路包括基准产生电路111、电流比较器12、电压比较电路13和启动电路112。
其中，电流比较器12包括第一场效应管M 1，第二场效应管M 2，第三场效应管M 3，第四场效应管M 4，其中，M 2、M 3和M 4的栅极在节点net 2连接，且M 3的栅极和漏极连接；
电压比较电路13包括电压比较器131、第五场效应管M 5、第一电阻1322、第二电阻1323和反相器133；
基准产生电路111包括第六场效应管～第十场效应管，即M 6～M 10，还包括运算放大器1111、第三电阻11142、第四电阻11123、第五电阻11133、第六电阻11134、第一双极性结型晶体管11121，以及第二双极性结型晶体管11131；
启动电路112包括第十一场效应管M 11、第十二场效应管M 12和第十三场效应管M 13；
各个元件之间的连接关系在实施例一至实施例五中详细描述，此处不再赘述。
此处基于图12所示的上电复位电路，分别对电源快上电和电源慢上电两种上电过程进行详细说明。
可选地，在电源慢上电时，即电源电压建立时间大于带隙基准电路的建立时间，例如，电源电压V DD上电需要1ms，而带隙基准电路建立完成需要100us。电源电压V DD从0开始缓慢上升时，因为带隙基准电路还没有开始工作，此时，带隙基准电路的第一输出端输出的电压V BG是低电平信号，因此，带隙基准电路的启动电路中，M 11首先导通，使得M 11的漏极net 1节点的电压翻转为跟随电源电压一起上升的高电平。当net 1节点的电压随电源电压V DD上升到大于M 13的阈值电压时，M 13导 通，V BP电压(即第二触发节点的电压)被下拉至低电平，导致M 9和M 10导通，带隙基准电路启动。因为慢上电过程中，带隙基准电路建立的时间比电源电压上电时间要快，在带隙基准电路已经完成建立时，带隙基准电路输出的第一信号的电压V BG大于第一预设值，电源电压还没有上电完成，此时，电源电压还没有达到使得电流比较器能够工作的电压，因此，电流比较器不工作，M 7的漏极net 3的电压为跟随电源电压一起上升的高电平，这使得M 5截止，电压比较器131的正相输入端net 5为低电位。电压比较器131的使能端net 4为低电位，电压比较器不工作，电压比较器输出的电压V OUT为0。
当电源电压上升到大于或等于M 2的阈值电压、M 3的阈值电压与M 6的过驱动电压之和(也可以说电源电压上升到使得电流比较器两端的电压大于或等于其工作电压，即电源电压大于或等于第二预设值)，此时V BG已经稳定输出高电平，M 1导通，电流比较器工作，使得net 3翻转为低电平，进而使得M 5导通，net 5翻转为跟随电源电压上升的高电平。net 4翻转为跟随电源电压上升的高电平，电压比较器开始工作，但是，因为电压比较器正相输入端的net 5的电压小于电压比较器反相输入端的电压V BG，因此电压比较器输出的电压V OUT仍为0。
当电源电压继续上升到使得net 5的电压大于V BG时(即电压比较器正相输入端的电压大于反相输入端的电压)，此时电源电压V DD等于电压比较器131输出复位信号的阈值电压V TH，阈值电压V TH的计算可以参考上述实施例三中的公式二，此处不再赘述，电压比较器的输出电压V OUT翻转为跟随电源电压上升的高电平，产生了复位信号。其过程如图13所示。
可选地，在电源快上电时，即电源电压建立时间小于带隙基准的建立时间，例如V DD上电10us，而带隙基准电路建立完成需要100us。电源电压V DD从0开始缓慢上升时，带隙基准的启动电路中的M 11首先导通，使得net 1翻转为跟随电源电压一起上升的高电平。当net 1的电平随V DD上升到大于M 3的阈值电压时，M 3导通，V BP电压被下拉至低电平，带隙基准开始启动。此时，net 3为跟随电源电压一起上升的高电平，使得M 5截止，因此net 5为低电位。net 4为低电位，电压比较器不工作，电压比较器输出为0。
由于电源电压V DD上升较快，在电源电压已经完成建立时，带隙基准电路还没有完成建立，此时，电源电压已经大于M 2的阈值电压、M 3的阈值电压与M 6的过驱动电压之和(也可以说电源电压上升到使得电流比较器两端的电压大于或等于其工作电压，即电源电压大于或等于第二预设值)。但由于带隙基准的建立时间相比 较长，V BG电压上升缓慢，因此M 1仍不导通，net 4为低电位，电压比较器不工作，依旧输出为0。
当V BG上升到让M 1开始导通时，即带隙基准电路输出的第一信号的电压V BG大于第一预设值，net 3翻转为低电平，使得M 5导通。net 4翻转为高电平，电压比较器开始工作。此时电压比较器正相输入端net 5的电平已经大于反相输入端的V BG，因此电压比较器立刻输出高电平，产生复位信号。其过程如图14所示。
本申请实施例提供的上电复位电路，包括带隙基准电路、电流比较器和电压比较电路，带隙基准电路、电流比较器及电压比较电路均由电压源供电，因为带隙基准电路输出的第一信号可以控制电流比较器工作，而电流比较器由电压源供电，因此，在电源电压和带隙基准电路都达到要求后，电流比较器才会工作，并输出第二信号，利用输出的第二信号控制电压比较器工作，并输出复位信号，避免在带隙基准电路不稳定时输出复位信号，导致出现错误，减少上电过程中的误触发，增加了上电的可靠性。
至此，已经对本主题的特定实施例进行了描述。其它实施例在所附权利要求书的范围内。在一些情况下，在权利要求书中记载的动作可以按照不同的顺序来执行并且仍然可以实现期望的结果。另外，在附图中描绘的过程不一定要求示出的特定顺序或者连续顺序，以实现期望的结果。在某些实施方式中，多任务处理和并行处理可以是有利的。
还需要说明的是，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上所述仅为本申请的实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (21)

  1. 一种上电复位电路，其特征在于，包括：带隙基准电路、电流比较器和电压比较电路，所述带隙基准电路、所述电流比较器及所述电压比较电路均由电压源供电；
    其中，所述带隙基准电路的第一输出端与所述电流比较器的控制端连接，用于向所述电流比较器的控制端输入第一信号，以控制所述电流比较器工作；
    所述电流比较器的第一电流输入端及第二电流输入端分别接入第一电流信号和第二电流信号，所述电流比较器的输出端与所述电压比较电路的控制端连接，用于向所述电压比较电路的控制端输入第二信号，以控制所述电压比较电路工作；
    所述电压比较电路的第一输入端与所述带隙基准电路的第一输出端连接，所述电压比较电路的第二输入端接入用于指示所述电压源电压大小的信号，所述电压比较电路的输出端用于输出上电复位信号。
  2. 根据权利要求1所述的上电复位电路，其特征在于，所述电流比较器包括第一开关和电流镜；
    所述电流镜的第一输入端接入所述第一电流信号；
    所述第一开关的第一端为所述电流比较器的第二电流输入端和所述输出端，所述第一开关的第二端与所述电流镜的第二输入端连接，所述第一开关的控制端为所述电流比较器的控制端。
  3. 根据权利要求2所述的上电复位电路，其特征在于，所述第一开关包括第一场效应管；
    所述第一场效应管的漏极为所述第一开关的第一端，所述第一场效应管的源极为所述第一开关的第二端，所述第一场效应管的栅极为所述第一开关的控制端；
    所述第一场效应管的漏极接入所述第二电流信号，所述第一场效应管的源极与所述电流镜的第二输入端连接，所述第一场效应管的栅极与所述带隙基准电路的第一输出端连接。
  4. 根据权利要求2所述的上电复位电路，其特征在于，所述电流比较器还包括限压元件；
    所述限压元件的第一端为所述电流比较器的第一电流输入端，所述限压元件的第二端与所述电流镜的第一输入端连接，所述电流镜的第一输入端通过所述限压元件接入所述第一电流信号。
  5. 根据权利要求4所述的上电复位电路，其特征在于，所述限压元件包括第二场效应管；
    所述第二场效应管的源极为所述限压元件的第一端，所述第二场效应管的漏极为所述限压元件的第二端；
    所述第二场效应管的源极接入所述第一电流信号，所述第二场效应管的漏极与所述电流镜的第一输入端连接，所述第二场效应管的栅极与所述第二场效应管的漏极连接。
  6. 根据权利要求2所述的上电复位电路，其特征在于，所述电流镜包括第三场效应管和第四场效应管；
    所述第三场效应管的漏极为所述电流镜的第一输入端，所述第四场效应管的漏极为所述电流镜的第二输入端；
    所述第三场效应管的漏极与栅极连接，所述第三场效应管的栅极与所述第四场效应管的栅极连接。
  7. 根据权利要求1所述的上电复位电路，其特征在于，
    所述第一电流信号的电流大于所述第二电流信号的电流，所述第二信号为高电平信号。
  8. 根据权利要求1-7任意一项所述的上电复位电路，其特征在于，所述电压比较电路包括分压控制支路和电压比较器；
    所述分压控制支路的输入端为所述电压比较电路的第二输入端，所述分压控制支路的控制端为所述电压比较电路的控制端，所述分压控制支路的控制端与所述电流比较器的输出端连接，所述分压控制支路的第一输出端与所述电压比较器的正相输入端连接，所述分压控制支路的第二输出端接地；
    所述电压比较器的反相输入端为所述电压比较电路的第一输入端，所述电压比较器的输出端为所述电压比较电路的输出端，所述电压比较器的反相输入端与所述带隙基准电路的第一输出端连接。
  9. 根据权利要求8所述的上电复位电路，其特征在于，所述分压控制支路包括第二开关、第一电阻和第二电阻；
    其中，所述第二开关的第一端为所述分压控制支路的输入端，所述第二开关的控制端为所述分压控制支路的控制端；
    所述第二开关的第一端与所述电压源连接，所述第二开关的第二端与所述第一电阻的第一端连接；
    所述第一电阻的第二端为所述分压控制支路的第一输出端，所述第一电阻的第二端与所述第二电阻的第一端连接，所述第一电阻的第二端与所述电压比较器的正 相输入端连接；
    所述第二电阻的第二端为所述分压控制支路的第二输出端，所述第二电阻的第二端接地。
  10. 根据权利要求9所述的上电复位电路，其特征在于，所述第二开关包括第五场效应管；
    所述第五场效应管的栅极为所述第二开关的控制端，所述第五场效应管的源极为所述第二开关的第一端，所述第五场效应管的漏极为所述第二开关的第二端；
    所述第五场效应管的栅极与所述电流比较器的输出端连接，所述第五场效应管的源极与所述电压源连接，所述第五场效应管的漏极与所述第一电阻的第一端连接。
  11. 根据权利要求8所述的上电复位电路，其特征在于，所述电压比较电路还包括反相器；
    所述反相器的输入端与所述电流比较器的输出端连接，所述反相器的输出端与所述电压比较器的使能端连接，用于向所述电压比较器的使能端输入使能信号。
  12. 根据权利要求1所述的上电复位电路，其特征在于，所述第一电流信号和所述第二电流信号来自所述带隙基准电路，所述带隙基准电路的第二输出端与所述电流比较器的第一电流输入端连接，用于向所述电流比较器输入第一电流信号；所述带隙基准电路的第三输出端与所述电流比较器的第二电流输入端连接，用于向所述电流比较器输入第二电流信号。
  13. 根据权利要求12所述的上电复位电路，其特征在于，所述带隙基准电路包括启动电路和基准产生电路；
    所述基准产生电路的第一输出端为所述带隙基准电路的第一输出端，所述基准产生电路的第二输出端为所述带隙基准电路的第二输出端，所述基准产生电路的第三输出端为所述带隙基准电路的第三输出端；
    所述启动电路的输入端与所述基准产生电路的第一输出端连接，所述启动电路的第一触发节点与所述基准产生电路的第二触发节点连接，用于向所述基准产生电路的第二触发节点输入触发信号，以触发所述基准产生电路工作。
  14. 根据权利要求13所述的上电复位电路，其特征在于，所述基准产生电路包括运算放大器，以及相互并联的第一支路、第二支路和第三支路；
    所述第一支路、所述第二支路和所述第三支路均与电压源连接；
    所述第一支路的输出端和所述第二支路的输出端分别与所述运算放大器的反相输入端和正向输入端连接，所述第一支路的输出端的电压与温度的相关性不同于所 述第二支路的输出端的电压与温度的相关性；
    所述运算放大器的输出端分别与所述第一支路的控制端、所述第二支路的控制端以及所述第三支路的控制端连接，所述第一支路的控制端和所述第二支路的控制端为所述基准产生电路的触发节点；
    所述第三支路的输出端为所述基准产生电路的第一输出端。
  15. 根据权利要求14所述的上电复位电路，其特征在于，所述基准产生电路还包括相互并联的第四支路和第五支路；
    所述第四支路的输出端为所述基准产生电路的第二输出端，所述第四支路的输入端与所述电压源连接，所述第四支路的控制端与所述运算放大器的输出端连接，所述第四支路的输出端与所述电流比较器的第一电流输入端连接，用于向所述电流比较器输入第一电流信号；
    所述第五支路的输出端为所述基准产生电路的第三输出端，所述第五支路的输入端与所述电压源连接，所述第五支路的控制端与所述运算放大器的输出端连接，所述第五支路的输出端与所述电流比较器的第二电流输入端连接，用于向所述电流比较器输入第二电流信号。
  16. 根据权利要求15所述的上电复位电路，其特征在于，所述第四支路包括第六场效应管；
    所述第六场效应管的栅极为所述第四支路的控制端，所述第六场效应管的源极为所述第四支路的输入端，所述第六场效应管的漏极为所述第四支路的输出端；
    所述第六场效应管的源极与所述电压源连接，所述第六场效应管的栅极与所述运算放大器的输出端连接，所述第六场效应管的漏极与所述电流比较器的第一电流输入端连接。
  17. 根据权利要求15所述的上电复位电路，其特征在于，所述第五支路包括第七场效应管；
    所述第七场效应管的栅极为所述第五支路的控制端，所述第七场效应管的源极为所述第五支路的输入端，所述第七场效应管的漏极为所述第五支路的输出端；
    所述第七场效应管的源极与所述电压源连接，所述第七场效应管的栅极与所述运算放大器的输出端连接，所述第七场效应管的漏极与所述电流比较器的第二电流输入端连接。
  18. 根据权利要求14所述的上电复位电路，其特征在于，所述第三支路包括第八场效应管和第三电阻；
    所述第八场效应管的漏极为所述第三支路的输出端；所述第八场效应管的源极与所述电压源连接，所述第八场效应管的栅极与所述运算放大器的输出端连接，所述第八场效应管的漏极与所述第三电阻的第一端连接；所述第三电阻的第二端接地。
  19. 根据权利要求14所述的上电复位电路，其特征在于，所述第一支路包括第一双极性结型晶体管、第九场效应管和第四电阻；
    所述第九场效应管的栅极为所述第一支路的控制端，所述第九场效应管的漏极为所述第一支路的输出端；
    所述第九场效应管的源极与所述电压源连接，所述第九场效应管的栅极与所述运算放大器的输出端连接，所述第九场效应管的漏极与所述运算放大器的正相输入端连接；
    所述第四电阻的一端与所述第九场效应管的漏极连接，另一端接地；
    所述第一双极性结型晶体管的发射极与所述第九场效应管的漏极连接，所述第一双极性结型晶体管的基极和集电极均接地。
  20. 根据权利要求14所述的上电复位电路，其特征在于，所述第二支路包括第二双极性结型晶体管、第十场效应管、第五电阻和第六电阻；
    所述第十场效应管的栅极为所述第二支路的控制端，所述第十场效应管的漏极为所述第二支路的输出端；
    所述第十场效应管的源极与所述电压源连接，所述第十场效应管的栅极与所述运算放大器的输出端连接，所述第十场效应管的漏极与所述运算放大器的反相输入端连接；
    所述第五电阻的一端与所述第十场效应管的漏极连接，另一端与所述第二双极性结型晶体管的发射极连接；
    所述第六电阻的一端与所述第十场效应管的漏极连接，另一端接地；
    所述第二双极性结型晶体管的集电极和基极均接地。
  21. 根据权利要求13所述的上电复位电路，其特征在于，所述启动电路包括第十一场效应管、第十二场效应管和第十三场效应管；
    其中，所述第十一场效应管的栅极和所述第十二场效应管的栅极为所述启动电路的输入端，所述第十三场效应管的漏极为所述第一触发节点；
    所述第十一场效应管的源极与所述电压源连接，所述第十一场效应管的栅极与所述基准产生电路的第一输出端连接，所述第十一场效应管的漏极分别与所述第十二场效应管的漏极和所述第十三场效应管的栅极连接；
    所述第十二场效应管的栅极与所述基准产生电路的第一输出端连接，所述第十二场效应管的源极接地；
    所述第十三场效应管的漏极与所述第二触发节点连接，所述第十三场效应管的源极接地。
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