WO2022061937A1 - 一种天线阵列、装置及无线通信设备 - Google Patents

一种天线阵列、装置及无线通信设备 Download PDF

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Publication number
WO2022061937A1
WO2022061937A1 PCT/CN2020/118586 CN2020118586W WO2022061937A1 WO 2022061937 A1 WO2022061937 A1 WO 2022061937A1 CN 2020118586 W CN2020118586 W CN 2020118586W WO 2022061937 A1 WO2022061937 A1 WO 2022061937A1
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WO
WIPO (PCT)
Prior art keywords
sub
arrays
antenna array
array
radio frequency
Prior art date
Application number
PCT/CN2020/118586
Other languages
English (en)
French (fr)
Inventor
彭杰
王伟锋
姚阿敏
张悦
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP20954784.3A priority Critical patent/EP4207495A4/en
Priority to PCT/CN2020/118586 priority patent/WO2022061937A1/zh
Priority to KR1020237014404A priority patent/KR20230074581A/ko
Priority to JP2023519554A priority patent/JP2023543068A/ja
Priority to CN202080105656.3A priority patent/CN116325364A/zh
Publication of WO2022061937A1 publication Critical patent/WO2022061937A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/06—Arrays of individually energised antenna units similarly polarised and spaced apart
    • H01Q21/061—Two dimensional planar arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/24—Supports; Mounting means by structural association with other equipment or articles with receiving set
    • H01Q1/241—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM
    • H01Q1/242—Supports; Mounting means by structural association with other equipment or articles with receiving set used in mobile communications, e.g. GSM specially adapted for hand-held use
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0006—Particular feeding systems
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0006—Particular feeding systems
    • H01Q21/0025—Modular arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0006—Particular feeding systems
    • H01Q21/0075—Stripline fed arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
    • H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas

Definitions

  • the present application relates to the field of antenna technology, and in particular, to an antenna array, an apparatus, and a wireless communication device.
  • An antenna array is formed by a plurality of radiating elements and the plurality of radiating elements are arranged in an array, which is also called an antenna array.
  • each radiation unit may also be called an Array Element.
  • phase shifter is used to control the phase of the radiating element.
  • multiple phase shifters are required.
  • Figure 1 shows an antenna array, each black dot represents a radiating element, the antenna array includes 24 (along the X-axis) ⁇ 32 (along the Y-axis) radiating elements, the antenna array is in the direction of the Y-axis
  • Each column has 8 sub-arrays, including a 1-to-2 sub-array, a 1-to-4 sub-array, a 1-to-6 sub-array, and a 1-to-8 sub-array.
  • the sub-array of 1-drive 2 means that one phase shifter controls two radiation units
  • the sub-array of 1-drive 4 means that one phase shifter controls four radiation units
  • the sub-array of 1-drive 6 means that one phase shifter controls six radiation units Radiation elements
  • a 1-to-8 sub-array means that one phase shifter controls eight radiation elements.
  • FIG. 2 is a schematic diagram illustrating the connection between a sub-array of the antenna array of FIG. 1 and a radio frequency integrated circuit (Radio Frequency Integrated Circuit, RFIC) chip.
  • RFIC Radio Frequency Integrated Circuit
  • FIG. 2 shows a first RFIC chip 01 , a second RFIC chip 02 , a third RFIC chip 03 and a fourth RFIC chip 04 , each of which is connected to a corresponding sub-array, respectively.
  • each sub-array has a feeding position M connected to the RFIC chip.
  • the antenna array shown in FIG. 1 can also be connected to more radio frequency integrated circuit chips, and the number and positions of the chips in FIG. 2 are only examples.
  • the first RFIC chip 01 has eight radio frequency transceiver channels, and the eight radio frequency transceiver channels are respectively connected one-to-one with eight sub-arrays through feed lines.
  • a radio frequency transceiving channel in the first RFIC chip is connected to a feeding position M of a sub-array in the antenna array through a feeding line 05 .
  • the connection relationship between the second RFIC chip 02 , the third RFIC chip 03 , and the fourth RFIC chip 04 and the feeding positions of the corresponding sub-arrays is similar to that shown in FIG. 3 .
  • the lengths of the feed lines connected between the RFIC chip and the feed positions of the multiple sub-arrays are inconsistent, some feed lines are long, and some feed lines are short. Due to the inconsistent length of the feeder connected to the same RFIC chip, the time delay of signal transmission is also different, resulting in different phases of the signals of multiple sub-arrays, which cannot achieve the effect of antenna array beam synthesis and deteriorate the broadband performance of the antenna array. .
  • the existing phase calibration compensation can only ensure the narrowband calibration effect, and the beamforming effect is poor in the case of wideband.
  • each RFIC chip is irregular, resulting in different lengths of the power splitter connecting the power splitter and each RFIC chip, which makes the design of the power splitter difficult, and It also further degrades the broadband performance of the antenna array.
  • the multiple RFIC chips shown in FIG. 2 are arranged irregularly, the heat dissipated by the RFIC chips in the antenna module where the antenna array is arranged will be unevenly distributed. In this case, the temperature of different positions of the antenna module will be different. There are also differences in the thermal expansion of the feeder at the location, and the difference in the thermal expansion of the feeder will also affect the phase of the signal of the sub-array.
  • Embodiments of the present application provide an antenna array, an apparatus, and a wireless communication device, aiming to improve the broadband performance of the antenna array by making the feed lines between the RFIC chip and the feeding positions of the sub-arrays of the antenna array substantially equal in length.
  • the present application provides an antenna array, the antenna array comprising:
  • a plurality of sub-arrays each sub-array is provided with a feeding position and at least one radiation unit, the plurality of sub-arrays are arranged along a first direction and a second direction, the first direction is perpendicular to the second direction, and along the first direction, a plurality of sub-arrays are arranged.
  • the feeding positions of the array are located on the same straight line, and along the second direction, the feeding positions of multiple sub-arrays are located on the same straight line; along the first direction, the sub-arrays to which the feeding positions located on the same straight line belong are in the same row, Along the second direction, the sub-arrays to which the feeding positions located on the same straight line belong are in the same column;
  • Each sub-array has a phase center, the phase centers of the sub-arrays in at least one row of the antenna array are not on the same straight line, and/or the phase centers of the sub-arrays in at least one column of the sub-arrays in the antenna array are not on the same straight line superior.
  • the feeding positions of any row of sub-arrays are located on the same straight line, the feeding positions of any column of sub-arrays are located on the same straight line. In this way, the feeding positions of the antenna array are arranged regularly.
  • each The lengths of the two feed lines are basically the same, so as to avoid the phenomenon that the lengths of multiple feed lines connected to the same radio frequency integrated circuit chip are different, so that the phases of the multiple sub-arrays are different.
  • the phase centers of the antenna array are arranged irregularly.
  • the irregular arrangement of the phase centers may cause the energy of the grating lobes of the antenna array to be dispersed to multiple angles, which can effectively improve the suppression of the grating lobes, and then Increase the gain of the antenna array.
  • the antenna array provided by the embodiments of the present application can also realize the isometric interconnection between the RFIC chip and the sub-array.
  • the antenna array includes N sub-arrays, each of the N sub-arrays is provided with an equal number of radiating elements, and the feeding position of at least one sub-array in the N sub-arrays is the same as that of the N sub-arrays.
  • the feeding positions of other sub-arrays in the array are different, where N is an integer greater than or equal to 2.
  • the antenna array includes at least two types of sub-arrays of the same type, and the sub-arrays in one type of sub-array are provided with the same number of radiating elements. That is, the antenna array may include a sub-array having two radiating elements, or a sub-array having three radiating elements, or a sub-array including more radiating elements.
  • the antenna array includes at least one first sub-array, at least two radiating elements are arranged on the first sub-array, and the at least two radiating elements are arranged in a straight line; the feeding of the first sub-array The position is between two adjacent radiating elements; or, the feeding position of the first sub-array is located on the side of the radiating element at the end of the first sub-array that is away from the remaining radiating elements. That is to say, when there are at least two radiating elements in the sub-array, the feeding positions also have various situations, and during specific implementation, the selection can be made according to the layout of the feeding positions of the entire antenna array.
  • the antenna array includes at least one second sub-array, a radiating element is arranged on the second sub-array, and the feeding position of the second sub-frame is located beside the radiating element.
  • the distance between the feeding positions of every two adjacent sub-arrays is equal, and/or, along the second direction, the feeding positions of every two adjacent sub-arrays are The spacing between them is equal. This facilitates the layout of the feed unit.
  • the antenna array includes dummy elements, and the dummy elements are radiating elements that are not fed.
  • the feeding positions of the antenna array regularly, in some cases, it is necessary to form a grid without radiating elements between two adjacent sub-arrays.
  • each sub-array can be The pattern of the array is kept consistent and the communication capacity of the wireless communication equipment is improved.
  • the radiation unit is a microstrip patch antenna, a symmetrical oscillator, an aperture waveguide antenna, or a helical antenna, or the like.
  • the radiation unit may be dual-polarized or single-polarized.
  • the polarization manner may be ⁇ 45° polarization, vertical or horizontal polarization, right-handed or left-handed circular polarization.
  • the feeder of the sub-array is a T-type power divider, a Wilkinson power divider, or a series feeder power divider.
  • the present application provides a device, the device comprising:
  • the antenna array in the first aspect or any implementation manner of the first aspect
  • a circuit carrying board, the feed lines are used to feed the sub-arrays in the antenna array, and the antenna array and the feed lines are arranged on the circuit carrying board.
  • the device provided by the embodiment of the present application includes the antenna array in any implementation manner of the first aspect. Since the feeding positions of the antenna array are regularly arranged, when a multi-channel radio frequency integrated circuit chip is passed through a plurality of feeding lines When connecting with the feeding positions of multiple sub-arrays one-to-one, the lengths of every two feed lines are basically equal to avoid the different lengths of multiple feed lines connected to the same RF integrated circuit chip, so that the phases of multiple sub-arrays are different. the same phenomenon.
  • phase centers of the sub-arrays of the antenna array are irregularly arranged, the irregular arrangement of the phase centers will cause the energy of the grating lobes of the antenna array to be dispersed to multiple angles, which can effectively improve the grating lobe. Suppression, reduce interference to external systems, and can also improve antenna gain to a certain extent.
  • the device further includes at least one radio frequency integrated circuit chip, the radio frequency integrated circuit chip is disposed on the circuit carrier board, the radio frequency integrated circuit chip includes at least two radio frequency transceiver channels, at least two radio frequency transceiver channels It is used for feeding power to at least two sub-arrays in the antenna array through feed lines respectively, and the radio frequency transceiver channel is connected to the sub-arrays one-to-one.
  • the antenna module includes a power divider and combiner and at least two radio frequency integrated circuit chips, and the power divider and combiner is respectively connected to the at least two radio frequency integrated circuit chips through at least two power division lines. , and the lengths of at least two power sub-lines are equal, and the power sub-lines are connected one-to-one with the radio frequency integrated circuit chip.
  • the equal-length design of the power divider between the power divider and the RFIC chip will further reduce the time delay difference between the power divider and combiner to different sub-arrays, and further improve the broadband performance.
  • the circuit carrier board is a package substrate;
  • the antenna module further includes a printed circuit board, and the package substrate is arranged on the printed circuit board and connected to the printed circuit board, and the power splitter and combiner set on the printed circuit board.
  • a digital-to-analog conversion module and a digital signal processing module are also provided on the printed circuit board.
  • the digital-signal processing module is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module is connected to the power divider and combiner.
  • the circuit carrier board is a printed circuit board, and the power splitter and combiner are arranged on the printed circuit board.
  • a digital-to-analog conversion module and a digital signal processing module are also provided on the printed circuit board, the digital-to-analog conversion module is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module is connected to the power divider and combiner.
  • the antenna array, the radio frequency integrated circuit chip, the digital-to-analog conversion module and the digital signal processing module are all arranged on the printed circuit board to form an Antenna-on-Board (AOB).
  • AOB Antenna-on-Board
  • the device further includes a heat sink, and the heat sink can dissipate heat from the radio frequency integrated circuit chip.
  • the radio frequency integrated circuit chip is dissipated through the heat sink to improve the performance of the radio frequency integrated circuit chip.
  • the application provides a device, the device comprising:
  • At least one radio frequency integrated circuit chip, the antenna array and the feed line are arranged on the packaging layer of the radio frequency integrated circuit chip, and the radio frequency integrated circuit chip includes at least two radio frequency transceiver channels, and the at least two radio frequency transceiver channels are used to transmit to the antenna array respectively through the feed line. At least two of the sub-arrays are fed with power, and the radio frequency transceiver channels are connected to the sub-arrays one-to-one.
  • the feeder and the antenna array are arranged on the radio frequency integrated circuit chip, and the antenna array is the antenna array in any implementation manner of the first aspect, so the antenna provided by the embodiment of the present application
  • the module and the antenna array of the above technical solution can solve the same technical problem and achieve the same expected effect.
  • the device includes a power divider and combiner and at least two radio frequency integrated circuit chips, and the power divider and combiner is respectively connected to the at least two radio frequency integrated circuit chips through at least two power division lines,
  • the lengths of at least two power sub-lines are equal, and the power sub-lines are connected to the radio frequency integrated circuit chip one-to-one.
  • the equal-length design of the power divider between the power divider and the RF integrated circuit chip will further reduce the time delay difference between the power divider and combiner to different sub-arrays, and further improve the broadband performance.
  • the device further includes a printed circuit board, and both the radio frequency integrated circuit chip and the power splitter combiner are arranged on the printed circuit board.
  • a digital-to-analog conversion module and a digital signal processing module are also provided on the printed circuit board, the digital-signal processing module is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module is connected to the power divider and combiner, that is, the antenna is directly connected to the
  • the array is disposed on the radio frequency integrated circuit chip and connected with the printed circuit board to form an antenna on chip (Antenna-On-Chip, AOC).
  • the present application further provides a wireless communication device, including the antenna array in any implementation manner of the first aspect, or the apparatus in any implementation manner of the second aspect or the third aspect.
  • the wireless communication device provided by the embodiments of the present application includes the antenna array provided by the above embodiments. Therefore, the wireless communication device provided by the embodiments of the present application and the antenna array of the above technical solutions can solve the same technical problems and achieve the same expected effects.
  • FIG. 1 is a schematic structural diagram of an antenna array in the prior art
  • FIG. 2 is a schematic diagram of the connection between the sub-array of the antenna array of FIG. 1 and the RFIC chip;
  • FIG. 3 is a schematic diagram of the connection relationship between the first RFIC chip and the feeding position in FIG. 2;
  • FIG. 4 is a schematic structural diagram of an antenna module according to an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of an antenna module according to an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an antenna module according to an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an antenna array according to an embodiment of the present application.
  • Fig. 8 is the arrangement diagram of the feeding position of the antenna array of Fig. 7;
  • FIG. 9 is a schematic diagram of the connection relationship between part of the feeding position of the antenna array of FIG. 8 and the RFIC chip;
  • FIG. 10 is a schematic diagram of the connection relationship between an RFIC chip and a feeding position
  • FIG. 11 is a schematic diagram of the connection relationship between a plurality of RFIC chips and a power splitter and combiner;
  • Fig. 12 is the arrangement diagram of the phase center of the antenna array of Fig. 7;
  • FIG. 13 is a schematic structural diagram of an antenna array according to an embodiment of the present application.
  • Fig. 14 is the arrangement diagram of the feeding position of the antenna array of Fig. 13;
  • FIG. 15 is a schematic diagram of the connection relationship between part of the feeding position of the antenna array of FIG. 14 and the RFIC chip;
  • 16 is a schematic diagram of the connection relationship between an RFIC chip and a feeding position
  • 17 is a schematic diagram of the connection relationship between a plurality of RFIC chips and a power splitter and combiner;
  • Fig. 18 is the arrangement diagram of the phase center of the antenna array of Fig. 13;
  • FIG. 19 is a graph comparing the grating lobe suppression curves of the antenna array according to the embodiment of the present application and the existing antenna array;
  • 20 is a comparison diagram of vertical scanning envelope gain curves of an antenna array according to an embodiment of the present application and an existing antenna array;
  • FIG. 21 is a schematic diagram of the layout of a partial sub-array of an antenna array according to an embodiment of the present application.
  • 22 is a schematic diagram of the layout of the feeding position of the sub-array including one radiating element in the antenna array according to the embodiment of the present application;
  • 23a is a schematic diagram of the layout of the feeding positions of a sub-array including two radiating elements in an antenna array according to an embodiment of the present application;
  • 23b is a schematic diagram of the layout of the feeding positions of a sub-array including two radiating elements in an antenna array according to an embodiment of the present application;
  • 23c is a schematic diagram of the layout of the feeding positions of a sub-array including two radiating elements in an antenna array according to an embodiment of the present application;
  • FIG. 24a is a schematic diagram of the layout of feeding positions of a sub-array including three radiating elements in an antenna array according to an embodiment of the present application;
  • FIG. 24b is a schematic diagram of the layout of feeding positions of a sub-array including three radiating elements in an antenna array according to an embodiment of the present application;
  • 24c is a schematic diagram of the layout of the feeding positions of the sub-arrays including three radiating elements in the antenna array according to the embodiment of the present application;
  • FIG. 24d is a schematic diagram of the layout of feeding positions of a sub-array including three radiating elements in an antenna array according to an embodiment of the present application;
  • FIG. 25 is a schematic structural diagram of an antenna array according to an embodiment of the present application.
  • FIG. 26 is a schematic structural diagram of an antenna array according to an embodiment of the present application.
  • the millimeter wave frequency band has been included in the 5th Generation Mobile Networks (5G) with higher data communication rates.
  • 5G 5th Generation Mobile Networks
  • higher requirements are placed on the performance of the antenna array. For example, the grating lobes suppression of the antenna array needs to be further improved, and the scanning of the antenna array The pattern gain envelope needs to be more refined.
  • the antenna array exists in a variety of different bearing modes.
  • Figures 4, 5 and 6 are three different ways of carrying.
  • the antenna array 1 is arranged on the circuit carrier board 4, and the feeder 05 is also arranged on the circuit carrier board 4.
  • the feeder 05 may be a metal trace arranged on the circuit carrier board.
  • the circuit in this structure carries
  • the board 4 is a packaging substrate (subatrate), for example, the packaging substrate may use a redistribution layer (RDL), or a coreless substrate (Coreless substrate) without a core layer, or the like.
  • RDL redistribution layer
  • Coreless substrate coreless substrate without a core layer, or the like.
  • the RFIC chip 3 is connected to the package substrate provided with the antenna array 1 and the feed line 05 through the connection structure 10 . Then, the package substrate provided with the RFIC chip 3 is connected to a printed circuit board (printed circuit board, PCB) 6 through the connection structure 10 .
  • the structure formed in this way may be called an Antenna-In-Package (AIP).
  • both the antenna array 1 and the feeder 05 are arranged on the RFIC chip 3 , and the RFIC chip 3 with the antenna array 1 and the feeder 05 is arranged on the PCB6 through the connection structure and connected to the PCB6 .
  • the structure thus formed may be called an Antenna-On-Chip (AOC).
  • the antenna array 1 is arranged on the circuit carrier board, and the feed line 05 is also arranged on the circuit carrier board.
  • the circuit carrier board in this structure is the PCB6 .
  • the RFIC chip 3 is connected to the PCB 6 through a connection structure.
  • the structure thus formed may be called an Antenna-on-Board (AOB).
  • AOB Antenna-on-Board
  • connection structure 10 may be a ball grid array (BGA), of course, other connection structures may also be selected.
  • BGA ball grid array
  • a heat sink 8 is also included.
  • the heat sink 8 is disposed close to the PCB6 and the RFIC chip 3 to dissipate the heat dissipated by the PCB6 and the RFIC chip 3 .
  • the heat sink 8 is disposed close to the PCB6, and the PCB6 has a channel 7 running through it, so that the RFIC chip 3 can also be dissipated.
  • the heat sink 8 is placed close to the RFIC chip 3 .
  • the present application does not specifically limit the structure and arrangement of the radiator.
  • the PCB6 is provided with a digital-to-analog conversion module, a digital signal processing module and a power divider and combiner, the digital signal processing module is connected to the digital-to-analog conversion module, and the digital-to-analog conversion module is connected to the power
  • the splitter and combiner are connected, and the power splitter and combiner are connected to the RFIC chip through a power splitter line, and the power splitter line can also be a metal wiring.
  • metal traces on the PCB 6 may be used to connect the digital signal processing module and the digital-to-analog conversion module, and to connect the digital-to-analog conversion module to the power splitter and combiner.
  • the above-mentioned antenna array can be applied to an analog active phased array, and can also be applied to a digital active phased array.
  • the above only gives three kinds of apparatuses for carrying the antenna array, in addition, the antenna array can also be arranged in other apparatuses.
  • This application does not make any special limitation on the device.
  • the antenna array involved in the present application includes a plurality of subarrays, each subarray includes at least one radiating element, and the plurality of subarrays are arranged along a first direction and a second direction, and the first direction is perpendicular to the second direction. That is, multiple sub-arrays are arranged horizontally and vertically to form an antenna array.
  • one power splitter and combiner is connected to at least two RFIC chips 3 through at least two power split lines.
  • an RFIC chip 3 includes at least two radio frequency transceiver channels, that is, an RFIC chip 3 has at least two radio frequency transceiver ports, that is, an RFIC chip 3 with at least two radio frequency transceiver channels passes at least two feeders to at least two sub-channels. The arrays are fed one-to-one so that the sub-arrays can send and receive signals.
  • the transmission path from the power divider and combiner to the sub-arrays includes not only the power division path, but also the feeder path. If the transmission paths from one power divider and combiner to multiple sub-arrays are different, the delay will not In turn, the phases of the multiple sub-arrays will be different, and in this case, the broadband performance of the antenna array will be deteriorated.
  • an embodiment of the present application provides an antenna array, which can be applied to the above-mentioned AIP, AOC, or AOB.
  • AIP AIP
  • AOC AOC
  • AOB A-mentioned AOB
  • the antenna array 1 is explained in detail below.
  • FIG. 7 shows a structure diagram of an antenna array 1.
  • the radiating elements 11 in the antenna array 1 form a plurality of sub-arrays (1A in FIG. 7 represents a sub-array), and the plurality of sub-arrays form an antenna array.
  • the sub-array 1A includes two radiating elements, and the sub-arrays including the same number of radiating elements may be homogeneous sub-arrays. Actually, the number of radiation units in the sub-array may be other numbers. For example, the sub-array 1B shown in FIG. 13 includes three radiation units. Subarrays comprising any number of radiating elements are within the scope of this application.
  • Each sub-array has a feeding position M.
  • the feeding position M also includes at least three.
  • the present application does not limit the polarization mode of the radiation element, as shown in FIG. 7 , it is a dual-polarized antenna with ⁇ 45° polarization. It can also be a single-polarized antenna, and the polarization mode can also be horizontal or vertical polarization, left-handed or right-handed circular polarization.
  • the feeding positions M of the multiple sub-arrays are located on at least one straight line, and along the second direction Y, the feeding positions M of the multiple sub-arrays are also located on at least one straight line.
  • first direction X multiple sub-arrays to which multiple feed positions M on the same straight line belong are in the same row
  • second direction Y multiple sub-arrays to which multiple feed positions M on the same straight line belong in the same column.
  • the plurality of feeding positions of each row of sub-arrays are arranged along a straight line, and the plurality of feeding positions of each column of sub-arrays are also arranged along a straight line. Therefore, the feeding positions of the antenna array are arranged regularly.
  • the spacing between two adjacent feeding positions in each row is equal, as can be seen from FIG.
  • the spacing between the feeding positions is d, and the spacing between every two adjacent feeding positions in the third row of sub-arrays is also d.
  • the spacing between every two adjacent feeding positions in each column is equal.
  • the spacing between every adjacent two feeding positions in any column is equal, and the spacing between every adjacent two feeding positions in any row is the same.
  • the same RFIC chip can be connected to the same RFIC chip.
  • the connected feed lines are basically of the same length, that is, the feed paths are the same, thus reducing the time delay difference of the multiple sub-arrays connected to the same RFIC chip, so that the phases of the multiple sub-arrays are basically the same.
  • the first RFIC chip 31 is an RFIC chip with eight radio frequency transceiver channels.
  • the first RFIC chip 31 is interconnected with the sub-array 1A1, the sub-array 1A2, the sub-array 1A3, the sub-array 1A4, the sub-array 1A5, the sub-array 1A6, the sub-array 1A7 and the sub-array 1A8.
  • the first RF transceiver channel of the first RFIC chip 31 is interconnected with the subarray 1A1 through the feeder 051
  • the second RF transceiver channel of the first RFIC chip 31 is interconnected with the subarray 1A2 through the feeder 052
  • the first RFIC chip 31 The third RF transceiver channel of the first RFIC chip 31 is interconnected with the subarray 1A3 through the feeder 053
  • the fourth RF transceiver channel of the first RFIC chip 31 is interconnected with the subarray 1A4 through the feeder 054, and the fifth RF transceiver channel of the first RFIC chip 31
  • the sub-array 1A5 is interconnected through the feed line 055
  • the sixth RF transceiver channel of the first RFIC chip 31 is interconnected with the sub-array 1A6 through the feed line 056, and the seventh RF transceiver channel of the first RFIC chip 31 is connected to the sub-array 1A6
  • this application only uses an RFIC chip having eight radio frequency transceiver channels as one of the embodiments. It can also be an RFIC chip with other numbers of radio frequency transceiver channels.
  • feeder 051, feeder 052, feeder 053, feeder 054, feeder 055, feeder 056, feeder 057 and feeder 058 are substantially equal.
  • the phases of the sub-array 1A1, the sub-array 1A2, the sub-array 1A3, the sub-array 1A4, the sub-array 1A5, the sub-array 1A6, the sub-array 1A7 and the sub-array 1A8 can be made consistent to improve the antenna array Broadband performance.
  • the arrangement of multiple RFIC chips in the device is also regular, and the length of at least two power split lines between one power splitter and combiner to at least two RFIC chips It is also basically the same length, which simplifies the design difficulty of the power split line.
  • the power division paths from one power divider and combiner to at least two RFIC chips are basically the same. In this case, the delay difference between the sub-arrays will be further reduced, and the broadband performance will be further improved.
  • the first RFIC chip 31 , the second RFIC chip 32 , the third RFIC chip 33 and the fourth RFIC chip 34 are all RFIC chips having eight radio frequency transceiver channels.
  • the power splitter 5 is connected to the first RFIC chip 31 , the second RFIC chip 32 , the third RFIC chip 33 and the fourth RFIC chip 34 respectively through the power splitter 9 .
  • the first RFIC chip 31 , the second RFIC chip 32 , the third RFIC chip 33 and the fourth RFIC chip 34 are arranged regularly, and the power dividing lines 9 are basically equal in length.
  • the first RFIC chip 31 , the second RFIC chip 32 , the third RFIC chip 33 and the fourth RFIC chip 34 are regularly arranged.
  • the heat dissipation of the RFIC chip will also be evenly distributed to avoid the phenomenon of high local temperature and low local temperature, and avoid affecting the performance of the entire wireless communication device.
  • At least two power dividing lines between one power divider and combiner 5 and at least two RFIC chips 3 are basically of the same length, and the feed lines between one RFIC chip 3 and at least two sub-arrays are basically the same length, so that , the transmission paths from one power divider and combiner 5 to at least two sub-arrays are basically the same length, and further, the delay difference between different sub-arrays will be significantly reduced compared with the prior art, which makes the phases of different sub-arrays basically equal. consistent, ultimately improving the broadband performance of the antenna array.
  • each sub-array has a phase center (Phase Center) N.
  • Phase Center Phase Center
  • the phase center N also includes at least three.
  • the spherical center of the spherical surface is the phase center of the sub-array, or the spherical center of the spherical surface is considered to be the phase center of the sub-array.
  • a surrounding area is the phase center of the subarray.
  • phase center coincides with its geometric center, which is the geometric center of the phase plane of the electromagnetic wave radiated by the sub-array, which is close to a spherical surface.
  • the first type the multiple phase centers of at least one row are not located on the same straight line.
  • the phase centers in the first row are arranged in a straight line, but the phase centers in the second row are arranged in a bent line, that is, the phase centers in the second row are misaligned.
  • the second type multiple phase centers of at least one column are not located on the same straight line.
  • the third type the multiple phase centers of at least one row are not located on the same straight line, and the multiple phase centers of at least one column are not located on the same straight line.
  • phase center of the antenna array satisfies any of the above, it is considered that the phase center of the antenna array is irregularly arranged.
  • the irregular arrangement of the phase centers can cause the energy of the grating lobes of the antenna array to no longer be superimposed on a small number of angles, but spread to multiple angles during scanning, so the grating lobes suppression capability of the antenna array can be greatly improved.
  • FIG. 13 shows a structural diagram of another antenna array, and the antenna array includes a sub-array 1A having two radiating elements 11 and a sub-array 1B having three radiating elements 11 .
  • the feeding position M in the antenna array also satisfies: the feeding positions of multiple sub-arrays in each row of sub-arrays are arranged along a straight line, and the feeding positions of multiple sub-arrays in each column of sub-arrays are also arranged along a straight line. Therefore, the feeding positions of the antenna array are regularly arranged. For example, the feeding positions of the plurality of sub-arrays in the first row and the feeding positions of the plurality of sub-arrays in the second row adjacent to the first row are all arranged in a straight line. The feeding positions of the plurality of sub-arrays in the first column and the feeding positions of the plurality of sub-arrays in the second column adjacent to the first column are also arranged in a straight line.
  • the fifth RFIC chip 35 is an RFIC chip having six radio frequency transceiver channels.
  • the fifth RFIC chip 35 is interconnected with the sub-array 1B1, the sub-array 1B2, the sub-array 1B3, the sub-array 1B4, the sub-array 1B5, and the sub-array 1B6.
  • the first RF transceiver channel of the fifth RFIC chip 35 is interconnected with the subarray 1B1 through the feeder 059
  • the second RF transceiver channel of the fifth RFIC chip 35 is interconnected with the subarray 1B2 through the feeder 0510
  • the fifth RFIC chip 35 The third RF transceiver channel is interconnected with the subarray 1B3 through the feeder 0511
  • the fourth RF transceiver channel of the fifth RFIC chip 35 is interconnected with the subarray 1B4 through the feeder 0512
  • the fifth RF transceiver channel of the fifth RFIC chip 35 The sub-array 1B5 is interconnected through the feed line 0513
  • the sixth radio frequency transceiver channel of the fifth RFIC chip 35 is interconnected with the sub-array 1B6 through the feed line 0514 .
  • the lengths of feeder line 059 to feeder line 0514 are substantially equal.
  • the phases of the subarrays 1B1, 1B2, 1B3, 1B4, 1B5, and 1B6 can be basically the same, so as to improve the broadband performance of the antenna array.
  • FIG. 17 shows the connection relationship between the four RFIC chips and the power divider/combiner 5 , and the four RFIC chips are the fifth RFIC chip 35 , the sixth RFIC chip 36 , the seventh RFIC chip 37 and the eighth RFIC chip 38 respectively .
  • the fifth RFIC chip 35, the sixth RFIC chip 36, the seventh RFIC chip 37 and the eighth RFIC chip 38 are arranged regularly, and the power splitting lines from the power splitter and combiner to the four RFIC chips are basically Equal length.
  • the phase centers N in the antenna array are irregularly arranged.
  • the phase centers of the sub-arrays in the first row form fold lines
  • the phase centers of the sub-arrays in the second row also form fold lines. Curved line.
  • the irregular phase center may cause the grating lobe energy of the antenna array to no longer be superimposed on a small number of angles during scanning, but spread to multiple angles, so the grating lobe suppression capability of the antenna array can be greatly improved.
  • curve (1) is the grating lobe when the antenna array provided by the embodiment of the present application is scanned along the Y-axis direction (vertical dimension) Suppression curve
  • curve (2) is the grating lobe suppression curve when the antenna array in the prior art scans along the Y-axis direction (vertical dimension). It can be clearly seen from curve (1) and curve (2) that within the vertical scanning angle range of -20° to 20°, the grating lobe suppression of the present application is significantly higher than the existing grating lobe suppression.
  • curve (11) is the beam scanning along the Y-axis direction (vertical dimension) of the antenna array provided by the present application
  • the pattern envelope gain curve, curve (12) is the beam scan pattern envelope gain curve of the existing antenna array along the Y-axis direction (vertical dimension)
  • the antenna array of the present application is in the range of -30° ⁇ -10° and The gain in the range of 10° to 30° is better than that of the existing antenna array, and the gain in the range of -10° to 10° is basically the same.
  • the beam scanning capability is defined by 10dB grating lobe suppression.
  • the existing antenna array scanning capability is in the range of -10° to 10°.
  • the scanning capability of the present application is greater than ⁇ 20°, and the actual capability can reach about ⁇ 30°.
  • Figure 20 is an example of beam scanning in the Y direction, and there are similar technical effects in the X direction.
  • each radiation unit is not limited to be distributed in each grid at equal intervals, that is, as shown in FIG. 21 , the radiation unit 11a, the radiation unit 11b and the radiation unit 11c are sequentially arranged along the same column, adjacent to each other.
  • the distance between the radiation unit 11a and the radiation unit 11b is d1
  • the distance between the adjacent radiation unit 11b and the radiation unit 11c is d2
  • d1 and d2 can be equal, or the absolute value of the difference between d1 and d2 Less than or equal to 1/4 of the wavelength corresponding to the frequency band of the antenna array.
  • the feeding positions of the plurality of sub-arrays along the first direction may allow a certain degree of misalignment, which is not limited to being completely on the same straight line.
  • the feeding positions of the plurality of sub-arrays along the second direction may be misaligned to a certain degree. A certain degree of misalignment can be tolerated, not limited to being completely on the same line.
  • the feeding position M1, feeding position M2 and feeding position M3 arranged along the first direction are misaligned with the feeding position M2 and the feeding position M3, and the misalignment distance d3 is less than or equal to the frequency band of the antenna array 1/4 of the corresponding wavelength.
  • the misalignment distance is less than or equal to 1/4 of the wavelength corresponding to the frequency band of the antenna array
  • the impact on the equal-length design of the feeder and the equalizer is very small. Yes, the broadband performance of the antenna array can still be improved.
  • the feeding positions are irregularly arranged, that is to say, in the same sub-array, the feeding positions may appear in various situations.
  • the following describes the specific setting method of the feeding position in order to realize the irregular arrangement by means of an embodiment.
  • FIG. 22 shows a sub-array including only one radiating element 11 , and in this sub-array, the feeding position M is on the side of the radiating element 11 .
  • Fig. 23a, Fig. 23b and Fig. 23c show the layout of feeding positions in a sub-array including two radiating elements, let these two radiating elements be the first radiating element 111 and the second radiating element 112, respectively.
  • the first arrangement mode referring to FIG. 23 a , the feeding position M is located between the first radiating element 111 and the second radiating element 112 .
  • the second arrangement position referring to FIG. 23 b , the feeding position M is on the side of the first radiating element 111 away from the second radiating element 112 .
  • the third arrangement position referring to FIG. 23 c , the feeding position M is on the side of the second radiating element 112 away from the first radiating element 111 .
  • the feeding position M may also be below the first radiating element 111 or below the second radiating element 112 .
  • the feeding positions include the above-mentioned arrangement positions, but are not limited to these arrangement positions.
  • Fig. 24a, Fig. 24b, Fig. 24c and Fig. 24d show the layout of the feeding positions in the sub-array including three radiating elements, let these three radiating elements be the first radiating element 111 and the second radiating element 112 respectively , and the third radiating element.
  • the first arrangement position referring to FIG. 24 a , the feeding position M is on the side of the first radiating element 111 away from the second radiating element 112 .
  • the second arrangement position referring to FIG. 24 b , the feeding position M is between the first radiating element 111 and the second radiating element 112 .
  • the third arrangement position referring to FIG. 24 c , the feeding position M is between the second radiating element 112 and the third radiating element 113 .
  • the fourth arrangement position Referring to FIG. 24 d , the feeding position M is on the side of the third radiating element 113 away from the second radiating element 112 .
  • the feeding position M may also be below the first radiating element 111 , below the second radiating element 112 , or below the third radiating element 113 .
  • the feeding positions include the above-mentioned arrangement positions, but are not limited to these arrangement positions.
  • the specific layout of the feeding position M is similar to the above layout example.
  • the feeding position is located between two adjacent radiating elements, or the feeding position is located in a part of the radiating element at the end that is far from the rest of the radiating elements. side, or the feeding position is located below all radiating elements in the subarray.
  • Setting the dummy elements can make the surrounding environment of each sub-array of the antenna array consistent, so that the pattern of each sub-array is basically consistent, which will ultimately improve the communication capacity of the antenna array.
  • the antenna array For the two-dimensional shape formed by the antenna array provided in this application, it can be a rectangular array as shown in FIG. 7 and FIG. 13 , a nearly circular shape as shown in FIG. 25 , or a polygonal shape (as shown in FIG. 26 ). hexagon shown).
  • the "plurality” refers to two or more than two, for example, “multiple sub-arrays” may include three or more sub-arrays, and “multiple radio frequency transceiver channels” may include Two or more radio frequency transceiver channels, “multiple RFIC chips” may include two or more RFIC chips, and so on.

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Abstract

本申请实施例提供一种天线阵列、装置及无线通信设备，涉及天线技术领域。该天线阵列包括：多个子阵，每个子阵上设置有馈电位置和至少一个辐射单元，多个子阵沿第一方向和第二方向排布，第一方向与第二方向相垂直，沿第一方向，多个子阵的馈电位置位于同一条直线上，沿第二方向，多个子阵的馈电位置位于同一条直线上；沿第一方向，位于同一直线上的馈电位置所属的子阵处于同一行，沿第二方向，位于同一直线上的馈电位置所属的子阵处于同一列；每个子阵具有相位中心，天线阵列中至少有一行子阵中的子阵的相位中心不在同一条直线上，和/或，天线阵列中至少有一列子阵中的子阵的相位中心不在同一条直线上。

Description

一种天线阵列、装置及无线通信设备 技术领域
本申请涉及天线技术领域，尤其涉及一种天线阵列、装置及无线通信设备。
背景技术
由多个辐射单元且多个辐射单元呈阵列式排布，以形成天线阵列，也称为天线阵。其中，每一个辐射单元也可以称为阵元(Array Element)。
一般采用移相器对辐射单元的相位进行控制，当天线阵列中的辐射单元数量较多时，就需要多个移相器。为了减少移相器的数量和简化控制电路，通常几个辐射单元会共用一个移相器，共用一个移相器的多个辐射单元就组成一个子阵。
图1所示的为一种天线阵列，每一个黑色圆点代表一个辐射单元，该天线阵列包括24(沿X轴)×32(沿Y轴)个辐射单元，该天线阵列在Y轴方向上每一列具有8个子阵，包括1驱2的子阵、1驱4的子阵、1驱6的子阵和1驱8的子阵。其中，1驱2的子阵表示一个移相器控制两个辐射单元，1驱4的子阵表示一个移相器控制四个辐射单元，1驱6的子阵表示一个移相器控制六个辐射单元，1驱8的子阵表示一个移相器控制八个辐射单元。
图2所示的为图1的天线阵列的子阵与射频集成电路(Radio Frequency Integrated Circuit，RFIC)芯片连接的示意图。示例性的，图2示出了第一RFIC芯片01、第二RFIC芯片02、第三RFIC芯片03和第四RFIC芯片04，上述各个RFIC芯片分别与相对应的子阵连接。其中，每一个子阵具有与RFIC芯片连接的馈电位置M。需要说明的是，图1所示的天线阵列还可以连接更多的射频集成电路芯片，图2中的芯片个数以及位置仅为示例。
以第一RFIC芯片为例，图3中，第一RFIC芯片01具有八个射频收发通道，八个射频收发通道分别通过馈电线与八个子阵一对一连接。例如，如图3所示，第一RFIC芯片中的一个射频收发通道通过馈电线05与天线阵列中的一个子阵的馈电位置M连接。第二RFIC芯片02、第三RFIC芯片03和第四RFIC芯片04与相对应的子阵的馈电位置之间的连接关系与图3所示类似。
由图3可以看出，RFIC芯片与多个子阵的馈电位置连接的馈电线的长度不一致，有些馈电线长，有些馈电线短。由于与同一个RFIC芯片连接的馈电线长度不一致，因此信号传输的时延也是有差异的，导致多个子阵的信号的相位不一样，无法实现天线阵列波束合成的效果，恶化天线阵列的宽带性能。现有的相位校准补偿只能保证窄带校准效果，在宽带的情况下波束合成效果较差。另外，如图2所示，各个RFIC芯片的排布位置也不规则，导致功分合路器与各个RFIC芯片连接的功分线的长度不一样，这样给功分线的设计造成难度，而且也会进一步恶化天线阵列的宽带性能。进一步的，由于图2所示的多个RFIC芯片呈不规则布设，会导致设置该天线阵列的天线模块中RFIC芯片散发的热量分布不均，这样的话，天线模块不同位置的温度出现差异，不同位置的馈电线热膨胀量也出现差异，馈电线的热膨胀量的不同，也会影响子阵的信号 的相位。
发明内容
本申请的实施例提供一种天线阵列、装置及无线通信设备，旨在通过使RFIC芯片与天线阵列的子阵的馈电位置之间的馈电线基本等长来提升天线阵列的宽带性能。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请提供了一种天线阵列，该天线阵列包括：
多个子阵，每个子阵上设置有馈电位置和至少一个辐射单元，多个子阵沿第一方向和第二方向排布，第一方向与第二方向相垂直，沿第一方向，多个子阵的馈电位置位于同一条直线上，沿第二方向，多个子阵的馈电位置位于同一条直线上；沿第一方向，位于同一直线上的馈电位置所属的子阵处于同一行，沿第二方向，位于同一直线上的馈电位置所属的子阵处于同一列；
每个子阵具有相位中心，天线阵列中至少有一行子阵中的子阵的相位中心不在同一条直线上，和/或，天线阵列中至少有一列子阵中的子阵的相位中心不在同一条直线上。
本申请实施例提供的天线阵列，由于任一行子阵的馈电位置位于同一直线上，任一列子阵的馈电位置位于同一直线上。这样一来，天线阵列的馈电位置呈规则布设，当将具有至少两个射频收发通道的射频集成电路芯片通过至少两个馈电线与至少两个子阵的馈电位置一对一连接时，每两个馈电线的长度基本相等，避免与同一个射频集成电路芯片连接的多个馈电线长度不一，以使多个子阵的相位不一样的现象。
另外，由于至少一行的多个相位中心不位于同一直线上，和/或，至少一列的多个相位中心不位于同一直线上。也就是说，天线阵列的相位中心呈非规则排布，这样，相位中心的非规则排布可能会造成天线阵列的栅瓣的能量分散到多个角度，可以有效的提升栅瓣的抑制，进而提高天线阵列的增益。
所以，本申请实施例提供的天线阵列在有效的提升栅瓣的抑制，提高天线阵列的增益的前提下，还可实现RFIC芯片与子阵的等长互连。
在第一方面可能的实现方式中，天线阵列中包括N个子阵，N个子阵中的每个子阵均设置数量相等的辐射单元，N个子阵中的至少一个子阵的馈电位置与N个子阵中的其他子阵的馈电位置不同，其中N为大于或等于2的整数。通过使数量相等的子阵的馈电位置设置的不同，就可以实现馈电位置的规则排布。
在第一方面可能的实现方式中，天线阵列包括至少两种同类子阵，一种同类子阵中的子阵设置数量相等的辐射单元。也就是说，该天线阵列中可以包括具有两个辐射单元的子阵，或者，也可以包括具有三个辐射单元的子阵，或者包括更多个辐射单元的子阵。
在第一方面可能的实现方式中，天线阵列包括至少一个第一子阵，第一子阵上排布至少两个辐射单元，至少两个辐射单元呈直线排布；第一子阵的馈电位置位于相邻两个辐射单元之间；或者，第一子阵的馈电位置位于处于第一子阵端部的辐射单元的远离其余辐射单元的一侧。也就是说，当子阵的辐射单元至少为两个时，馈电位置也具有多种情况，在具体实施时，可根据整个天线阵列的馈电位置的布局进行选择。
在第一方面可能的实现方式中，天线阵列包括至少一个第二子阵，第二子阵上排 布有一个辐射单元，第二子帧的馈电位置位于辐射单元的旁侧。
在第一方面可能的实现方式中，沿第一方向，每相邻两个子阵的馈电位置之间的间距相等，和/或，沿第二方向，每相邻两个子阵的馈电位置之间的间距相等。这样便于对馈电单元进行布局。
在第一方面可能的实现方式中，天线阵列中包含哑元，哑元为不馈电的辐射单元。为了使天线阵列的馈电位置呈规则布设，在有些情况下，需要在相邻两个子阵之间形成不需要设置辐射单元的栅格，通过在该栅格内设置哑元，能够使各个子阵的方向图保持一致，提高无线通信设备的通信容量。
在第一方面可能的实现方式中，辐射单元为微带贴片天线、对称振子、开口波导天线或者螺旋天线等。
在第一方面可能的实现方式中，辐射单元可以为双极化，也可以为单极化。
在第一方面可能的实现方式中，极化方式可以为±45°极化、垂直或水平极化、右旋或左旋圆极化。
在第一方面可能的实现方式中，子阵的馈电线为T型功分、威尔金森功分或者串联馈电功分。
第二方面，本申请提供了一种装置，该装置包括：
上述第一方面或第一方面的任一实现方式中的天线阵列；
馈电线；
电路承载板，馈电线用于为天线阵列中的子阵馈电，天线阵列和馈电线设置在电路承载板上。
本申请实施例提供的装置中，包括第一方面任一实现方式中的天线阵列，由于该天线阵列的馈电位置呈规则布设，所以，当将多通道的射频集成电路芯片通过多根馈电线与多个子阵的馈电位置一对一连接时，每两个馈电线的长度基本相等，避免与同一个射频集成电路芯片连接的多个馈电线长度不一，以使多个子阵的相位不一样的现象。
另外，由于该天线阵列的子阵的相位中心呈非规则排布，这样，相位中心的非规则排布就会造成天线阵列的栅瓣的能量分散到多个角度，可以有效的提升栅瓣的抑制，减少对外部系统的干扰，同时也能够一定程度的提升天线增益。
在第二方面可能的实现方式中，该装置还包括至少一个射频集成电路芯片，射频集成电路芯片设置在电路承载板上，射频集成电路芯片包括至少两个射频收发通道，至少两个射频收发通道用于分别通过馈电线向天线阵列中的至少两个子阵馈电，射频收发通道与子阵一对一连接。
在第二方面可能的实现方式中，该天线模块包括功分合路器和至少两个射频集成电路芯片，功分合路器通过至少两个功分线分别与至少两个射频集成电路芯片连接，且至少两个功分线的长度相等，功分线与射频集成电路芯片一对一连接。功分合路器与RFIC芯片之间的功分线等长设计，会使功分合路器到不同子阵的时延差进一步缩小，进一步提高宽带性能。
在第二方面可能的实现方式中，电路承载板为封装基板；该天线模块还包括印制电路板，封装基板设置在印制电路板上，且与印制电路板连接，功分合路器设置在印 制电路板上。通常，印制电路板上还设置有数模变换模块和数字信号处理模块，数字信号处理模块与数模变换模块连接，数模变换模块与功分合路器连接，通过将天线阵列设置在封装基板上，并将射频集成电路芯片也设置在封装基板上，再将他们作为一个整体封装，并与印制电路板连接，以形成封装天线(Antenna-In-Package，AIP)。
在第二方面可能的实现方式中，电路承载板为印制电路板；功分合路器设置在所述印制电路板上。一般，印制电路板上还设置有数模变换模块和数字信号处理模块，数字信号处理模块与数模变换模块连接，数模变换模块与功分合路器连接。将天线阵列、射频集成电路芯片、数模变换模块和数字信号处理模块均设置在印制电路板上，以形成板上天线(Antenna-on-Board，AOB)。
在第二方面可能的实现方式中，该装置还包括散热器，散热器能够对射频集成电路芯片进行散热。通过散热器对射频集成电路芯片进行散热，以提高该射频集成电路芯片的性能。
第三方面，本申请提供了一种装置，该装置包括：
上述第一方面的天线阵列；
馈电线；
至少一个射频集成电路芯片，天线阵列和馈电线设置在射频集成电路芯片的封装层上，射频集成电路芯片包括至少两个射频收发通道，至少两个射频收发通道用于分别通过馈电线向天线阵列中的至少两个子阵馈电，射频收发通道与子阵一对一连接。
本申请实施例提供的装置中，是将馈电线和天线阵列设置在射频集成电路芯片上，且所述天线阵列为第一方面任一实现方式中的天线阵列，因此本申请实施例提供的天线模块与上述技术方案的天线阵列能够解决相同的技术问题，并达到相同的预期效果。
在第三方面可能的实现方式中，该装置包括功分合路器和至少两个射频集成电路芯片，功分合路器通过至少两个功分线分别与至少两个射频集成电路芯片连接，且至少两个功分线的长度相等，功分线与射频集成电路芯片一对一连接。功分合路器与射频集成电路芯片之间的功分线等长设计，会使功分合路器到不同子阵的时延差进一步缩小，进一步提高宽带性能。
在第三方面可能的实现方式中，该装置还包括印制电路板，射频集成电路芯片和功分合路器均设置在印制电路板上。通常，印制电路板上还设置有数模变换模块和数字信号处理模块，数字信号处理模块与数模变换模块连接，数模变换模块与功分合路器连接，也就是说，直接将天线阵列设置于射频集成电路芯片上，并与印制电路板连接，以形成片上天线(Antenna-On-Chip，AOC)。
第四方面，本申请还提供了一种无线通信设备，包括上述第一方面任一实现方式中的天线阵列，或者第二方面或第三方面任一实现方式中的装置。
本申请实施例提供的无线通信设备包括上述实施例提供的天线阵列，因此本申请实施例提供的无线通信设备与上述技术方案的天线阵列能够解决相同的技术问题，并达到相同的预期效果。
附图说明
图1为现有技术中天线阵列的结构示意图；
图2为图1的天线阵列的子阵与RFIC芯片连接的示意图；
图3为图2中的第一RFIC芯片与馈电位置的连接关系示意图；
图4为本申请实施例天线模块的结构示意图；
图5为本申请实施例天线模块的结构示意图；
图6为本申请实施例天线模块的结构示意图；
图7为本申请实施例天线阵列的结构示意图；
图8为图7的天线阵列的馈电位置的排布图；
图9为图8的天线阵列的部分馈电位置与RFIC芯片的连接关系示意图；
图10为一个RFIC芯片与馈电位置的连接关系示意图；
图11为多个RFIC芯片与功分合路器的连接关系示意图；
图12为图7的天线阵列的相位中心的排布图；
图13为本申请实施例天线阵列的结构示意图；
图14为图13的天线阵列的馈电位置的排布图；
图15为图14的天线阵列的部分馈电位置与RFIC芯片的连接关系示意图；
图16为一个RFIC芯片与馈电位置的连接关系示意图；
图17为多个RFIC芯片与功分合路器的连接关系示意图；
图18为图13的天线阵列的相位中心的排布图；
图19为本申请实施例天线阵列与现有的天线阵列的栅瓣抑制曲线对比图；
图20为本申请实施例天线阵列与现有的天线阵列的垂直扫描包络增益曲线对比图；
图21为本申请实施例天线阵列的部分子阵的布设示意图；
图22为本申请实施例天线阵列中的包括一个辐射单元的子阵的馈电位置的布设示意图；
图23a为本申请实施例天线阵列中的包括两个辐射单元的子阵的馈电位置的布设示意图；
图23b为本申请实施例天线阵列中的包括两个辐射单元的子阵的馈电位置的布设示意图；
图23c为本申请实施例天线阵列中的包括两个辐射单元的子阵的馈电位置的布设示意图；
图24a为本申请实施例天线阵列中的包括三个辐射单元的子阵的馈电位置的布设示意图；
图24b为本申请实施例天线阵列中的包括三个辐射单元的子阵的馈电位置的布设示意图；
图24c为本申请实施例天线阵列中的包括三个辐射单元的子阵的馈电位置的布设示意图；
图24d为本申请实施例天线阵列中的包括三个辐射单元的子阵的馈电位置的布设示意图；
图25为本申请实施例天线阵列的结构示意图；
图26为本申请实施例天线阵列的结构示意图。
附图标记：
01-第一RFIC芯片；02-第二RFIC芯片；03–第三RFIC芯片；04–第四RFIC芯片；05-馈电线；1-天线阵列；1A、1B-子阵；11-辐射单元；111-第一辐射单元；112-第二辐射单元；113-第三辐射单元；M-馈电位置；N-相位中心；2-哑元；3-RFIC芯片；31-第一RFIC芯片；32-第二RFIC芯片；33-第三RFIC芯片；34-第四RFIC芯片；35-第五RFIC芯片；36-第六RFIC芯片；37-第七射RFIC芯片；38-第八RFIC芯片；4-电路承载板；5-功分合路器；6-印制电路板；7-通道；8-散热器；9-功分线；10-连接结构。
具体实施方式
在无线通信设备，例如无线基站中，随着更高的数据通信速率，已经将毫米波频段列入第五代移动通信(5th Generation Mobile Networks，5G)。这样的话，在满足5G高频基站与卫星共存的协议要求的基础上，对天线阵列性能提出了更高的要求，比如，天线阵列的栅瓣(Grating lobes)抑制需要进一步提升，天线阵列的扫描方向图增益包络需要更优等。
在上述的无线通信设备中，天线阵列具有多种不同的承载方式存在。例如，图4、图5和图6是三种不同的承载方式。
结合图4，天线阵列1设置在电路承载板4上，且馈电线05也设置在电路承载板4上，馈电线05可以是布设在电路承载板上的金属走线，此结构中的电路承载板4为封装基板(subatrate)，比如，该封装基板可以采用重新布线层(redistribution layer，RDL)，或者采用无核心层的无芯基板(Coreless基板)等。
RFIC芯片3通过连接结构10与设置有天线阵列1和馈电线05的封装基板连接。再将设置有RFIC芯片3的封装基板通过连接结构10与印制电路板(printed circuit board，PCB)6连接。这样形成的结构可以称为封装天线(Antenna-In-Package，AIP)。
结合图5，天线阵列1和馈电线05均设置在RFIC芯片3上，设置有天线阵列1和馈电线05的RFIC芯片3通过连接结构设置在PCB6上，并与PCB6连接。这样形成的结构可以称为片上天线(Antenna-On-Chip，AOC)。
结合图6，天线阵列1设置在电路承载板上，且馈电线05也设置在电路承载板上，此结构中的电路承载板为PCB6。RFIC芯片3通过连接结构与PCB6连接。这样形成的结构可以称为板上天线(Antenna-on-Board，AOB)。
上述的连接结构10可以是焊球阵列(ball grid array，BGA)，当然，也可以选用其他连接结构。
在上述的AIP中、AOC中、或者AOB中，还包括散热器8，在AIP中，散热器8靠近PCB6和RFIC芯片3设置，以驱散PCB6和RFIC芯片3所散发的热量。在AOC中，散热器8靠近PCB6设置，且PCB6贯通有通道7，这样也可以对RFIC芯片3进行散热。在AOB中，散热器8靠近RFIC芯片3设置。本申请对散热器的结构、布设方式不做特殊限定。
在上述的AIP中、AOC中、或者AOB中，PCB6上设置有数模变换模块、数字信号处理模块和功分合路器，数字信号处理模块与数模变换模块连接，数模变换模块与功分合路器连接，功分合路器通过功分线与RFIC芯片连接，功分线也可以是金属走线。在可选择的实施方式中，可以采用PCB6上的金属走线连接数字信号处理模块与数模变换模块，以及连接数模变换模块与功分合路器。
上述的天线阵列可以应用在模拟有源相控阵列，也可以应用在数字有源相控阵列。
上述仅给出三种用于承载天线阵列的装置，除此之外，也可以将天线阵列设置在其他装置中。本申请对该装置不做特殊限定。
本申请涉及的天线阵列中包括多个子阵(Subarray)，每个子阵包括至少一个辐射单元，且多个子阵沿第一方向和第二方向排布，第一方向与第二方向相垂直。也就是多个子阵沿横、纵排布，以构成天线阵列。
上述的三种结构中，一个功分合路器通过至少两个功分线与至少两个RFIC芯片3连接。又因为一个RFIC芯片3包括至少两个射频收发通道，也就是一个RFIC芯片3具有至少两个射频收发端口，即具有至少两个射频收发通道的RFIC芯片3通过至少两个馈电线向至少两个子阵一对一的馈电，以使子阵收发信号。
也可以这样理解，功分合路器到子阵的传输路径不仅包括功分路径，还包括馈电路径，若一个功分合路器到多个子阵的传输路径不一样，时延就会不一样，进而会导致多个子阵的相位不一样，这样的话，会恶化天线阵列的宽带性能。
为了使不同子阵的时延差进一步缩小，进一步提高宽带性能，本申请实施例提供了一种天线阵列，该天线阵列可应用在上述的AIP中、AOC中、或者AOB中，当然，也可以应用在其他包含天线阵列的装置中。
下述对天线阵列1进行详细解释。
图7所示的为一种天线阵列1的结构图，天线阵列1中的辐射单元11形成多个子阵(如图7中1A代表一个子阵)，多个子阵形成天线阵列。
如图7，子阵1A包括两个辐射单元，包括数量相等的辐射单元的子阵可以是同类子阵。其实，子阵中的辐射单元可以为其他数量，例如，图13所示的子阵1B包括三个辐射单元。包括任何数量辐射单元的子阵均在本申请的保护范围之内。
每个子阵具有馈电位置M，例如，当该天线阵列包括至少三个子阵，那么，馈电位置M也包括至少三个。如图8所示，
需要说明的是：本申请对辐射单元的极化方式不做限定，如图7所示的为±45°极化的双极化天线。也可以是单极化天线，极化方式也可以是水平或垂直极化，左旋或右旋圆极化。
本申请实施例提供的天线阵列中的馈电位置M的排布满足下述条件：
沿第一方向X，多个子阵的馈电位置M位于至少一条直线上，沿第二方向Y，多个子阵的馈电位置M也位于至少一条直线上。
沿第一方向X，位于同一条直线上的多个馈电位置M所属的多个子阵处于同一行，沿第二方向Y，位于同一条直线上的多个馈电位置M所属的多个子阵处于同一列。
这样的话，结合图8，每一行子阵的多个馈电位置均沿直线布设，每一列子阵的多个馈电位置也沿直线布设。从而使得该天线阵列的馈电位置为规则排布。
另外，进一步的为了便于对馈电位置进行布局，每一行的相邻两个馈电位置之间的间距是相等的，由图8可以看出，第一行子阵的每相邻的两个馈电位置之间的间距均为d，第三行子阵的每相邻的两个馈电位置之间的间距也均为d。或者，每一列的每相邻两个馈电位置之间的间距相等。或者，任一列的每相邻两个馈电位置之间的间距相等，以及任一行的每相邻两个馈电位置之间的间距相等。
当该天线阵列的馈电位置呈规则排布时，具有至少两个射频收发通道的RFIC芯片通过至少两个馈电线与至少两个馈电位置一对一连接时，可使与同一个RFIC芯片连接的多个馈电线基本等长，也就是馈电路径一样，从而，会缩小与同一个RFIC芯片连接的多个子阵的时延差，以使多个子阵的相位基本一致。
例如，如图9和图10所示，第一RFIC芯片31为具有八个射频收发通道的RFIC芯片。第一RFIC芯片31与子阵1A1、子阵1A2、子阵1A3、子阵1A4、子阵1A5、子阵1A6、子阵1A7和子阵1A8相互连。即第一RFIC芯片31的第一射频收发通道通过馈电线051与子阵1A1互连，第一RFIC芯片31的第二射频收发通道通过馈电线052与子阵1A2互连，第一RFIC芯片31的第三射频收发通道通过馈电线053与子阵1A3互连，第一RFIC芯片31的第四射频收发通道通过馈电线054与子阵1A4互连，第一RFIC芯片31的第五射频收发通道通过馈电线055与子阵1A5互连，第一RFIC芯片31的第六射频收发通道通过馈电线056与子阵1A6互连，第一RFIC芯片31的第七射频收发通道通过馈电线057与子阵1A7互连，第一RFIC芯片31的第八射频收发通道通过馈电线058与子阵1A8互连。
需要说明的是；本申请仅采用具有八个射频收发通道的RFIC芯片作为其中的一个实施例。也可以是具有其他数量射频收发通道的RFIC芯片。
由图10可以看出，馈电线051、馈电线052、馈电线053、馈电线054、馈电线055、馈电线056、馈电线057和馈电线058的长度基本相等。当馈电线的长度相等时，可使子阵1A1、子阵1A2、子阵1A3、子阵1A4、子阵1A5、子阵1A6、子阵1A7和子阵1A8的相位一致，以提高该天线阵列的宽带性能。
当该天线阵列的馈电位置呈规则排布时，装置中的多个RFIC芯片的排布也规律，一个功分合路器到至少两个RFIC芯片之间的至少两个功分线的长度也基本等长，简化了功分线的设计难度。尤其是，一个功分合路器到至少两个RFIC芯片的功分路径也基本一样，这样的话，会进一步缩小各子阵之间的时延差，进一步提高宽带性能。
例如，如图11所示，第一RFIC芯片31、第二RFIC芯片32、第三RFIC芯片33和第四RFIC芯片34均为具有八个射频收发通道的RFIC芯片。功分合路器5通过功分线9分别与第一RFIC芯片31、第二RFIC芯片32、第三RFIC芯片33和第四RFIC芯片34相连接。
由图11可以看出，第一RFIC芯片31、第二RFIC芯片32、第三RFIC芯片33和第四RFIC芯片34排布规律，功分线9基本等长。
当该天线阵列的馈电位置呈规则排布时，由图9可以看出，第一RFIC芯片31、第二RFIC芯片32、第三RFIC芯片33和第四RFIC芯片34呈规律排布，这些RFIC芯片的散热也会均布，避免局部温度高、局部温度低的现象，避免对整个无线通信设备的性能造成影响。
需要说明的是，上述仅通过部分RFIC芯片，部分子阵进行技术效果分析，其余RFIC芯片和其余子阵所产生的技术效果是一样的。
基于上述，一个功分合路器5到至少两个RFIC芯片3之间的至少两个功分线基本等长，一个RFIC芯片3到至少两个子阵之间的馈电线基本等长，这样的话，从一个功分合路器5到至少两个子阵的传输路径基本等长，进而，不同子阵之间的时延差 相比现有技术会明显的减小，促使不同子阵的相位基本一致，最终提高天线阵列的宽带性能。
如图12所示，每个子阵具有相位中心(Phase Center)N，例如，当天线阵列中包括至少三个子阵，那么，相位中心N也包括至少三个。
需要说明的是：子阵所辐射出的电磁波在离开子阵一定的距离后，其等相位面会近似为一个球面，该球面的球心即为该子阵的相位中心，或者认为该球面球心周围的一个区域为该子阵的相位中心。在实际中，对于平面子阵，通常可以认为其相位中心与其几何中心重合，该几何中心是子阵辐射出的电磁波的接近球面的相位面的几何中心。
本申请实施例提供的天线阵列中的相位中心M的排布满足下述条件：
第一种：至少一行的多个相位中心不位于同一条直线上。
如图12所示的天线阵列中，第一行的多个相位中心呈直线排布，但是，第二的多个相位中心呈折弯线排布，即第二行的相位中心具有错位现象。
第二种：至少一列的多个相位中心不位于同一条直线上。
第三种：至少一行的多个相位中心不位于同一条直线上，以及，至少一列的多个相位中心不位于同一条直线上。
当天线阵列的相位中心满足上述任一种时，均认为该天线阵列的相位中心为不规则排布。
相位中心不规则排布可以造成天线阵列在扫描时栅瓣(Grating lobes)的能量不再叠加在少量角度上，而是分散到多个角度，因此该天线阵列的栅瓣抑制能力能大幅提升。
图13给出了另一种天线阵列的结构图，该天线阵列包括具有两个辐射单元11的子阵1A，还包括具有三个辐射单元11的子阵1B。
结合图14，该天线阵列中的馈电位置M也满足：每一行子阵的多个子阵的馈电位置均沿直线布设，每一列子阵的多个子阵的馈电位置也沿直线布设。从而，该天线阵列的馈电位置为规则排布。例如，第一行的多个子阵的馈电位置，以及与第一行相邻的第二行的多个子阵的馈电位置均呈直线排布。第一列的多个子阵的馈电位置，以及与第一列相邻的第二列的多个子阵的馈电位置也呈直线排布。
图15和图16所示，第五RFIC芯片35为具有六个射频收发通道的RFIC芯片。第五RFIC芯片35与子阵1B1、子阵1B2、子阵1B3、子阵1B4、子阵1B5、和子阵1B6相互连。即第五RFIC芯片35的第一射频收发通道通过馈电线059与子阵1B1互连，第五RFIC芯片35的第二射频收发通道通过馈电线0510与子阵1B2互连，第五RFIC芯片35的第三射频收发通道通过馈电线0511与子阵1B3互连，第五RFIC芯片35的第四射频收发通道通过馈电线0512与子阵1B4互连，第五RFIC芯片35的第五射频收发通道通过馈电线0513与子阵1B5互连，第五RFIC芯片35的第六射频收发通道通过馈电线0514与子阵1B6互连。
由图16可以看出，馈电线059至馈电线0514的长度基本相等。当馈电线的长度相等时，可使子阵1B1、子阵1B2、子阵1B3、子阵1B4、子阵1B5、和子阵1B6的相位基本一致，以提高该天线阵列的宽带性能。
图17中体现了四个RFIC芯片与功分合路器5的连接关系，且四个RFIC芯片分别为第五RFIC芯片35、第六RFIC芯片36、第七RFIC芯片37和第八RFIC芯片38。
由图17可以看出，第五RFIC芯片35、第六RFIC芯片36、第七RFIC芯片37和第八RFIC芯片38排布规律，功分合路器至该四个RFIC芯片的功分线基本等长。
如图18所示，该天线阵列中的相位中心N呈不规则排布，比如，第一行的多个子阵的相位中心形成折弯线，第二行的多个子阵的相位中心也形成折弯线。这样的话，相位中心不规则可能会导致天线阵列在扫描时栅瓣的能量不再叠加在少量角度上，而是分散到多个角度，因此该天线阵列的栅瓣抑制能力能大幅提升。
图19是本申请提供的一种天线阵列与现有天线阵列的栅瓣抑制曲线对比图，其中，曲线⑴是本申请实施例提供的天线阵列沿Y轴方向(垂直维)扫描时的栅瓣抑制曲线，曲线⑵是现有技术中的天线阵列沿Y轴方向(垂直维)扫描时的栅瓣抑制曲线。由曲线⑴和曲线⑵明显的看出，在垂直扫描角为-20°至20°区间内，本申请的栅瓣抑制明显的高于现有的栅瓣抑制。
图20是本申请提供的一种天线阵列与现有天线阵列的垂直扫描包络增益曲线对比图，在该图中，曲线⑾是本申请提供的天线阵列沿Y轴方向(垂直维)波束扫描方向图包络增益曲线，曲线⑿是现有的天线阵列沿Y轴方向(垂直维)波束扫描方向图包络增益曲线，可以看出本申请的天线阵列在-30°～-10°区间以及10°～30°区间增益均优于现有天线阵列，在-10°至10°区间内增益基本相当。另外，以10dB栅瓣抑制定义波束扫描能力，参考图21，现有天线阵列扫描能力为-10°至10°区间，本申请扫描能力大于±20°，实际能力可达到±30°左右。图20是以在Y方向波束扫描为例，X方向上也有类似的技术效果。
在可选择的实施方式中，各个辐射单元不限于等间距的分布在各个栅格内，即如图21所示，辐射单元11a、辐射单元11b和辐射单元11c沿同一列依次排布，相邻的辐射单元11a和辐射单元11b之间的间距为d1，相邻的辐射单元11b和辐射单元11c之间的间距为d2，d1与d2可以相等，也可以是d1与d2的差值的绝对值小于或等于该天线阵列的频段所对应的波长的1/4。
在可选择的实施方式中，沿第一方向的多个子阵的馈电位置可以允许一定程度的错位，不限于完全处于同一直线上，同样的，沿第二方向的多个子阵的馈电位置可以允许一定程度的错位，不限于完全处于同一直线上。如图21所示，沿第一方向布设的馈电位置M1、馈电位置M2和馈电位置M3，馈电位置M2和馈电位置M3错位，且错位距离d3小于或等于该天线阵列的频段所对应的波长的1/4。在两个相邻的馈电位置出现错位，且错位距离小于或等于该天线阵列的频段所对应的波长的1/4的情况下，对馈电线和均分线的等长设计影响是很小的，依然可以提升天线阵列的宽带性能。
上述介绍了在天线阵列中，馈电位置是呈不规则排布，也就是说，在同类子阵中，馈电位置会出现多种情况。下面通过实施例说明为了实现不规则排布，馈电位置的具体设置方式。
图22给出的是仅包括一个辐射单元11的子阵，在该子阵中，馈电位置M处于该辐射单元11的旁侧。
图23a、图23b和图23c给出了包括两个辐射单元的子阵中的馈电位置的布设方式， 令这两个辐射单元分别为第一辐射单元111和第二辐射单元112。
第一种布设方式：参照图23a，馈电位置M位于第一辐射单元111和第二辐射单元112之间。
第二种布设位置：参照图23b，馈电位置M在第一辐射单元111的远离第二辐射单元112的一侧。
第三种布设位置：参照图23c，馈电位置M在第二辐射单元112的远离第一辐射单元111的一侧。
另外，馈电位置M也可以在第一辐射单元111的下方或者在第二辐射单元112的下方。
当然，当天线阵列包括具有两个辐射单元的子阵时，馈电位置包括上述布设位置，但不限于这些布设位置。
图24a、图24b、图24c和图24d给出了包括三个辐射单元的子阵中的馈电位置的布设方式，令这三个辐射单元分别为第一辐射单元111和第二辐射单元112，以及第三辐射单元。
第一种布设位置：参照图24a，馈电位置M在第一辐射单元111的远离第二辐射单元112的一侧。
第二种布设位置：参照图24b，馈电位置M在第一辐射单元111和第二辐射单元112之间。
第三种布设位置：参照图24c，馈电位置M在第二辐射单元112和第三辐射单元113之间。
第四种布设位置：参照图24d，馈电位置M在第三辐射单元113的远离第二辐射单元112的一侧。
除此之外，馈电位置M也可以在第一辐射单元111的下方、第二辐射单元112的下方或者第三辐射单元113的下方。
同样的，当天线阵列包括具有三个辐射单元的子阵时，馈电位置包括上述布设位置，但不限于这些布设位置。
当天线阵列包括更多个辐射单元的子阵，馈电位置M的具体布设方式和上面布设示例是类似的。
也可以这样理解，当天线阵列包括具有至少两个辐射单元的子阵，馈电位置位于相邻两个辐射单元之间，或者馈电位置位于处于端部的辐射单元的远离其余辐射单元的一侧，或者馈电位置位于该子阵中所有辐射单元的下方。
为了实现相位中心呈不规则排布，馈电位置呈规则排布，在部分行中，部分列中，会存在相邻两个子阵之间具有空置的栅格，如图14所示，在空置的栅格内设置哑元2(Dummy Element)，哑元指的是没有馈电的辐射单元。
设置哑元可使天线阵列的各个子阵的周边环境一致，以使每一个子阵的方向图基本保持一致，最终会提高天线阵列的通信容量。
对于本申请提供的天线阵列所形成的二维形状，可以是图7和图13提供的矩形阵列，也可以是图25所示的接近圆形的形状，也可以是多边形形状(如图26所示的六边形)。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
在本说明书的描述中，所述“多个”是指两个或者两个以上，例如，“多个子阵”可以包括三个或三个以上的子阵，“多个射频收发通道”可以包括两个或两个以上的射频收发通道，“多个RFIC芯片”可以包括两个或两个以上的RFIC芯片，等等。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本发明的保护范围之内。因此，本发明的保护范围应以所述权利要求的保护范围为准。

Claims (16)

  1. 一种天线阵列，其特征在于，包括：
    多个子阵，每个所述子阵上设置有馈电位置和至少一个辐射单元，所述多个子阵沿第一方向和第二方向排布，所述第一方向与所述第二方向相垂直，沿所述第一方向，所述多个子阵的所述馈电位置位于同一条直线上，沿所述第二方向，所述多个子阵的所述馈电位置位于同一条直线上；沿所述第一方向，位于同一直线上的馈电位置所属的子阵处于同一行，沿所述第二方向，位于同一直线上的馈电位置所属的子阵处于同一列；
    每个所述子阵具有相位中心，所述天线阵列中至少有一行子阵中的子阵的相位中心不在同一条直线上，和/或，所述天线阵列中至少有一列子阵中的子阵的相位中心不在同一条直线上。
  2. 根据权利要求1所述的天线阵列，其特征在于，所述天线阵列中包括N个子阵，所述N个子阵中的每个子阵均设置数量相等的辐射单元，所述N个子阵中的至少一个子阵的馈电位置与所述N个子阵中的其他子阵的馈电位置不同，其中N为大于或等于2的整数。
  3. 根据权利要求1或2所述的天线阵列，其特征在于，所述天线阵列包括至少两种同类子阵，一种所述同类子阵中的子阵设置数量相等的辐射单元。
  4. 根据权利要求1-3中任一项所述的天线阵列，其特征在于，
    所述天线阵列包括至少一个第一子阵，所述第一子阵上设置至少两个辐射单元，所述至少两个辐射单元呈直线排布；
    所述第一子阵的馈电位置位于两个辐射单元之间；或者，
    所述第一子阵的馈电位置位于处于第一子阵端部的辐射单元的远离其余辐射单元的一侧。
  5. 根据权利要求1-4中任一项所述的天线阵列，其特征在于，所述天线阵列包括至少一个第二子阵，所述第二子阵上设置一个辐射单元，所述第二子阵的馈电位置位于所述辐射单元的旁侧。
  6. 根据权利要求1-5中任一项所述的天线阵列，其特征在于，沿所述第一方向，每两个相邻子阵的馈电位置之间的间距相等，和/或，沿所述第二方向，每两个相邻子阵的馈电位置之间的间距相等。
  7. 根据权利要求1-6中任一项所述的天线阵列，其特征在于，所述天线阵列中包含哑元，所述哑元为不馈电的辐射单元。
  8. 一种装置，其特征在于，包括：
    如权利要求1～7中任一项所述的天线阵列，
    馈电线，和
    电路承载板，其中，所述馈电线用于为所述天线阵列中的子阵馈电，所述天线阵列和所述馈电线设置在所述电路承载板上。
  9. 如权利要求8所述的装置，其特征在于，还包括：
    至少一个射频集成电路芯片，所述射频集成电路芯片设置在所述电路承载板上，所述射频集成电路芯片包括至少两个射频收发通道，所述至少两个射频收发通道用于 分别通过所述馈电线向所述天线阵列中的至少两个所述子阵馈电，所述射频收发通道与所述子阵一对一连接。
  10. 根据权利要求9所述的装置，其特征在于，
    所述装置包括功分合路器和至少两个所述射频集成电路芯片；所述功分合路器通过至少两个功分线分别与所述至少两个射频集成电路芯片连接，且所述至少两个功分线的长度相等，所述功分线与所述射频集成电路芯片一对一连接。
  11. 根据权利要求10所述的装置，其特征在于，所述电路承载板为封装基板；
    所述装置还包括：
    印制电路板，所述封装基板设置在所述印制电路板上，并与所述印制电路板连接，所述功分合路器设置在所述印制电路板上。
  12. 根据权利要求10所述的装置，其特征在于，所述电路承载板为印制电路板；
    所述功分合路器设置在所述印制电路板上。
  13. 一种装置，其特征在于，包括：
    如权利要求1～7中任一项所述的天线阵列；
    馈电线；和
    至少一个射频集成电路芯片，所述天线阵列和所述馈电线设置在所述射频集成电路芯片的封装层上，所述射频集成电路芯片包括至少两个射频收发通道，所述至少两个射频收发通道用于分别通过所述馈电线向天线阵列中的至少两个所述子阵馈电，所述射频收发通道与所述子阵一对一连接。
  14. 根据权利要求13所述的装置，其特征在于，所述装置包括功分合路器和至少两个射频集成电路芯片；
    所述功分合路器通过至少两个功分线分别与所述至少两个射频集成电路芯片连接，且所述至少两个功分线的长度相等，所述功分线与所述射频集成电路芯片一对一连接。
  15. 根据权利要求13或14所述的装置，其特征在于，所述装置还包括：
    印制电路板，所述射频集成电路芯片和所述功分合路器均设置在所述印制电路板上。
  16. 一种无线通信设备，其特征在于，包括
    如权利要求1～7中任一项所述的天线阵列，或者如权利要求8-15任一项所述的装置。
PCT/CN2020/118586 2020-09-28 2020-09-28 一种天线阵列、装置及无线通信设备 WO2022061937A1 (zh)

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JP2023519554A JP2023543068A (ja) 2020-09-28 2020-09-28 アンテナアレイ、装置、および無線通信デバイス
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