WO2022061670A1 - 纹路识别模组、其制作方法及显示装置 - Google Patents

纹路识别模组、其制作方法及显示装置 Download PDF

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Publication number
WO2022061670A1
WO2022061670A1 PCT/CN2020/117533 CN2020117533W WO2022061670A1 WO 2022061670 A1 WO2022061670 A1 WO 2022061670A1 CN 2020117533 W CN2020117533 W CN 2020117533W WO 2022061670 A1 WO2022061670 A1 WO 2022061670A1
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WIPO (PCT)
Prior art keywords
light
layer
pattern recognition
recognition module
area
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PCT/CN2020/117533
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English (en)
French (fr)
Inventor
海晓泉
丁小梁
梁轩
王迎姿
马森
Original Assignee
京东方科技集团股份有限公司
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Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to DE112020007197.9T priority Critical patent/DE112020007197T5/de
Priority to CN202080002097.3A priority patent/CN114641808B/zh
Priority to US17/417,918 priority patent/US20220336510A1/en
Priority to PCT/CN2020/117533 priority patent/WO2022061670A1/zh
Publication of WO2022061670A1 publication Critical patent/WO2022061670A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
    • G02B27/30—Collimators
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B5/00—Optical elements other than lenses
    • G02B5/005—Diaphragms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition
    • G06V10/12—Details of acquisition arrangements; Constructional details thereof
    • G06V10/14—Optical characteristics of the device performing the acquisition or on the illumination arrangements
    • G06V10/145—Illumination specially adapted for pattern recognition, e.g. using gratings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V10/00—Arrangements for image or video recognition or understanding
    • G06V10/10—Image acquisition
    • G06V10/12—Details of acquisition arrangements; Constructional details thereof
    • G06V10/14—Optical characteristics of the device performing the acquisition or on the illumination arrangements
    • G06V10/147—Details of sensors, e.g. sensor lenses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1318—Sensors therefor using electro-optical elements or layers, e.g. electroluminescent sensing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14623—Optical shielding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14685—Process for coatings or optical elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B2207/00—Coding scheme for general features or characteristics of optical elements and systems of subclass G02B, but not including elements and systems which would be classified in G02B6/00 and subgroups
    • G02B2207/123—Optical louvre elements, e.g. for directional light blocking

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a pattern recognition module, a manufacturing method thereof, and a display device.
  • An embodiment of the present disclosure provides a pattern recognition module, including a pattern recognition area and a peripheral area surrounding the pattern recognition area, the peripheral area including a binding area, wherein the pattern recognition module includes:
  • an optical sensing structure located on the substrate and in the pattern recognition area
  • the collimation structure located on the side of the optical sensing structure away from the substrate, at least in the pattern recognition area and not covering the binding area, the collimation structure includes at least two light-shielding layers stacked in layers and a light-transmitting layer located between every two adjacent light-shielding layers, each of the light-shielding layers has light-transmitting holes arranged in an array, and the light-transmitting holes in each of the light-shielding layers correspond one-to-one and are on the substrate.
  • the orthographic projections of are at least partially coincident.
  • the light-transmitting layer includes a transparent resin layer and a transparent inorganic insulating layer; between two adjacent light-shielding layers, the light-transmitting layer
  • the transparent resin layer is adjacent to the light shielding layer on the side adjacent to the substrate, and the transparent inorganic insulating layer is adjacent to the light shielding layer on the side away from the substrate.
  • the collimation structure includes a first light-shielding layer, a first transparent layer and a first transparent layer that are sequentially stacked on the optical sensing structure. a resin layer, a first transparent inorganic insulating layer, a second light shielding layer, a second transparent resin layer, a second transparent inorganic insulating layer and a third light shielding layer;
  • the first light-shielding layer includes first light-transmitting holes arranged in an array
  • the second light-shielding layer includes second light-transmitting holes arranged in an array
  • the third light-shielding layer includes third light-transmitting holes arranged in an array .
  • the aperture of the first light-transmitting hole is greater than or equal to the aperture of the third light-transmitting hole.
  • the aperture of the second light-transmitting hole is equal to the aperture of the first light-transmitting hole.
  • the aperture of the second light-transmitting hole is 50%-80% of the aperture of the first light-transmitting hole.
  • the apertures of the first light-transmitting hole, the second light-transmitting hole, and the third light-transmitting hole are successively decreased. .
  • the thickness of the first transparent resin layer is greater than the thickness of the second transparent resin layer.
  • the aperture of the first light-transmitting hole is 3 ⁇ m-8 ⁇ m, and the period of the first light-transmitting hole is 10 ⁇ m-40 ⁇ m , the thickness of the first transparent resin layer is 10 ⁇ m-15 ⁇ m, and the thickness of the second transparent resin layer is 8 ⁇ m-12 ⁇ m.
  • the collimation structure includes a first light-shielding layer and a transparent resin layer that are sequentially stacked on the optical sensing structure. , a transparent inorganic insulating layer and a second light shielding layer;
  • the first light-shielding layer includes first light-transmitting holes arranged in an array
  • the second light-shielding layer includes second light-transmitting holes arranged in an array.
  • the aperture of the first light-transmitting hole is equal to the aperture of the second light-transmitting hole.
  • the aperture of the first light-transmitting hole is 2 ⁇ m-10 ⁇ m, and the period of the first light-transmitting hole is 13 ⁇ m-60 ⁇ m , the thickness of the transparent resin layer is 5 ⁇ m-30 ⁇ m.
  • the orthographic projections of the centers of the corresponding light-transmitting holes in each of the light-shielding layers on the substrate overlap, and each The periods of the light-transmitting holes in the light-shielding layer are the same.
  • the optical sensing structure includes a plurality of optical sensors arranged in an array, and one optical sensor corresponds to each layer of the optical sensor. A plurality of light-transmitting holes in the light-shielding layer.
  • the optical sensing structure includes a gate, a gate insulating layer, an active layer, a source and drain layer, a gate insulating layer, an active layer, a source and drain layer, and A first insulating layer, a first electrode, a semiconductor layer, a second electrode, a protective layer, a passivation layer, a second insulating layer, a bias voltage line, and a blocking layer.
  • the orthographic projection of the source and drain layers on the substrate completely covers and is larger than that of the first electrode on the substrate orthographic projection on .
  • the source-drain layer and the first electrode are multiplexed into the same film layer.
  • the light shielding layer extends from the pattern recognition area to an adjacent edge of the peripheral area
  • the orthographic projection of the transparent resin layer on the substrate completely covers the orthographic projection of the adjacent light-shielding layer on the substrate;
  • the orthographic projection of the transparent inorganic insulating layer on the substrate completely covers and is larger than the orthographic projection of the adjacent transparent resin layer on the substrate.
  • the alignment structure further includes a retaining wall structure, and the retaining wall structure is arranged around the transparent resin layer and is connected to the The light-shielding layers adjacent to the transparent resin layers are arranged independently of each other in the same layer.
  • the material of the transparent inorganic insulating layer includes silicon nitride or silicon oxynitride formed by low temperature chemical vapor deposition.
  • the above-mentioned pattern recognition module provided by the embodiment of the present disclosure further includes: a planarization layer located between the collimation structure and the optical sensing structure, the planarization layer The layers are arranged over the entire surface and have a cutout pattern only in the binding area.
  • the material of the planarization layer includes silicon oxide or silicon nitride.
  • the above-mentioned pattern recognition module provided by the embodiment of the present disclosure further includes: a ground shielding layer located between the planarization layer and the optical sensing structure;
  • the ground shield layer is adjacent to the planarization layer, and the pattern of the ground shield layer is covered by the pattern of the planarization layer, and the orthographic projection of the ground shield layer on the substrate covers the optical sensor structure.
  • the material of the ground shielding layer includes indium tin oxide.
  • the above-mentioned pattern recognition module provided by the embodiment of the present disclosure further includes: a noise reduction metal layer located between the ground shielding layer and the optical sensing structure;
  • the texture recognition area is divided into a photosensitive area, a spacer area and a light-shielding area, and the spacer area is located between the light-sensitive area and the light-shielding area;
  • the optical sensing structure is arranged in the photosensitive area and the light-shielding area, and no pattern is arranged in the spacer area;
  • the noise reduction metal layer covers the light shielding area.
  • the light-shielding area is located on one side or opposite sides of the photosensitive area.
  • the above-mentioned pattern recognition module provided by the embodiment of the present disclosure further includes: a third insulating layer located between the grounding shielding layer and the noise reduction metal layer;
  • the noise reduction metal layer covers the spacer region; in the spacer region, the noise reduction metal layer is electrically connected to the ground shielding layer through a plurality of through holes penetrating through the third insulating layer.
  • the above-mentioned pattern recognition module provided by the embodiment of the present disclosure further includes: a binding electrode located in the binding area, the binding electrode and the noise reduction metal layer Same layer settings.
  • the material of the noise reduction metal layer and the binding electrode includes titanium/aluminum/titanium.
  • the binding area includes a gate driving chip binding area, and the binding area located in the gate driving chip binding area
  • the fixed electrode is called the first binding electrode
  • first connection electrode located in the film layer where the gate electrode is located, and a second connection electrode located in the source and drain layers, located in the film layer where the first electrode is located.
  • the third connection electrode is located at the fourth connection electrode of the bias voltage line; the first connection electrode is electrically connected to the second connection electrode through the first via hole penetrating the gate insulating layer, and the first connection electrode is Two connection electrodes are electrically connected to the third connection electrode through a second via hole penetrating the first insulating layer, and the third connection electrode is electrically connected to the fourth connection electrode through a third via hole penetrating the second insulating layer
  • the connection electrode is electrically connected, and the fourth connection electrode is electrically connected to the first binding electrode through a fourth via hole penetrating the third insulating layer; the first connection electrode is routed through the gate line and the gate line fan-out Electrically connected to the gate.
  • the first via hole, the second via hole and the first via hole corresponding to one of the first binding electrodes The number of the three via holes is at least two, and the orthographic projections of the first via hole, the second via hole and the third via hole on the substrate do not overlap each other and are located along the first binding electrode.
  • the extending directions of the electrodes are alternately arranged, one of the first binding electrodes corresponds to one of the fourth via holes, and the orthographic projection of the fourth via hole on the substrate simultaneously covers the first via hole and the second via hole. vias and the third vias.
  • the binding area further includes a data-driven chip binding area, and the binding area located in the data-driven chip binding area
  • the electrodes are called the second binding electrode and the third binding electrode
  • connection electrode located in the source and drain layers between the second binding electrode and the substrate, a sixth connection electrode located in the film layer where the first electrode is located, and a sixth connection electrode located in the bias voltage line.
  • a seventh connection electrode the seventh connection electrode is electrically connected to the source-drain layer through a data line and a data line fan-out trace;
  • the third binding electrode is located on one side edge of the data driving chip binding area, and an eighth connection electrode located on the bias voltage line is arranged between the third binding electrode and the substrate; the The eighth connection electrode is electrically connected to the bias voltage line through the bias voltage signal line and the bias voltage fan-out wiring.
  • the orthographic projections of the centers of the corresponding light-transmitting holes in each of the light-shielding layers on the substrate overlap, and each The periods of the light-transmitting holes in the light-shielding layer are the same;
  • the optical sensing structure includes a plurality of optical sensors arranged in an array, and one of the optical sensors corresponds to a plurality of light-transmitting holes in each of the light-shielding layers.
  • an embodiment of the present disclosure further provides a display device, including the above-mentioned texture recognition module provided by the embodiment of the present disclosure, and a display panel located on the texture recognition module, the display panel is connected to the texture recognition module.
  • the pattern recognition modules are fixed by optical glue.
  • the display panel is an OLED display panel
  • the OLED display panel includes a flexible OLED display backplane, a polarizer and a protective cover plate that are stacked in sequence, and the material of the protective cover plate includes polyimide.
  • the thickness of the OLED display panel ranges from 0.4 mm to 0.65 mm.
  • an embodiment of the present disclosure also provides a method for making a texture recognition module, the texture recognition module includes a texture identification area and a peripheral area surrounding the texture identification area, the peripheral area includes a binding area, wherein , the production method includes:
  • a low-temperature process is used to form a collimation structure on the optical sensing structure, the collimation structure is at least in the pattern recognition area and does not cover the binding area, and the collimation structure includes at least two layers stacked.
  • Each of the light-shielding layers has light-transmitting holes arranged in an array, and the light-transmitting holes in each of the light-shielding layers correspond one-to-one and are located in each of the light-shielding layers.
  • the orthographic projections on the substrate at least partially coincide.
  • the method before forming the collimation structure on the optical sensing structure, the method further includes:
  • grounding shielding layer on the binding electrode and the noise reduction metal layer, the grounding shielding layer and the binding electrode do not overlap each other;
  • Plasma-enhanced chemical vapor deposition is used to form a planarization layer on the ground shielding layer, and the planarization layer is disposed on the entire surface of the substrate and has a hollow pattern only in the binding area.
  • forming the light-transmitting layer in the collimating structure specifically includes:
  • a transparent resin layer is formed on the light-shielding layer by means of inkjet printing
  • a low temperature chemical vapor deposition method is used to form a transparent inorganic insulating layer covering and larger than the transparent resin layer on the transparent resin layer.
  • FIG. 1 is a schematic structural diagram of a pattern recognition module provided by an embodiment of the present disclosure
  • FIG. 2 is another schematic structural diagram of a texture recognition module provided by an embodiment of the present disclosure
  • 3a is a schematic structural diagram of an optical sensor in a pattern recognition module provided by an embodiment of the present disclosure
  • 3b is another schematic structural diagram of an optical sensor in a pattern recognition module provided by an embodiment of the present disclosure
  • 3c is another schematic structural diagram of an optical sensor in a pattern recognition module provided by an embodiment of the present disclosure.
  • 3d is a schematic top view of an optical sensor in the pattern recognition module provided by the embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an arrangement of light-transmitting holes in a pattern recognition module provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of another arrangement of light-transmitting holes in a pattern recognition module according to an embodiment of the present disclosure
  • FIG. 6 is another schematic structural diagram of a texture recognition module provided by an embodiment of the present disclosure.
  • FIG. 7 is a schematic top view of a pattern recognition module provided by an embodiment of the present disclosure.
  • FIG. 8a is another schematic top view of the pattern recognition module provided by the embodiment of the disclosure.
  • 8b is another schematic top view of the pattern recognition module provided by the embodiment of the present disclosure.
  • FIG. 8c is another schematic top view of the pattern recognition module provided by the embodiment of the present disclosure.
  • FIG. 9 is a partial top view schematic diagram of a pattern recognition area in a pattern recognition module provided by an embodiment of the present disclosure.
  • 10a is another schematic structural diagram of a pattern recognition module provided by an embodiment of the present disclosure.
  • 10b is another schematic structural diagram of the pattern recognition module provided by the embodiment of the present disclosure.
  • 10c is a schematic structural diagram of a gate drive binding area in a pattern recognition module provided by an embodiment of the present disclosure
  • 10d is another schematic structural diagram of the pattern recognition module provided by the embodiment of the present disclosure.
  • FIG. 10e is another schematic structural diagram of the pattern recognition module provided by the embodiment of the present disclosure.
  • FIG. 11 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 12 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 13 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 14 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • FIG. 15 is another schematic structural diagram of a display device provided by an embodiment of the present disclosure.
  • Embodiments of the present disclosure provide a pattern recognition module, a manufacturing method thereof, and a display device.
  • the specific implementations of the pattern recognition module, its manufacturing method and the display device provided by the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the preferred embodiments described below are only used to illustrate and explain the present disclosure, but not to limit the present disclosure. And the embodiments in this application and the features in the embodiments may be combined with each other without conflict.
  • An embodiment of the present disclosure provides a pattern recognition module, which is used for identification and detection of biometric features such as fingerprints and palm prints. As shown in Figure 1 and Figure 2, it includes a texture recognition area A and a peripheral area B surrounding the texture recognition area A, and the peripheral area B includes a binding area C, wherein the texture recognition module includes:
  • Substrate 1 Specifically, the material of substrate 1 can be PI or glass and other materials;
  • the optical sensing structure 2 is located on the substrate 1 and in the pattern recognition area A;
  • the collimation structure 3 is located on the side of the optical sensing structure 2 away from the substrate 1, at least in the pattern recognition area A and does not cover the binding area C.
  • the light-transmitting layer 32 between two adjacent light-shielding layers, each light-shielding layer 31 has light-transmitting holes 311 arranged in an array, and the light-transmitting holes 311 in each light-shielding layer 31 are in one-to-one correspondence and are orthographic projections on the substrate 1 at least partially overlap.
  • the number of light-transmitting holes 311 in each light-shielding layer 31 is the same, and the positions are the same, forming a one-to-one correspondence.
  • the centers of the one-to-one corresponding light-transmitting holes 311 in each light-shielding layer 31 can be set to overlap the orthographic projections on the substrate 1, so as to ensure that the period P of the light-transmitting holes 311 in each light-shielding layer 31 is the same, and the light is transparent.
  • the period of the holes 311 refers to the distance between the centers of two adjacent light-transmitting holes 311 .
  • the orthographic projections of the light-transmitting holes 311 of the light-shielding layers 31 at the same position on the substrate 1 overlap as completely as possible.
  • the light-shielding layers 31 are at the same position. There will be a certain offset between the light-transmitting holes 311, and the complete overlap cannot be guaranteed, that is, there may be partial overlap.
  • the area where the orthographic projections of the light-transmitting holes 311 at the same position of each light-shielding layer 31 on the substrate 1 are completely overlapped constitutes a hole structure, which plays the role of collimating the light incident at various angles of the position, so that the The light rays with a certain range of angles (small angles) to the normal line perpendicular to the surface of the collimating structure can pass through the set of holes structure, and the light rays beyond the range of angles (large angles) are cut off.
  • the difference between the minimum angle and the maximum angle through which the light can pass is the light receiving angle ⁇ .
  • a collimation structure composed of multiple light-shielding layers 31 with light-transmitting holes 311 is adopted, and the distance between the light-shielding layers 31 is adjusted through the light-transmitting layer 32 .
  • determine the distance between the light-shielding layer 31 at the top and the light-shielding layer 31 at the bottom and the aperture size and period of the light-transmitting hole 311, so as to adjust the required aspect ratio of the casing hole, and define the light-receiving angle ⁇ of the collimating structure the required collimation effect has been achieved, so that the information of the valleys and ridges of the texture can be accurately obtained.
  • the aperture sizes of the top light shielding layer 31 and the bottom light shielding layer 31 generally need to be set to be the same to ensure the required light-receiving angle ⁇ .
  • the number of layers of the light shielding layer 31 in the collimation structure 3 may be as shown in FIG. 1 , using two light shielding layers 31 and a light transmitting layer 32 in the middle, or by setting the middle light shielding layer 31 2, using three layers of light-shielding layers 31 and two layers of light-transmitting layers 32 in the middle, using the light-transmitting layer 32 to adjust the distance between each light-shielding layer 31, so that all adjacent light-transmitting holes 311
  • the light from the shading layer 31 will be blocked or absorbed by the light shielding layer 31, so that there will be no influence of stray light.
  • the specific parameters of the collimation structure 3 will be described in detail in the subsequent display device.
  • the period of the light-transmitting holes 311 in the light shielding layer 31 ie, the distance between the light-transmitting holes 311
  • the aperture of the light-transmitting holes 311 is smaller
  • the light crosstalk between the light-transmitting holes 311 is smaller, but Increasing the period of the light-transmitting holes 311 and reducing the aperture of the light-transmitting holes 311 will affect the light transmittance of the light-shielding layer 31.
  • the top light-shielding layer 31 and the bottom light-shielding layer 31 The aperture of the middle light-transmitting hole 311 needs to be set to a relative value, and the light-transmitting hole 311 in the middle light-shielding layer 31 has relatively little influence on the light transmittance.
  • the aperture mode can weaken the light crosstalk between adjacent light-transmitting holes 311 .
  • the aperture of the middle light shielding layer 31 may be 20% to 50% smaller than the aperture size of the top light shielding layer 31 .
  • the pattern recognition module provided by the embodiment of the present disclosure, it is only necessary to directly fabricate at least two light-shielding layers 31 and light-transmitting layers 32 with relatively simple structures after the optical sensing structure 2 is fabricated on the substrate 1 .
  • a better collimation effect is achieved, and the device structure is light and thin, which can reduce the processing difficulty of the device. Avoid problems such as blistering and other problems affecting yield caused by using optical adhesive (OCA) to fit the alignment structure on the pattern recognition module.
  • OCA optical adhesive
  • the collimation structure 3 can be fabricated by using a common device for fabricating a film layer on the array substrate without adding new fabrication equipment.
  • the optical sensing structure 2 is generally only arranged in the pattern recognition area A (generally corresponding to the display area in the display panel),
  • the wiring leading from the pattern recognition area A will be set in the peripheral area B and the binding electrode 7 will be set in the binding area C.
  • the surface of the binding electrode 7 needs to be exposed so as to be fixed with the driver chip. Since the function of the collimating structure 3 is to collimate the light obtained by the optical sensing structure 2, the film layer of the collimating structure 3 needs to cover the optical sensing structure 2 and avoid covering the binding electrodes in the binding area C 7.
  • the optical sensing structure 2 includes a plurality of optical sensors 21 arranged in an array, and a driver for driving the optical sensors 21 transistor 22.
  • the optical sensor includes a PIN photodiode and a PN photodiode, wherein the PIN photodiode includes a second electrode 213, a first electrode 211, and a semiconductor layer 212 between the second electrode 213 and the first electrode 211.
  • the first electrode 211 is connected to the driving
  • the transistor 22 is electrically connected, so that the driving transistor 22 can control the voltage applied to the first electrode 211 , thereby controlling the working state of the optical sensor 21 .
  • the semiconductor layer 212 includes a stacked P-type semiconductor layer and an N-type semiconductor layer (eg, an N-type Si layer), or includes a stacked P-type semiconductor layer (eg, a P-type Si layer), an intrinsic semiconductor layer (eg, a native semiconductor layer). (Si layer) and N-type semiconductor layer (such as N-type Si layer), for example, the I layer is a-Si material, the P layer is a-Si doped B ion material, and the N layer is a-Si doped P ion material Material.
  • the second electrode 213 is a transparent electrode, which can be made of transparent metal oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), and gallium zinc oxide (GZO).
  • the first electrode 211 is a metal electrode, and a metal material or alloy material such as copper (Cu), aluminum (Al), and titanium (Ti) is used.
  • the driving transistor 22 includes a gate, a gate insulating layer, an active layer, a source and a drain.
  • the optical sensing structure 2 includes a gate 221, a gate insulating layer 222, an active layer 223, a source and drain layer 224, a first insulating layer 225, a first electrode 211, a semiconductor ( PIN) layer 212 , a second electrode 213 , a protective layer 231 , a passivation layer 232 , a second insulating layer 233 , a bias voltage line 234 and a blocking layer 235 .
  • the source and drain layers extend to one side of the PIN, and the orthographic projection of the source and drain layers 224 on the substrate 1 can be completely covered and larger than the orthographic projection of the first electrodes 211 on the substrate 1, which can increase the photosensitive area.
  • the process of making masks for each film layer in the texture identification area A includes: gate 221 ⁇ gate insulating layer 222 ⁇ active layer 223 ⁇ source and drain layer 224 ⁇ first insulating layer 225 ⁇ first electrode 211 ⁇ PIN212 ⁇ second electrode 213 ⁇ passivation layer 232 ⁇ second insulating layer 233 ⁇ bias voltage line 234 ⁇ blocking layer 235, etc., wherein the pattern of the data line 224' is also set in the source and drain layers 224, passivation The layer 232 and the second insulating layer 233 are respectively patterned, so the via holes of the two are different in size.
  • 3d is a schematic top view of an optical sensor 21 and a driving transistor 22, in which it can be seen that the via holes in the passivation layer 232 232a is larger than the via hole 233a of the second insulating layer 233 .
  • the structure of the optical sensing structure 2 is not limited to the specific structure shown in FIG. 3a, and as shown in FIG. 3b, the source and drain layers 224 and the first electrodes 211 can be multiplexed into the same film layer, that is, the source and drain layers and the The first electrode can be integrally formed, that is, the source and drain layers extend to the PIN side and are multiplexed into the first electrode of the PIN.
  • the size of an optical sensor 21 is generally 50.4 ⁇ m-127.5 ⁇ m
  • the PPI of the optical sensor 21 is generally 200-500
  • the period of the light-transmitting holes 311 in the collimating structure 3 is generally 13 ⁇ m-60 ⁇ m Therefore, one optical sensor 21 corresponds to a plurality of light-transmitting holes 311 in each light-shielding layer 31 , for example, corresponding to several to several hundreds of light-transmitting holes 311 .
  • the light-transmitting holes 311 in the light shielding layer 31 may be arranged in a matrix manner, that is, the light-transmitting holes 311 are arranged in both the row direction and the column direction.
  • the light-transmitting holes 311 in the light-shielding layer 31 may also be arranged in a hexagonal manner, that is, as shown in FIG. 5 , the light-transmitting holes 311 are aligned in two diagonal directions.
  • the hole shape of the light-transmitting hole 311 may be circular or square, which is not limited herein.
  • the light-shielding layer 31 can generally be made of a material with strong light-shielding ability such as black resin such as BM.
  • the process parameters of each light shielding layer 31 are generally the same, the thickness is generally 500 angstroms to 16000 angstroms, and the OD value of each light shielding layer 31 needs to be guaranteed not less than 3.
  • the light-shielding layer 31 is generally coated with a film layer on the substrate 1 in its entirety during fabrication, and then the light-transmitting holes 311 are fabricated by means of photolithography or nano-imprinting.
  • the light-transmitting layer 32 may include a transparent resin layer 321 and a transparent inorganic insulating layer 322; Between the layers 31 , the transparent resin layer 321 is adjacent to the light shielding layer 31 on the side adjacent to the substrate 1 , and the transparent inorganic insulating layer 322 is adjacent to the light shielding layer 31 on the side away from the substrate 1 .
  • the transparent resin layer 321 and the transparent inorganic insulating layer 322 in the light-transmitting layer 32 can be fabricated by using the equipment for fabricating the thin-film encapsulation structure in the array substrate, that is, the transparent inorganic insulating layer 322 can be fabricated using the chemical vapor phase used to fabricate the inorganic thin-film encapsulation layer.
  • Deposition (CVD) equipment fabrication the transparent resin layer 321 can be fabricated using ink jet printing (IJP) equipment for making organic thin film encapsulation layers.
  • IJP ink jet printing
  • the transparent resin layer 321 can be formed first to ensure that the thickness required for the entire light-transmitting layer 32 is generally in the order of microns, and then a transparent inorganic layer with a thinner thickness in the nanometer order is formed on the transparent resin layer 321
  • the process parameters and thickness of each transparent inorganic insulating layer 322 are generally the same.
  • the transparent resin layer 321 can be specifically made of acrylic resin material. Directly coating black resin material on it cannot form a film layer with a relatively uniform thickness, and problems such as local material aggregation will occur. Therefore, transparent inorganic insulation is added on the transparent resin layer 321.
  • the layer 322 can ensure the uniformity of the film formation of the light shielding layer 31 formed thereon.
  • the material of the transparent inorganic insulating layer 322 may be silicon nitride (NxSi) or silicon oxynitride (NOxSi) formed by low temperature chemical vapor deposition.
  • the temperature used by the low temperature chemical vapor deposition method is about 80°C. Since the light-shielding layer 31 and the transparent resin layer 321 are fabricated at low temperature, forming the transparent inorganic insulating layer 322 by low-temperature chemical vapor deposition can avoid damage to the underlying light-shielding layer 31 pattern and the transparent resin layer 321 caused by a high temperature environment.
  • the light-shielding layer 31 may extend from the pattern recognition area A to the adjacent edge of the peripheral area B, that is, the area covered by the light-shielding layer 31 . It is larger than the pattern recognition area A to ensure that the stray light incident from the peripheral area B to the optical sensing structure 2 can be blocked.
  • the orthographic projection of the transparent resin layer 321 on the substrate 1 should completely cover the orthographic projection of the adjacent light-shielding layer 31 on the substrate 1. In actual production, due to the fluidity of the resin material, the final transparent resin layer 321 will be formed from the light-shielding layer 31.
  • the orthographic projection of the transparent inorganic insulating layer 322 formed on the transparent resin layer 321 on the substrate 1 should be completely covered and larger than the adjacent The orthographic projection of the transparent resin layer 321 on the substrate 1 .
  • the alignment structure 3 may further include a retaining wall structure 33, and the retaining wall structure 33 is arranged around the transparent resin layer 321,
  • the light shielding layer 31 adjacent to the transparent resin layer 321 is disposed independently of each other in the same layer.
  • a blocking wall structure 33 is formed around the light-shielding layer 31 at a certain distance from the periphery of the light-shielding layer 31, and the gap between the light-shielding layer 31 and the blocking wall structure 33 is used as the subsequent transparent resin.
  • the edge overflow area D of the layer 321 when the material of the transparent resin layer 321 with a certain fluidity is subsequently coated on the light-shielding layer 31, the retaining wall structure 33 can play the role of blocking the edge of the transparent resin layer 321 from reaching the retaining wall structure 33. spillover problem.
  • other light shielding layers 31 can be fabricated simultaneously with the blocking wall structure 33 .
  • the pattern recognition module may further include: a planarization layer 4 located between the collimation structure 3 and the optical sensing structure 2 ,
  • the planarization layer 4 is disposed on the entire surface and only has a hollow pattern in the binding region C. As shown in FIG. 1 and FIG. 2 , it may further include: a planarization layer 4 located between the collimation structure 3 and the optical sensing structure 2 , The planarization layer 4 is disposed on the entire surface and only has a hollow pattern in the binding region C. As shown in FIG.
  • planarization layer 4 is first fabricated. On the one hand, it is conducive to the subsequent formation of the collimation structure 3 thereon. On the other hand, the planarization layer 4 can cover the underlying The film layer plays a protective role.
  • the planarization layer 4 is provided with a hollow pattern in the binding area C to expose the binding electrode 7 to facilitate the subsequent binding of the driver chip.
  • the hollow pattern can be set in a one-to-one correspondence with each binding electrode 7, or can be set in the entire binding area C. A hollow pattern, which is not limited here.
  • the planarization layer 4 is generally made of inorganic insulating materials, for example, silicon oxide (SiO 2 ) or silicon nitride (SiN) materials, wherein silicon nitride (SiN) can be used.
  • the film-forming compactness is good, which is conducive to the uniformity of the film formation of the first light-shielding layer 31 in the collimation structure 3 on the planarization layer 4, and at the same time, it can better protect the ITO when etching the first light-shielding layer. Not affected by etching solution.
  • the planarization layer 4 can also be formed by a high temperature process without damaging the underlying film layer.
  • the planarization layer 4 can be fabricated using a plasma-enhanced chemical vapor deposition (PECVD) equipment, and the fabrication temperature can be about 230°C.
  • PECVD plasma-enhanced chemical vapor deposition
  • the pattern recognition module may further include: a ground shielding layer 5 located between the planarization layer 4 and the optical sensing structure 3 ;
  • the grounding shielding layer 5 is adjacent to the planarization layer 4, and the pattern of the grounding shielding layer 5 is covered by the pattern of the planarizing layer 4.
  • the orthographic projection of the grounding shielding layer 5 on the substrate 1 covers the positive projection of the optical sensing structure 2 on the substrate 1. projection.
  • the grounding shielding layer 5 covers the entire fingerprint identification area, or the grounding shielding layer 5 covers the photosensitive area.
  • the ground shielding layer 5 is generally disposed in the pattern recognition area A on the entire surface to shield the electromagnetic interference of the external optical sensing structure 2 , and is generally made of ITO to ensure transmittance.
  • the planarization layer 4 completely covers the grounding shielding layer 5, which can protect the grounding shielding layer 5 and prevent the grounding shielding layer 5 from being exposed to a hydrogen-rich environment when the film layer of the alignment structure 3 is fabricated in the subsequent chemical vapor deposition equipment.
  • the indium ions in the ITO are replaced by hydrogen gas, which causes the problem of atomization of the ground shielding layer 5 and affects the transmittance.
  • the pattern recognition area A is divided into a photosensitive area A1, a spacer area A2 and a light-shielding area A3, and the spacer area A2 is located between the light-sensitive area A1 and the light-shielding area A3.
  • the optical sensing structure 2 is arranged in the photosensitive area A1 and the light-shielding area A3, and no pattern is arranged in the spacer area A2.
  • the photosensitive area A1 and the light-shielding area A3 are shown in a block and arranged in an array. an optical sensor 21 .
  • the noise reduction metal layer 6 only covers the spacer region A2 and the light-shielding region A3, and the ground shielding layer 5 covers the photosensitive region A1, the spacer region A2 and the light-shielding region A3. That is to say, the optical sensing structures 2 in the light-shielding area A3 and the photosensitive area A1 are the same, and the difference between the two is that a noise reduction metal layer 6 is added in the light-shielding area A3.
  • Figure 3c shows the optical sensor structure in the light-shielding area A3
  • Figure 3a shows the optical sensing structure of the photosensitive area A1.
  • the output signal can be used as a noise signal (electrical signal noise) to perform denoising processing on the signal output by the photosensitive area A1.
  • a noise signal electrical signal noise
  • an integral multiple of 32 columns of optical sensors 21 may be provided in the light shielding area A3.
  • no optical sensor 21 is provided in the spacer A2 set between the photosensitive area A1 and the light-shielding area A3.
  • the spacer A2 can be set with a spacing of at least 2 columns of optical sensors 21 to avoid the signal of the light-sensitive area A1 and the light-shielding area A3. The signals interfere with each other.
  • the light-shielding area A3 may be located on one side or opposite sides of the photosensitive area A1, for example, the light-shielding area A3 may be It is arranged on the side of the photosensitive area A1 close to the gate driver chip bonding area C1, and/or the light shielding area A3 can be arranged on the side of the photosensitive area A1 away from the gate driver chip bonding area C1, or the light shielding area A3 can be arranged on the side of the bonding area C1 of the gate driver chip.
  • Both sides of the photosensitive area A1, or the light area A3 can be set on the side of the photosensitive area A1 close to the data driver chip binding area C2, and/or the light shielding area A3 can be set on the photosensitive area A1 away from the data driver chip binding area C2. side.
  • the orthographic projection of the noise reduction metal layer 6 disposed between the ground shielding layer 5 and the optical sensing structure 2 on the substrate 1, as shown in FIG. 8a, may be located adjacent to the texture recognition area A and the binding area C side, so as to reduce the noise interference between the optical sensing structure 2 and the driver chip bound to the binding area C.
  • the bonding area C includes a gate driver chip bonding area C1 located on the right side of the texture recognition area A and a data driver chip bonding area C2 located on the lower side of the texture recognition area A.
  • the pattern setting of the noise reduction metal layer 6 On the right and lower sides of the pattern recognition area A.
  • FIG. 8b shows a schematic diagram of the light shielding layers A3 being located on the left and right sides, respectively.
  • the noise reduction metal layer 6 is electrically connected to the grounding shielding layer 5 through a plurality of through holes 81 penetrating the third insulating layer 8, so that the noise reduction metal layer 6 can be grounded to avoid two A coupling capacitance is generated between them, which interferes with the signal read by the light shielding layer A3.
  • the binding electrode 7 located in the binding area C, the binding electrode 7 and the noise reduction
  • the metal layer 6 is arranged in the same layer.
  • the binding electrode 7 in the present disclosure is made at the same time as the noise reduction metal layer 6, That is, the bonding electrode 7 is made of metal material instead of ITO, that is, the pattern of the ground shielding layer 5 and the pattern of the bonding electrode 7 do not overlap with each other.
  • the gate driver chip bonding area C1 on the right side of the pattern recognition area A is generally used for bonding gate driver chips
  • the data driver chip bonding area C2 on the lower side of the pattern recognition area A is generally used for bonding A fixed data drive chip or a data read chip.
  • the bonding electrode 7 located in the bonding area C1 of the gate driver chip is referred to as the first bonding electrode 71
  • the bonding electrode 7 located in the bonding area C2 of the data driving chip is referred to as the first bonding electrode 71.
  • the second binding electrode 72 and the third binding electrode 73 Referred to as the second binding electrode 72 and the third binding electrode 73 .
  • the first binding electrode 71 is used for supplying a signal to the gate electrode 221
  • the second binding electrode 72 is used for connecting with the source and drain layers 224
  • the third binding electrode 73 is used for supplying a signal to the bias voltage line 234 .
  • a corresponding connection electrode may be provided under each binding electrode 7 to the film layer where the components to be connected are located.
  • the first binding electrode 71 has a first connecting electrode 91 located in the film layer where the gate electrode 221 is located between the first binding electrode 71 and the substrate 1, and a second connecting electrode 92 located in the source and drain layer 224, located in the first
  • the third connection electrode 93 of the film layer where the electrode 211 is located is located at the fourth connection electrode 94 of the bias voltage line 234 .
  • the first connection electrode 71 is electrically connected to the second connection electrode 92 through the first via hole 222 a penetrating the gate insulating layer 222
  • the second connection electrode 92 is electrically connected to the third connection electrode 93 through the second via hole 225 a penetrating the first insulating layer 225
  • the third connection electrode 93 is electrically connected to the fourth connection electrode 94 through the third via hole 233a penetrating the second insulating layer 233
  • the fourth connection electrode 94 is connected to the fourth connection electrode 94 through the fourth via hole 8a penetrating the third insulating layer 8 .
  • a binding electrode 71 is electrically connected; the first connection electrode 71 is electrically connected to the gate electrode 221 through the gate line and the gate line fan-out wiring.
  • the number of the first via hole 222a, the second via hole 225a and the third via hole 233a corresponding to one first binding electrode 71 is at least two, and the first via hole 222a, the second via hole 222a, the second via hole
  • the orthographic projections of 225a and the third via hole 233a on the substrate 1 do not overlap each other and are alternately arranged along the extending direction of the first binding electrode 71.
  • One first binding electrode 71 corresponds to one fourth via hole 8a, and the fourth The orthographic projection of the hole 8a on the substrate 1 simultaneously covers the first via hole 222a, the second via hole 225a and the third via hole 233a.
  • first via holes 222a, second via holes 225a and third via holes 233a can improve connection yield and reduce resistance, and the first via hole 222a, second via hole 225a and third via hole 233a Staggering the settings can improve connection yield.
  • FIG. 10b an embodiment in which each via hole overlaps with each other or partially overlaps is also within the protection scope of the present disclosure.
  • connection electrode 95 located in the source-drain layer 224 between the second binding electrode 72 and the substrate 1 , which is located in the film where the first electrode 213 is located.
  • the sixth connection electrode 96 of the layer is located at the seventh connection electrode 97 of the bias voltage line 234; the seventh connection electrode 97 is electrically connected to the source and drain layers 224 through the data line and the data line fanout.
  • the corresponding via holes may also be staggered and provided in multiples, which will not be described in detail here.
  • the third binding electrode 73 is generally located on one side edge of the data driving chip binding area C2, and there is an eighth connection electrode 98 located on the bias voltage line between the third binding electrode 73 and the substrate 1; Eight connection electrodes 98 are electrically connected to bias voltage lines 234 through bias voltage signal lines and bias voltage fan-out traces.
  • alignment marks with a shape similar to "+” can also be made at the four corners of the film layer where the noise reduction metal layer 6 is located, and the alignment marks are used for alignment when each film layer in the alignment structure 3 is subsequently fabricated.
  • the materials of the noise reduction metal layer 6 and the bonding electrode 7 can be changed from the general molybdenum (MO) material to Titanium/Aluminum/Titanium (Ti/Al/Ti) material.
  • an embodiment of the present disclosure provides a display device, as shown in FIG. 11 , comprising the above-mentioned pattern recognition module 100 provided by the embodiment of the present disclosure, and a display panel 200 located on the pattern recognition module 100 , The display panel 200 and the pattern recognition module 100 are fixed by an optical adhesive 300 (OCA).
  • OCA optical adhesive 300
  • the optical sensing structure 2 is fabricated on the substrate 1 in the pattern recognition module 100, at least two light-shielding layers 31 and light-transmitting layers with relatively simple structures are directly fabricated. 32 can achieve a better collimation effect, and the device structure is light and thin, which can reduce the processing difficulty of the device. Problems such as blistering and other problems affecting the yield caused by using optical adhesive (OCA) to adhere the alignment structure on the pattern recognition module 100 are avoided.
  • OCA optical adhesive
  • the collimation structure 3 can be fabricated by using a common device for fabricating a film layer on the array substrate without adding new fabrication equipment.
  • the display panel 200 may be an organic light emitting diode (Organic Light Emitting Diode, OLED) display panel or a quantum dot light emitting diode (Quantum Dot Light Emitting Diode) Diodes, QLED) display panels, etc., which are not specifically limited in the embodiments of the present disclosure.
  • the OLED display panel may be, for example, a flexible OLED display panel.
  • OLED display panels and QLED display panels have self-luminous properties, and the luminescence of their display pixel units can also be controlled or modulated as needed, which can facilitate pattern collection and help improve device integration. ;
  • the OLED display panel generally includes a flexible OLED display backplane 210, a polarizer 220 and a protective cover plate 230 which are stacked in sequence, and the material of the protective cover plate 230 can be polyimide PI.
  • the substrate of the flexible OLED display backplane 210 is a flexible substrate, and the specific material may be PI or other flexible materials.
  • the OLED display panel can realize flexible display, for example, it can be made into a folding screen according to customer requirements.
  • the protective cover plate 230 in the OLED display panel is made of PI material, so that the panel can be made light and thin, and the panel thickness requirement required by the customer can be met.
  • the required thickness of the ultra-thin folding screen can be achieved, and its value range is 0.4 mm to 0.65 mm, so as to meet the design requirements of the folding screen.
  • the collimation structure 3 in the pattern recognition module 100 may include two light-shielding layers 31 and one light-transmitting layer 32 .
  • the distance between the light-shielding layers 31 is used to determine the height of the collimation structure 3
  • the light-transmitting holes in the light-shielding layer 31 are used to determine the collimation light-receiving angle.
  • the first light-shielding layer 31a includes first light-transmitting holes 311a arranged in an array
  • the second light-shielding layer 31b includes second light-transmitting holes 311b arranged in an array.
  • the centers of the light-transmitting holes 311 in the two light shielding layers 31 overlap with each other, and the periods P of the light-transmitting holes 311 are the same.
  • the specific size range is affected by the thickness of the OLED display panel thereon.
  • the aperture D1 of the first light-transmitting hole 311a may be equal to the aperture D2 of the second light-transmitting hole 311b.
  • the period P affects the transmittance of the signal light received by each optical sensor PIN in the optical sensing structure, and the light crosstalk between adjacent light-transmitting holes 311 .
  • the thickness Hx of the OLED display panel may range from 0.4 mm to 0.65 mm.
  • the value of ⁇ ranges from 20° to 50°, and ⁇ 0 is a fixed value of 70°. Therefore, the aperture D1 of the first light-transmitting hole 311a' is 2 ⁇ m-10 ⁇ m, and the period P of the light-transmitting hole 311 is set to The value range is affected by Hx, therefore, the period of the first light-transmitting holes 311a is 13 ⁇ m-60 ⁇ m, and the thickness H of the transparent resin layer 321 is 5 ⁇ m-30 ⁇ m.
  • the collimation structure 3 in the pattern recognition module 100 may include three layers of light-shielding layers 31 and two layers of light-transmitting layers 32 Specifically, it includes a first light shielding layer 31a, a first transparent resin layer 321a, a first transparent inorganic insulating layer 322a, a second light shielding layer 31b, a second transparent resin layer 321b, a first light shielding layer 321b, a second light shielding layer 321b, a Two transparent inorganic insulating layers 322b and a third light shielding layer 31c;
  • the first light-shielding layer 31a includes first light-transmitting holes 311a arranged in an array
  • the second light-shielding layer 31b includes second light-transmitting holes 311b arranged in an array
  • the third light-shielding layer 31c includes third light-transmitting holes 311c arranged in an array.
  • the centers of the light-transmitting holes 311 in the three light shielding layers 31 overlap with each other, and the periods of the light-transmitting holes 311 are the same.
  • the specific size range is affected by the thickness of the OLED display panel thereon.
  • the aperture D1 of the first light-transmitting hole 311a may be greater than or equal to the aperture D3 of the third light-transmitting hole 311c;
  • the thickness H1 of the transparent resin layer 321a may be greater than the thickness H2 of the second transparent resin layer 321b, so that the second light shielding layer 31b is closer to the three light shielding layers 31c, and the effect of reducing light crosstalk between adjacent light-transmitting holes is enhanced.
  • the aperture D2 of the second light-transmitting hole 311b may be equal to the aperture D1 of the first light-transmitting hole 311a , or, as shown in FIG. 14 , , the aperture D2 of the second light-transmitting hole 311b may be 50%-80% of the aperture D1 of the first light-transmitting hole 311a, which can further weaken the light crosstalk between adjacent light-transmitting holes.
  • the apertures of the third light-transmitting holes 311 c , the second light-transmitting holes 311 b , and the first light-transmitting holes 311 a may be arranged in a manner of increasing sequentially.
  • the thickness Hx of the OLED display panel can be in the range of 0.4mm-0.65mm, and the period P of the light-transmitting holes 311 The value range is affected by Hx, the period of the first light-transmitting hole 311a is 10 ⁇ m-40 ⁇ m, according to the required collimation light-receiving angle requirements, the aperture of the first light-transmitting hole 311a can be 3 ⁇ m-8 ⁇ m, the first transparent resin The thickness of the layer 321a is 10 ⁇ m-15 ⁇ m, and the thickness of the second transparent resin layer 321b is 8 ⁇ m-12 ⁇ m.
  • a planarization layer 4 can be fabricated on top of it, and its material is SiN or SiO2, with a thickness of 800 angstroms to 8000 angstroms, plays a flattening role.
  • a black first light-shielding layer 31a is formed thereon, for example, a film layer with a thickness of 500 angstroms to 16,000 angstroms is made of BM resin material, and then photolithography or nano-imprinting is used to make light-transmitting holes 311a and light-transmitting holes 311a
  • the aperture size D1 is 3 ⁇ m ⁇ 8 ⁇ m, and the period, ie, the pitch value P, of the adjacent light-transmitting holes 311 a is 10 ⁇ m ⁇ 40 ⁇ m.
  • a first transparent resin layer 321a covering the entire surface of the first light shielding layer 31a is formed on the first light shielding layer 31a, and its thickness H1 is 10 ⁇ m ⁇ 15 ⁇ m.
  • the first transparent inorganic insulating layer 322a is formed, and then the second light-shielding layer 31b is formed.
  • the aperture size D2 of the second light-transmitting holes 311b is 3 ⁇ m ⁇ 8 ⁇ m, and then the second transparent resin layer 321b is formed, and the thickness H2 is 8 ⁇ m ⁇ 12 ⁇ m.
  • the second transparent inorganic insulating layer 322b and the third light-shielding layer 31c are formed, and the aperture size D3 of the third light-transmitting hole 311c is 3 ⁇ m ⁇ 8 ⁇ m.
  • the specific value of P can be selected as 18 ⁇ m
  • the specific value of H1 can be selected as 15 ⁇ m
  • the specific value of H2 can be selected as 10 ⁇ m.
  • D2 is 20%-50% smaller than the value of D1, and can be selected as 3 ⁇ m-3.5 ⁇ m.
  • the above-mentioned display device provided by the embodiment of the present disclosure is not limited to the structure of two or three layers of light-shielding layers, and the number of layers of light-shielding layers can also be increased, for example, it can be four or more layers of light-shielding layers. Not detailed.
  • the display device further includes signal lines (including gate lines, data lines, detection lines, etc.) for providing electrical signals (including scan signals, data signals, detection signals, etc.), for example, the light-emitting device can be controlled by a driving circuit to emit light state to achieve sub-pixel lighting.
  • the display panel also has functional layers such as an encapsulation layer and a touch layer. For these functional layers, reference may be made to related technologies, and details are not described herein again.
  • the display device may be any product or component with a texture recognition function, such as a mobile phone, a tablet computer, a display, a notebook computer, etc., which is not specifically limited in the embodiments of the present disclosure.
  • an embodiment of the present disclosure also provides a method for making the above-mentioned pattern recognition module, wherein the pattern recognition module includes a pattern recognition area and a peripheral area surrounding the pattern recognition area, the peripheral area includes a binding area, and the production method includes :
  • a low-temperature process is used to form a collimation structure on top of the optical sensing structure.
  • the collimation structure is at least in the pattern recognition area and does not cover the binding area.
  • the collimation structure includes at least two light-shielding layers stacked on top of each other and two adjacent layers.
  • the light-transmitting layers between the light-shielding layers each have light-transmitting holes arranged in an array, and the light-transmitting holes in the light-shielding layers correspond one-to-one and the orthographic projections on the substrate at least partially overlap.
  • the device structure is light and thin, which can reduce the processing difficulty of the device. Avoid problems such as blistering and other problems affecting yield caused by using optical adhesive (OCA) to fit the alignment structure on the pattern recognition module.
  • OCA optical adhesive
  • the fabrication of the collimation structure can be completed by using a common device for fabricating a film layer on the array substrate without adding new fabrication equipment.
  • the light shielding layer in the formation of the collimation structure can generally be made of a material with strong light shielding ability such as black resin such as BM.
  • the process parameters of each light shielding layer are generally the same.
  • a film layer is generally coated on the substrate as a whole, and then the light-transmitting holes are fabricated by means of photolithography or nano-imprinting.
  • forming the light-transmitting layer in the collimation structure specifically includes:
  • a transparent resin layer is formed on the light-shielding layer by inkjet printing
  • a low temperature chemical vapor deposition method is used to form a transparent inorganic insulating layer covering and larger than the transparent resin layer on the transparent resin layer.
  • the transparent resin layer and the transparent inorganic insulating layer in the light-transmitting layer can be fabricated by using the equipment for fabricating the thin-film encapsulation structure in the array substrate, that is, the transparent inorganic insulating layer can be fabricated by chemical vapor deposition (CVD) for fabricating the inorganic thin-film encapsulation layer.
  • the transparent resin layer can be fabricated using ink jet printing (IJP) equipment for making organic thin film encapsulation layers.
  • a transparent resin layer can be formed first to ensure that the overall thickness of the light-transmitting layer 32 is generally in the order of microns, and then a transparent inorganic insulating layer with a thinner thickness in the nanometer order is formed on the transparent resin layer.
  • the process parameters and thicknesses of each transparent inorganic insulating layer are generally the same.
  • the transparent resin layer can be specifically made of acrylic resin material. Directly coating black resin material on it cannot form a film layer with a relatively uniform thickness, and problems such as local material aggregation will occur. Therefore, a transparent inorganic insulating layer is added on top of the transparent resin layer. The uniformity of film formation of the light-shielding layer formed thereon can be ensured.
  • a low-temperature process is used to form the alignment structure.
  • the temperature used in the low temperature process is about 80°C. Since the light-shielding layer and the transparent resin layer are fabricated at low temperature, forming the transparent inorganic insulating layer by low-temperature chemical vapor deposition can avoid damage to the underlying light-shielding layer pattern and the transparent resin layer caused by a high temperature environment.
  • the method may further include:
  • a noise reduction metal layer is formed on the optical sensing structure, and a binding electrode is formed in the binding area;
  • a grounding shielding layer is formed on the binding electrode and the noise reduction metal layer, and the grounding shielding layer and the binding electrode do not overlap each other;
  • Plasma-enhanced chemical vapor deposition is used to form a planarization layer on the ground shielding layer.
  • the planarization layer is arranged on the entire surface of the substrate and only has a hollow pattern in the binding area.
  • the ground shielding layer is generally arranged on the entire surface of the pattern recognition area, which plays the role of shielding the electromagnetic interference of the external optical sensing structure, and is generally made of ITO in order to ensure the transmittance.
  • the planarization layer completely covers the grounding shielding layer, which can protect the grounding shielding layer and prevent the grounding shielding layer from being exposed in a hydrogen-rich environment to be replaced by hydrogen when the film layer of the alignment structure is fabricated in the subsequent chemical vapor deposition equipment.
  • the indium ions in the ground shield cause the fogging problem of the ground shield and affect the transmittance.
  • the binding electrode is made of ITO in the same layer as the grounding shielding layer
  • the binding electrode is made at the same time as the noise reduction metal layer, that is, the binding electrode is made of metal material instead of ITO, that is, the grounding shield is made.
  • the pattern of the layers and the pattern of the bonding electrodes do not coincide with each other. Avoid using the binding electrode formed of ITO material to make the film layer of the alignment structure in the subsequent chemical vapor deposition equipment, and the binding electrode will affect its electrical properties after being exposed to a hydrogen-rich environment.

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Abstract

一种纹路识别模组（100）、其制作方法及显示装置，在纹路识别模组（100）中的基底（1）上制作完成光学传感结构（2）后直接制作结构相对简单的至少两层遮光层（31）和透光层（32）即可达到较好的准直效果，且器件结构较轻薄，可以降低器件的加工工艺难度。避免采用在纹路识别模组（100）之上采用光学胶(OCA)（300）贴合准直结构（3）的方式带来的起泡等影响良率的问题。并且，由于在光学传感结构（2）之上直接制作膜层形成准直结构（3），因此，可以采用阵列基板之上膜层制作通用的设备完成准直结构（3）的制作，无需增加新的制作设备。

Description

纹路识别模组、其制作方法及显示装置 技术领域
本公开涉及显示技术领域，尤指一种纹路识别模组、其制作方法及显示装置。
背景技术
在光学图像获取过程中，当物体与光学传感结构的距离过大时，会造成获取到的图像模糊的问题。而且获取的物体的光线存在串扰问题，导致最终无法获取到物体的清晰图像。
发明内容
本公开实施例提供了一种纹路识别模组，包括纹路识别区域和包围纹路识别区域的周边区域，所述周边区域包括绑定区域，其中，所述纹路识别模组包括：
基底；
光学传感结构，位于所述基底之上且在所述纹路识别区域内；
准直结构，位于所述光学传感结构背离所述基底的一侧、至少在所述纹路识别区域内且未覆盖所述绑定区域，所述准直结构包括至少两层层叠设置的遮光层和位于每相邻两层遮光层之间的透光层，各所述遮光层具有呈阵列排布的透光孔，各所述遮光层中的透光孔一一对应且在所述基底上的正投影至少部分重合。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述透光层包括透明树脂层和透明无机绝缘层；在相邻两层遮光层之间，所述透明树脂层与邻近所述基底一侧的遮光层邻接，所述透明无机绝缘层与远离所述基底一侧的遮光层邻接。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中， 所述准直结构包括在所述光学传感结构之上依次层叠设置的第一遮光层、第一透明树脂层、第一透明无机绝缘层、第二遮光层、第二透明树脂层、第二透明无机绝缘层和第三遮光层；
所述第一遮光层包括阵列排布的第一透光孔，所述第二遮光层包括阵列排布的第二透光孔，所述第三遮光层包括阵列排布的第三透光孔。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述第一透光孔的孔径大于或等于所述第三透光孔的孔径。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述第二透光孔的孔径等于第一透光孔的孔径。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述第二透光孔的孔径为所述第一透光孔的孔径的50％-80％。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述第一透光孔、所述第二透光孔和所述第三透光孔的孔径依次递减。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述第一透明树脂层的厚度大于所述第二透明树脂层的厚度。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述第一透光孔的孔径为3μm-8μm，所述第一透光孔的周期为10μm-40μm，所述第一透明树脂层的厚度为10μm-15μm，所述第二透明树脂层的厚度为8μm-12μm。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述准直结构包括在所述光学传感结构之上依次层叠设置的第一遮光层、透明树脂层、透明无机绝缘层和第二遮光层；
所述第一遮光层包括阵列排布的第一透光孔，所述第二遮光层包括阵列排布的第二透光孔。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述第一透光孔的孔径等于所述第二透光孔的孔径。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中， 所述第一透光孔的孔径为2μm-10μm，所述第一透光孔的周期为13μm-60μm，透明树脂层的厚度为5μm-30μm。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述准直结构的准直收光角θ满足以下关系：tanθ＝D/H＝Cmin/2Hx，其中，D为透光孔的孔径，H为所述准直结构的高度，Cmin为手指谷脊间距，Hx为手指到所述准直结构的间距。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，各所述遮光层内一一对应的透光孔的中心在所述基底上的正投影重合，各所述遮光层内的透光孔的周期相同。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述光学传感结构包括呈阵列排布的多个光学传感器，一个所述光学传感器对应每层所述遮光层中的多个透光孔。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述光学传感结构包括依次层叠设置的栅极、栅绝缘层、有源层、源漏极层、第一绝缘层、第一电极、半导体层、第二电极、保护层、钝化层、第二绝缘层、偏置电压线、和阻隔层。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述源漏极层在所述基底上的正投影完全覆盖且大于所述第一电极在所述基底上的正投影。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述源漏极层和所述第一电极复用为同一膜层。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述遮光层从所述纹路识别区域延伸至所述周边区域的邻接边缘；
所述透明树脂层在所述基底上的正投影完全覆盖邻接的遮光层在所述基底上的正投影；
所述透明无机绝缘层在所述基底上的正投影完全覆盖且大于邻接的所述透明树脂层在所述基底上的正投影。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述准直结构还包括挡墙结构，所述挡墙结构围绕所述透明树脂层设置，且与所述透明树脂层邻接的遮光层同层相互独立设置。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述透明无机绝缘层的材料包括采用低温化学气相沉积方式形成的氮化硅或氮氧化硅。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，还包括：位于所述准直结构与所述光学传感结构之间的平坦化层，所述平坦化层整面设置且仅在所述绑定区域具有镂空图案。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述平坦化层的材料包括氧化硅或氮化硅。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，还包括：位于所述平坦化层和所述光学传感结构之间的接地屏蔽层；
所述接地屏蔽层与所述平坦化层邻接，且所述接地屏蔽层的图案被所述平坦化层的图案覆盖，所述接地屏蔽层在所述基底上的正投影覆盖所述光学传感结构。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述接地屏蔽层的材料包括氧化铟锡。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，还包括：位于所述接地屏蔽层与所述光学传感结构之间的降噪金属层；
所述纹路识别区域分为感光区、间隔区和遮光区，所述间隔区位于所述感光区和所述遮光区之间；
所述光学传感结构设置在所述感光区和所述遮光区内，在所述间隔区未设置图案；
所述降噪金属层覆盖所述遮光区。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述遮光区位于所述感光区的一侧或相对的两侧。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，还包括：位于所述接地屏蔽层和所述降噪金属层之间的第三绝缘层；
所述降噪金属层覆盖所述间隔区；在所述间隔区内，所述降噪金属层通过贯穿所述第三绝缘层的多个通孔与所述接地屏蔽层电连接。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，还包括：位于所述绑定区域内的绑定电极，所述绑定电极与所述降噪金属层同层设置。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述降噪金属层和所述绑定电极的材料包括钛/铝/钛。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，所述绑定区域包括栅极驱动芯片绑定区域，位于所述栅极驱动芯片绑定区域内的绑定电极称为第一绑定电极；
所述第一绑定电极与所述基底之间具有位于所述栅极所在膜层的第一连接电极，位于所述源漏极层的第二连接电极，位于所述第一电极所在膜层的第三连接电极，位于所述偏置电压线的第四连接电极；所述第一连接电极通过贯穿所述栅绝缘层的第一过孔与所述第二连接电极电连接，所述第二连接电极通过贯穿所述第一绝缘层的第二过孔与所述第三连接电极电连接，所述第三连接电极通过贯穿所述第二绝缘层的第三过孔与所述第四连接电极电连接，所述第四连接电极通过贯穿所述第三绝缘层的第四过孔与所述第一绑定电极电连接；所述第一连接电极通过栅线和栅线扇出走线与栅极电连接。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，一个所述第一绑定电极对应的所述第一过孔、所述第二过孔和所述第三过孔的数量均为至少两个，所述第一过孔、所述第二过孔和所述第三过孔在基底上的正投影均互不重叠且沿所述第一绑定电极的延伸方向交替排列，一个所述第一绑定电极对应一个所述第四过孔，所述第四过孔在所述基底上的正投影同时覆盖所述第一过孔、所述第二过孔和所述第三过孔。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中， 所述绑定区域还包括数据驱动芯片绑定区域，位于所述数据驱动芯片绑定区域内的绑定电极称为第二绑定电极和第三绑定电极；
所述第二绑定电极与所述基底之间具有位于所述源漏极层的第五连接电极，位于所述第一电极所在膜层的第六连接电极，位于所述偏置电压线的第七连接电极；所述第七连接电极通过数据线和数据线扇出走线与所述源漏极层电连接；
所述第三绑定电极位于所述数据驱动芯片绑定区域的一侧边缘，所述第三绑定电极与所述基底之间具有位于所述偏置电压线的第八连接电极；所述第八连接电极通过偏置电压信号线和偏置电压扇出走线与所述偏置电压线电连接。
在一种可能的实现方式中，在本公开实施例提供的上述纹路识别模组中，各所述遮光层内一一对应的透光孔的中心在所述基底上的正投影重合，各所述遮光层内的透光孔的周期相同；
所述光学传感结构包括呈阵列排布的多个光学传感器，一个所述光学传感器对应每层所述遮光层中的多个透光孔。
另一方面，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述纹路识别模组，以及位于所述纹路识别模组之上的显示面板，所述显示面板与所述纹路识别模组之间通过光学胶固定。
在一种可能的实现方式中，在本公开实施例提供的上述显示装置中，所述显示面板为OLED显示面板；
所述OLED显示面板包括依次层叠设置的柔性OLED显示背板、偏光片和保护盖板，所述保护盖板的材料包括聚酰亚胺。
在一种可能的实现方式中，在本公开实施例提供的上述显示装置中，所述OLED显示面板的厚度取值范围为0.4mm-0.65mm。
另一方面，本公开实施例还提供了一种纹路识别模组的制作方法，所述纹路识别模组包括纹路识别区域和包围纹路识别区域的周边区域，所述周边区域包括绑定区域，其中，所述制作方法包括：
提供一基底；
在所述基底之上且在所述纹路识别区域内形成呈阵列排布的光学传感结构；
在所述光学传感结构之上采用低温工艺形成准直结构，所述准直结构至少在所述纹路识别区域内且未覆盖所述绑定区域，所述准直结构包括至少两层层叠设置的遮光层和位于每相邻两层遮光层之间的透光层，各所述遮光层具有呈阵列排布的透光孔，各所述遮光层中的透光孔一一对应且在所述基底上的正投影至少部分重合。
在一种可能的实现方式中，在本公开实施例提供的上述制作方法中，在所述光学传感结构之上形成所述准直结构之前，还包括：
在所述光学传感结构之上形成降噪金属层，同时在所述绑定区域形成绑定电极；
在所述绑定电极和所述降噪金属层之上形成接地屏蔽层，所述接地屏蔽层与所述绑定电极互不交叠；
采用等离子体增强化学气相沉积方式，在所述接地屏蔽层之上形成平坦化层，所述平坦化层在所述基底上整面设置且仅在所述绑定区域具有镂空图案。
在一种可能的实现方式中，在本公开实施例提供的上述制作方法中，形成所述准直结构中的透光层，具体包括：
采用喷墨打印方式，在所述遮光层上形成透明树脂层；
采用低温化学气相沉积方式，在所述透明树脂层上形成覆盖且大于所述透明树脂层的透明无机绝缘层。
附图说明
图1为本公开实施例提供的纹路识别模组的一种结构示意图；
图2为本公开实施例提供的纹路识别模组的另一种结构示意图；
图3a为本公开实施例提供的纹路识别模组中一个光学传感器的结构示意 图；
图3b为本公开实施例提供的纹路识别模组中一个光学传感器的另一种结构示意图；
图3c为本公开实施例提供的纹路识别模组中一个光学传感器的另一种结构示意图；
图3d为本公开实施例提供的纹路识别模组中一个光学传感器的俯视示意图；
图4为本公开实施例提供的纹路识别模组中透光孔的一种排列示意图；
图5为本公开实施例提供的纹路识别模组中的透光孔的另一种排列示意图；
图6为本公开实施例提供的纹路识别模组的另一种结构示意图；
图7为本公开实施例提供的纹路识别模组的一种俯视示意图；
图8a为本公开实施例提供的纹路识别模组的另一种俯视示意图；
图8b为本公开实施例提供的纹路识别模组的另一种俯视示意图；
图8c为本公开实施例提供的纹路识别模组的另一种俯视示意图；
图9为本公开实施例提供的纹路识别模组中纹路识别区域的局部俯视示意图；
图10a为本公开实施例提供的纹路识别模组的另一种结构示意图；
图10b为本公开实施例提供的纹路识别模组的另一种结构示意图；
图10c为本公开实施例提供的纹路识别模组中栅极驱动绑定区域的结构示意图；
图10d为本公开实施例提供的纹路识别模组的另一种结构示意图；
图10e为本公开实施例提供的纹路识别模组的另一种结构示意图；
图11为本公开实施例提供的显示装置的一种结构示意图；
图12为本公开实施例提供的显示装置的另一种结构示意图；
图13为本公开实施例提供的显示装置的另一种结构示意图；
图14为本公开实施例提供的显示装置的另一种结构示意图；
图15为本公开实施例提供的显示装置的另一种结构示意图。
具体实施方式
本公开实施例提供了一种纹路识别模组、其制作方法及显示装置。为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的纹路识别模组、其制作方法及显示装置的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
附图中各部件的形状和大小不反应真实比例，目的只是示意说明本公开内容。
本公开实施例提供的一种纹路识别模组，用于指纹、掌纹等生物特征识别和检测。如图1和图2所示，包括纹路识别区域A和包围纹路识别区域A的周边区域B，周边区域B包括绑定区域C，其中，纹路识别模组包括：
基底1；具体地，基底1的材料可以为PI或玻璃等材料；
光学传感结构2，位于基底1之上且在纹路识别区域A内；
准直结构3，位于光学传感结构2背离基底1的一侧、至少在纹路识别区域A内且未覆盖绑定区域C，准直结构3包括至少两层层叠设置的遮光层31和位于每相邻两层遮光层之间的透光层32，各遮光层31具有呈阵列排布的透光孔311，各遮光层31中的透光孔311一一对应且在基底1上的正投影至少部分重合。
具体地，在本公开实施例提供的上述纹路识别模组的准直结构3中，每一个遮光层31中的透光孔311数量相同，且位置相同，构成一一对应关系。可选地，可以将各遮光层31内一一对应的透光孔311的中心设置为在基底1上的正投影重合，保证各遮光层31内的透光孔311的周期P相同，透光孔311的周期指的是相邻的两个透光孔311中心之间的距离。在制作时，各遮光层31在同一位置处的透光孔311之间在基底1上的正投影尽可能的完全重叠， 但是根据实际制作工艺的对位误差，各遮光层31在同一位置处的透光孔311之间会存在一定的偏移，并不能保证完全重叠，即可能存在部分重叠的情况。
各遮光层31在同一位置处的透光孔311之间在基底1上的正投影完全重叠的区域构成套孔结构，起到对入射至该位置的各个角度的光线进行准直的作用，使与垂直于准直结构表面的法线呈在一定范围角度(小角度)的光线可以通过该套孔结构，超过该范围角度(大角度)的光线被截止。可以通过光线的最小角度和最大角度之间的差值即为收光角θ。
具体地，在本发明实施例提供的上述纹路识别模组中，采用具有透光孔311的多层遮光层31构成的准直结构，通过透光层32调整各层遮光层31之间的距离，确定出顶部的遮光层31和底部的遮光层31之间的距离以及透光孔311的孔径大小和周期，以调节所需的套孔深宽比，而限定准直结构的收光角θ，已达到所需的准直效果，从而可以实现精确获取纹路的谷与脊的信息。并且，顶部的遮光层31和底部的遮光层31的孔径大小一般需要设置一致，以保证所需的收光角θ。
具体地，在准直结构3中遮光层31的层数可以如图1所示，采用两层挡光层31且中间设置一层透光层32的方式，也可以通过设置中间的遮光层31的方式，即如图2所示采用三层遮光层31且中间设置两层透光层32的方式，采用透光层32调节各遮光层31之间的距离，使相邻所有透光孔311的光都会被遮光层31遮挡或者吸收，从而不会有杂散光的影响，即中间的遮光层31可以遮挡透光孔311之间的光线串扰，提高识别出的纹路信息的准确性。对于准直结构3的具体参数在后续显示装置中进行详细描述。并且，由于在遮光层31中透光孔311的周期(即透光孔311之间的距离)越大且透光孔311的孔径越小，透光孔311之间的光线串扰越小，但是增大透光孔311的周期且减小透光孔311的孔径会影响遮光层31的光透过率，因此，考虑到光透过率的问题，顶部的遮光层31和底部的遮光层31中透光孔311的孔径需要设定为一相对数值，而中间的遮光层31中透光孔311对光透过率的影响相对较小，通过缩小中间的遮光层31的透光孔311的孔径方式，可以削弱相邻透光 孔311之间的光线串扰。具体地，中间的遮光层31的孔径相对于顶部的遮光层31的孔径尺寸数值可以小20％～50％。
具体地，在本公开实施例提供的上述纹路识别模组中，仅需要在基底1上制作完成光学传感结构2后直接制作结构相对简单的至少两层遮光层31和透光层32即可达到较好的准直效果，且器件结构较轻薄，可以降低器件的加工工艺难度。避免采用在纹路识别模组之上采用光学胶(OCA)贴合准直结构的方式带来的起泡等影响良率的问题。并且，由于在光学传感结构2之上直接制作膜层形成准直结构3，因此，可以采用阵列基板之上膜层制作通用的设备完成准直结构3的制作，无需增加新的制作设备。
具体地，在本公开实施例提供的上述纹路识别模组中，如图10a和图10c所示，光学传感结构2一般仅设置在纹路识别区域A(一般对应显示面板中的显示区域)，在周边区域B会设置从纹路识别区域A引出的布线以及在绑定区域C会设置绑定电极7，绑定电极7的表面需要裸露以便与驱动芯片固定。由于准直结构3的作用是对光学传感结构2获取到的光线进行准直，因此，准直结构3的膜层需要覆盖光学传感结构2且避免覆盖绑定区域C中的绑定电极7。可选地，在本公开实施例提供的上述纹路识别模组中，如图3a所示，光学传感结构2包括呈阵列排布的多个光学传感器21，以及用于驱动光学传感器21的驱动晶体管22。其中，光学传感器包括PIN光电二极管和PN光敏二极管，其中PIN光电二极管包括第二电极213、第一电极211及第二电极213和第一电极211之间的半导体层212，第一电极211与驱动晶体管22电连接，从而驱动晶体管22可以控制施加在第一电极211的电压，进而控制光学传感器21的工作状态。半导体层212包括叠层设置的P型半导体层以及N型半导体层(例如N型Si层)，或者包括叠层设置的P型半导体层(例如P型Si层)、本征半导体层(例如本征Si层)以及N型半导体层(例如N型Si层)，例如I层为a-Si材料，P层为a-Si掺杂B离子的材料，N层为a-Si掺杂P离子的材料。例如，第二电极213为透明电极，可以采用氧化铟锡(ITO)、氧化铟锌(IZO)、氧化镓锌(GZO)等透明金属氧化物等材料。第一电极211 为金属电极，采用铜(Cu)、铝(Al)、钛(Ti)等金属材料或者合金材料。驱动晶体管22包括栅极，栅极绝缘层，有源层，源漏极。具体地，光学传感结构2在基底1上包括依次层叠设置的栅极221、栅绝缘层222、有源层223、源漏极层224、第一绝缘层225，第一电极211、半导体(PIN)层212、第二电极213、保护层231、钝化层232、第二绝缘层233、偏置电压线234和阻隔层235。并且，源漏极层延伸至PIN的一侧，源漏极层224在基底1上的正投影可以完全覆盖且大于第一电极211在基底1上的正投影，可以增大感光区域。对应的，在纹路识别区域A内各膜层掩模制作的工序包括：栅极221→栅绝缘层222→有源层223→源漏极层224→第一绝缘层225→第一电极211→PIN212→第二电极213→钝化层232→第二绝缘层233→偏置电压线234→阻隔层235等，其中，在源漏极层224中还会设置数据线224’的图案，钝化层232和第二绝缘层233分别进行构图工艺，因此两者的过孔大小不同，图3d为一个光学传感器21和驱动晶体管22的俯视示意图，其中可以看出，在钝化层232的过孔232a大于第二绝缘层233的过孔233a。光学传感结构2的结构不局限于图3a所示的具体结构，还可以如图3b所示，将源漏极层224和第一电极211复用合并为同一膜层，即源漏极和第一电极可以一体成型，即源漏极层延伸至PIN侧，并复用为PIN的第一电极。
具体地，由于工艺制作限制，一般一个光学传感器21的尺寸在50.4μm-127.5μm，光学传感器21的PPI一般在200-500，而准直结构3中透光孔311的周期一般在13μm-60μm左右，因此，一个光学传感器21对应每层遮光层31中的多个透光孔311，例如对应几个～几百个透光孔311。
具体地，如图4所示，在遮光层31中的透光孔311可以采用矩阵方式排布，即在行方向和列方向透光孔311均对其排列。在遮光层31中的透光孔311也可以采用六角排布，即如图5所示，在两个对角线方向透光孔311均对齐排列。透光孔311的孔型可以是圆形也可以是方形，在此不做限定。
具体地，在本公开实施例提供的上述纹路识别模组中，遮光层31一般可以选用黑色树脂诸如BM等遮光能力较强的材料制作。各遮光层31的工艺参 数一般相同，其厚度较薄一般为500埃～16000埃，并且各遮光层31的OD值需要保证不小于3。其中，OD值指的是膜层的光透过率，OD值＝1则膜层的光透过率为10％，OD值＝2则膜层的光透过率为1％，OD值＝3则膜层的光透过率为0.1％，OD值＝4则膜层的光透过率为0.01％。即OD值越大，膜层的遮光效果越好。具体地，遮光层31在制作时一般在基底1上整层涂布膜层，之后，使用光刻或者纳米压印的方式制作透光孔311。
可选地，在本公开实施例提供的上述纹路识别模组中，如图1和图2所示，透光层32可以包括透明树脂层321和透明无机绝缘层322；在相邻两层遮光层31之间，透明树脂层321与邻近基底1一侧的遮光层31邻接，透明无机绝缘层322与远离基底1一侧的遮光层31邻接。
具体地，透光层32中的透明树脂层321和透明无机绝缘层322可以采用制作阵列基板中的薄膜封装结构的设备完成制作，即透明无机绝缘层322可以使用制作无机薄膜封装层的化学气相沉积(CVD)设备制作，透明树脂层321可以使用制作有机薄膜封装层的喷墨打印(IJP)设备制作。在遮光层31制作完成后，可以先形成透明树脂层321以保证透光层32整体所需要的厚度一般在微米量级，之后在透明树脂层321上形成厚度较薄在纳米量级的透明无机绝缘层322，各透明无机绝缘层322的工艺参数和厚度一般相同。透明树脂层321具体可以采用亚克力树脂材料制作，在其上直接涂布黑色树脂材料无法形成厚度较为均一膜层，会发生局部材料聚集等问题，因此，在透明树脂层321之上增加透明无机绝缘层322，可以保证在其上形成的遮光层31成膜均匀性。
可选地，在本公开实施例提供的上述纹路识别模组中，透明无机绝缘层322的材料可以采用低温化学气相沉积方式形成的氮化硅(NxSi)或氮氧化硅(NOxSi)。
具体地，低温化学气相沉积方式所使用的温度约80℃左右。由于遮光层31和透明树脂层321制作时采用低温，因此，采用低温化学气相沉积方式形成透明无机绝缘层322可以避免高温环境对下方的遮光层31图案和透明树脂 层321造成损坏。
可选地，在本公开实施例提供的上述纹路识别模组中，如图6所示，遮光层31可以从纹路识别区域A延伸至周边区域B的邻接边缘，即遮光层31所覆盖的区域要大于纹路识别区域A，以保证能阻挡从周边区域B入射至光学传感结构2的杂散光。透明树脂层321在基底1上的正投影应完全覆盖邻接的遮光层31在基底1上的正投影，在实际制作时由于树脂材料的流动性，最终形成的透明树脂层321会从遮光层31的边缘溢出，因此，为了保证后续形成的遮光层31在边缘位置处厚度的均一性，在透明树脂层321上形成的透明无机绝缘层322在基底1上的正投影应完全覆盖且大于邻接的透明树脂层321在基底1上的正投影。
可选地，在本公开实施例提供的上述纹路识别模组中，如图6和图7所示，准直结构3还可以包括挡墙结构33，挡墙结构33围绕透明树脂层321设置，且与透明树脂层321邻接的遮光层31同层相互独立设置。
具体地，在制作遮光层31的同时，在遮光层31的外围一定间距处制作环绕遮光层31一圈设置的挡墙结构33，遮光层31与挡墙结构33之间的间隙作为后续透明树脂层321的边缘溢流区D，后续在遮光层31之上涂布具有一定流动性的透明树脂层321的材料时，挡墙结构33可以起到阻挡透明树脂层321边缘向挡墙结构33之外溢出的问题。并且，由于在制作每层透明树脂层321时都可能存在边缘溢流的问题，因此，除了最后制作的遮光层31之外，其他遮光层31在制作的同时均可以制作挡墙结构33。
可选地，在本公开实施例提供的上述纹路识别模组中，如图1和图2所示，还可以包括：位于准直结构3与光学传感结构2之间的平坦化层4，平坦化层4整面设置且仅在绑定区域C具有镂空图案。
具体地，在光学传感结构2制作完成后，先制作一层平坦化层4，一方面有利于后续在其上形成准直结构3，另一方面，平坦化层4可以对其下覆盖的膜层起到保护作用。平坦化层4在绑定区域C设置镂空图案以露出绑定电极7便于后续绑定驱动芯片，镂空图案具体可以与每一个绑定电极7一一对应设 置，也可以在整个绑定区域C设置一个镂空图案，在此不做限定。
可选地，在本公开实施例提供的上述纹路识别模组中，平坦化层4一般选用无机绝缘材料制作，例如可以采用氧化硅(SiO2)或氮化硅(SiN)材料，其中氮化硅成膜致密性较好，有利于准直结构3中第一层遮光层31在平坦化层4上成膜的均匀性，同时可以在刻蚀所述第一层遮光层时更好的保护ITO不受刻蚀液的影响。由于光学传感结构2的各膜层采用高温工艺形成，因此平坦化层4也可以采用高温工艺形成而不会损坏下方膜层。具体地，平坦化层4可以采用等离子体增强化学气相沉积(PECVD)设备制作，其制作温度可以230℃左右。
可选地，在本公开实施例提供的上述纹路识别模组中，如图3a至图3c所示，还可以包括：位于平坦化层4和光学传感结构3之间的接地屏蔽层5；接地屏蔽层5与平坦化层4邻接，且接地屏蔽层5的图案被平坦化层4的图案覆盖，接地屏蔽层5在基底1上的正投影覆盖光学传感结构2在基底1上的正投影。具体的，接地屏蔽层5覆盖整个指纹识别区，或接地屏蔽层5覆盖感光区。
具体地，如图6所示，接地屏蔽层5一般整面设置在纹路识别区域A，起到屏蔽外界光学传感结构2电磁干扰的作用，且为了保证透过率一般采用ITO制作。平坦化层4完全覆盖接地屏蔽层5，可以起到保护接地屏蔽层5的作用，避免接地屏蔽层5在后续化学气相沉积设备中制作准直结构3的膜层时，暴露在富氢环境中被氢气置换出ITO中的铟离子，而导致接地屏蔽层5雾化问题影响透过率。
可选地，在本公开实施例提供的上述纹路识别模组中，如图6所示，还可以包括：位于接地屏蔽层5与光学传感结构2之间的降噪金属层6。如图8a、图8b和图9所示，纹路识别区域A分为感光区A1、间隔区A2和遮光区A3，间隔区A2位于感光区A1和遮光区A3之间。光学传感结构2设置在感光区A1和遮光区A3内，在间隔区A2未设置图案，在图9中以方框示出了在感光区A1和遮光区A3设置的呈阵列排布的多个光学传感器21。降噪金属 层6仅覆盖间隔区A2和遮光区A3，接地屏蔽层5覆盖感光区A1、间隔区A2和遮光区A3。即可以认为，在遮光区A3和感光区A1的光学传感结构2相同，两者的区别在于在遮光区A3增加了降噪金属层6，图3c示出了遮光区A3内的光学传感器结构，图3a示出了感光区A1的光学传感结构。遮光区A3的光学传感器21由于不受光照，因此其输出的信号可以作为噪声信号(电信号噪声)对感光区A1输出的信号进行去噪处理，一般地，读取芯片以32列光学传感器21为周期进行数据读取，因此，为了便于去噪处理，可以在遮光区A3设置32列的整数倍的光学传感器21。而在感光区A1和遮光区A3之间设置的间隔区A2内未设置光学传感器21，间隔区A2一般可以设置间隔至少2列光学传感器21的间距，避免感光区A1的信号与遮光区A3的信号之间相互干扰。
可选地，在本公开实施例提供的上述纹路识别模组中，如图8a和图8b所示，遮光区A3可以位于感光区A1的一侧或相对的两侧，比如，遮光区A3可以设置在感光区A1靠近栅极驱动芯片绑定区域C1的一侧，和/或遮光区A3可以设置在感光区A1远离栅极驱动芯片绑定区域C1的一侧，或遮光区A3可以设置在感光区A1的两侧，或光区A3可以设置在感光区A1靠近数据驱动芯片绑定区域C2的一侧，和/或遮光区A3可以设置在感光区A1远离数据驱动芯片绑定区域C2的一侧。
具体地，在接地屏蔽层5与光学传感结构2之间设置的降噪金属层6在基底1的正投影，如图8a所示，可以位于纹路识别区域A与绑定区域C相邻的侧边，以起到降低光学传感结构2与绑定区域C绑定的驱动芯片之间的噪声干扰。在图8a中绑定区域C包括位于纹路识别区域A右侧的栅极驱动芯片绑定区域C1和位于纹路识别区域A下侧的数据驱动芯片绑定区域C2，降噪金属层6的图案设置在纹路识别区域A的右侧和下侧。在图8b中示出了遮光层A3分别位于左右两侧的示意图。
可选地，在本公开实施例提供的上述纹路识别模组中，如图10a，图10b和图10d所示，还可以包括：位于接地屏蔽层5和降噪金属层6之间的第三 绝缘层8。如图9所示，在间隔区A2内，降噪金属层6通过贯穿第三绝缘层8的多个通孔81与接地屏蔽层5电连接，可以将降噪金属层6接地处理，避免两者之间产生耦合电容而对遮光层A3读取的信号产生干扰。
可选地，在本公开实施例提供的上述纹路识别模组中，如图10a至图10e所示，还可以包括：位于绑定区域C内的绑定电极7，绑定电极7与降噪金属层6同层设置。相对于绑定电极7采用与接地屏蔽层5同层的ITO制作，如图10a、图10b、图10d和图10e所示，本公开中绑定电极7采用与降噪金属层6同时制作，即采用金属材料制作而不采用ITO制作绑定电极7，即接地屏蔽层5的图案与绑定电极7的图案互不重合。避免采用ITO材料形成的绑定电极7在后续化学气相沉积设备中制作准直结构3的膜层时，绑定电极7暴露在富氢环境后影响其电学性能。
具体地，在位于纹路识别区域A右侧的栅极驱动芯片绑定区域C1一般用于绑定栅极驱动芯片，在位于纹路识别区域A下侧的数据驱动芯片绑定区域C2一般用于绑定数据驱动芯片或称为数据读取芯片。为了方便描述，如图8c所示，将位于栅极驱动芯片绑定区域C1内的绑定电极7称为第一绑定电极71，将位于数据驱动芯片绑定区域C2内的绑定电极7称为第二绑定电极72和第三绑定电极73。第一绑定电极71用于向栅极221提供信号，第二绑定电极72用于与源漏极层224连接，第三绑定电极73用于向偏置电压线234提供信号。
为了便于不同类型的绑定电极7与对应的部件连接，可以在各绑定电极7下方设置对应的连接电极至所需连接的部件所在膜层，例如，在图10a和图10b中示出针对第一绑定电极71，在第一绑定电极71与基底1之间具有位于栅极221所在膜层的第一连接电极91，位于源漏极层224的第二连接电极92，位于第一电极211所在膜层的第三连接电极93，位于偏置电压线234的第四连接电极94。第一连接电极71通过贯穿栅绝缘层222的第一过孔222a与第二连接电极92电连接，第二连接电极92通过贯穿第一绝缘层225的第二过孔225a与第三连接电极93电连接，第三连接电极93通过贯穿第二绝缘层233 的第三过孔233a与第四连接电极94电连接，第四连接电极94通过贯穿第三绝缘层8的第四过孔8a与第一绑定电极71电连接；第一连接电极71通过栅线和栅线扇出走线与栅极221电连接。
如图10c所示，一个第一绑定电极71对应的第一过孔222a、第二过孔225a和第三过孔233a的数量均为至少两个，第一过孔222a、第二过孔225a和第三过孔233a在基底1上的正投影均互不重叠且沿第一绑定电极71的延伸方向交替排列，一个第一绑定电极71对应一个第四过孔8a，第四过孔8a在基底1上的正投影同时覆盖第一过孔222a、第二过孔225a和第三过孔233a。具体地，第一过孔222a、第二过孔225a和第三过孔233a设置多个可以提高连接良率以及减少电阻，且第一过孔222a、第二过孔225a和第三过孔233a错开设置可以提高连接良率。并且，如图10b所示，各过孔相互重叠或部分重叠的实施方式也在本公开保护范围内。
同理，在图10d中示出针对第二绑定电极72，在第二绑定电极72与基底1之间具有位于源漏极层224的第五连接电极95，位于第一电极213所在膜层的第六连接电极96，位于偏置电压线234的第七连接电极97；第七连接电极97通过数据线和数据线扇出走线与源漏极层224电连接。类似于第一绑定电极71与对应连接电极的连接关系，对应过孔也可以错开设置，且设置多个，在此不作详述。
图10e所示，第三绑定电极73一般位于数据驱动芯片绑定区域C2的一侧边缘，第三绑定电极73与基底1之间具有位于偏置电压线的第八连接电极98；第八连接电极98通过偏置电压信号线和偏置电压扇出走线与偏置电压线234电连接。
具体地，在降噪金属层6所在膜层的四角还可以制作形状类似“+”的对位标记，该对位标记用于在后续制作准直结构3中各膜层时进行对位。
具体地，在绑定电极7与接地屏蔽层5同时制作时，为了提高绑定电极7的电学性能，降噪金属层6和绑定电极7的材料可以从通用的钼(MO)材料变更为钛/铝/钛(Ti/Al/Ti)材料。
基于同一发明构思，本公开实施例提供了一种显示装置，如图11所示，包括本公开实施例提供的上述纹路识别模组100，以及位于纹路识别模组100之上的显示面板200，显示面板200与纹路识别模组100之间通过光学胶300(OCA)固定。
具体地，在本公开实施例提供的上述显示装置中，在纹路识别模组100中的基底1上制作完成光学传感结构2后直接制作结构相对简单的至少两层遮光层31和透光层32即可达到较好的准直效果，且器件结构较轻薄，可以降低器件的加工工艺难度。避免采用在纹路识别模组100之上采用光学胶(OCA)贴合准直结构的方式带来的起泡等影响良率的问题。并且，由于在光学传感结构2之上直接制作膜层形成准直结构3，因此，可以采用阵列基板之上膜层制作通用的设备完成准直结构3的制作，无需增加新的制作设备。
可选地，在本公开实施例提供的上述显示装置中，如图11所示，显示面板200可以为有机发光二极管(Organic Light Emitting Diode，OLED)显示面板或者量子点发光二极管(Quantum Dot Light Emitting Diodes，QLED)显示面板等，本公开的实施例对此不作具体限定。OLED显示面板例如可以为柔性OLED显示面板。例如，OLED显示面板以及QLED显示面板具有自发光特性，并且其显示像素单元的发光还可以根据需要进行控制或调制，从而可以为纹路采集提供便利，而且有助于提高装置的集成度。；
OLED显示面板一般包括依次层叠设置的柔性OLED显示背板210、偏光片220和保护盖板230，保护盖板230的材料可以为聚酰亚胺PI。柔性OLED显示背板210的衬底为柔性衬底，具体材料可以是PI或其它柔性材料。
具体地，OLED显示面板可以实现柔性显示，例如可以按照客户需求制作成折叠屏。并且，将OLED显示面板中的保护盖板230采用PI材料制作，可以实现面板轻薄化，达到客户所需的面板厚度要求。例如可以达到要求的超薄折叠屏的厚度，其取值范围为0.4mm～0.65mm，以实现折叠屏的设计要求。
可选地，在本公开实施例提供的上述显示装置中，如图12所示，纹路识别模组100中的准直结构3可以包括两层遮光层31和一层透光层32，两层遮 光层31之间的距离用于确定准直结构3的高度，遮光层31中的透光孔用作确定准直收光角，具体包括在光学传感结构2之上依次层叠设置的第一遮光层31a、透明树脂层321、透明无机绝缘层322和第二遮光层31b；
第一遮光层31a包括阵列排布的第一透光孔311a，第二遮光层31b包括阵列排布的第二透光孔311b。
具体地，两个遮光层31中的透光孔311的中心相互重合，且透光孔311的周期P相同，具体尺寸范围受其上的OLED显示面板的厚度影响。
可选地，在本公开实施例提供的上述显示装置中，第一透光孔311a的孔径D1可以等于第二透光孔311b的孔径D2。
具体地，如图13所示，在显示装置中的准直收光角满足以下关系：tanθ＝D/H＝Cmin/2Hx，手指谷脊间距Cmin为0.3mm～0.45mm，透光孔311的周期P影响光学传感结构中各光学传感器PIN接收信号光的透过率，以及相邻透光孔311之间的光线串扰。OLED显示面板发出的最大光线角度为θ 0也代表着手指反射光的最大角度，P＝H/tanθ 0。
可选地，在本公开实施例提供的上述显示装置中，按照超薄折叠屏厚度的要求，OLED显示面板的厚度Hx取值范围可以为0.4mm-0.65mm，根据工艺制作能力及保证显示装置的轻薄型，θ的取值范围为20°～50°，θ 0为固定值70°，因此，第一透光孔311a’的孔径D1为2μm-10μm，透光孔311的周期P的取值范围受Hx的影响，因此，第一透光孔311a的周期为13μm-60μm，透明树脂层321的厚度H为5μm-30μm。
可选地，在本公开实施例提供的上述显示装置中，如图13和图14所示，纹路识别模组100中的准直结构3可以包括三层遮光层31和两层透光层32，具体包括在光学传感结构2之上依次层叠设置的第一遮光层31a、第一透明树脂层321a、第一透明无机绝缘层322a、第二遮光层31b、第二透明树脂层321b、第二透明无机绝缘层322b和第三遮光层31c；
第一遮光层31a包括阵列排布的第一透光孔311a，第二遮光层31b包括阵列排布的第二透光孔311b，第三遮光层31c包括阵列排布的第三透光孔311c。
具体地，三个遮光层31中的透光孔311的中心相互重合，且透光孔311的周期相同，具体尺寸范围受其上的OLED显示面板的厚度影响。
可选地，在本公开实施例提供的上述显示装置中，如图13至图15所示，第一透光孔311a的孔径D1可以大于或等于第三透光孔311c的孔径D3；第一透明树脂层321a的厚度H1可以大于第二透明树脂层321b的厚度H2，以便使第二遮光层31b更靠近三遮光层31c，增强降低相邻透光孔之间的光线串扰效果。
可选地，在本公开实施例提供的上述显示装置中，如图13所示，第二透光孔311b的孔径D2可以等于第一透光孔311a的孔径D1，或者，如图14所示，第二透光孔311b的孔径D2可以为第一透光孔311a的孔径D1的50％-80％，可以进一步削弱相邻透光孔之间的光线串扰。或者，如图15所示，第三透光孔311c、第二透光孔311b和第一透光孔311a的孔径可以呈依次增大的方式设置。
可选地，在本公开实施例提供的上述显示装置中，按照超薄折叠屏厚度的要求，OLED显示面板的厚度Hx取值范围可以为0.4mm-0.65mm，透光孔311的周期P的取值范围受Hx的影响，第一透光孔311a的周期为10μm-40μm，根据所需的准直收光角要求，第一透光孔311a的孔径可以为3μm-8μm，第一透明树脂层321a的厚度为10μm-15μm，第二透明树脂层321b的厚度为8μm-12μm。
具体地，在准直结构3采用三层遮光层31和两层透光层32时，在光学传感结构制程结束后，可以在其上方先制作一层平坦化层4，其材料为SiN或SiO2，厚度为800埃～8000埃，起到平坦化作用。然后在其上方制作黑色的第一遮光层31a，例如采用BM树脂材料制作厚度为500埃～16000埃的膜层，之后使用光刻或者纳米压印的方式制作透光孔311a，透光孔311a的孔径大小D1为3μm～8μm，相邻透光孔311a的周期即间距值P为10μm～40μm。然后在第一遮光层31a上方制作整面覆盖第一遮光层31a的第一透明树脂层321a，其厚度H1为10μm～15μm。接着制作第一透明无机绝缘层322a、然 后制作第二遮光层31b，其第二透光孔311b的孔径大小D2为3μm～8μm、然后制作第二透明树脂层321b，其厚度H2为8μm～12μm，然后，制作第二透明无机绝缘层322b和第三遮光层31c，其第三透光孔311c的孔径大小D3为3μm～8μm。具体地，P的具体取值可以选取18μm，H1的具体取值可以选取15μm，H2的具体取值可以选取10μm。D1＝D2＝D3，可以选取为4μm，或者，D1＝D3，可以选取为4μm，D2比D1的数值小20％～50％，可以选取为3μm～3.5μm。并且，本公开实施例提供的上述显示装置并不局限于两层或三层遮光层的结构，遮光层的层数还可以增加，比如可以为四层遮光层或更多层遮光层，在此不作详述。
例如，显示装置还包括用于提供电信号(包括扫描信号、数据信号、检测信号等)的信号线(包括栅线、数据线、检测线等)，例如，可以通过驱动电路控制发光器件的发光状态以实现子像素的点亮。例如，显示面板还具有封装层、触控层等功能层，这些功能层可以参考相关技术，在此不再赘述。
该显示装置可以为手机、平板电脑、显示器、笔记本电脑等任何具有纹路识别功能的产品或部件，本公开的实施例对此不作具体限定。
基于同一发明构思，本公开实施例还提供了上述纹路识别模组的制作方法，其中，纹路识别模组包括纹路识别区域和包围纹路识别区域的周边区域，周边区域包括绑定区域，制作方法包括：
提供一基底；
在基底之上且在纹路识别区域内形成呈阵列排布的光学传感结构；
在光学传感结构之上采用低温工艺形成准直结构，准直结构至少在纹路识别区域内且未覆盖绑定区域，准直结构包括至少两层层叠设置的遮光层和位于每相邻两层遮光层之间的透光层，各遮光层具有呈阵列排布的透光孔，各遮光层中的透光孔一一对应且在基底上的正投影至少部分重合。
具体地，在本公开实施例提供的上述制作方法中，仅需要在基底上制作完成光学传感结构后直接制作结构相对简单的至少两层遮光层和透光层即可达到较好的准直效果，且器件结构较轻薄，可以降低器件的加工工艺难度。 避免采用在纹路识别模组之上采用光学胶(OCA)贴合准直结构的方式带来的起泡等影响良率的问题。并且，由于在光学传感结构之上直接制作膜层形成准直结构，因此，可以采用阵列基板之上膜层制作通用的设备完成准直结构的制作，无需增加新的制作设备。
具体地，在本公开实施例提供的上述制作方法中，形成准直结构中的遮光层一般可以选用黑色树脂诸如BM等遮光能力较强的材料制作。各遮光层的工艺参数一般相同。具体地，遮光层在制作时一般在基底上整层涂布膜层，之后，使用光刻或者纳米压印的方式制作透光孔。
可选地，在公开实施例提供的上述制作方法中，形成准直结构中的透光层，具体包括：
采用喷墨打印方式，在遮光层上形成透明树脂层；
采用低温化学气相沉积方式，在透明树脂层上形成覆盖且大于透明树脂层的透明无机绝缘层。
具体地，透光层中的透明树脂层和透明无机绝缘层可以采用制作阵列基板中的薄膜封装结构的设备完成制作，即透明无机绝缘层可以使用制作无机薄膜封装层的化学气相沉积(CVD)设备制作，透明树脂层可以使用制作有机薄膜封装层的喷墨打印(IJP)设备制作。在遮光层制作完成后，可以先形成透明树脂层以保证透光层32整体所需要的厚度一般在微米量级，之后在透明树脂层上形成厚度较薄在纳米量级的透明无机绝缘层，各透明无机绝缘层的工艺参数和厚度一般相同。透明树脂层具体可以采用亚克力树脂材料制作，在其上直接涂布黑色树脂材料无法形成厚度较为均一膜层，会发生局部材料聚集等问题，因此，在透明树脂层之上增加透明无机绝缘层，可以保证在其上形成的遮光层成膜均匀性。
具体地，在本公开实施例提供的上述制作方法中，采用低温工艺形成准直结构。具体地，低温工艺所使用的温度约80℃左右。由于遮光层和透明树脂层制作时采用低温，因此，采用低温化学气相沉积方式形成透明无机绝缘层可以避免高温环境对下方的遮光层图案和透明树脂层造成损坏。
可选地，在公开实施例提供的上述制作方法中，在光学传感结构之上形成准直结构之前，还可以包括：
在光学传感结构之上形成降噪金属层，同时在绑定区域形成绑定电极；
在绑定电极和降噪金属层之上形成接地屏蔽层，接地屏蔽层与绑定电极互不交叠；
采用等离子体增强化学气相沉积方式，在接地屏蔽层之上形成平坦化层，平坦化层在基底上整面设置且仅在绑定区域具有镂空图案。
具体地，接地屏蔽层一般整面设置在纹路识别区域，起到屏蔽外界光学传感结构电磁干扰的作用，且为了保证透过率一般采用ITO制作。平坦化层完全覆盖接地屏蔽层，可以起到保护接地屏蔽层的作用，避免接地屏蔽层在后续化学气相沉积设备中制作准直结构的膜层时，暴露在富氢环境中被氢气置换出ITO中的铟离子，而导致接地屏蔽层雾化问题影响透过率。
并且，相对于绑定电极采用与接地屏蔽层同层的ITO制作，本公开中绑定电极采用与降噪金属层同时制作，即采用金属材料制作而不采用ITO制作绑定电极，即接地屏蔽层的图案与绑定电极的图案互不重合。避免采用ITO材料形成的绑定电极在后续化学气相沉积设备中制作准直结构的膜层时，绑定电极暴露在富氢环境后影响其电学性能。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (39)

  1. 一种纹路识别模组，包括纹路识别区域和设置在所述纹路识别区域的周边区域的绑定区域，其中，所述纹路识别模组包括：
    基底；
    光学传感结构，位于所述基底之上且在所述纹路识别区域内；
    准直结构，位于所述光学传感结构背离所述基底的一侧、至少在所述纹路识别区域内且未覆盖所述绑定区域，所述准直结构包括至少两层层叠设置的遮光层和位于每相邻两层遮光层之间的透光层，各所述遮光层具有呈阵列排布的透光孔，各所述遮光层中的透光孔一一对应且在所述基底上的正投影至少部分重合。
  2. 如权利要求1所述的纹路识别模组，其中，所述透光层包括透明树脂层和透明无机绝缘层；
    在相邻两层遮光层之间，所述透明树脂层与邻近所述基底一侧的遮光层邻接，所述透明无机绝缘层与远离所述基底一侧的遮光层邻接。
  3. 如权利要求2所述的纹路识别模组，其中，所述准直结构包括在所述光学传感结构之上依次层叠设置的第一遮光层、第一透明树脂层、第一透明无机绝缘层、第二遮光层、第二透明树脂层、第二透明无机绝缘层和第三遮光层；
    所述第一遮光层包括阵列排布的第一透光孔，所述第二遮光层包括阵列排布的第二透光孔，所述第三遮光层包括阵列排布的第三透光孔。
  4. 如权利要求3所述的纹路识别模组，其中，所述第一透光孔的孔径大于或等于所述第三透光孔的孔径。
  5. 如权利要求4所述的纹路识别模组，其中，所述第二透光孔的孔径等于第一透光孔的孔径。
  6. 如权利要求4所述的纹路识别模组，其中，述第二透光孔的孔径为所述第一透光孔的孔径的50％-80％。
  7. 如权利要求4所述的纹路识别模组，其中，所述第一透光孔、所述第二透光孔和所述第三透光孔的孔径依次递减。
  8. 如权利要求3所述的纹路识别模组，其中，所述第一透明树脂层的厚度大于所述第二透明树脂层的厚度。
  9. 如权利要求5所述的纹路识别模组，其中，所述第一透光孔的孔径为3μm-8μm，所述第一透光孔的周期为10μm-40μm，所述第一透明树脂层的厚度为10μm-15μm，所述第二透明树脂层的厚度为8μm-12μm。
  10. 如权利要求2所述的纹路识别模组，其中，所述准直结构包括在所述光学传感结构之上依次层叠设置的第一遮光层、透明树脂层、透明无机绝缘层和第二遮光层；
    所述第一遮光层包括阵列排布的第一透光孔，所述第二遮光层包括阵列排布的第二透光孔。
  11. 如权利要求10所述的纹路识别模组，其中，所述第一透光孔的孔径等于所述第二透光孔的孔径。
  12. 如权利要求11所述的纹路识别模组，其中，所述第一透光孔的孔径为2μm-10μm，所述第一透光孔的周期为13μm-60μm，透明树脂层的厚度为5μm-30μm。
  13. 如权利要求1-12任一项所述的纹路识别模组，其中，所述准直结构的准直收光角θ满足以下关系：tanθ＝D/H＝Cmin/2Hx，其中，D为透光孔的孔径，H为所述准直结构的高度，Cmin为手指谷脊间距，Hx为手指到所述准直结构的间距。
  14. 如权利要求1-12任一项所述的纹路识别模组，其中，各所述遮光层内一一对应的透光孔的中心在所述基底上的正投影重合，各所述遮光层内的透光孔的周期相同。
  15. 如权利要求1-12任一项所述的纹路识别模组，其中，所述光学传感结构包括呈阵列排布的多个光学传感器，一个所述光学传感器对应每层所述遮光层中的多个透光孔。
  16. 如权利要求1-15任一项所述的纹路识别模组，其中，所述光学传感结构包括依次层叠设置的栅极、栅绝缘层、有源层、源漏极层、第一绝缘层、第一电极、半导体层、第二电极、保护层、钝化层、第二绝缘层、偏置电压线、和阻隔层。
  17. 如权利要求16所述的纹路识别模组，其中，所述源漏极层在所述基底上的正投影完全覆盖且大于所述第一电极在所述基底上的正投影。
  18. 如权利要求16所述的纹路识别模组，其中，所述源漏极层直接与所述半导体层接触，所述源漏极层复用为所述第一电极。
  19. 如权利要求2-18任一项所述的纹路识别模组，其中，所述遮光层从所述纹路识别区域延伸至所述周边区域的邻接边缘；
    所述透明树脂层在所述基底上的正投影完全覆盖邻接的遮光层在所述基底上的正投影；
    所述透明无机绝缘层在所述基底上的正投影完全覆盖且大于邻接的所述透明树脂层在所述基底上的正投影。
  20. 如权利要求19所述的纹路识别模组，其中，所述准直结构还包括挡墙结构，所述挡墙结构围绕所述透明树脂层设置，且与所述透明树脂层邻接的遮光层同层相互独立设置。
  21. 如权利要求2-20任一项所述的纹路识别模组，其中，所述透明无机绝缘层的材料包括采用低温化学气相沉积方式形成的氮化硅或氮氧化硅。
  22. 如权利要求1-20任一项所述的纹路识别模组，其中，还包括：位于所述准直结构与所述光学传感结构之间的平坦化层，所述平坦化层整面设置且仅在所述绑定区域具有镂空图案。
  23. 如权利要求22所述的纹路识别模组，其中，所述平坦化层的材料包括氧化硅或氮化硅。
  24. 如权利要求22所述的纹路识别模组，其中，还包括：位于所述平坦化层和所述光学传感结构之间的接地屏蔽层；
    所述接地屏蔽层与所述平坦化层邻接，且所述接地屏蔽层的图案被所述 平坦化层的图案覆盖，所述接地屏蔽层在所述基底上的正投影覆盖所述光学传感结构。
  25. 如权利要求24所述的纹路识别模组，其中，所述接地屏蔽层的材料包括氧化铟锡。
  26. 如权利要求24所述的纹路识别模组，其中，还包括：位于所述接地屏蔽层与所述光学传感结构之间的降噪金属层；
    所述纹路识别区域分为感光区、间隔区和遮光区，所述间隔区位于所述感光区和所述遮光区之间；
    所述光学传感结构设置在所述感光区和所述遮光区内，在所述间隔区未设置图案；
    所述降噪金属层覆盖所述遮光区。
  27. 如权利要求26所述的纹路识别模组，其中，所述遮光区位于所述感光区的一侧或相对的两侧。
  28. 如权利要求26所述的纹路识别模组，其中，还包括：位于所述接地屏蔽层和所述降噪金属层之间的第三绝缘层；
    所述降噪金属层覆盖所述间隔区；在所述间隔区内，所述降噪金属层通过贯穿所述第三绝缘层的多个通孔与所述接地屏蔽层电连接。
  29. 如权利要求26所述的纹路识别模组，其中，还包括：位于所述绑定区域内的绑定电极，所述绑定电极与所述降噪金属层同层设置。
  30. 如权利要求29所述的纹路识别模组，其中，所述降噪金属层和所述绑定电极的材料包括钛/铝/钛。
  31. 如权利要求29所述的纹路识别模组，其中，所述绑定区域包括栅极驱动芯片绑定区域，位于所述栅极驱动芯片绑定区域内的绑定电极称为第一绑定电极；
    所述第一绑定电极与所述基底之间具有位于栅极所在膜层的第一连接电极，位于源漏极层的第二连接电极，位于第一电极所在膜层的第三连接电极，位于偏置电压线的第四连接电极；
    所述第一连接电极通过贯穿栅绝缘层的第一过孔与第二连接电极电连接，所述第二连接电极通过贯穿第一绝缘层的第二过孔与所述第三连接电极电连接，所述第三连接电极通过贯穿第二绝缘层的第三过孔与所述第四连接电极电连接，所述第四连接电极通过贯穿第三绝缘层的第四过孔与所述第一绑定电极电连接；所述第一连接电极通过栅线和栅线扇出走线与栅极电连接。
  32. 如权利要求31所述的纹路识别模组，其中，一个所述第一绑定电极对应的所述第一过孔、所述第二过孔和所述第三过孔的数量均为至少两个，所述第一过孔、所述第二过孔和所述第三过孔在基底上的正投影均互不重叠且沿所述第一绑定电极的延伸方向交替排列，一个所述第一绑定电极对应一个所述第四过孔，所述第四过孔在所述基底上的正投影同时覆盖所述第一过孔、所述第二过孔和所述第三过孔。
  33. 如权利要求32所述的纹路识别模组，其中，所述绑定区域还包括数据驱动芯片绑定区域，位于所述数据驱动芯片绑定区域内的绑定电极称为第二绑定电极和第三绑定电极；
    所述第二绑定电极与所述基底之间具有位于所述源漏极层的第五连接电极，位于所述第一电极所在膜层的第六连接电极，位于所述偏置电压线的第七连接电极；所述第七连接电极通过数据线和数据线扇出走线与所述源漏极层电连接；
    所述第三绑定电极位于所述数据驱动芯片绑定区域的一侧边缘，所述第三绑定电极与所述基底之间具有位于所述偏置电压线的第八连接电极；所述第八连接电极通过偏置电压扇出走线与所述偏置电压线电连接。
  34. 一种显示装置，其中，包括如权利要求1-33任一项所述的纹路识别模组，以及位于所述纹路识别模组之上的显示面板，所述显示面板与所述纹路识别模组之间通过光学胶固定。
  35. 如权利要求34所述的显示装置，其中，所述显示面板为OLED显示面板；
    所述OLED显示面板包括依次层叠设置的柔性OLED显示背板、偏光片 和保护盖板，所述保护盖板的材料包括聚酰亚胺。
  36. 如权利要求35所述的显示装置，其中，所述OLED显示面板的厚度取值范围为0.4mm-0.65mm。
  37. 一种纹路识别模组的制作方法，所述纹路识别模组包括纹路识别区域和包围纹路识别区域的周边区域，所述周边区域包括绑定区域，其中，所述制作方法包括：
    提供一基底；
    在所述基底之上且在所述纹路识别区域内形成呈阵列排布的光学传感结构；
    在所述光学传感结构之上采用低温工艺形成准直结构，所述准直结构至少在所述纹路识别区域内且未覆盖所述绑定区域，所述准直结构包括至少两层层叠设置的遮光层和位于每相邻两层遮光层之间的透光层，各所述遮光层具有呈阵列排布的透光孔，各所述遮光层中的透光孔一一对应且在所述基底上的正投影至少部分重合。
  38. 如权利要求37所述的制作方法，其中，在所述光学传感结构之上形成所述准直结构之前，还包括：
    在所述光学传感结构之上形成降噪金属层，同时在所述绑定区域形成绑定电极；
    在所述绑定电极和所述降噪金属层之上形成接地屏蔽层，所述接地屏蔽层与所述绑定电极互不交叠；
    采用等离子体增强化学气相沉积方式，在所述接地屏蔽层之上形成平坦化层，所述平坦化层在所述基底上整面设置且仅在所述绑定区域具有镂空图案。
  39. 如权利要求37所述的制作方法，其中，形成所述准直结构中的透光层，具体包括：
    采用喷墨打印方式，在所述遮光层上形成透明树脂层；
    采用低温化学气相沉积方式，在所述透明树脂层上形成覆盖且大于所述 透明树脂层的透明无机绝缘层。
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