WO2022057735A1

WO2022057735A1 - Method for increasing precision of flat edge of semiconductor wafer, and laser chip

Info

Publication number: WO2022057735A1
Application number: PCT/CN2021/117639
Authority: WO
Inventors: 艾佳瑞; 丁新琪; 郑兆祯; 王菊; 廖桂波; 焦旺; 吴阳烽
Original assignee: 深圳市中光工业技术研究院
Priority date: 2020-09-17
Filing date: 2021-09-10
Publication date: 2022-03-24
Also published as: CN114204401A

Abstract

Disclosed in the present application are a method for increasing the precision of a flat edge of a semiconductor wafer, and a laser chip. The method comprises: cleaving an obtained epitaxial wafer to obtain at least one cleavage edge; measuring the angle between each cleavage edge and a corresponding lithographic line on the epitaxial wafer to obtain a deflection angle; repeating the described steps a plurality of times to obtain a plurality of deflection angles; and using the plurality of deflection angles to calculate a compensation angle and cleaving another epitaxial wafer according to the compensation angle so that a cleavage edge corresponding to the other epitaxial wafer is parallel to a flat edge and/or lithographic line corresponding to another epitaxial wafer. By means of the described method, the present application can improve the yield of a laser chip.

Description

A method for improving the precision of flat edge of semiconductor wafer and laser chip

technical field

The present application relates to the technical field of semiconductors, and in particular to a method for improving the precision of a flat edge of a semiconductor wafer and a laser chip.

Background technique

A semiconductor laser is a miniaturized laser with a PN junction or PIN junction composed of a direct bandgap semiconductor material as the working material. Taking a GaAs laser chip as an example, the fabrication process of a GaAs laser chip can be shown in Figure 1. As shown, the design requirement of GaAs laser chip is that the resonant cavity surface of the chip is formed by cleavage along the cleavage side of the wafer. Therefore, when the GaAs wafer is subjected to the first step of lithography, the lithography pattern and The flat edge characterizing the direction of the cleavage edge is aligned; however, errors inevitably occur in the process of making the reference plane, single crystal orientation and single crystal cutting, which leads to the difference between the flat edge of the epitaxial wafer and the actual crystal orientation. There is a certain difference, there is a corresponding deviation between the two, resulting in a deviation in the dissociation according to the lithography line corresponding to the flat edge, which affects the yield of the laser chip, so it is necessary to improve the flat edge accuracy of the semiconductor wafer .

SUMMARY OF THE INVENTION

The present application provides a method for improving the precision of a flat edge of a semiconductor wafer and a laser chip, which can improve the yield of the laser chip.

In order to solve the above technical problems, the technical solution adopted in the present application is to provide a method for improving the accuracy of the flat edge of a semiconductor wafer, the method comprising: cleaving the obtained epitaxial wafer to obtain at least one cleavage edge; measuring each cleavage edge; The angle between each cleavage edge and the corresponding lithography line on the epitaxial wafer is obtained to obtain the deflection angle; the above steps are performed multiple times to obtain multiple deflection angles; the compensation angle is calculated by using the plurality of deflection angles, and other epitaxial wafers are calculated according to the compensation angle. Cleavage is performed so that the cleavage edges corresponding to the other epitaxial wafers are parallel to the flat edges and/or lithography lines corresponding to the other epitaxial wafers.

In order to solve the above-mentioned technical problem, another technical solution adopted in the present application is to provide a kind of laser chip, and this laser chip is the laser chip that adopts the above-mentioned method for improving the precision of the flat edge of the semiconductor wafer to make.

Through the above solution, the beneficial effects of the present application are: performing a cleavage process on the epitaxial wafer to obtain a plurality of cleavage sides; measuring the angle between each cleavage side and the corresponding lithography line to obtain the deflection angle; By processing multiple epitaxial wafers, multiple deflection angles can be obtained, and then the compensation angle can be calculated by using the multiple deflection angles; when other epitaxial wafers are operated, other epitaxial wafers are artificially cleaved according to the compensation angle. Making the cleavage edge of the other epitaxial wafer parallel to the flat edge and/or lithography line of the other epitaxial wafer can eliminate the deviation between the two, and can effectively improve the performance and yield of the laser chip, and is simple and easy to implement, Low implementation cost.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without creative effort. in:

Figure 1 is the manufacturing process of GaAs laser chip;

2 is a schematic flowchart of an embodiment of a method for improving the flat edge accuracy of a semiconductor wafer provided by the present application;

3 is a schematic structural diagram of an epitaxial wafer in the embodiment shown in FIG. 2;

4 is a schematic flowchart of another embodiment of the method for improving the flat edge accuracy of a semiconductor wafer provided by the present application;

5 is a schematic structural diagram of photolithography in the embodiment shown in FIG. 4;

Fig. 6 is the structural representation of deflection angle in the embodiment shown in Fig. 4;

7(a) is a schematic structural diagram of the flat sides of other epitaxial wafers in the embodiment shown in FIG. 4;

Figure 7(b) is a schematic structural diagram of compensating the flat side of 7(a);

Fig. 7(c) is another structural schematic diagram of compensating the flat side of 7(a);

FIG. 8 is a schematic structural diagram of an embodiment of a laser chip provided by the present application.

detailed description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

At present, although some solutions can compensate the deflection angle between the flat edge and the cleavage edge, for purchased epitaxial wafers, it cannot be guaranteed that each batch of epitaxial wafers is grown from the same batch of substrates , which inevitably leads to the difference between the epitaxial wafers, making the compensation scheme unfeasible, and the scheme of the present application can obtain the difference between the cleavage edge and the flat edge of each epitaxial wafer by cleaving and measuring the epitaxial wafer. The deflection angle is adjusted accordingly, the applicability is more extensive, and it is simple and easy to implement.

Please refer to FIG. 2. FIG. 2 is a schematic flowchart of an embodiment of a method for improving the flat edge accuracy of a semiconductor wafer provided by the present application. The method includes:

Step 21: Cleavage the obtained epitaxial wafer to obtain at least one cleavage edge.

A piece of epitaxial wafer can be randomly selected as an epitaxial wafer from the epitaxial wafers that have been produced, and these epitaxial wafers can be grown from the same batch of substrates or from different batches of substrates; or can be produced in sequence The selection is made at a certain interval, or the epitaxial wafer can also be selected in other reasonable ways; after the epitaxial wafer is selected, the epitaxial wafer can be cleaved to obtain at least one cleaved edge.

Step 22: Measure the angle between each cleavage edge and the corresponding lithography line on the epitaxial wafer to obtain the deflection angle.

After the cleavage operation is performed, the angle between the cleavage edge corresponding to each laser chip and the lithography line on the epitaxial wafer, that is, the deflection angle, can be measured; specifically, each epitaxial wafer can be dissociated once to obtain a deflection At this time, the deflection angle is the deflection angle corresponding to the epitaxial wafer; or each epitaxial wafer can be dissociated multiple times, and each cleavage corresponds to a deflection angle, so as to obtain multiple deflection angles, which can be divided into multiple The average value of the deflection angle (that is, the average deflection angle) is used as the deflection angle corresponding to the epitaxial wafer; since the lithography line is parallel to the flat edge of the epitaxial wafer, the deflection angle is the angle formed by the flat edge of the epitaxial wafer and the cleavage edge; For example, as shown in FIG. 3, the flat side of the epitaxial wafer 30 is denoted as 31, the laser chip is located in the shaded part 32 in the figure, and the blank area above the flat side 31 can be mirror-cleaved to obtain the laser chip.

Step 23: Perform the above steps multiple times to obtain multiple deflection angles.

Obtain different epitaxial wafers. For each epitaxial wafer, the processing from step 21 to step 22 can be performed to measure the deflection angle; for multiple epitaxial wafers, each epitaxial wafer corresponds to a deflection angle or an average deflection angle. After multiple measurements, multiple deflection angles can be obtained; further, the specific number of epitaxial wafers can be set according to specific application scenarios, for example, can be set to 5 times, 10 times or 20 times.

Step 24 : calculating the compensation angle by using the multiple deflection angles, and cleaving other epitaxial wafers according to the compensation angle, so that the cleavage edges corresponding to the other epitaxial wafers are parallel to the flat edges and/or lithography lines corresponding to the other epitaxial wafers.

After obtaining multiple deflection angles, the compensation angle can be calculated according to the distribution law of deflection angles, which is the angle for compensating the current flat edge; the flat edge or lithography line can be compensated; the flat edge can be compensated directly; Angle compensation is performed on the edge, and the position of the flat edge is adjusted. When etching the lithography line, the lithography line is parallel to the flat edge; or the flat edge may not be processed. On the basis that the flat edges are parallel, angle compensation is performed on the lithography line, that is, the angle compensation is placed in the scribing process, which can save the operation of adjusting the flat edges.

For example, if the angle between the current flat edge and the horizontal rightward direction is 0°, and the calculated compensation angle is 0.15°, then adjust the position of the flat edge so that the angle between it and the horizontal rightward direction changes. 0.15°, or compensate the lithography line on the basis that the lithography line is parallel to the flat edge, so that the angle between the lithography line and the horizontal right direction becomes 0.15°; due to the compensation for the flat edge , Scribe on the basis of the flat edge after compensation, so that the flat edge after compensation is parallel to the cleavage edge, at this time, the lithography line is parallel to the lattice direction, and the cleavage edge is parallel to the lithography line. Cleavage is performed at the location where there is no angular deviation, which improves the yield of cleavage.

This embodiment provides a method for improving the accuracy of the flat edge of a semiconductor wafer. The mirror cleavage process is manually performed on the opposite position of the flat edge of the epitaxial wafer to obtain the cleavage edge, and then the distance between the cleavage edge and the lithography line is measured. When working on other epitaxial wafers, artificially compensate the deflection angle between the flat edge/lithography line and the cleavage edge of the epitaxial wafer, eliminating the difference between the flat edge/lithography line and the cleavage edge of the epitaxial wafer. The deflection angle between the two is not controllable, which effectively improves the performance and yield of the laser chip, and is simple and easy to implement, and the implementation cost is low.

Please refer to FIG. 4. FIG. 4 is a schematic flowchart of another embodiment of the method for improving the flat edge accuracy of a semiconductor wafer provided by the present application, and the method includes:

Step 41 : Obtain a piece of epitaxial wafer as an epitaxial wafer from a plurality of epitaxial wafers corresponding to the same batch of substrates.

In order to compensate for the deviation between the flat edge and the cleavage edge, a preset number of epitaxial wafers may be selected from multiple epitaxial wafers corresponding to the same batch of substrates as epitaxial wafers.

Step 42: Perform photolithography on the epitaxial wafer with the flat edge as a reference to obtain at least one photolithography line.

The flat edge of the epitaxial wafer is aligned with the reference, and the epitaxial wafer is etched to obtain multiple parallel lithography lines, that is, the lithography pattern is a series of straight lines parallel to the flat edge; for example, as shown in FIG. A plurality of lithographic lines 52 can be obtained by performing photolithography on the flat side 51 of the wafer.

Step 43: Cleavage the obtained epitaxial wafer to obtain at least one cleavage edge.

After the lithography lines are etched on the epitaxial wafer, the epitaxial wafer can be cleaved and split according to the lithography lines obtained by lithography, thereby obtaining a plurality of laser chips.

It should be noted that the actual cleavage position represents the atomic lattice direction inside the epitaxial wafer, and the resonant cavity of the laser chip obtained by splitting in this direction has a better effect, that is, the actual cleavage is not performed according to the lithography line. Cleavage, the resulting cleavage edges may deviate from the lithographic lines.

Step 44: Measure the angle between each cleavage edge and the corresponding lithography line on the epitaxial wafer to obtain the deflection angle.

The deflection angle includes an upper deflection angle and a lower deflection angle, the angle formed by the upper deflection angle corresponding to the cleavage side and the flat side is an acute angle, and the angle formed by the lower deflection angle corresponding to the cleavage side and the flat side is an obtuse angle; The region is manually cleaved to obtain a cleavage plane. At this time, cleavage planes in two directions may be obtained due to the difference of the substrate itself. As shown in FIG. The angle between the directions is an acute angle, denoted as α, or the angle between the cleavage side 61b and the horizontal rightward direction is an obtuse angle, denoted as β; further, the XYθ precision alignment platform can be used to measure the deflection angle , the photoresist can be washed off after measuring the angle.

Step 45: Perform the above steps for multiple times to obtain multiple deflection angles.

Wherein, step 45 is similar to step 23 in the foregoing embodiment, and details are not repeated here.

Step 46: Calculate statistical information corresponding to a plurality of compensation angles, and determine whether the statistical information meets a preset condition.

After a plurality of deflection angles are measured, statistics and calculations can be performed on the plurality of deflection angles to obtain statistical information, and then the statistical information is used to calculate the compensation angle to determine whether the compensation according to the compensation angle can meet the requirements; further, pre- It is assumed that the condition matches the specific content of the statistical information. For example, if the statistical information is variance, the preset condition may be that the calculated variance is smaller than the preset variance.

In a specific embodiment, the statistical information is variance, and the variance of a continuous preset number of deflection angles can be calculated to determine whether the variance of the continuous preset number of deflection angles is less than the preset variance; If the variance is less than the preset variance, it indicates that the current statistical information meets the preset conditions, and the last deflection angle can be used as the compensation angle; specifically, the preset number is less than or equal to the number of multiple deflection angles, and the preset variance can be It is the variance preset according to experience; for example, the preset variance is 0.01, the preset number is 5, the number of deflection angles measured so far is 7, and the third deflection angle to the seventh deflection angle corresponds to If the variance is less than 0.01, it can be considered that the change of the deflection angle is basically stable, and the seventh deflection angle can be used as the compensation angle.

It can be understood that the compensation angle can also be determined by calculating the standard deviation or the difference, for example, calculating the angle difference between the current deflection angle and the previous deflection angle, and if the difference is smaller than the preset difference, it is determined that the pre-defined angle is met. Set the condition and use the current deflection angle as the compensation angle.

In another specific embodiment, the statistical information is an average value, the average value of multiple deflection angles can be calculated, and then it is determined whether the average value of the plurality of deflection angles is smaller than the first preset average value; If the value is smaller than the first preset average value, it indicates that the current statistical information meets the preset condition, and in this case, the average value of the multiple deflection angles can be used as the compensation angle.

In another specific embodiment, the statistical information is an average value, and the epitaxial wafer can be cleaved multiple times to obtain multiple cleavage edges, wherein each cleavage edge corresponds to a deflection angle; The average value of the deflection angles is obtained to obtain the average deflection angle; it is judged whether the average value of the average deflection angles corresponding to the plurality of epitaxial wafers is smaller than the second preset average value; if the average value of the average deflection angles is smaller than the second preset average value, then Indicates that the current statistical information complies with the preset conditions, and at this time, the average value of the average deflection angle can be used as the compensation angle.

It can be understood that when the statistical information does not meet the preset conditions, the measurement can be continued, and the cleavage of the obtained epitaxial wafer can be performed back, that is, step 43 or step 45 is performed.

Step 47: Calculate the compensation angle by using the multiple deflection angles, and cleavage the other epitaxial wafers according to the compensation angle, so that the cleavage edges corresponding to the other epitaxial wafers are parallel to the flat edges and/or lithography lines corresponding to the other epitaxial wafers.

In the lithography alignment of the subsequent epitaxial wafer, the angle of the flat edge/lithography line can be manually compensated according to the compensation angle. Direction rotation compensation angle; when the type of deflection angle is the lower deflection angle, rotate the flat edge/lithography line in the clockwise direction to compensate the angle, that is, if it is an upper deflection angle, perform counterclockwise positioning compensation, if it is a lower deflection angle Just perform clockwise bit compensation, so as to complete the calibration compensation for the flat edges/lithographic lines of other epitaxial wafers by using the compensation angle.

For example, taking the flat edge compensation as an example, before the alignment compensation is performed, the flat edge 71a of the epitaxial wafer 70 is shown in Fig. 7(a); when the type of deflection angle is the upper deflection angle, as shown in Fig. 7(b) As shown, the flat side 71a is rotated by an angle θ relative to the flat side 71b counterclockwise; when the type of deflection angle is the lower deflection angle, as shown in FIG. 7(c), the flat side 71a is rotated by an angle θ relative to the flat side 71c clockwise .

In this embodiment, a pattern parallel to the flat edge is first formed on the epitaxial wafer through a photolithography process, and then cleaved according to the lithography pattern to obtain at least one cleavage edge; by measuring the angle between each cleavage edge and the flat edge , to obtain the deflection angle; by cleaving multiple epitaxial wafers, multiple deflection angles can be obtained; when the fluctuation of successive deflection angles is small, the last deflection angle can be used as the compensation angle; or the average of multiple deflection angles When the value meets the requirements, the average value is used as the compensation angle; then other epitaxial wafers are manually compensated according to the type of compensation angle, and the position of the flat edge/lithography line of these epitaxial wafers is adjusted to realize the lattice direction and cleavage. The alignment of the edge can improve the accuracy of the flat edge and improve the yield of the laser chip.

Please refer to FIG. 8 . FIG. 8 is a schematic structural diagram of an embodiment of a laser chip provided by the present application. The laser chip 80 is a laser chip fabricated by using the method for improving the precision of the flat edge of a semiconductor wafer in the above embodiment.

The above descriptions are only the embodiments of the present application, and are not intended to limit the scope of the patent of the present application. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present application, or directly or indirectly applied to other related technologies Fields are similarly included within the scope of patent protection of this application.

Claims

A method for improving the precision of the flat edge of a semiconductor wafer, comprising:

Cleavage the obtained epitaxial wafer to obtain at least one cleavage edge;

measuring the angle between each of the cleavage edges and the corresponding lithography line on the epitaxial wafer to obtain a deflection angle;

Perform the above steps multiple times to obtain multiple deflection angles;

Compensation angles are calculated by using the plurality of deflection angles, and other epitaxial wafers are cleaved according to the compensation angles, so that the cleavage edges corresponding to the other epitaxial wafers are the flat edges and/or the corresponding flat edges of the other epitaxial wafers. The lithographic lines are parallel.
The method for improving the precision of the flat edge of a semiconductor wafer according to claim 1, wherein the compensation angle is calculated by using the plurality of deflection angles, and the flat edge of the other epitaxial wafer is calculated according to the compensation angle. Before proceeding with the steps of cleavage, including:

Calculate the statistical information corresponding to the plurality of compensation angles, and determine whether the statistical information meets a preset condition.
The method for improving the flat edge accuracy of a semiconductor wafer according to claim 2, wherein the statistical information is variance, and the method further comprises:

Calculate the variance of a continuous preset number of the deflection angles, and determine whether the variance is less than a preset variance;

If so, take the last deflection angle as the compensation angle;

Wherein, the preset number is less than or equal to the number of the plurality of deflection angles.
The method for improving the flat edge accuracy of a semiconductor wafer according to claim 2, wherein the statistical information is an average value, and the method further comprises:

calculating an average value of the plurality of deflection angles, and judging whether the average value is less than a first preset average value;

If so, take the average value as the compensation angle.
The method for improving the flat edge accuracy of a semiconductor wafer according to claim 2, wherein the statistical information is an average value, and the method further comprises:

The epitaxial wafer is cleaved multiple times to obtain a plurality of the cleaved edges, wherein each of the cleaved edges corresponds to one of the deflection angles;

calculating the average value of a plurality of deflection angles corresponding to the epitaxial wafer to obtain the average deflection angle;

judging whether the average value of the average deflection angles corresponding to the plurality of epitaxial wafers is less than the second preset average value;

If so, take the average value of the average deflection angles as the compensation angle.
The method for improving the precision of the flat edge of a semiconductor wafer according to claim 2, wherein the method further comprises:

When the statistical information does not meet the preset condition, returning to the step of cleaving the acquired epitaxial wafer.
The method for improving the precision of the flat edge of a semiconductor wafer according to claim 1, wherein,

The deflection angle includes an upper deflection angle and a lower deflection angle, the upper deflection angle corresponding to the angle formed by the cleavage side and the flat side is an acute angle, and the lower deflection angle corresponds to the cleavage side and the flat side. The angle formed by the sides is an obtuse angle.
The method for improving the accuracy of the flat edge of a semiconductor wafer according to claim 7, wherein the step of cleaving other epitaxial wafers according to the compensation angle comprises:

When the type of the deflection angle is the upper deflection angle, rotating the flat side by the compensation angle in a counterclockwise direction;

When the type of the deflection angle is the lower deflection angle, the flat side is rotated by the compensation angle in a clockwise direction.
The method for improving the accuracy of a flat edge of a semiconductor wafer according to claim 1, wherein before the step of cleaving the obtained epitaxial wafer to obtain at least one cleavage edge, the method comprises:

One piece of epitaxial wafer is obtained from multiple epitaxial wafers corresponding to the same batch of substrates as the epitaxial wafer.
The method for improving the precision of a flat edge of a semiconductor wafer according to claim 1, wherein before the step of cleaving the obtained epitaxial wafer to obtain at least one cleavage edge, the method further comprises:

Photolithography is performed on the epitaxial wafer based on the flat edge to obtain at least one lithography line.
A laser chip, characterized in that the laser chip is a laser chip produced by the method for improving the precision of the flat edge of a semiconductor wafer according to any one of claims 1-10.