CN103681250A - Method for controlling CD (Critical Dimension) of double etching formed graphs - Google Patents
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
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- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
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- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
- G03F1/80—Etching
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- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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Abstract
The invention discloses a method for controlling the CD (Critical Dimension) of double etching formed graphs. The method comprises the following steps: (1) growing a film layer on a silicon slice; (2) photoetching a first graph layer, and measuring the CD and overlay; (3) etching the first graph layer; (4) photoetching a second graph layer, and measuring the CD and overlay; (5) etching the second graph layer, and forming graphs with symmetrical-structures; (6) measuring the CDs of the graphs with the symmetrical-structures; (7) converting the difference of the CDs of the symmetrical graphs into the overlay of the second graph layer; (8) feeding back the converted overlay of the second graph layer to a photoetching machine so as to correct the overlay of the second graph layers of the next batch of silicon slices, and finally realizing the control over the CDs after the symmetrical graphs are etched. Meanwhile, the method solves the problem that the CD of the symmetrical graphs after etching is inconsistent as the photoetching overlay is not good and the etching rates are different.
Description
Technical field
The invention belongs to semiconductor integrated circuit manufacturing process, relate to a kind of control method of critical size, relate in particular to a kind of control method of critical size of twice etching moulding figure.
Background technology
Critical size (CD:Critical Dimension) and alignment precision (overlay) are very important two on-line monitoring parameters in integrated circuit technology, wherein CD is for monitoring photoetching and the etching size of figure later, in actual production process, all generally to use CDSEM (critical size scanning electron microscopy) to measure the CD of monitoring pattern, when monitored figure CD surpasses desired specification, energy during generally by adjusting photolithographic exposure regulates the CD of monitoring pattern, makes it to meet desired specification.And overlay is for monitoring aligning (or alignment) situation when layer pattern and front layer pattern, in actual production process, the center offset that generally measures custom-designed upper and lower two-layer overlay mark (Overlay Mark) by optical means is monitored overlay, when overlay surpasses desired specification, the method that generally the alignment parameter when to current layer photolithographic exposure compensates, regulate the photoetching overlay of figure afterwards, make it to meet desired specification.
For some special semiconductor device, the figure that need to prepare symmetrical structure, and according to process requirements, the figure of this symmetrical structure need form by twice etching, schematic diagram after the semiconductor device part technique with symmetrical structure as shown in Figure 1 completes, require the polysilicon 401 on the left side and the polysilicon 402 on the right to there is identical CD, because second implanted layer 602 on second implanted layer 601 on the left side and the right is to using respectively the polysilicon 401 on the left side and the polysilicon 402 on the right as one of barrier layer and inject and form, so if the CD of the polysilicon 401 on the left side and the polysilicon 402 on the right is inconsistent, the position that will make second implanted layer 601 on the left side and second implanted layer 602 on the right form is also asymmetric, and cause the channel length L1 on the left side different with the channel length L2 on the right, the final performance that affects product.
In order to form symmetrical structure device as shown in Figure 1, generally by following steps, complete: (1) is silicon dioxide thin film growth layer 300 and layer polysilicon film (not shown complete layer polysilicon film only illustrates the polysilicon 401 on the later left side of etching and the polysilicon 402 on the right) on the silicon chip that completes raceway groove 200 techniques; The photoetching of (2) first graph layers, the measurement of CD and overlay; Polysilicon membrane etching, the injection of (3) first graph layers, form the first implanted layer 500; (4) photoetching of second graph layer, the measurement of CD and overlay, and by the measurement feedback of overlay to the mask aligner of second graph layer, the overlay of the second graph layer of the overlay correcting system correction next batch silicon chip by mask aligner; (5) the polysilicon membrane etching of second graph layer, forms containing the left side polysilicon 401 of symmetrical structure and the figure of the right polysilicon 402; (6) the 3rd graph layer photoetching, and then using the polysilicon 401 on photoetching offset plate figure and the left side and the polysilicon 402 on the right simultaneously and carry out injection technology as implant blocking layer, after annealing, form respectively second implanted layer 601 on the left side and second implanted layer 602 on the right.From above-mentioned steps, there are two factors to affect the CD of the polysilicon 401 on the left side and the polysilicon 402 on the right, the one, the alignment precision of second graph layer to the first graph layer in step (4), the 2nd, the homogeneity of etch rate in step (5).For first factor, in step (4), by the overlay correcting system of mask aligner, revise, but for second factor, above-mentioned technological process is not considered, but in actual production process, due to the impact (pattern density is different) of periphery figure and the restriction of the process conditions of etching own, can make to form in the polysilicon 401 on the left side and polysilicon 402 processes on the right in etching, both etch rates are different, thereby cause the CD of the polysilicon 401 on the left side and the polysilicon 402 on the right different.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of control method of critical size of twice etching moulding figure, can solve because the inconsistent problem of symmetric figure CD after the not good etching causing of photoetching alignment precision, can solve again because the inconsistent problem of symmetric figure CD after the etching that causes of etch rate difference.
For solving the problems of the technologies described above, the invention provides a kind of control method of critical size of twice etching moulding figure, comprise that step is as follows:
(1) growing film layer on silicon chip;
The photoetching of (2) first graph layers, the measurement of critical size and alignment precision;
The etching of (3) first graph layers, photoresist is removed;
(4) photoetching of second graph layer, the measurement of critical size and alignment precision;
(5) etching of second graph layer, the figure of formation symmetrical structure;
(6) measurement of the critical size of symmetrical structure figure;
(7) the critical size difference of above-mentioned symmetric figure is converted to the alignment precision of second graph layer;
(8) alignment precision of the second graph layer after above-mentioned conversion is fed back to the mask aligner of second graph layer, the alignment precision of the second graph layer of the alignment precision correcting system correction next batch silicon chip by mask aligner, thus realize the control to the critical size of above-mentioned symmetric figure.
In step (1), described silicon chip is mating plate, or has completed the silicon chip of some semiconductor common technologies.Preferably, described silicon chip is the silicon chip that has completed conducting groove manufacturing process.
In step (1), described thin layer is one or more in silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, metal silicide, metallic aluminium one or more layers thin layers of combining.Preferably, described thin layer is comprised of silica membrane layer and layer polysilicon film.
In step (3) and (5), described etching can formed one or more layers thin layer of etch step (1).Described etching is the conventional polysilicon dry etching of industry, contains the plasma dry etching of chlorine, hydrogen bromide and oxygen mixed gas.
Preferably, in step (3), after the etching of the first graph layer, according to process requirements, can increase by a step injection technology.
Preferably, in step (1), described thin layer is comprised of silica membrane layer and layer polysilicon film, i.e. first silicon dioxide thin film growth layer, layer polysilicon film successively on silicon chip; In step (3) and (5), described etching can etch step (1) layer polysilicon film that forms, but can not etch step (1) the silica membrane layer that forms; The layer polysilicon film that described injection technology is usingd after the first graph layer etching, as implant blocking layer, forms the first implanted layer after annealing.
In step (4), the photoetching of described second graph layer, is to take formed the first graph layer of step (3) as aiming at layer, and the figure of the photoresist forming after photoetching is for subsequent step (5) barrier layer of etching for the second time.
In step (6), the measurement of the critical size of described symmetrical structure figure, refers to the critical size of measuring respectively directions X and two groups of symmetric figures of Y-direction.Described measurement, must select at least 5 exposing units in silicon chip to measure, wherein must there be 4 above exposing units to be positioned at the peripheral position of silicon chip, and in each exposing unit, must measure and lay respectively at the described directions X at 4 angles of exposing unit and the critical size of two groups of symmetric figures of Y-direction.
In step (7), the alignment precision of described second graph layer, comprise following parameter: directions X side-play amount, Y-direction side-play amount, directions X silicon chip scaling, Y-direction silicon chip scaling, silicon slice rotating angle, silicon chip orthogonality, directions X exposing unit scaling, Y-direction exposing unit scaling, the exposing unit anglec of rotation, exposing unit orthogonality, wherein directions X side-play amount and Y-direction side-play amount are used following formula to calculate:
Difference/2 of directions X side-play amount=directions X symmetrical structure graphics critical dimension
Difference/2 of Y-direction side-play amount=Y-direction symmetrical structure graphics critical dimension
Obtain after above-mentioned directions X side-play amount and Y-direction side-play amount, re-use the formula that industry is general and can calculate other alignment precision parameters.
Preferably, in step (8), increase afterwards following steps: the 3rd graph layer photoetching, and then the layer polysilicon film of simultaneously usining after photoetching offset plate figure and second graph layer etching carries out injection technology as implant blocking layer, after annealing, form the second implanted layer.
Compare with existing method, the present invention moves to after etching by the revisal step of overlay from photoetching, and convert out real overlay parameter by the otherness of the CD after etching, and using the revisal reference value of this overlay parameter as mask aligner, both solved because the inconsistent problem of symmetric figure CD after the photoetching alignment precision not good etching causing, solved again because the inconsistent problem of symmetric figure CD after the etching that etch rate difference causes.
Accompanying drawing explanation
Fig. 1 is the schematic diagram after the semiconductor device part technique with symmetrical structure completes;
Fig. 2 is the control method flow chart of the critical size of twice etching moulding figure of the present invention;
Fig. 3 (A)-Fig. 3 (G) is the schematic diagram after each step of the inventive method completes; Wherein, Fig. 3 (A) is the schematic diagram after the step (1) of the inventive method completes; Fig. 3 (B) is the schematic diagram after the step (2) of the inventive method completes; Fig. 3 (C) is the schematic diagram after the step (3) of the inventive method completes; Fig. 3 (D) is the schematic diagram after the step (4) of the inventive method completes; Fig. 3 (E) is the schematic diagram after the step (5) of the inventive method completes, Fig. 3 (F) is the middle example schematic that measures figure position in silicon chip of the step (6) of the inventive method, and Fig. 3 (G) is the middle example schematic that measures figure position in exposing unit of the step (6) of the inventive method.
In figure, description of reference numerals is as follows:
100-silicon chip, 200-conducting groove, 300-silica membrane layer, 400-layer polysilicon film, the polysilicon on the left side after 401a-the first graph layer etching, the polysilicon on the left side after 401-second graph layer etching, the polysilicon on the right after 402a-the first graph layer etching, the polysilicon on the right after 402-second graph layer etching, 500-the first implanted layer, the 601-left side the second implanted layer, 602-the right the second implanted layer, photoresist after 700-the first graph layer photoetching, the photoresist after 800-second graph layer photoetching.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further detailed explanation.
Embodiment mono-
The control method of the critical size of a kind of twice etching moulding figure of the present invention, its method flow as shown in Figure 2, compare with existing method, it is characterized in that the revisal step of overlay from photoetching, to move to after etching, and convert out real overlay parameter by the otherness of the CD after etching, and using the revisal reference value of this overlay parameter as mask aligner, there is following technique effect: solved because of the inconsistent problem of symmetric figure CD after the not good etching causing of photoetching alignment precision, solved again because symmetric figure CD inconsistent problem after the etching that etch rate difference causes.
As shown in Figures 2 and 3, the control method of the critical size of a kind of twice etching moulding figure of the present invention, its detailed method step is as follows:
(1) as shown in Fig. 3 (A), growing film layer on silicon chip: described silicon chip 100 can be mating plate, also can be the silicon chip that has completed some semiconductor common technologies, in the present embodiment, described silicon chip 100 have completed the manufacturing process of conducting groove 200; Described thin layer is one or more thin layers that combine in silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, metal silicide, metallic aluminium, in the present embodiment, described thin layer is comprised of silica membrane layer 300 and layer polysilicon film 400, also first i.e. silicon dioxide thin film growth layer 300 on silicon chip 100, then on silica membrane layer 300 preparing polysilicon film layer 400.
(2) as shown in Fig. 3 (B), the photoetching of the first graph layer, the measurement of critical size and alignment precision; After this step completes, the figure of the photoresist 700 of formation is for the follow-up barrier layer of etching/injection for the first time.
(3) as shown in Fig. 3 (C), etching/the injection of the first graph layer, photoresist is removed: described etching can formed one or more layers thin layer of etch step (1), in the present embodiment, described etching can etch step (1) layer polysilicon film that forms 400, but can not etch step (1) the silica membrane layer 300 that forms, adopt the conventional polysilicon dry etching of industry, containing chlorine, the plasma dry etching of hydrogen bromide and oxygen mixed gas, layer polysilicon film 400 is originally through forming respectively the polysilicon 401a on the left side and the polysilicon 402a on the right after etching for the first time.According to process requirements, described injection technology can not done yet, in the present embodiment, described injection using photoresist 700 or layer polysilicon film 400 for the first time after etching the polysilicon 401a on the left side and the polysilicon 402a on the right as implant blocking layer, after annealing, form the first implanted layer 500.
(4) as shown in Fig. 3 (D), the photoetching of second graph layer, the measurement of critical size and alignment precision: the photoetching of described second graph layer, be to take formed the first graph layer of step (3) as aiming at layer, the figure of the photoresist 800 forming after photoetching is for the barrier layer of follow-up etching for the second time.
(5) as shown in Fig. 3 (E), the etching of second graph layer, form the figure of symmetrical structure: described etching can formed one or more layers thin layer of etch step (1), in the present embodiment, described etching can etch step (1) layer polysilicon film that forms 400, but can not etch step (1) the silica membrane layer 300 that forms, adopt the conventional polysilicon dry etching of industry, containing chlorine, the plasma dry etching of hydrogen bromide and oxygen mixed gas, layer polysilicon film 400(is originally the polysilicon 401a on the left side and the polysilicon 402a on the right) through forming respectively the polysilicon 401 on the left side and the polysilicon 402 on the right after etching for the second time.
(6) measurement of the critical size of symmetrical structure figure: the polysilicon 401 on the left side of formation and the critical size of the polysilicon 402 on the right after using CDSEM equipment difference measuring process (5) to complete, as shown in Fig. 3 (E), a and b are respectively the critical sizes of directions X symmetric figure 401 and 402, making to use the same method to obtain the critical size of Y-direction symmetric figure (being to illustrate in Fig. 3 (E)), is assumed to be c and d.For follow-up, can calculate the alignment precision parameter relevant with silicon chip, when to directions X and Y-direction symmetrical structure graphical measurement, in an example as shown in Fig. 3 (F), must select at least 5 exposing units (exposing unit of figure acceptance of the bid " X ") in silicon chip to measure, wherein must have 4 above exposing units to be positioned at the peripheral position of silicon chip; For follow-up, can calculate the alignment precision parameter relevant with exposing unit, when to the directions X of each exposing unit and Y-direction symmetrical structure graphical measurement, in an example as shown in Fig. 3 (G), must measure and lay respectively at the directions X at 4 angles of exposing unit and the critical size of two groups of symmetric figures of Y-direction.
(7) the critical size difference of above-mentioned symmetric figure is converted to the alignment precision of second graph layer: described alignment precision, comprise following parameter: directions X side-play amount, Y-direction side-play amount, directions X silicon chip scaling, Y-direction silicon chip scaling, silicon slice rotating angle, silicon chip orthogonality, directions X exposing unit scaling, Y-direction exposing unit scaling, the exposing unit anglec of rotation, exposing unit orthogonality, wherein directions X side-play amount and Y-direction side-play amount are used following formula to calculate:
Difference/2=|a-b|/2 of directions X side-play amount=directions X symmetrical structure graphics critical dimension
Difference/2=|c-d|/2 of Y-direction side-play amount=Y-direction symmetrical structure graphics critical dimension
Obtain after above-mentioned directions X side-play amount and Y-direction side-play amount, re-use the formula that industry is general and can calculate other alignment precision parameters.
(8) alignment precision of the second graph layer after above-mentioned conversion is fed back to the mask aligner of second graph layer, the alignment precision of the second graph layer of the alignment precision correcting system correction next batch silicon chip by mask aligner, thereby realize the control to the critical size of above-mentioned symmetric figure: current general semiconductor production producer, there is a set of perfect APC (Advanced Process Control, advanced process control) system is for the alignment precision of production control process photoetching, its principle is: mask aligner is before the silicon chip of batch exposes, alignment precision value after last batch of silicon chip photoetching of meeting Automatically invoked (comprising the parameters that step (7) is described), as reference, existing every alignment precision parameter in mask aligner is revised, thereby required best alignment precision parameter while obtaining this batch of silicon wafer exposure, make the silicon chip after photoetching also can obtain best alignment precision.In the present invention, reference value is no longer the alignment precision of measuring after (second graph layer) photoetching in conventional method, but the alignment precision of converting via CD difference after (second graph layer) etching, therefore more can reflect the situation that etching is later, realization to etching after the control of symmetric figure critical size, solved because the inconsistent problem of symmetric figure CD after (second graph layer) photoetching alignment precision not good etching causing, solved again because the inconsistent problem of symmetric figure CD after the etching that (second graph layer) etch rate difference causes.
(9) according to process requirements, can increase afterwards following steps in step (8): the 3rd graph layer photoetching, and then using the polysilicon 401 on photoetching offset plate figure and the left side and the polysilicon 402 on the right simultaneously and carry out injection technology as implant blocking layer, after annealing, form respectively second implanted layer 601 on the left side and second implanted layer 602 (seeing Fig. 1) on the right.
Claims (14)
1. a control method for the critical size of twice etching moulding figure, is characterized in that, comprises that step is as follows:
(1) growing film layer on silicon chip;
The photoetching of (2) first graph layers, the measurement of critical size and alignment precision;
The etching of (3) first graph layers, photoresist is removed;
(4) photoetching of second graph layer, the measurement of critical size and alignment precision;
(5) etching of second graph layer, the figure of formation symmetrical structure;
(6) measurement of the critical size of symmetrical structure figure;
(7) the critical size difference of above-mentioned symmetric figure is converted to the alignment precision of second graph layer;
(8) alignment precision of the second graph layer after above-mentioned conversion is fed back to the mask aligner of second graph layer, the alignment precision of the second graph layer of the alignment precision correcting system correction next batch silicon chip by mask aligner, thus realize the control to the critical size of above-mentioned symmetric figure.
2. method according to claim 1, is characterized in that, in step (1), described silicon chip is mating plate, or has completed the silicon chip of some semiconductor common technologies.
3. method according to claim 2, is characterized in that, in step (1), described silicon chip is the silicon chip that has completed conducting groove manufacturing process.
4. method according to claim 1, it is characterized in that, in step (1), described thin layer is one or more in silicon dioxide, silicon nitride, silicon oxynitride, polysilicon, metal silicide, metallic aluminium one or more layers thin layers of combining.
5. method according to claim 4, is characterized in that, in step (1), described thin layer is comprised of silica membrane layer and layer polysilicon film.
6. method according to claim 1, is characterized in that, in step (3) and (5), described etching can formed one or more layers thin layer of etch step (1).
7. according to the method described in claim 1 or 6, it is characterized in that, in step (3), after the etching of the first graph layer, according to process requirements, increase by a step injection technology.
8. according to the method described in claim 1 or 6, it is characterized in that, in step (3) and (5), described etching is the conventional polysilicon dry etching of industry, contains the plasma dry etching of chlorine, hydrogen bromide and oxygen mixed gas.
9. method according to claim 7, is characterized in that, in step (1), described thin layer is comprised of silica membrane layer and layer polysilicon film, i.e. first silicon dioxide thin film growth layer, layer polysilicon film successively on silicon chip; In step (3) and (5), described etching can etch step (1) layer polysilicon film that forms, but can not etch step (1) the silica membrane layer that forms; The layer polysilicon film that described injection technology is usingd after the first graph layer etching, as implant blocking layer, forms the first implanted layer after annealing.
10. method according to claim 1, it is characterized in that, in step (4), the photoetching of described second graph layer, be to take formed the first graph layer of step (3) as aiming at layer, the figure of the photoresist forming after photoetching is for subsequent step (5) barrier layer of etching for the second time.
11. methods according to claim 1, is characterized in that, in step (6), the measurement of the critical size of described symmetrical structure figure, refers to the critical size of measuring respectively directions X and two groups of symmetric figures of Y-direction.
12. methods according to claim 11, it is characterized in that, in step (6), described measurement, must select at least 5 exposing units in silicon chip to measure, wherein must there be 4 above exposing units to be positioned at the peripheral position of silicon chip, and in each exposing unit, must measure and lay respectively at the described directions X at 4 angles of exposing unit and the critical size of two groups of symmetric figures of Y-direction.
13. methods according to claim 1, it is characterized in that, in step (7), the alignment precision of described second graph layer, comprise following parameter: directions X side-play amount, Y-direction side-play amount, directions X silicon chip scaling, Y-direction silicon chip scaling, silicon slice rotating angle, silicon chip orthogonality, directions X exposing unit scaling, Y-direction exposing unit scaling, the exposing unit anglec of rotation, exposing unit orthogonality, wherein directions X side-play amount and Y-direction side-play amount are used following formula to calculate:
Difference/2 of directions X side-play amount=directions X symmetrical structure graphics critical dimension
Difference/2 of Y-direction side-play amount=Y-direction symmetrical structure graphics critical dimension
Obtain after above-mentioned directions X side-play amount and Y-direction side-play amount, re-use the formula that industry is general and calculate other alignment precision parameters.
14. methods according to claim 1, it is characterized in that, in step (8), increase afterwards following steps: the 3rd graph layer photoetching, and then the layer polysilicon film of simultaneously usining after photoetching offset plate figure and second graph layer etching carries out injection technology as implant blocking layer, after annealing, form the second implanted layer.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104977801A (en) * | 2015-07-30 | 2015-10-14 | 上海华力微电子有限公司 | Overlay error-guided photolithography technique rule detection method |
| CN106154754A (en) * | 2015-04-02 | 2016-11-23 | 上海和辉光电有限公司 | The control method of alignment precision and device |
| CN108109966A (en) * | 2018-01-30 | 2018-06-01 | 德淮半导体有限公司 | Static RAM and its manufacturing method |
| CN108198765A (en) * | 2017-12-28 | 2018-06-22 | 上海华力微电子有限公司 | Suitable for the appraisal procedure of ion implantation technology alignment precision |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050118531A1 (en) * | 2003-12-02 | 2005-06-02 | Hsiu-Chun Lee | Method for controlling critical dimension by utilizing resist sidewall protection |
| CN1816905A (en) * | 2003-06-30 | 2006-08-09 | 东京毅力科创株式会社 | Feedforward, feedback wafer to wafer control method for an etch process |
| CN101329986A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| CN102099906A (en) * | 2008-07-21 | 2011-06-15 | 恪纳腾公司 | Improved metrology through use of feed forward feed sideways and measurement cell re-use |
| TW201207898A (en) * | 2010-04-14 | 2012-02-16 | Asm Genitech Korea Ltd | Method of forming semiconductor patterns |
-
2012
- 2012-09-17 CN CN201210344778.5A patent/CN103681250B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1816905A (en) * | 2003-06-30 | 2006-08-09 | 东京毅力科创株式会社 | Feedforward, feedback wafer to wafer control method for an etch process |
| US20050118531A1 (en) * | 2003-12-02 | 2005-06-02 | Hsiu-Chun Lee | Method for controlling critical dimension by utilizing resist sidewall protection |
| CN101329986A (en) * | 2007-06-21 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Etching method |
| CN102099906A (en) * | 2008-07-21 | 2011-06-15 | 恪纳腾公司 | Improved metrology through use of feed forward feed sideways and measurement cell re-use |
| TW201207898A (en) * | 2010-04-14 | 2012-02-16 | Asm Genitech Korea Ltd | Method of forming semiconductor patterns |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106154754A (en) * | 2015-04-02 | 2016-11-23 | 上海和辉光电有限公司 | The control method of alignment precision and device |
| CN104977801A (en) * | 2015-07-30 | 2015-10-14 | 上海华力微电子有限公司 | Overlay error-guided photolithography technique rule detection method |
| CN104977801B (en) * | 2015-07-30 | 2019-07-19 | 上海华力微电子有限公司 | A kind of photoetching process rule inspection method introducing overlay error |
| CN108198765A (en) * | 2017-12-28 | 2018-06-22 | 上海华力微电子有限公司 | Suitable for the appraisal procedure of ion implantation technology alignment precision |
| CN108198765B (en) * | 2017-12-28 | 2020-04-10 | 上海华力微电子有限公司 | Method for evaluating alignment precision of ion implantation process |
| CN108109966A (en) * | 2018-01-30 | 2018-06-01 | 德淮半导体有限公司 | Static RAM and its manufacturing method |
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