CN106444307A - Photoetching method for flat edge compensation and alignment in laser chip fabrication - Google Patents
Photoetching method for flat edge compensation and alignment in laser chip fabrication Download PDFInfo
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- CN106444307A CN106444307A CN201610874047.XA CN201610874047A CN106444307A CN 106444307 A CN106444307 A CN 106444307A CN 201610874047 A CN201610874047 A CN 201610874047A CN 106444307 A CN106444307 A CN 106444307A
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
- G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
- G03F9/7003—Alignment type or strategy, e.g. leveling, global alignment
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- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A photoetching method for flat edge compensation and alignment in laser chip fabrication comprises the steps of firstly, selecting one of epitaxial wafers corresponding to a certain batch of substrates randomly for photoetching, corrosion, grinding and cleavage, wherein a deflection angle between a photoetching pattern and a flat edge of a wafer is measured after a photoetching process is completed, a deflection angle between a cleavage edge and the photoetching pattern is measured after a cleavage process is completed, and a deflection angle between the flat edge and the cleavage edge of the wafer is obtained by calculation; and finally, compensating the deflection between the flat edge and the cleavage edge of the wafer by manual according to the calculated deflection angle between the flat edge and the cleavage edge of the wafer when first photoetching on a subsequent wafer of the batch of the substrates is performed. The invention proposes the photoetching method for flat edge compensation and alignment in laser chip fabrication. An uncontrollable factor for the deflection between the flat edge and the cleavage edge of the wafer is eliminated, the finished rate of a gallium arsenide laser chip is effectively improved, and the photoetching method is relatively low in implementation cost.
Description
Technical field
The present invention relates to a kind of method for reducing lithography alignment deviation in manufacture for laser chip.
Background technology
The design of gallium arsenide laser chip, it is desirable to which the resonant-cavity surface of chip is along wafer<110>Cleavage edge direction cleavage shape
Become, therefore gaas wafer is when first step photoetching is carried out, need litho pattern and characterize which<110>The flat side of cleavage edge direction
It is aligned.Bar stripe shape laser chip, its light-emitting area length is that 20000um, the relief area of light-emitting area is only 60um, it is desirable to cleavage
The deviation requirement on side is that every 20000um deviation controls within 60um, is converted into alignment and is deflected in -0.17 °～0.17 °.
Gaas wafer is when first step photoetching is carried out, and the alignment deflection on the flat side of litho pattern and wafer can control
Within -0.12 °～0.12 °, but due to wafer flat while and deflection during cleavage larger, cause cleavage side and the light for wafer occur
The deflection angle of needle drawing shape exceeds specification, the problem that chip cannot be used.Using high-precision cutting technique, crystal ingot is cut
Cut, last alignment perhaps can be made to deflect control in -0.17 °～0.17 °, but higher precision is proposed to location equipment will
Ask, relatively costly.
Content of the invention
The present invention proposes a kind of photoetching method of flat side compensation alignment in manufacture for laser chip, eliminates the flat side of wafer
With the uncontrollable factor of the deflection on cleavage side, the yield rate of gallium arsenide laser chip is effectively improved, and cost of implementation is relatively low.
The basic principle of the present invention is as follows：
Gaas wafer in process of production, the wafer that cuts down from same crystal ingot, wafer flat while and during cleavage
Deflection angle identical.For certain a collection of gaas wafer, the processing technology such as photoetching and corrosion can be carried out to wafer, survey
Measure wafer flat while and concrete deflection angle during cleavage.In the first step photoetching of operation subsequent wafer, with reference to above-mentioned deviation
Value is artificially compensated, so as to ensure that the cleavage side of gaas wafer and the deflection of litho pattern reach the specification that chip is required.
The solution of the present invention is as follows：
First, arbitrarily select a piece of from the corresponding epitaxial wafer of certain a collection of substrate, carry out photoetching, burn into grinding, cleavage；
Wherein, the deflection angle after the completion of photoetching process between measurement litho pattern and the flat side of wafer, surveys after the completion of cleavage process
Amount cleavage side and litho pattern between deflection angle, calculate wafer flat in cleavage between deflection angle；
Then, according to the wafer that calculates flat in cleavage between deflection angle, follow-up in the operation substrate batch
During the first step photoetching of wafer, artificially flat to wafer in cleavage between deflection compensate.
The present invention has following technique effect：
Eliminate wafer flat while and the uncontrollable factor of deflection during cleavage, it is ensured that alignment deflection control -0.17 °～
The yield rate of gallium arsenide laser chip in 0.17 °, is effectively improved, and cost of implementation is relatively low.
Description of the drawings
Fig. 1 is the schematic diagram for taking the deflection angle between arbitrarily a piece of measurement litho pattern and the flat side of wafer.
Fig. 2 is the schematic diagram for taking the deflection angle between arbitrarily a piece of measurement cleavage side and litho pattern.
Fig. 3 is the schematic diagram of the deflection angle between calculating cleavage when wafer is flat.
Fig. 4 is the schematic diagram of the compensation alignment of other wafers follow-up.
Specific embodiment
1st, the deflection angle between sampling and measuring litho pattern and the flat side of wafer
Arbitrarily select a piece of from the corresponding epitaxial wafer of certain a collection of substrate, carry out photoetching, aobvious detection limit.As shown in figure 1, meter
When calculating the deflection angle between litho pattern and the flat side of wafer, acquiescence left end is streaked from center.
2nd, the deflection angle between sampling and measuring cleavage side and litho pattern
The techniques such as the thinning grinding of burn into, cleavage are carried out to the wafer, measure the deflection between its cleavage side and litho pattern
Angle, as shown in Fig. 2 when calculating deflection angle, acquiescence left end is streaked from center.
3rd, the deflection angle between calculating cleavage when wafer is flat
As shown in figure 3, according to the litho pattern for drawing above and wafer flat while deflection angle, cleavage while and litho pattern
Deflection angle, cleavage while and deflection angle computing formula while wafer is flat as follows：
Deflection angleCleavage is when to wafer is flat=deflection angleCleavage side to litho pattern+ deflection angleThe flat side of litho pattern to wafer
4th, the compensation alignment of other wafers
In the first step photoetching of the operation substrate batch subsequent wafer, artificially flat to wafer in cleavage between
Deflection angle is compensated.As shown in figure 4, for the wafer of poor (overgauge) the θ degree of right avertence, during first time photoetching, can be using the right side
The right compensation of deviation, the mode of the left compensation of left avertence difference.
Claims (1)
1. the photoetching method that in a kind of manufacture for laser chip, flat side compensation is aligned, it is characterised in that：
First, arbitrarily select a piece of from the corresponding epitaxial wafer of certain a collection of substrate, carry out photoetching, burn into grinding, cleavage；Wherein,
Deflection angle after the completion of photoetching process between measurement litho pattern and the flat side of wafer, measures cleavage after the completion of cleavage process
While the deflection angle between litho pattern, calculate wafer flat in cleavage between deflection angle；
Then, according to the wafer that calculates flat in cleavage between deflection angle, in the operation substrate batch subsequent wafer
The first step photoetching when, artificially flat to wafer in cleavage between deflection compensate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874047.XA CN106444307B (en) | 2016-09-30 | 2016-09-30 | The photolithography method of flat side compensation alignment in a kind of manufacture for laser chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610874047.XA CN106444307B (en) | 2016-09-30 | 2016-09-30 | The photolithography method of flat side compensation alignment in a kind of manufacture for laser chip |
Publications (2)
| Publication Number | Publication Date |
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| CN106444307A true CN106444307A (en) | 2017-02-22 |
| CN106444307B CN106444307B (en) | 2017-11-21 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022057735A1 (en) * | 2020-09-17 | 2022-03-24 | 深圳市中光工业技术研究院 | Method for increasing precision of flat edge of semiconductor wafer, and laser chip |
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| WO2009109939A1 (en) * | 2008-03-07 | 2009-09-11 | Universita' Degli Studi Di Genova | Method for the synthesis of an array of metal nanowires capable of supporting localized plasmon resonances and photonic device comprising said array |
| US20100052191A1 (en) * | 2008-08-29 | 2010-03-04 | Qimonda Ag | Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method |
| US20100157233A1 (en) * | 2004-12-24 | 2010-06-24 | Byung Chul Ahn | Liquid crystal display device |
| CN102460633A (en) * | 2009-05-20 | 2012-05-16 | 迈普尔平版印刷Ip有限公司 | Pattern data conversion for lithography system |
| CN102981223A (en) * | 2012-12-07 | 2013-03-20 | 武汉光迅科技股份有限公司 | Optical waveguide chip and PD (photodiode) array coupling packaging structure |
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2016
- 2016-09-30 CN CN201610874047.XA patent/CN106444307B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20100157233A1 (en) * | 2004-12-24 | 2010-06-24 | Byung Chul Ahn | Liquid crystal display device |
| WO2009109939A1 (en) * | 2008-03-07 | 2009-09-11 | Universita' Degli Studi Di Genova | Method for the synthesis of an array of metal nanowires capable of supporting localized plasmon resonances and photonic device comprising said array |
| US20100052191A1 (en) * | 2008-08-29 | 2010-03-04 | Qimonda Ag | Metrology Mark with Elements Arranged in a Matrix, Method of Manufacturing Same and Alignment Method |
| CN102460633A (en) * | 2009-05-20 | 2012-05-16 | 迈普尔平版印刷Ip有限公司 | Pattern data conversion for lithography system |
| CN102981223A (en) * | 2012-12-07 | 2013-03-20 | 武汉光迅科技股份有限公司 | Optical waveguide chip and PD (photodiode) array coupling packaging structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022057735A1 (en) * | 2020-09-17 | 2022-03-24 | 深圳市中光工业技术研究院 | Method for increasing precision of flat edge of semiconductor wafer, and laser chip |
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| CN106444307B (en) | 2017-11-21 |
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