WO2022056760A1 - Dispositifs de mémoire à changement de phase comportant un sélecteur de commutation de seuil à filament métallique et procédés de formation de ceux-ci - Google Patents

Dispositifs de mémoire à changement de phase comportant un sélecteur de commutation de seuil à filament métallique et procédés de formation de ceux-ci Download PDF

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WO2022056760A1
WO2022056760A1 PCT/CN2020/115786 CN2020115786W WO2022056760A1 WO 2022056760 A1 WO2022056760 A1 WO 2022056760A1 CN 2020115786 W CN2020115786 W CN 2020115786W WO 2022056760 A1 WO2022056760 A1 WO 2022056760A1
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Prior art keywords
selector
mfts
solid electrolyte
metal ion
pcm
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PCT/CN2020/115786
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English (en)
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Jun Liu
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Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
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Priority to PCT/CN2020/115786 priority Critical patent/WO2022056760A1/fr
Priority to CN202080002423.0A priority patent/CN112243527A/zh
Publication of WO2022056760A1 publication Critical patent/WO2022056760A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5614—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/71—Three dimensional array
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode

Definitions

  • Embodiments of the present disclosure relate to phase-change memory (PCM) devices and fabrication methods thereof.
  • PCM phase-change memory
  • Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process.
  • feature sizes of the memory cells approach a lower limit
  • planar process and fabrication techniques become challenging and costly.
  • memory density for planar memory cells approaches an upper limit.
  • a three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
  • the 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.
  • PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally.
  • PCM array cells can be vertically stacked in 3D to form a 3D PCM.
  • Embodiments of PCM devices and methods for forming the same are disclosed herein.
  • a 3D memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines.
  • Each of the plurality of memory cells includes stacked a PCM element and a metal filament threshold switching (MFTS) selector.
  • MFTS metal filament threshold switching
  • a PCM cell in another example, includes a PCM element, and a MFTS selector including a metal ion reservoir and a solid electrolyte in contact with the metal ion reservoir.
  • a method for forming a PCM cell is disclosed.
  • An MFTS selector including a metal ion reservoir and a solid electrolyte in contact with the metal ion reservoir is formed.
  • a PCM element is formed.
  • a method for forming a 3D memory device is disclosed.
  • a plurality of gaps are formed in the memory stack to separate the memory stack into a plurality of memory cells each including part of the layers of the MFTS selector, the first electrode, the PCM element, and the second electrode.
  • a plurality of insulating structures are formed in the plurality of gaps between the plurality of memory cells.
  • FIG. 1 illustrates a perspective view of an exemplary 3D XPoint memory device, according to some embodiments of the present disclosure.
  • FIG. 2 illustrates a side view of a cross-section of a 3D XPoint memory device having ovonic threshold switch (OTS) selectors.
  • OTS ovonic threshold switch
  • FIG. 3A illustrates a side view of a cross-section of an exemplary 3D PCM device having MFTS selectors, according to some embodiments of the present disclosure.
  • FIG. 3B illustrates a side view of a cross-section of another exemplary 3D PCM device having MFTS selectors, according to some embodiments of the present disclosure.
  • FIG. 4 illustrates the formation and dissolution of a metal filament in an exemplary MFTS selector, according to some embodiments of the present disclosure.
  • FIG. 5 illustrates a schematic diagram of the operation of an exemplary array of PCM cells having MFTS selectors, according to some embodiments of the present disclosure.
  • FIGs. 6A–6H illustrate an exemplary fabrication process for forming a 3D PCM device having MFTS selectors, according to some embodiments of the present disclosure.
  • FIG. 7 illustrates a flowchart of an exemplary method for forming a 3D PCM device having MFTS selectors, according to some embodiments of the present disclosure.
  • references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
  • terminology may be understood at least in part from usage in context.
  • the term “one or more” as used herein, depending at least in part upon context may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense.
  • terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.
  • the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
  • spatially relative terms such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • the term “substrate” refers to a material onto which subsequent material layers are added.
  • the substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc.
  • the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.
  • a layer refers to a material portion including a region with a thickness.
  • a layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface.
  • a substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow.
  • a layer can include multiple layers.
  • an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.
  • the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value.
  • the range of values can be due to slight variations in manufacturing processes or tolerances.
  • the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10–30%of the value (e.g., ⁇ 10%, ⁇ 20%, or ⁇ 30%of the value) .
  • 3D memory device refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate.
  • vertical/vertically means nominally perpendicular to the lateral surface of a substrate.
  • a PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally.
  • phase-change materials e.g., chalcogenide alloys
  • the phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data.
  • PCM cells can be vertically stacked in 3D to form a 3D PCM.
  • 3D PCMs include 3D cross-point (XPoint) memory, which stores data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array to be bit-addressable.
  • FIG. 1 illustrates a perspective view of an exemplary 3D XPoint memory device 100, according to some embodiments of the present disclosure.
  • 3D XPoint memory device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors, according to some embodiments.
  • 3D XPoint memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above lower bit lines 102.3D XPoint memory device 100 also includes a plurality of parallel word lines 106 in the same plane vertically between lower bit lines 102 and upper bit lines 104. As shown in FIG. 1, each lower bit line 102 and each upper bit line 104 extend laterally along the bit line direction in the plan view (parallel to the wafer plane) , and each word line 106 extends laterally along the word line direction in the plan view. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.
  • x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane.
  • the x-direction is the word line direction
  • the y-direction is the bit line direction.
  • z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D XPoint memory device 100.
  • the substrate (not shown) of 3D XPoint memory device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer.
  • the z-axis is perpendicular to both the x and y axes.
  • one component e.g., a layer or a device
  • another component e.g., a layer or a device
  • a semiconductor device e.g., 3D XPoint memory device 100
  • 3D XPoint memory device 100 includes a plurality of memory cells 108 each disposed at an intersection of lower or upper bit line 102 or 104 and respective word line 106.
  • Each memory cell 108 has a vertical square pillar shape.
  • Each memory cell 108 includes at least a PCM element 110 and a selector 112 stacked vertically.
  • Each memory cell 108 stores a single bit of data and can be written or read by varying the voltage applied to respective selector 112, which replaces the need for transistors.
  • Each memory cell 108 is accessed individually by a current applied through the top and bottom conductors in contact with each memory cell 108, e.g., respective word line 106 and lower or upper bit line 102 or 104.
  • Memory cells 108 in 3D XPoint memory device 100 are arranged in a memory array.
  • the materials of selector 112 are ovonic threshold switch (OTS) materials, such as zinc telluride (ZnTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage (V a ) higher than the threshold voltage is applied (V th ) .
  • OTS phenomenon a field-dependent volatile resistance switching behavior
  • FIG. 2 illustrates a side view of a cross-section of a 3D XPoint memory device 200 having OTS selectors.
  • 3D XPoint memory device 200 includes a plurality of parallel bit lines 204 above a substrate 202 and a plurality of parallel word lines 216 above bit lines 204.3D XPoint memory device 200 also includes a plurality of memory cells 201 each disposed at an intersection of a respective pair of bit line 204 and word line 216. Adjacent memory cells 201 are separated by an insulating structure 203. Each memory cell 201 includes an OTS selector 208 and a PCM element 212 above OTS selector 208. Each memory cell 201 further includes three electrodes 206, 210, and 214 vertically between a respective bit line 204, OTS selector 208, PCM element 212, and a respective word line 216, respectively.
  • OTS selector 208 includes an OTS material, such as ZnTe.
  • ⁇ V th the high resistance of OTS selector 208 in its off-state keeps the off-state current (I off ) low.
  • > V th the higher voltage
  • > V th OTS selector 208 undergoes OTS phenomenon and switches to the on-state with low resistance; thus, the current through OTS selector 208 in the on-state (I on ) increases. The volatile on-state is maintained as long as high voltage is supplied.
  • the on/off ratio (I on /I off ) of OTS selector 208 is usually between 10 3 and 10 6 , the range of which can still cause current leakage through unselected memory cells 201 to degrade read operation margin and can introduce parasitic resistance-related voltage that limits larger cell array.
  • an MFTS selector includes a metal ion reservoir for supplying metal ions, such as silver (Ag) and copper (Cu) ions, in contact with a solid electrolyte.
  • a memory cell including the MFTS selector in series with a PCM element is formed in a self-aligned manner at the intersection of a pair of word line and bit line.
  • FIG. 3A illustrates a side view of a cross-section of an exemplary 3D PCM device 300 having MFTS selectors, according to some embodiments of the present disclosure.
  • 3D PCM device 300 such as a 3D XPoint memory device, can include a plurality of bit lines 304 above a substrate 302, which can include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials.
  • Bit lines 304 can be parallel to one another and in the same plane.
  • a plurality of parallel bit lines 304 each extends laterally in the y-direction (e.g., the bit line direction) in FIG. 3A.
  • 3D PCM device 300 can further include a plurality of word lines 318 above bit lines 304.
  • Word lines 318 can be parallel to one another and in the same plane.
  • a plurality of parallel word lines 318 each extends laterally in the x-direction (e.g., the word line direction) in FIG. 3A.
  • Word lines 318 and bit lines 304 of 3D PCM device 300 such as a 3D XPoint memory device, can be perpendicularly arranged conductors in a cross-point architecture.
  • Bit lines 304 and word lines 318 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polysilicon, doped silicon, silicides, or any combination thereof.
  • each of bit lines 304 and word lines 318 includes a metal, such as tungsten.
  • 3D PCM device 300 includes a plurality of memory cells 301 each disposed at an intersection of a respective one of bit lines 304 and a respective one of word lines 318. Each memory cell 301 can be accessed individually by a current applied through a respective word line 318 and a respective bit line 304 in contact with memory cell 301. As shown in FIG. 3A, 3D PCM device 300 can further include insulating structures 303 laterally between adjacent memory cells 301. In some embodiments, each memory cell 301 has a vertical pillar shape (e.g., similar to memory cell 108 in FIG. 1) , and insulating structures 303 can extend laterally in both x-direction and y-direction to separate the pillar-shaped memory cells 301.
  • insulating structure 303 includes one or more dielectric layers, such as an encapsulation layer 322 formed along the sidewalls of memory cells 301 and bit lines 304 and a capping layer 323 filling the remaining space between memory cells 301.
  • the dielectric layers of insulating structures 303 can include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.
  • encapsulation layer 322 and capping layer 323 include silicon nitride and silicon oxide, respectively.
  • Each memory cell 301 can include stacked a PCM element 314, an MFTS selector 320, and a plurality of electrodes 312 and 316.
  • PCM element 314 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. Electrical currents can be applied to switch the phase-change material (or at least a fraction of it that blocks the current path) of PCM element 314 repeatedly between the two phases to store data.
  • a single bit of data can be stored in each memory cell 301 and can be written or read by varying the voltage applied to a respective MFTS selector 320, which eliminates the need for transistors and replaces the conventional OTS selectors (e.g., OTS selector 208 in FIG. 2) .
  • two electrodes 312 and 316 are disposed between MFTS selector 320 and PCM element 314 and between PCM element 314 and word line 318, respectively. That is, electrodes 312 and 316 can be arranged on opposite sides (e.g., above and below) of PCM element 314 to separate PCM element 314 from direct contacts with other components. It is understood that the structure of memory cell 301 is not limited to the example in FIG.
  • 3A may include any suitable structures.
  • the relative positions of MFTS selector 320 and PCM element 314 may be switched in other examples.
  • the number and relative positions of electrodes 312 and 316 in memory cell 301 may vary in other examples as well.
  • the materials of PCM element 314 include chalcogenide-based alloys (chalcogenide glass) , such as germanium antimony telluride (GeSbTe or GST) alloy, or any other suitable phase-change materials, according to some embodiments.
  • Electrodes 312 and 316 can include conductive materials including, but not limited to, W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicides, or any combination thereof.
  • each of electrodes 312 and 316 includes carbon, such as amorphous carbon (a-C) .
  • MFTS selector 320 includes stacked a metal ion reservoir 306, a solid electrolyte 308, and a selector electrode 310.
  • metal ion reservoir 306 is above and in contact with a respective bit line 304
  • solid electrolyte 308 is above in contact with metal ion reservoir 306,
  • selector electrode 310 is above and in contact with solid electrolyte 308. That is, solid electrolyte 308 can be vertically between, i.e., sandwiched between, metal ion reservoir 306 and selector electrode 310.
  • selector electrode 310 of MFTS selector 320 is below and in contact with electrode 312.
  • Solid electrolyte 308 can include multiple layers of different materials.
  • solid electrolyte 308 includes a separator (not shown) in contact with metal ion reservoir 306.
  • the thickness of metal ion reservoir 306 is between about 5 nm and about 50 nm, such as between 5 nm and 50 nm (e.g., 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) .
  • the thickness of solid electrolyte is between about 10 nm and about 100 nm, such as between 10 nm and 100 nm (e.g., 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) .
  • Metal ion reservoir 306 can serve as the source of metal ions, such as Ag ions or Cu ions.
  • metal ion reservoir 306 includes Ag, Cu, silver sulfide (AgS) , copper sulfide (CuS) , silver selenide (AgSe) , copper selenide (CuSe) , or any combinations thereof.
  • Solid electrolyte 308 can be the place where the metal ions form a metal filament, or the metal filament dissolves into the metal ions under different voltages.
  • solid electrolyte 308 includes germanium selenide (GeSe) , germanium sulfide (GeS) , silver selenide (AgSe) , silver sulfide (AgS) , copper telluride (CuTe) , or any combination thereof.
  • GeSe germanium selenide
  • GeS germanium sulfide
  • AgSe and AgS may be used as the materials of metal ion reservoir 306 and/or solid electrolyte 308, for example, depending on the concentration of AgSe or AgS in metal ion reservoir 306 and/or solid electrolyte 308.
  • the concentration of AgSe or AgS in metal ion reservoir 306 may be greater than the concentration of AgSe or AgS in solid electrolyte 308.
  • solid electrolyte 308 can further include a separator in contact with metal ion reservoir 306, including, for example, gadolinium oxide (GdO) .
  • solid electrolyte 308 may include a layer of GdO as the separator and another layer of GeSe, GeS, AgSe, AgS, and/or CuTe.
  • Selector electrode 310 can be electrically connected to or electrically separated from metal ion reservoir 306 in the on-state and off-state, respectively.
  • Selector electrode 310 can include conductive materials including, but not limited to, W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicides, or any combination thereof.
  • selector electrode 310 includes W or titanium nitride (TiN) .
  • metal ion reservoir 306 may include Ag, solid electrolyte 308 may include GeSe or GeS, and selector electrode 310 may include W.
  • metal ion reservoir 306 may include AgSe, solid electrolyte 308 may include GeSe or GeS, and selector electrode 310 may include W.
  • metal ion reservoir 306 may include Cu
  • solid electrolyte 308 may include GdO (as the separator) /CuTe
  • selector electrode 310 may include TiN.
  • FIG. 4 illustrates the formation and dissolution of a metal filament in MFTS selector 320, according to some embodiments of the present disclosure.
  • An intrinsic threshold voltage (V th ) of MFTS selector 320 can be determined based on various properties of MFTS selector 320, including but not limited to the materials of metal ion reservoir 306 and solid electrolyte 308, and the thickness of solid electrolyte 308.
  • Va the voltage applied to MFTS selector 320 of memory cell 301, i.e., between a pair of word line 318 and bit line 304
  • MFTS selector 320 can switch between the off-state and the on-state.
  • MFTS selector 320 The I-V characteristics of MFTS selector 320 are based on the metal filament formation in solid electrolyte 308.
  • MFTS selector 320 In the on-state (e.g.,
  • metal ions such as Ag or Cu ions
  • V th the intrinsic threshold voltage of MFTS selector 320
  • Metal filament 402 can act as the bridge between metal ion reservoir 306 and selector electrode 310 to significantly lower the overall resistance therebetween and drastically increase the on-state current (I on ) .
  • MFTS selector 320 is configured to dissolve metal filament 402 in solid electrolyte 308 to electrically separate metal ion reservoir 306 and selector electrode 310, keeping the off-state current (I off ) remarkably low (e.g., almost zero) .
  • I off off-state current
  • the overall resistance between metal ion reservoir 306 and selector electrode 310 returns back to the resistance of solid electrolyte 308 in the off-state, which may be significantly higher than that in the on-state with the existence of metal filament 402.
  • the on/off ratio (I on /I off ) of MFTS selector 320 based on the formation/dissolution of metal filaments can be significantly increased, for example, greater than 10 6 (the upper limit of the on/off ratio for OTS selectors) , to reduce leakage current and parasitic resistance.
  • the on/off ratio of MFTS selector 320 is between about 10 6 and about 10 9 , such as between 10 6 and 10 9 , (e.g., 1 ⁇ 10 6 , 5 ⁇ 10 6 , 1 ⁇ 10 7 , 5 ⁇ 10 7 , 1 ⁇ 10 8 , 5 ⁇ 10 8 , 1 ⁇ 10 9 , any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . Therefore, the electrical performance and array cell density of 3D PCM device 300 having MFTS selectors 320 can be improved compared with conventional 3D PCM devices having OTS selectors.
  • FIG. 5 illustrates a schematic diagram of the operation of an exemplary array of PCM cells having MFTS selectors, according to some embodiments of the present disclosure.
  • an array of PCM cells 502 e.g., corresponding to memory cells 301 in FIG. 3A
  • word lines 504 e.g., corresponding to word lines 318 in FIG. 3A
  • bit lines 506 e.g., corresponding to bit lines 304 in FIG. 3A
  • Each PCM cell 502 can include a PCM element 508 (e.g., corresponding to PCM element 314 in FIG.
  • MFTS selector 320 in series with an MFTS selector (e.g., corresponding to MFTS selector 320 in FIG. 3A) .
  • a word line voltage (V w ) having a value of either 0 or Vhh can be applied to each word line 504, and a bit line voltage (V b ) having a value of either 0 or Vll can be applied to each bit line 506.
  • the voltage (Va) applied to each PCM cell 502 (and MFTS selector 510 thereof) can thus be either Vhh, –Vll, 0, or Vhh–Vll.
  • Vhh and Vll are set based on the intrinsic threshold voltage (V th ) of MFTS selector 510, such that
  • the voltage (Va) is equal to or greater than the threshold voltage (V th ) at only one intersection of word line 504 and bit line 506 with non-zero voltages, according to some embodiments.
  • PCM cell 502 in the dotted circle in FIG.
  • PCM cells 502 are not selected and are in the off-state, according to some embodiments.
  • 3D PCM device 300 can be a 3D XPoint memory device in which MFTS selector 320 and PCM element 314 can be in a double-stacked storage/selector structure.
  • MFTS selector 320 and PCM element 314 can be in a double-stacked storage/selector structure.
  • FIG. 3B another array of memory cells 321 in the same plane can be formed above the array of memory cells 301 and share word lines 318 with the array of memory cells 301.
  • Each memory cell 321 can include stacked MFTS selector 320, electrode 312, PCM element 314, and electrode 316 from bottom to top, like memory cell 301.
  • a plurality of bit lines 324 can be formed above and in contact with memory cells 321 to drive memory cells 321 along with word lines 318.
  • Insulating structures 325 can be formed above word lines 318 and laterally between memory cells 321 as well, like insulating structures 303.
  • FIGs. 6A–6H illustrate an exemplary fabrication process for forming a 3D PCM device having MFTS selectors, according to some embodiments of the present disclosure.
  • FIG. 7 illustrates a flowchart of an exemplary method 700 for forming a 3D PCM device having MFTS selectors, according to some embodiments of the present disclosure. Examples of the 3D PCM device depicted in FIGs. 6A–6H and 7 include 3D PCM device 300 depicted in FIGs. 3A and 3B. FIGs. 6A–6H and 7 will be described together. It is understood that the operations shown in method 700 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7.
  • method 700 starts at operation 702, in which a memory stack including layers of an MFTS selector, a first electrode, a PCM element, and a second electrode is formed above a substrate.
  • layers of a metal ion reservoir, a solid electrolyte, a selector electrode, the first electrode, the PCM element, and the second electrode are sequentially deposited.
  • the metal ion reservoir can include at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide.
  • the solid electrolyte can include at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride.
  • the PCM element can include a chalcogenide-based alloy.
  • a conductor layer is formed on the substrate prior to the formation of the memory stack, such that the memory stack is formed on the conductor layer.
  • a conductor layer 604 is formed on a substrate 602.
  • a metal layer such as a W layer, is deposited using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , or any combination thereof.
  • CVD chemical vapor deposition
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • a memory stack 605 is formed on conductor layer 604.
  • a metal ion reservoir layer 606, a solid electrolyte layer 608, a selector electrode layer 610, a first electrode layer 612, a PCM element layer 614, and a second electrode layer 616 are sequentially deposited on conductor layer 604 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.
  • each of first and second electrode layers 612 and 616 may include amorphous carbon
  • selector electrode layer 610 may include W or TiN
  • PCM element layer 614 may include chalcogenide-based alloy, such as GST alloy.
  • metal ion reservoir layer 606 may include Ag, Cu, AgS, CuS, AgSe, CuSe, or any combinations thereof
  • solid electrolyte layer 608 may include GeSe, GeS, AgSe, AgS, CuTe, or any combination thereof.
  • the thickness of solid electrolyte layer 608 may be between about 10 nm and about 100 nm.
  • a dielectric layer 618 is formed on memory stack 605 by depositing dielectric materials, such as silicon nitride, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof to act as the etching mask of memory stack 605 in the later process.
  • dielectric materials such as silicon nitride
  • thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof to act as the etching mask of memory stack 605 in the later process.
  • Method 700 proceeds to operation 704, as illustrated in FIG. 7, in which a plurality of gaps are formed in the memory stack to separate the memory stack into a plurality of memory cells each including part of the layers of the MFTS selector, the first electrode, the PCM element, and the second electrode.
  • a plurality of gaps are formed in the memory stack to separate the memory stack into a plurality of memory cells each including part of the layers of the MFTS selector, the first electrode, the PCM element, and the second electrode.
  • the memory stack is double patterned, and the double-patterned memory stack is etched through.
  • memory stack 605, conductor layer 604, and dielectric layer 618 are etched through in the y-direction (e.g., the bit line direction) to form a plurality of gaps 620.
  • memory stack 605, conductor layer 604, and dielectric layer 618 are double patterned first.
  • dielectric layer 618 may be patterned by lithography, development, and etching. Double patterning can include, but not limited to, litho-etch-litho-etch (LELE) pitch-splitting or self-aligned double patterning (SADP) , to control the critical dimensions of memory cells 622 to be formed from memory stack 605.
  • LELE litho-etch-litho-etch
  • SADP self-aligned double patterning
  • double-patterned memory stack 605 and conductor layer 604 are then etched through in the y-direction to form parallel gaps 620 in the y-direction using double-patterned dielectric layer 618 as the etching mask.
  • Memory stack 605 and conductor layer 604 can be etched through by one or more wet etching and/or dry etching processes, such as deep reactive-ion etching (DRIE) , using the double-patterned etching mask to simultaneously form parallel gaps 620.
  • DRIE deep reactive-ion etching
  • Memory cells 622 separated by gaps 620 and each including parts of metal ion reservoir layer 606, solid electrolyte layer 608, selector electrode layer 610, first electrode layer 612, PCM element layer 614, and second electrode layer 616 are thereby formed, according to some embodiments.
  • conductor layer 604 is separated by gaps 620 as well, forming bit lines below and in contact with memory cells 622, respectively.
  • Method 700 proceeds to operation 706, as illustrated in FIG. 7, in which a plurality of insulating structures are formed in the plurality of gaps between the plurality of memory cells.
  • a plurality of insulating structures are formed in the plurality of gaps between the plurality of memory cells.
  • one or more dielectric layers are deposited on the plurality of memory cells and into the plurality of gaps to fill the plurality of gaps, and the deposited dielectric layers are planarized to expose the part of the layer of the second electrode.
  • an encapsulation layer 624 is deposited on memory cells 622 and into gaps 620 to protect the exposed memory cells 622.
  • a dielectric layer such as a silicon nitride layer, is deposited along the sidewalls and top surfaces of memory cells 622 to fully cover memory cells 622 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof to form encapsulation layer 624.
  • encapsulation layer 624 is deposited using ALD to form a thin, conformal layer without fully filling gaps 620 between memory cells 622.
  • a capping layer 626 is deposited over encapsulation layer 624 to fill gaps 620.
  • a dielectric layer such as a silicon oxide layer
  • a dielectric layer is deposited over encapsulation layer 624 and into gaps 620 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof to form capping layer 626.
  • capping layer 626 is formed by depositing silicon oxide using ALD or flowable CVD or by spin-coating spin-on dielectrics (SODs) . Insulating structures 629 laterally between memory cells 622 and each including encapsulation layer 624 and capping layer 626 are thereby formed, according to some embodiments.
  • a planarization process such as chemical mechanical polishing (CMP) , grinding, or etching, is used to planarized capping layer 626 and encapsulation layer 624 to remove parts of planarized capping layer 626 and encapsulation layer 624 on the top surfaces of memory cells 622.
  • CMP chemical mechanical polishing
  • the planarization process continues to remove dielectric layer 618 (as shown in FIG. 6D) to expose second electrode layer 616 of each memory cell 622.
  • memory stack 605 may need to be etched in two perpendicular directions (e.g., both the x-direction and y-direction) to form perpendicular gaps filled with insulating structures.
  • the same gap etching and filling processes described above with respect to FIGs. 6A–6E may be performed again in the x-direction as needed.
  • Method 700 proceeds to operation 708, as illustrated in FIG. 7, in which a plurality of word lines are formed above and in contact with the plurality of memory cells.
  • a conductor layer 630 is formed on memory cells 622 and insulating structures 629.
  • a metal layer such as a W layer, is deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.
  • Conductor layer 630 can then be patterned using, for example, double patterning, and etched, for example, using RIE, in the x-direction (e.g., the word line direction) of FIG. 6F to form a plurality of word lines above and in contact with memory cells 622 (e.g., second electrode layer 616) .
  • another array of memory cells are formed above and in contact with the word lines using similar processes as described above with respect to FIGs. 6A–6E and 7.
  • a memory stack 631 is formed on conductor layer 630 (forming the word lines)
  • a conductor layer 644 is formed on memory stack 631.
  • a metal ion reservoir layer 632, a solid electrolyte layer 634, a selector electrode layer 636, a first electrode layer 638, a PCM element layer 640, a second electrode layer 642, and conductor layer 644 are sequentially deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in FIG.
  • memory cells 651 each including parts of metal ion reservoir layer 632, solid electrolyte layer 634, selector electrode layer 636, first electrode layer 638, PCM element layer 640, and second electrode layer 642 and laterally separated by insulating structures 649 are formed from memory stack 631 using the processes described above with respect to FIGs. 6B–6E.
  • Conductor 644 can be patterned and etched to form a plurality of bit lines above and in contact with memory cells 651, respectively, as well. The processes for forming the similar components that have been described above with respect to FIGs. 6A–6E are not repeated for ease of description.
  • a 3D memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines.
  • Each of the plurality of memory cells includes stacked a PCM element and an MFTS selector.
  • the MFTS selector includes stacked a metal ion reservoir, a solid electrolyte, and a selector electrode, the solid electrolyte being vertically between the metal ion reservoir and the selector electrode.
  • the metal ion reservoir includes at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide.
  • the solid electrolyte includes at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride.
  • the solid electrolyte includes a separator in contact with the metal ion reservoir.
  • the separator includes gadolinium oxide.
  • a thickness of the solid electrolyte is between about 10 nm and about 100 nm.
  • a thickness of the metal ion reservoir is between about 5 nm and about 50 nm.
  • the MFTS selector is configured to, when a voltage between the respective word line and bit line of the memory cell is equal to or above a threshold voltage of the MFTS selector, form a metal filament having metal ions from the metal ion reservoir in the solid electrolyte to electrically connect the metal ion reservoir and the selector electrode.
  • the MFTS selector is further configured to, when the voltage between the respective word line and bit line of the memory cell is below the threshold voltage of the MFTS selector, dissolve the metal filament in the solid electrolyte to electrically separate the metal ion reservoir and the selector electrode.
  • an on/off ratio of the MFTS selector is between about 10 6 and about 10 9 .
  • the plurality of word lines and the plurality of bit lines are in a cross-point architecture.
  • each of the plurality of memory cells further includes a first electrode vertically between the PCM element and the MFTS selector, and a second electrode vertically between the PCM element and the respective word line.
  • a PCM cell includes a PCM element, and an MFTS selector including a metal ion reservoir and a solid electrolyte in contact with the metal ion reservoir.
  • the MFTS selector is configured to, when a voltage applied to the MFTS selector is equal to or above a threshold voltage of the MFTS selector, form a metal filament having metal ions from the metal ion reservoir in the solid electrolyte. In some embodiments, the MFTS selector is further configured to, when the voltage applied to the MFTS selector is below the threshold voltage of the MFTS selector, dissolve the metal filament in the solid electrolyte.
  • the MFTS selector further includes a selector electrode in contact with the solid electrolyte.
  • the metal ion reservoir includes at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide
  • the solid electrolyte includes at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride.
  • a thickness of the solid electrolyte is between about 10 nm and about 100 nm, and a thickness of the metal ion reservoir is between about 5 nm and about 50 nm.
  • the solid electrolyte includes a separator in contact with the metal ion reservoir.
  • the separator includes gadolinium oxide.
  • an on/off ratio of the MFTS selector is between about 10 6 and about 10 9 .
  • the PCM element includes a chalcogenide-based alloy.
  • the PCM cell further includes an electrode between the PCM element and the MFTS selector.
  • a method for forming a PCM cell is disclosed.
  • An MFTS selector including a metal ion reservoir and a solid electrolyte in contact with the metal ion reservoir is formed.
  • a PCM element is formed.
  • the metal ion reservoir, the solid electrolyte in contact with the metal ion reservoir, and a selector electrode in contact with the solid electrolyte are sequentially formed.
  • a separator including gadolinium oxide is formed in contact with the metal ion reservoir.
  • the metal ion reservoir includes at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide
  • the solid electrolyte includes at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride.
  • a thickness of the solid electrolyte is between about 10 nm and about 100 nm, and a thickness of the metal ion reservoir is between about 5 nm and about 50 nm.
  • the PCM element includes a chalcogenide-based alloy.
  • an electrode is formed between the PCM element and the MFTS selector.
  • a method for forming a 3D memory device is disclosed.
  • a memory stack including layers of an MFTS selector, a first electrode, a PCM element, and a second electrode is formed.
  • a plurality of gaps are formed in the memory stack to separate the memory stack into a plurality of memory cells each including part of the layers of the MFTS selector, the first electrode, the PCM element, and the second electrode.
  • a plurality of insulating structures are formed in the plurality of gaps between the plurality of memory cells.
  • layers of a metal ion reservoir, a solid electrolyte, a selector electrode, the first electrode, the PCM element, and the second electrode are sequentially deposited.
  • the metal ion reservoir includes at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide
  • the solid electrolyte includes at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride
  • the PCM element includes a chalcogenide-based alloy.
  • the memory stack is double patterned, and the double-patterned memory stack is etched through.
  • one or more dielectric layers are deposited on the plurality of memory cells and into the plurality of gaps to fill the plurality of gaps, and the deposited dielectric layers are planarized to expose the part of the layer of the second electrode.
  • a plurality of word lines are formed above and in contact with the plurality of memory cells.

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Abstract

Des modes de réalisation de mémoire à changement de phase (PCM) et des procédés de formation de ceux-ci sont divulgués. Dans un exemple, un dispositif de mémoire 3D comprend une pluralité de lignes de bits, une pluralité de lignes de mots, et une pluralité de cellules de mémoire disposées chacune à une intersection d'une ligne de bits respective de la pluralité de lignes de bits et d'une ligne de mots respective de la pluralité de lignes de mots. Chacune de la pluralité de cellules de mémoire comprend un élément PCM empilé et un sélecteur de commutation de seuil à filament métallique (MFTS).
PCT/CN2020/115786 2020-09-17 2020-09-17 Dispositifs de mémoire à changement de phase comportant un sélecteur de commutation de seuil à filament métallique et procédés de formation de ceux-ci WO2022056760A1 (fr)

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CN202080002423.0A CN112243527A (zh) 2020-09-17 2020-09-17 具有金属丝阈值切换选择器的相变存储器件及其形成方法

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US20220407000A1 (en) * 2021-06-16 2022-12-22 Macronix International Co., Ltd. Memory with laminated cell
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916776A (zh) * 2014-03-11 2015-09-16 科洛斯巴股份有限公司 用于两端点存储器的选择器装置
US9613689B1 (en) * 2016-07-08 2017-04-04 Sandisk Technologies Llc Self-selecting local bit line for a three-dimensional memory array
CN110914994A (zh) * 2019-10-14 2020-03-24 长江存储科技有限责任公司 用于形成三维相变存储器件的方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
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US6483736B2 (en) * 1998-11-16 2002-11-19 Matrix Semiconductor, Inc. Vertically stacked field programmable nonvolatile memory and method of fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104916776A (zh) * 2014-03-11 2015-09-16 科洛斯巴股份有限公司 用于两端点存储器的选择器装置
US9613689B1 (en) * 2016-07-08 2017-04-04 Sandisk Technologies Llc Self-selecting local bit line for a three-dimensional memory array
CN110914994A (zh) * 2019-10-14 2020-03-24 长江存储科技有限责任公司 用于形成三维相变存储器件的方法

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