WO2023168696A1 - Dispositif de mémoire tridimensionnel et son procédé de fabrication - Google Patents

Dispositif de mémoire tridimensionnel et son procédé de fabrication Download PDF

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Publication number
WO2023168696A1
WO2023168696A1 PCT/CN2022/080348 CN2022080348W WO2023168696A1 WO 2023168696 A1 WO2023168696 A1 WO 2023168696A1 CN 2022080348 W CN2022080348 W CN 2022080348W WO 2023168696 A1 WO2023168696 A1 WO 2023168696A1
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Prior art keywords
bit line
cells
layer
gap
dummy
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PCT/CN2022/080348
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English (en)
Inventor
Heng Zhang
Jun Liu
Weifeng LEI
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Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
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Priority to PCT/CN2022/080348 priority Critical patent/WO2023168696A1/fr
Priority to CN202280001144.1A priority patent/CN114793471A/zh
Publication of WO2023168696A1 publication Critical patent/WO2023168696A1/fr

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides

Definitions

  • the present disclosure relates to three-dimensional (3D) memory devices, layouts, and the method of manufacturing thereof.
  • Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process.
  • feature sizes of the memory cells approach a lower limit
  • planar process and fabrication techniques become challenging and costly.
  • memory density for planar memory cells approaches an upper limit.
  • a three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.
  • the 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.
  • a phase-change memory PCM
  • PCM array cells can be vertically stacked in 3D to form a 3D PCM device.
  • a layout configuration of peripheral devices in a memory device corresponds to the patterns and arrangements of multiple peripheral units or components therein.
  • a memory device includes a plurality of bottom phase-change memory (PCM) cells, a plurality of top PCM cells on the plurality of bottom PCM cells, a plurality of bottom dummy cells at least partially surrounding the plurality of bottom PCM cells in the plan view, a plurality of top dummy cells on the plurality of bottom dummy cells, a first gap-filling layer between adjacent bottom PCM cells, a second gap-filling layer at least partially surrounding the plurality of bottom PCM cells in the plan view, a third gap-filling layer between adjacent top PCM cells, and a fourth gap-filling layer at least partially surrounding the plurality of top PCM cells in the plan view.
  • PCM phase-change memory
  • the first gap-filling layer has a better gap-filling capability than that of the second gap-filling layer
  • the third gap-filling layer has a better gap-filling capability than that of the fourth gap-filling layer.
  • the first gap-filling layer has a better heat-insulating capability than that of the second gap-filling layer
  • the third gap-filling layer has a better heat-insulating capability than that of the fourth gap-filling layer.
  • the first gap-filling layer comprises the same material as that of the third gap-filling layer
  • the second gap-filling layer comprises the same material as that of the fourth gap-filling layer
  • the first gap-filling layer includes ceramics, glass, air, polymers, other related heat insulating material, or a combination thereof.
  • a thermal conductivity of the first gap-filling layer is no more than 0.6 W/ (m ⁇ K) .
  • the second gap-filling layer includes silicon oxide, aluminum oxide, other related oxide material, or a combination thereof.
  • the memory device further includes a bottom bit line, a word line, a top bit line, a bottom bit line contact, a word line contact, and a top bit line contact.
  • the bottom bit line is connected between the bottom bit line contact and the bottom PCM cells
  • the word line is connected between the word line contact and the bottom PCM cells and between the word line contact and the top PCM cells
  • the top bit line is connected between the top bit line contact and the top PCM cells.
  • the memory device further includes a peripheral stack below the plurality of bottom PCM cells.
  • the peripheral stack includes a bottom bit line selector connected to the bottom bit line contact, a top bit line selector connected to the top bit line contact, and a word line driver connected to the word line contact.
  • a method of manufacturing a memory device includes forming a bottom bit line layer, forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer, filling a plurality of first trenches between adjacent bottom PCM cells and adjacent bottom dummy cells to form a first gap-filling layer, removing the first gap-filling layer outside of a memory region and patterning the bottom bit line layer in a dummy region to form a bottom bit line, forming a word line layer on the plurality of bottom PCM cells and the bottom dummy cells, forming a plurality of top PCM cells and a plurality of top dummy cells on the word line layer, filling a plurality of second trenches between adjacent top PCM cells and adjacent top dummy cells to form a third gap-filling layer, removing the third gap-filling layer outside of the memory region and patterning the word line layer in the dummy region to form a word line, forming a top bit line layer
  • the method further includes, after removing the first gap-filling layer outside of the memory region and patterning the bottom bit line layer in the dummy region, forming a word line contact.
  • the word line contact is connected between the word line layer and the bottom PCM cells.
  • the method further includes, after removing the first gap-filling layer outside of the memory region and patterning the bottom bit line layer in the dummy region, filling to form a second gap-filling layer covering the bottom PCM cells and the bottom dummy cells.
  • the method further includes, before forming the word line layer on the plurality of bottom PCM cells and the bottom dummy cells, applying a first planarization process to the second gap-filling layer to expose a first top surface of the bottom PCM cells.
  • the method further includes, after removing the third gap-filling layer outside of the memory region and patterning the word line layer in the dummy region, forming a top bit line contact.
  • the top bit line contact is connected between the top bit line layer and the top PCM cells.
  • the method further includes, after removing the third gap-filling layer outside of the memory region and patterning the word line layer in the dummy region, filling to form a fourth gap-filling layer covering the top PCM cells and the top dummy cells.
  • the method further includes, before forming the top bit line layer on the plurality of top PCM cells and the top dummy cells, applying a second planarization process to the fourth gap-filling layer to expose a second top surface of the top PCM cells.
  • a length of each the bottom bit line layer, the word line layer, and the top bit line layer is less than that of a memory block.
  • the bottom dummy cells are at least partially surrounding the bottom PCM cells in the memory block in the plan view.
  • patterning the bottom bit line layer in the dummy region to form the bottom bit line also patterning the bottom bit line layer in the memory region in a first lateral direction such that the bottom bit line in the memory region is extending in a second lateral direction.
  • patterning the word line layer in the dummy region to form the word line also patterning the word line layer in the memory region in the second lateral direction such that the word line in the memory region is extending in the first lateral direction.
  • patterning the top bit line layer in the dummy region to form the top bit line also patterning the top bit line layer in the memory region in the first lateral direction such that the top bit line in the memory region is extending in the second lateral direction.
  • a method of manufacturing a memory device includes forming a bottom bit line layer, forming a plurality of bottom PCM cells and a plurality of bottom dummy cells on the bottom bit line layer, patterning the bottom bit line layer in a dummy region to form a bottom bit line, forming a word line layer on the plurality of bottom PCM cells and the bottom dummy cells, forming a plurality of top PCM cells and a plurality of top dummy cells on the word line layer, patterning the word line layer in the dummy region to form a word line, forming a top bit line layer on the plurality of top PCM cells and the top dummy cells, and patterning the top bit line layer on the top dummy cells to form a top bit line.
  • a length of each of the bottom bit line layer, the word line layer, and the top bit line layer is less than that of a memory block, and the bottom dummy cells are at least partially surrounding the bottom PCM cells in the memory block in a plan view.
  • the method further includes, after patterning the bottom bit line layer in the dummy region, forming a word line contact.
  • the word line contact is connected between the word line layer and the bottom PCM cells.
  • the method further includes after patterning the word line layer in the dummy region, forming a top bit line contact.
  • the top bit line contact is connected between the top bit line layer and the top PCM cells.
  • patterning the bottom bit line layer in the dummy region to form the bottom bit line also patterning the bottom bit line layer in the memory region in a first lateral direction such that the bottom bit line in the memory region is extending in a second lateral direction.
  • patterning the word line layer in the dummy region to form the word line also patterning the word line layer in the memory region in the second lateral direction such that the word line in the memory region is extending in the first lateral direction.
  • patterning the top bit line layer in the dummy region to form the top bit line also patterning the top bit line layer in the memory region in the first lateral direction such that the top bit line in the memory region is extending in the second lateral direction.
  • FIG. 1 illustrates a perspective view of an exemplary 3D PCM device, according to some aspects of the present disclosure.
  • FIGs. 2A and 2B illustrate side views of cross-sections of an exemplary 3D PCM device, according to some aspects of the present disclosure.
  • FIG. 3 illustrates a perspective view of an exemplary 3D memory device including an exemplary 3D PCM device with interconnect layers, according to some aspects of the present disclosure.
  • FIGs. 4A and 4B illustrate side views of cross-sections of an exemplary 3D memory device including an exemplary 3D PCM device, interconnect layers, and peripheral devices, according to some aspects of the present disclosure.
  • FIGs. 5A and 5B illustrate side views of cross-sections of an exemplary 3D memory device including a 3D PCM device and interconnect layers, according to some aspects of the present disclosure.
  • FIGs. 6A-6L illustrate a fabrication process for forming an exemplary 3D memory device, according to some aspects of the present disclosure.
  • FIG. 7 illustrates a flowchart of a method for forming an exemplary 3D memory device, according to some aspects of the present disclosure.
  • references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some implementations, ” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other implementations whether or not explicitly described.
  • terminology may be understood at least in part from usage in context.
  • the term “one or more” as used herein, depending at least in part upon context may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense.
  • terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.
  • the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
  • spatially relative terms such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) , and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • the term “substrate” refers to a material onto which subsequent material layers are added.
  • the substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned.
  • the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc.
  • the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.
  • a layer refers to a material portion including a region with a thickness.
  • a layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface.
  • a substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow.
  • a layer can include multiple layers.
  • an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.
  • the term “3D” memory device or PCM device refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate.
  • the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.
  • a PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally.
  • phase-change materials e.g., chalcogenide alloys
  • the phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data.
  • PCM cells can be vertically stacked in 3D to form a 3D PCM device.
  • 3D PCM device stores data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array, to be bit-addressable.
  • memory devices With the development of memory device, more stacks of memory cells are arranged in a memory device.
  • multiple memory cells are stacked and arranged in a memory block.
  • multiple memory blocks are arranged in a single die.
  • memory blocks are arranged in a die having memory cells predetermined in certain areas of the die as memory regions, while dummy cells are arranged on dummy regions of the die between the adjacent memory blocks.
  • the dummy cells may have multiple usages depending on the circuit design.
  • the dummy cells are configured to work as storage capacitors, to be connected to a source line to provide bias voltages, or to be connected to a source of ground level.
  • One of the manufacturing methods of forming the memory cells in the memory blocks and the dummy cells are forming memory blocks first and then forming dummy cells around the memory blocks later.
  • the gaps between the dummy cells and the memory blocks may have some etch loading effects. That is, the depth of the etching cannot be well-controlled at the narrow block edge, thereby causing uneven distribution of the etch depth or even creating some leakage paths between the dummy cells and the memory cells.
  • the chemical mechanical polishing (CMP) or other planarization processes may not be easily performed at the block edge as well.
  • the low local pattern density at the block edge leads to an uneven surface, such as metal dishing or dielectric erosion after the CMP process. These also create more defects on memory cells at the block edge.
  • Another manufacturing method of forming the memory blocks and the dummy cells are forming both the memory cells and the dummy cells including the bit lines and word lines connected between memory cells and the dummy cells in a single process, and then cutting all the bit lines and word lines connected between adjacent dummy cells and also the bit lines and word lines connected between dummy cells and the memory cells. Therefore, the regions of the memory blocks are well-defined after the cutting process.
  • one of the issues is that the bit lines and word lines connected between cells and extending along the entire die are too long. The lengthy bit lines and word line may have a high peeling risk or bending issue during the fabrication, thereby creating some short circuits or contact failure issues between adjacent memory cells and thus reducing the overall performance and yield rate.
  • the present disclosure introduces the memory device and the method of manufacturing thereof in which the lithographic printing over the memory device is block-wise. That is, to solve the issue of full lithographic printing over the entire die in which it creates high peeling risk and bending issue of bit lines and word lines, by lithographic printing the memory cells and dummy cells block by block, the bit lines and word lines are less lengthy, and thus the peeling risk and bending issue are minimized.
  • the method includes forming a first semiconductor stack, patterning the first semiconductor stack to form bottom memory cells in a memory region and bottom dummy cells in a dummy region in which both bottom memory cells and bottom dummy cells are connected with sacrificial bottom bit lines, gap-filling the bottom memory cells and the bottom dummy cells to form a first gap-filling layer, planarizing (e.g., CMP) the first gap-filling layer until the top of the bottom memory cells and the bottom dummy cells, patterning to cut off the sacrificial bottom bit lines to form bottom bit lines and also to remove the first gap-filling layer outside of the memory region, forming a word line contact in a contact region, gap-filling the dummy region, the memory region, and the contact region to form a second gap-filling layer, planarizing the second gap-filling layer until the top of the bottom memory cells and the bottom dummy cells, forming sacrificial bottom word lines on the bottom
  • the method also includes forming a second semiconductor stack, patterning the second semiconductor stack to form top memory cells in the memory region and top dummy cells in the dummy region in which both the top memory cells and the top dummy cells are connected with the sacrificial top word lines, gap-filling the top memory cells and the top dummy cells to form a third gap-filling layer, planarizing (e.g., CMP) the third gap-filling layer until the top of the top memory cells and the top dummy cells, patterning to cut off the sacrificial top word lines to form top word lines and also to remove the third gap-filling layer outside of the memory region, forming a top bit line contact in the contact region, gap-filling the dummy region, the memory region, and the contact region to form a fourth gap-filling layer, planarizing the fourth gap-filling layer until the top of the top memory cells and the top dummy cells, forming sacrificial top bit lines on the top memory cells connected between the top bit line contact
  • the first gap-filling layer (and also the third gap-filling layer) and the second gap-filling layer (and also the fourth gap-filling layer) may include different material such that the first gap-filling layer formed between trenches of memory cells may provide a better gap fill capability to fill the trenches under narrower space compared with the second gap-filling layer. Also, the first gap-filling layer formed between trenches of memory cells may provide a better heat-insulating capability such that it can reduce the heat crosstalk, which may undesirably switch adjacent unselected memory cells.
  • the sacrificial bit lines and sacrificial word lines are deposited for only a block long, thereby minimizing the peeling risk and the bending issue of bit lines and word lines.
  • FIG. 1 illustrates a perspective view of an exemplary 3D PCM device 100, according to some implementations of the present disclosure.
  • 3D PCM device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors, according to some implementations.
  • 3D PCM device 100 includes one or more bottom bit lines 133 in the same plane and one or more parallel top bit lines 131 in the same plane above bottom bit lines 133.3D PCM device 100 also includes one or more parallel word lines (e.g., top word line 141, bottom word line 143, or a combination thereof) in the same plane vertically between bottom bit lines 133 and top bit lines 131. As shown in FIG.
  • each bottom bit line 133 and each top bit line 131 extend laterally along the bit line direction (e.g., x-direction) in the plan view (parallel to the wafer plane)
  • each word line 141/143 extends laterally along the word line direction (e.g., y-direction) in the plan view.
  • Each word line 141/143 is intersected with each bottom bit line 133 and each top bit line 131 in the plan view.
  • each word line 141/143 is perpendicular to each bottom bit line 133 and each top bit line 131.
  • the x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane.
  • the x-direction is the bit line direction
  • the y-direction is the word line direction.
  • the x-direction and the y-direction are exchangeable; that is, the x-direction may be the word line direction, and the y-direction may be the bit line direction.
  • the z-axis is included in FIG. 1 to further illustrate the spatial relationship of the components in 3D PCM device 100.
  • the substrate (not shown) of 3D PCM device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer.
  • the z-axis is perpendicular to both the x and y axes.
  • one component e.g., a layer or a device
  • another component e.g., a layer or a device
  • 3D PCM device 100 3D PCM device 100
  • 3D PCM device 100 includes one or more top PCM cells 151 each disposed at an intersection of top bit line 131 and respective word line 141/143, and one or more bottom PCM cells 153 each disposed at an intersection of bottom bit line 133 and respective word line 141/143.
  • each of top PCM cells 151 or bottom PCM cells 153 has a vertical square pillar shape.
  • each of top PCM cells 151 or bottom PCM cells 153 includes at least a PCM element and a selector stacked vertically. In some implementations, the selector is formed between bottom bit line 133 and the PCM element.
  • each of top PCM cells 151 or bottom PCM cells 153 further includes a heater connected to the PCM element.
  • Each of top PCM cells 151 or bottom PCM cells 153 stores a single bit of data and can be written or read by varying the voltage applied to the respective selector, which replaces the need for transistors.
  • Each of top PCM cells 151 or bottom PCM cells 153 is accessed individually by a current applied through the top and bottom conductors in contact with each PCM cell, e.g., respective word line 141/143 and top or bottom bit line 131 or 133.
  • Top PCM cells 151 or bottom PCM cells 153 in 3D PCM device 100 are arranged in a memory array.
  • the PCM element may include a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .
  • each of bit lines 131, 133, and word lines 141/143 includes a metal, such as tungsten.
  • the PCM element may be a binary (two-element) compound such as GaSb, InSb, InSe, SbTe, or GeTe, a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe, or a quaternary (four-element) compound such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe) , or TeGeSbS.
  • a binary (two-element) compound such as GaSb, InSb, InSe, SbTe, or GeTe
  • a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe
  • a quaternary (four-element) compound such as AgInSbTe, (GeSn) SbT
  • the selector may be an ovonic threshold switch (OTS) device made of at least one of oxygen (O) , sulfur (S) , selenium (Se) , tellurium (Te) , germanium (Ge) , antimony (Sb) , silicon (Si) , or arsenic (As) .
  • OTS ovonic threshold switch
  • the OTS device is formed by OTS material exhibiting an OTS property.
  • 3D PCM device 100 may also include one or more top bit line contacts 121 connected to top bit line 131, one or more bottom bit line contacts 123 connected to bottom bit line 133, and one or more word line contacts 125 connected to word lines 141/143.
  • Top bit line contacts 121, bottom bit line contacts 123, and word line contacts 125 may extend vertically in a z-direction.
  • each of top bit line contacts 121, bottom bit line contacts 123, and word line contacts 125 includes a metal, such as tungsten.
  • FIGs. 2A and 2B illustrate side views of schematic cross-sections of an exemplary 3D PCM device 100, according to some aspects of the present disclosure.
  • 3D PCM device 100 in a y-z plane cross-section, includes one or more parallel top bit lines 131 formed on top PCM cells 151, and one or more parallel bottom bit lines 133 formed below the bottom PCM cells 153.
  • Word lines 141/143 extend laterally in the y-direction between top PCM cells 151 and bottom PCM cells 153.
  • 3D PCM device 100 in an x-z plane cross-section, includes top bit lines 131 extending laterally in the x-direction and connected to top bit line contact 121, which extends vertically in the z-direction. 3D PCM device 100 further includes bottom bit lines 133 extending laterally in the x-direction and connected to bottom bit line contact 123, which extends vertically in the z-direction. In some implementations, top bit line contact 121 and word line contact 125 extend vertically in regions where no top or bottom PCM cells 151 or 153 are formed above or below.
  • FIG. 3 illustrates a perspective view of an exemplary 3D PCM device 300, according to some implementations of the present disclosure.
  • 3D PCM device 300 includes one or more parallel bottom bit lines 333 (e.g., corresponding to bottom bit lines 133 in FIG. 1) , one or more parallel top bit lines 331 (e.g., corresponding to bottom bit lines 131 in FIG. 1) in the same plane above bottom bit lines 333, one or more parallel word lines 341/343 (e.g., corresponding to word lines 141/143 in FIG. 1) in the same plane vertically between bottom bit lines 333 and top bit lines 331. As shown in FIG.
  • each bottom bit line 333 and each top bit line 331 extend laterally along the bit line direction (e.g., x-direction) in the plan view (parallel to the wafer plane)
  • each word line 341/343 extends laterally along the word line direction (e.g., y-direction) in the plan view.
  • Each word line 341/343 is intersected with each bottom bit line 333 and each top bit line 331 in the plan view.
  • each word line 341/343 is perpendicular to each bottom bit line 333 and each top bit line 331.
  • 3D PCM device 300 includes one or more top PCM cells 351 (e.g., corresponding to top PCM cells 151 in FIG. 1) each disposed at an intersection of top bit line 331 and respective word line 341/343, and one or more bottom PCM cells 353 (e.g., corresponding to top PCM cells 153 in FIG. 1) each disposed at an intersection of bottom bit line 333 and respective word line 341/343.
  • each of top PCM cells 351 or bottom PCM cells 353 has a vertical square pillar shape.
  • each of top PCM cells 351 or bottom PCM cells 353 includes at least a PCM element (not shown) and a selector (not shown) stacked vertically.
  • Each of top PCM cells 351 or bottom PCM cells 353 stores a single bit of data and can be written or read by varying the voltage applied to the respective selector (not shown) , which replaces the need for transistors.
  • Each of top PCM cells 351 or bottom PCM cells 353 is accessed individually by a current applied through the top and bottom conductors in contact with each PCM cell, e.g., respective word line 341/343 and top or bottom bit line 331 or 333.
  • Top PCM cells 351 or bottom PCM cells 353 in 3D PCM device 300 are arranged in a memory array.
  • 3D PCM device 300 may also include one or more top bit line contacts 321 (e.g., corresponding to top bit line contact 121 in FIG.
  • top bit line contacts 321, bottom bit line contacts 323, and word line contacts 325 may extend vertically in a z-direction.
  • each of top bit line contact 321, bottom bit line contact 323, and word line contact 325 includes a metal, such as tungsten.
  • 3D PCM device 300 may include one or more top interconnect layer 365 (a.k.a. top metal layer or M5 layer) extending laterally above the memory cells (e.g., top PCM cells 351 or bottom PCM cells 353) of the memory array.
  • 3D PCM device 300 may further include one or more first interconnect layer 364 (a.k.a. M4 layer) extending laterally below PCM cells 351/353 of the memory array.
  • 3D PCM device 300 may further include one or more through via contacts 327 extending vertically (e.g., in a z-direction) and connected between top interconnect layer 365 and first interconnect layer 364.
  • FIGs. 4A and 4B illustrate side views of schematic cross-sections of an exemplary 3D PCM device 300, according to some aspects of the present disclosure.
  • 3D PCM device 300 in a y-z plane cross-section, includes one or more parallel top bit lines 331 formed on top PCM cells 351 extending in the x-direction, and one or more parallel bottom bit lines 333 formed below bottom PCM cells 353 extending the x-direction.
  • Top bit lines 331 are connected to top bit line contacts 321, and bottom bit lines 333 are connected to bottom bit line contacts 323.
  • Word lines 341/343 extend laterally in the y-direction between top PCM cells 351 and bottom PCM cells 353.
  • Word lines 341/343 are also connected to word line contact 325.
  • Top interconnect layer 365 (a.k.a. top metal layer or M5 layer) extends laterally (e.g., in the x-or y-direction) above PCM cells 351/353 of the memory array. In some implementations, top interconnect layer 365 extends in a y-direction, which is perpendicular to bit lines and parallel to word lines. First interconnect layer 364 extends laterally in the x-direction or the y-direction below PCM cells 351/351 of the memory array. Through via contacts 327 extend vertically in the z-direction and is connected between top interconnect layer 365 and first interconnect layer 364. In some implementations, through via contacts 327 may further extend until the substrate, into the substrate, or penetrating the substrate. Since the FIGs. 4A and 4B are only for illustration, a partially enlarged side view 500 of exemplary 3D PCM device 300 will be discussed later to illustrate more detailed structures.
  • 3D PCM device 300 in an x-z plane cross-section, includes top bit lines 331 extending laterally in the x-direction and connected to top bit line contact 321, which extends vertically in the z-direction. 3D PCM device 300 further includes bottom bit lines 333 extending laterally in the x-direction and connected to bottom bit line contact 323, which extends vertically in the z-direction. In some implementations, top bit line contact 321, and word line contact 325 extend vertically in regions where no top PCM cells 351 or bottom PCM cells 353 are formed above or below.
  • 3D PCM device 300 may further include one or more peripheral blocks located underneath the memory array.
  • the peripheral blocks may include one or more peripheral units including bottom bit line selector 303, word line driver 305, or top bit line selector 301.
  • 3D PCM device 300 includes a substrate 307.
  • the one or more peripheral units include bottom bit line selector 303, word line driver 305, or top bit line selector 301 formed on substrate 307.
  • Word line driver 305 may be connected to word lines 341/343 via word line contact 325.
  • Multiple interconnect layers e.g., top interconnect layer 365, first interconnect layer 364, second interconnect layer 363 (a.k.a.
  • Substrate 307 may include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials.
  • each of the word line drivers includes p-channel metal–oxide–semiconductor (PMOS) transistor, n-channel metal–oxide–semiconductor (NMOS) transistor, or a combination thereof.
  • PMOS metal–oxide–semiconductor
  • NMOS n-channel metal–oxide–semiconductor
  • the peripheral units and the substrate can be referred to as a peripheral stack 309, and the memory cells that formed on peripheral stack 309 can be referred to as a memory stack.
  • FIGs. 5A and 5B are partially enlarged side views 500 of FIGs. 4A and 4B illustrating cross-sections of the exemplary 3D PCM device 300. Since FIGs. 5A and 5B (and also the FIGs. 6A-6L) focus only on the memory stack, it is noted that peripheral stack 309 located below the memory stack remains the same or similar as to those in FIGs. 4A and 4B.
  • 3D PCM device 300 includes bottom PCM cells 353 and top PCM cells 351 on bottom PCM cells 353. Bottom PCM cells 353 are connected to one or more bottom bit line contacts 323 via one or more bottom bit lines 333. And top PCM cells 351 are connected to one or more top bit line contacts 321 via one or more top bit lines 331. Word lines 341/343 are between top PCM cells and bottom PCM cells and extending in the y-direction.
  • a first gap-filling layer 371 is formed and filled between adjacent bottom PCM cells 353.
  • first gap-filling layer 371 is filled in a memory region 381-an area where the memory cells are located.
  • a second gap-filling layer 373 is formed and filled outside of memory region 381 and may be formed within a contact region 385-an area where the contacts (e.g., word line contacts 325 and/or top bit line contacts 321) are located.
  • Second gap-filling layer 373 is at least partially surrounding first gap-filling layer 371 or bottom PCM cells 353 in a plan view. As such, second gap-filling layer 373 is at least partially surrounding memory region 381 in a plan view.
  • first gap-filling layer 371 may include ceramics, glass, air, polymers, other related heat insulating material, or a combination thereof (e.g., polymers surrounding air) . In some implementations, a thermal conductivity of first gap-filling layer 371 is no more than 0.6 W/ (m ⁇ K) .
  • second gap-filling layer 373 may include silicon oxide, aluminum oxide, other related oxide material, or a combination thereof. In some implementations, first gap-filling layer 371 has a better gap-filling capability than that of second gap-filling layer 373 since first gap-filling layer 371 is configured to fill into the trenches between adjacent bottom PCM cells 353. In some implementations, first gap-filling layer 371 has a better heat-insulating capability such that it can reduce the heat crosstalk, which may undesirably switch adjacent unselected memory cells.
  • a third gap-filling layer 375 is formed and filled between adjacent top PCM cells 351.
  • third gap-filling layer 375 is filled in memory region 381.
  • a fourth gap-filling layer 377 is formed and filled outside of memory region 381 and may be formed within contact region 385.
  • Fourth gap-filling layer 377 is at least partially surrounding third gap-filling layer 375 or top PCM cells 351 in a plan view.
  • fourth gap-filling layer 377 is at least partially surrounding memory region 381 in a plan view.
  • third gap-filling layer 375 may include ceramics, glass, air, polymers, other related heat insulating material, or a combination thereof (e.g., polymers surrounding air) .
  • a thermal conductivity of third gap-filling layer 375 is no more than 0.6 W/ (m ⁇ K) .
  • fourth gap-filling layer 377 may include silicon oxide, aluminum oxide, other related oxide material, or a combination thereof.
  • third gap-filling layer 375 has a better gap-filling capability than that of fourth gap-filling layer 377 since third gap-filling layer 375 is configured to fill into the trenches between adjacent top PCM cells 351.
  • third gap-filling layer 375 has a better heat-insulating capability such that it can reduce the heat crosstalk, which may undesirably switch adjacent unselected memory cells. It is noted that third gap-filling layer 375 may include the same or similar material as that of first gap-filling layer 371. Also, fourth gap-filling layer 377 may include the same or similar material as that of second gap-filling layer 373.
  • FIG. 5B illustrates another side view of cross-sections of the exemplary 3D PCM device 300.
  • 3D PCM device 300 may further include dummy cells (e.g., top dummy cells 355 and bottom dummy cells 357) arranged to surround the memory cells (e.g., top PCM cells 351 and bottom PCM cells 353) in a memory block.
  • These dummy cells 355/357 are located in one or more dummy regions 383.
  • These dummy regions 383 may at least partially surround memory region 381 in the memory block in a plan view.
  • these dummy cells are configured to work as storage capacitors, to be connected to a source line to provide bias voltages, or to be connected to a source of ground level.
  • second gap filling layer may not be formed and filled between adjacent dummy cells 355/357 in dummy region 383, or may only be partially formed and filled between adjacent dummy cells 355/357.
  • FIGs. 6A-6L illustrate a fabrication process for forming an exemplary 3D memory device, according to some aspects of the present disclosure.
  • FIG. 7 illustrates a flowchart of a method for forming an exemplary 3D memory device, according to some aspects of the present disclosure.
  • the 3D memory device may be any suitable 3D memory device disclosed herein. It is understood that the operations shown in method 700 may not be exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7. FIGs. 6A-6L and FIG. 7 may be discussed together.
  • method 700 starts at operation 702 in which a plurality of bottom memory cells and a plurality of bottom dummy cells are formed on a peripheral stack. Furthermore, a plurality of first trenches between adjacent bottom memory cells are filled with a first gap-filling material to form a first gap-filling layer.
  • a plurality of bottom PCM cells 353 and a plurality of bottom dummy cells 357 are formed on a peripheral stack (e.g., 309 in FIGs. 4A and 4B) .
  • bottom PCM cells 353 and bottom dummy cells 357 may be formed by depositing a bottom bit line layer, and a first semiconductor stack on the bottom bit line layer.
  • the bottom bit line layer is deposited only for a memory block long. That is, the bottom bit line layer may not extend from one memory block to another. The length of the bottom bit line layer is less than that of the memory block. As such, the peeling risk or bending issue is minimized.
  • the first semiconductor stack may include a first bottom electrode layer, a first selector layer on the first bottom electrode layer, a first PCM element layer on the first selector layer, and a first top electrode layer on the first PCM element layer. By further etching or patterning the first semiconductor stack, bottom PCM cells 353 and bottom dummy cells 357 are formed.
  • etching or patterning to form bottom PCM cells 353 and bottom dummy cells 357 includes a two-step etching process (a.k.a. double patterning process) . That is, a first step etching is applied upon the first semiconductor stack to form first trenches 391 between adjacent bottom PCM cells 353, and a second step etching is applied to cut off the bottom bit line layer in the y-direction to form bottom bit line 333 extending in the x-direction.
  • a first step etching is applied upon the first semiconductor stack to form first trenches 391 between adjacent bottom PCM cells 353, and a second step etching is applied to cut off the bottom bit line layer in the y-direction to form bottom bit line 333 extending in the x-direction.
  • a second step etching is applied to cut off the bottom bit line layer in the y-direction to form bottom bit line 333 extending in the x-direction.
  • first trenches 391 between adjacent bottom PCM cells 353 are filled with a first gap-filling material 3711.
  • a chemical mechanical polishing (CMP) or planarization can be applied to first gap-filling material 3711 until a top surface of bottom PCM cells 353 such that the top surface of bottom PCM cells 353 is exposed.
  • Method 700 proceeds to operation 704, as illustrated in FIG. 7 in which the first gap-filling layer outside of a memory region is removed. Furthermore, a word line contact is formed thereafter. For example, as shown in FIG. 6C, by removing first gap-filling material 3711 outside of memory region 381, first gap-filling layer 371 is formed only on memory region 381. In some implementations, first gap-filling material 3711 in contact region 385 and dummy region 383 are removed. The removal can be done by wet etching, dry etching, or a combination thereof.
  • a word line contact 325 is formed in contact with, for instance, the first interconnect layer (a.k.a. M4 layer 364 in FIG. 4B) .
  • Word line contact 325 is configured to extend vertically (e.g., in the z-direction) and connect between the word line and the peripheral units below the memory stack.
  • a second gap-filling layer 373 is then filled and covering first gap-filling layer 371, bottom PCM cells 353, bottom dummy cells 357, and word line contact 325.
  • CMP chemical mechanical polishing
  • planarization can be applied to second gap-filling material 373 until a top surface of bottom PCM cells 353 such that the top surface of bottom PCM cells 353 is exposed.
  • Method 700 proceeds to operation 706, as illustrated in FIG. 7 in which a word line connected between the word line contact and the plurality of bottom memory cells are formed.
  • a bottom word line layer 3431 is formed and connected between word line contact 325, bottom PCM cells 353, and bottom dummy cells 357.
  • bottom word line layer 3431 is deposited only for a memory block long. That is, bottom word line layer 3431 may not extend from one memory block to another. The length of bottom word line layer 3431 is less than that of the memory block. As such, the peeling risk or bending issue is minimized.
  • an etching or patterning (e.g., a double patterning) is applied to remove a portion of second gap-filling layer 373 in dummy region 383 and to cut off bottom word line layer 3431 to form bottom word line 343. That is, a first step etching is applied to cut off bottom word line layer 3431 in the x-direction to form bottom word line 343 extending in the y-direction. And then, a second step etching is applied to remove the portion of second gap-filling layer 373 in dummy region 383. Bottom word line 343 can be connected between word line contact 325 and bottom PCM cells 353 shown in another cross-sectional view. When patterning bottom word line layer 3431, it is also patterning bottom word line layer 3431 in dummy region 383 such that the dummy cells are isolated from each other.
  • a first step etching is applied to cut off bottom word line layer 3431 in the x-direction to form bottom word line 343 extending in the y-direction.
  • Method 700 proceeds to operation 708, as illustrated in FIG. 7 in which a plurality of top memory cells are formed on the plurality of bottom memory cells. Furthermore, a plurality of second trenches between adjacent top memory cells are filled to form a third gap-filling layer.
  • top PCM cells 351 are formed on bottom PCM cells 353, and top dummy cells 355 are formed on bottom dummy cells 357. Same or similar to forming bottom PCM cells 353 and bottom dummy cells 357, top PCM cells 351 and top dummy cells 355 may be formed by depositing a top word line layer, and a second semiconductor stack on the top word line layer.
  • the second semiconductor stack may include a second bottom electrode layer, a second selector layer on the second bottom electrode layer, a second PCM element layer on the second selector layer, and a second top electrode layer on the second PCM element layer.
  • second trenches 393 between adjacent top PCM cells 351 are filled with a third gap-filling material 3751.
  • a chemical mechanical polishing (CMP) or planarization can be applied to third gap-filling material 3751 until a top surface of top PCM cells 351 such that the top surface of top PCM cells 351 is exposed.
  • Method 700 proceeds to operation 710, as illustrated in FIG. 7 in which the third gap-filling layer outside of the memory region is removed, and a top bit line contact is formed. For instance, as shown in FIG. 6I, an etching or patterning process is applied to remove third gap-filling material 3751 in dummy region 383 and contact region 385 to form third gap-filling layer 375.
  • top bit line contact 321 is formed in contact with, for instance, another first interconnect layer (a.k.a. M4 layer 364 in FIG. 4B) .
  • Method 700 proceeds to operation 712, as illustrated in FIG. 7 in which a top bit line connected between the top bit line contact and the plurality of top memory cells is formed.
  • a top bit line connected between the top bit line contact and the plurality of top memory cells is formed.
  • a fourth gap-filling material (not shown) is filled and covering third gap-filling layer 375, top PCM cells 351, top dummy cells 355, and top bit line contact 321.
  • top bit line layer 3311 connected between top bit line contact 321 and top PCM cells 351 is deposited.
  • top bit line layer 3311 is deposited only for a memory block long. That is, top bit line layer 3311 may not extend from one memory block to another. The length of top bit line layer 3311 is less than that of the memory block. As such, the peeling risk or bending issue is minimized.
  • an etching or patterning (e.g., a double patterning) is applied to remove a portion of fourth gap-filling layer 377 in dummy region 383 and cut off top bit line layer 3311 (e.g., in FIG. 6K) to form top bit line 331. That is, a first step etching is applied to cut off top bit line layer 3311 in the x-direction to form top bit line 331 extending in the y-direction. And then, a second etching step is applied to remove a portion of fourth gap-filling layer 377 in dummy region 383.
  • a first step etching is applied to cut off top bit line layer 3311 in the x-direction to form top bit line 331 extending in the y-direction.
  • a second etching step is applied to remove a portion of fourth gap-filling layer 377 in dummy region 383.
  • top bit line layer 3311 in memory region 381 it is also patterning top bit line layer 3311 in dummy region 383 such that the dummy cells are isolated from each other. It is also noted that top bit line 331 can be connected between top bit line contact 321 and top PCM cells 351 in another cross-sectional view.

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Abstract

Selon certains aspects, un dispositif de mémoire comprend une pluralité de cellules de mémoire à changement de phase (PCM) inférieures, une pluralité de cellules PCM supérieures sur la pluralité de cellules PCM inférieures, une pluralité de cellules factices inférieures entourant au moins partiellement la pluralité de cellules PCM inférieures sur une vue en plan, une pluralité de cellules factices supérieures sur la pluralité de cellules factices inférieures, une première couche de remplissage entre les cellules PCM inférieures adjacentes, une deuxième couche de remplissage entourant au moins partiellement la pluralité de cellules PCM inférieures sur la vue en plan, une troisième couche de remplissage entre les cellules PCM supérieures adjacentes, et une quatrième couche de remplissage entourant au moins partiellement la pluralité de cellules PCM supérieures sur la vue en plan.
PCT/CN2022/080348 2022-03-11 2022-03-11 Dispositif de mémoire tridimensionnel et son procédé de fabrication WO2023168696A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100127234A1 (en) * 2008-11-21 2010-05-27 Park Hae Chan Phase change memory device having an increased sensing margin for cell efficiency and method for manufacturing the same
CN112234140A (zh) * 2020-12-11 2021-01-15 长江先进存储产业创新中心有限责任公司 相变存储器及其制造方法、读取方法
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CN113517310A (zh) * 2021-04-02 2021-10-19 长江先进存储产业创新中心有限责任公司 一种半导体器件及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100127234A1 (en) * 2008-11-21 2010-05-27 Park Hae Chan Phase change memory device having an increased sensing margin for cell efficiency and method for manufacturing the same
CN112234140A (zh) * 2020-12-11 2021-01-15 长江先进存储产业创新中心有限责任公司 相变存储器及其制造方法、读取方法
CN112951994A (zh) * 2021-03-11 2021-06-11 长江先进存储产业创新中心有限责任公司 一种三维存储器及散热管道的形成方法
CN113517310A (zh) * 2021-04-02 2021-10-19 长江先进存储产业创新中心有限责任公司 一种半导体器件及其制造方法

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