WO2022048124A1 - 一种光电芯片封装结构及其封装方法 - Google Patents

一种光电芯片封装结构及其封装方法 Download PDF

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Publication number
WO2022048124A1
WO2022048124A1 PCT/CN2021/079336 CN2021079336W WO2022048124A1 WO 2022048124 A1 WO2022048124 A1 WO 2022048124A1 CN 2021079336 W CN2021079336 W CN 2021079336W WO 2022048124 A1 WO2022048124 A1 WO 2022048124A1
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Prior art keywords
optical
chip
layer
redistribution
conductive plug
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PCT/CN2021/079336
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English (en)
French (fr)
Inventor
曹立强
王全龙
严阳阳
戴风伟
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华进半导体封装先导技术研发中心有限公司
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Publication of WO2022048124A1 publication Critical patent/WO2022048124A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4204—Packages, e.g. shape, construction, internal or external details the coupling comprising intermediate optical elements, e.g. lenses, holograms
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/14—Mode converters
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4219—Mechanical fixtures for holding or positioning the elements relative to each other in the couplings; Alignment methods for the elements, e.g. measuring or observing methods especially used therefor
    • G02B6/4236—Fixing or mounting methods of the aligned elements
    • G02B6/424—Mounting of the optical light guide
    • G02B6/4243—Mounting of the optical light guide into a groove
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4249—Packages, e.g. shape, construction, internal or external details comprising arrays of active devices and fibres
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/24—Coupling light guides
    • G02B6/42—Coupling light guides with opto-electronic elements
    • G02B6/4201—Packages, e.g. shape, construction, internal or external details
    • G02B6/4274—Electrical aspects
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12038—Glass (SiO2 based materials)
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12035—Materials
    • G02B2006/12061—Silicon
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12133—Functions
    • G02B2006/12138—Sensor
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12133—Functions
    • G02B2006/12142—Modulator
    • G—PHYSICS
    • G02—OPTICS
    • G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12—Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B2006/12133—Functions
    • G02B2006/12152—Mode converter

Definitions

  • the present application relates to the field of packaging, and in particular, to an optoelectronic chip packaging structure and a packaging method thereof.
  • Optical communication is a communication method in which light waves are used as carriers. With the development of technology, the amount of communication data is getting larger and larger, so the requirements for the transmission rate of optical communication modules are getting higher and higher.
  • the optoelectronic chip integrated structure is the core component of the optical communication module.
  • the photoelectric chip integration result integrates the photonic chip and the electric chip of its peripheral circuit together to realize the function of converting between the optical signal and the electric signal.
  • One edge of the optical chip has an optical coupling area, and the optical coupling area generally has a mode spot converter.
  • One end of the mode spot converter has a larger mode spot size that matches the mode spot size of the optical fiber.
  • the other end has a smaller mode spot size to match the mode spot size of the waveguide in the optical chip, and the mode spot converter is used to reduce the optical connection loss between the optical fiber and the waveguide in the optical chip.
  • the mode spot converter Even if the mode spot converter is used, the optical signal leakage from the area of the mode spot converter to the outside (optical chip silicon substrate) still exists. Therefore, it is a problem that needs to be solved to reduce the leakage of the optical signal to the outside of the optical coupling region.
  • the optical coupling area needs to avoid contamination and increase the strength of the coupling area to ensure package reliability.
  • the technical problem to be solved by the present application is to overcome how to simultaneously improve the packaging reliability and reduce the light leakage in the prior art.
  • the present application also provides an optoelectronic chip packaging structure, comprising: an optical chip, the optical chip includes an optical medium layer, and an edge region of one side of the optical medium layer is an optical coupling region; The protective structure on the surface of the light coupling region, the refractive index of the protective structure is smaller than the refractive index of the optical medium layer.
  • the refractive index of the protective structure is 94%-99% of the refractive index of the optical medium layer.
  • the material of the protective structure is quartz glass doped with modified ions, and the modified ions include fluoride ions or boron ions; or, the material of the protective structure is magnesium fluoride.
  • the thickness of the protection structure in contact with the surface of the light coupling region is 300 micrometers to 800 micrometers.
  • the protection structure protrudes from the sidewall of the light coupling region; the protection structure has a positioning groove, and the positioning groove is used for positioning and assembling the optical fiber.
  • the shape of the positioning groove includes a "V" shape.
  • the positioning groove has a first side wall and a second side wall connected to the first side wall, the first side wall is flush with the side wall of the light coupling area and is suitable for being connected with the optical fiber.
  • Part of the end faces are opposite to each other, and the second side wall is adapted to be in contact with the side wall of the optical fiber.
  • it further includes: an optical fiber structure located in the positioning groove; the optical fiber structure is a single optical fiber; or the optical fiber structure is an optical fiber array.
  • it further includes: a first electrical chip disposed on the front side of the optical chip, the first electrical chip is electrically connected to the optical chip, and the first electrical chip is located on the side of the protection structure; and a plastic sealing layer, wherein the plastic sealing layer integrally seals the front surface of the optical chip, the first electrical chip and the protection structure.
  • the method further includes: the optical chip further includes an optical core semiconductor substrate located at the bottom of the optical medium layer, and the optical core semiconductor substrate exposes the light coupling region.
  • it further includes: a first conductive plug penetrating the optical medium layer and the optical core semiconductor substrate; a first redistribution layer located on the back of the optical chip; one end of the first conductive plug The first electrical chip is electrically connected, the other end of the first conductive plug is connected to the first redistribution layer; the first solder ball is electrically connected to the first redistribution layer.
  • the first redistribution structure located on the back of the optical chip, the first redistribution structure is located on the surface of the optical medium layer, and the first redistribution structure exposes the light coupling region, so
  • the first redistribution structure includes a first insulating layer and a first redistribution layer located in the first insulating layer.
  • it further includes: a first conductive plug penetrating the optical medium layer; one end of the first conductive plug is electrically connected to the first electrical chip, and the other end of the first conductive plug is connected to the first electrical chip.
  • the first redistribution layer is connected; the first solder ball is electrically connected to the first redistribution layer; the second electrical chip is located on the back of the optical chip, and the second electrical chip is connected to the first solder ball .
  • it further includes: a second redistribution layer located on the surface of the plastic sealing layer and facing the back of the first electrical chip; a second conductive plug penetrating the plastic sealing layer, the second conductive plug One end is electrically connected to the first electrical chip, the other end of the second conductive plug is connected to the second redistribution layer; the second solder ball is electrically connected to the second redistribution layer.
  • the present application also provides a packaging method for an optoelectronic chip packaging structure, including: providing an optical chip, the optical chip includes an optical medium layer, and an edge region of one side of the optical medium layer is an optical coupling region; A protective structure in contact with the surface of the light coupling region is formed on the front side, and the refractive index of the protective structure is smaller than that of the optical medium layer.
  • it further includes: disposing a first electrical chip on the front side of the optical chip, and the first electrical chip is electrically connected to the optical chip; after the protection structure is formed, the first electrical chip is located in the optical chip. Protecting the side of the structure; forming a plastic encapsulation layer, the plastic encapsulation layer integrally encapsulates the front surface of the optical chip, the first electrical chip and the protective structure.
  • the optical chip further includes an optical core semiconductor substrate located at the bottom of the optical medium layer; the packaging method further includes: before disposing the first electrical chip and forming the protection structure, A first conductive plug is formed in the optical medium layer and the optical core semiconductor substrate; an optical core redistribution layer is formed on the front side of the optical chip, and the optical core redistribution layer is respectively connected with the first conductive plug and the first electrical chip ; After forming the plastic encapsulation layer, a first redistribution layer structure is formed on the back of the optical core semiconductor substrate, and the first redistribution layer structure includes a first redistribution layer, the first redistribution layer and the the first conductive plug is connected; first solder balls are formed on the surface of the first redistribution layer structure; after the first solder balls are formed, dicing is performed.
  • the method further includes: etching and removing the optical core semiconductor substrate at the bottom of the light coupling region to expose the light coupling region.
  • the optical chip further includes an optical core semiconductor substrate located at the bottom of the optical medium layer; the packaging method further includes: after disposing the first electrical chip and forming the first electrical chip.
  • a first conductive plug is formed in the optical medium layer, an optical core redistribution layer is formed on the front side of the optical chip, and the optical core redistribution layer is respectively connected to the first conductive plug and the first conductive plug.
  • a second conductive plug is formed above the front surface of the optical chip; after the plastic encapsulation layer is formed, the plastic encapsulation layer also integrally encapsulates the second conductive plug, and The plastic sealing layer exposes the top surface of the second conductive plug; a second redistribution layer is formed on the surface of the plastic sealing layer, and the second redistribution layer is connected to the second conductive plug; the second redistribution layer is formed; After the redistribution layer, the optical core semiconductor substrate is removed; after the optical core semiconductor substrate is removed, a first redistribution structure is formed on the back side of the optical medium layer, and the first redistribution structure includes a first redistribution layer, the first redistribution layer is connected to the first conductive plug.
  • the method further includes: removing the first redistribution structure at the bottom of the light coupling region to expose the light coupling region.
  • it further includes: after forming the first redistribution structure, forming second solder balls on the surface of the second redistribution layer; after forming the second solder balls, performing dicing cutting; after dicing and cutting, A second electrical chip is mounted on the first redistribution layer through the first solder balls.
  • the protection structure protrudes from the sidewall of the light coupling region; the protection structure has a positioning groove; an optical fiber structure is provided, and the optical fiber structure is positioned and assembled in the positioning groove.
  • the front surface of the optical chip has a protective structure in contact with the surface of the optical coupling area, so that there is no cavity between the optical coupling area and the protective structure, and the front surface of the optical coupling area is The protection structure is limited, so the light coupling area is not easy to warp, and the reliability of the package is improved. Since the refractive index of the protective structure is smaller than the refractive index of the optical medium layer, the light in the light coupling region is not easily leaked to the protective structure. Therefore, the performance of the optoelectronic chip package structure is improved.
  • a protective structure in contact with the surface of the optical coupling area is formed on the front side of the optical chip, so that there is no cavity between the optical coupling area and the protective structure, and the optical coupling
  • the front side of the region is limited by the protective structure, so the light coupling region is not easily warped, and the reliability of the package is improved. Since the refractive index of the protective structure is smaller than the refractive index of the optical medium layer, the light in the light coupling region is not easily leaked to the protective structure. Therefore, the performance of the optoelectronic chip package structure is improved.
  • Fig. 1 is a kind of photoelectric chip packaging structure
  • FIGS. 2 to 12 are schematic structural diagrams of a process of forming an optoelectronic chip packaging structure according to an embodiment of the present application
  • 13 to 24 are schematic structural diagrams of a process of forming an optoelectronic chip package structure provided by another embodiment of the present application.
  • An optoelectronic chip packaging structure includes: an optical chip including an optical core semiconductor substrate 110 and an optical interconnection structure 111; an electrical chip 150 (150-1, 150-2); a cover plate 160; The plastic sealing layer 170 ; the conductive connection member 120 ; the first wiring layer 130 ; the second wiring layer 140 ; the solder balls 180 .
  • one side of the optical interconnect structure 111 has a light coupling region, and the light coupling region has a mode spot converter.
  • the material of the cover plate 160 is usually glass, and the cover plate 160 is not in contact with the light coupling region. , but a cavity is formed suspended between the cover plate 160 and the light coupling region. There is a cavity between the cover plate 160 and the light coupling region, and the refractive index inside the cavity is smaller than the refractive index of the dielectric layer of the optical interconnect structure 111, so that the light in the light coupling region is not easy to reach the space between the cover plate 160 and the light coupling region. leaks inside the cavity.
  • the thickness of the semiconductor substrate 110 under the light coupling region is partially removed. Specifically, etching holes are formed in the light coupling region of the optical interconnection structure 111, The optical core semiconductor substrate 110 located at the bottom of the etched hole is etched to remove a part of the thickness of the semiconductor substrate 110 at the bottom of the optical coupling region, so that a bottom cavity is formed between the semiconductor substrate 110 and the optical coupling region of the optical interconnection structure 111 .
  • a bottom cavity is formed between the semiconductor substrate 110 and the optical coupling region of the optical interconnection structure 111, and since there is no effective support between the cover plate 160 and the optical coupling region, and the thickness of the optical coupling region is relatively thin, the thickness is 4 ⁇ m- Therefore, when the temperature changes, the photocoupling region is not restricted by other structures and is easily warped, which affects the reliability of the package.
  • an embodiment of the present application provides an optoelectronic chip packaging structure, including: an optical chip, the optical chip includes an optical medium layer, and an edge region of one side of the optical medium layer is an optical coupling region; A protective structure on the front surface of the optical chip and in contact with the surface of the light coupling region, the refractive index of the protective structure is smaller than the refractive index of the optical medium layer.
  • the optoelectronic chip packaging structure improves packaging reliability and reduces light leakage.
  • an optical chip 200 is provided, the optical chip 200 includes an optical medium layer 210 and an optical core semiconductor substrate 220 located at the bottom of the optical medium layer 210 , and an edge region of one side of the optical medium layer 210 is for optical coupling District A.
  • the optical medium layer 210 has several optical units, the optical units include an optical waveguide, a modulator, a detector, and a mode spot converter, wherein the mode spot converter is located in the light coupling area A, the Optical waveguides, modulators and detectors are located on the side of the optical coupling region A.
  • the host material of the optical medium layer 210 includes silicon oxide.
  • the material of the optical core semiconductor substrate 220 is a semiconductor material, such as silicon, silicon carbide, or indium, gallium, arsenic, and phosphorus compound semiconductor materials.
  • the method of forming the optical chip 200 includes: providing a semiconductor-on-insulator layer, the semiconductor-on-insulator layer including a bottom semiconductor layer, a top semiconductor layer, and a buried layer between the bottom semiconductor layer and the top semiconductor layer; on the top semiconductor layer Several optical units are formed in the layer; after the optical units are formed, a main medium layer covering the optical units is formed, the main medium layer and the buried layer constitute the optical medium layer 210, and the underlying semiconductor layer constitutes the optical medium layer 210.
  • Core semiconductor substrate 220 is provided.
  • the semiconductor-on-insulator layer is silicon-on-insulator (SOI)
  • the material of the bottom semiconductor layer and the top semiconductor layer is monocrystalline silicon
  • the material of the buried layer is silicon oxide.
  • the material of the main dielectric layer includes silicon oxide.
  • lead lines are formed in the optical medium layer 210 , and the lead lines are located on some of the optical units.
  • the lead wires are used to lead out active devices in the optical unit.
  • a first conductive plug 230 is formed in the optical medium layer 210 and the optical core semiconductor substrate 220 ; an optical core redistribution layer 240 is formed on the front surface of the optical chip 200 .
  • a first through hole is formed in the optical medium layer 210 and the optical core semiconductor substrate 220, and a first conductive plug is formed in the first through hole; after the first conductive plug 230 is formed, in the An optical core redistribution layer 240 is formed on the front surface of the optical chip 200 , and the optical core redistribution layer 240 is connected to one end of the first conductive plug 230 .
  • Part of the optical core redistribution layer 240 is connected to one end of the first conductive plug 230, and part of the optical core redistribution layer 240 is connected to the lead wire.
  • a first electrical chip 300 is provided on the front side of the optical chip 200 , and the first electrical chip 300 is electrically connected to the optical chip 200 ; and the optical coupling area is formed on the front side of the optical chip 200 A protective structure 400 in contact with the surface, the refractive index of the protective structure 400 is smaller than the refractive index of the optical medium layer 210 .
  • the front side of the first electrical chip 300 has cell pads, the surface of the cell pads has cell solder balls, and the first electrical chip 300 is connected to part of the optical core rewiring layer through the cell solder balls 240 connections.
  • a protection structure 400 is provided, and the protection structure 400 is mounted with the surface of the light coupling region A. As shown in FIG. After the protection structure 400 is mounted, the first electrical chip 300 is located on the side of the protection structure 400 .
  • the first electrical chip 300 is a driving chip of a laser or a modulator, and may also be an amplifying chip of a detector.
  • the first electrical chip 300 is disposed above the front surface of the optical chip 200 .
  • the protection structure 400 is formed on the front surface of the optical chip 200 .
  • the refractive index of the protective structure 400 is 94% ⁇ 99% of the refractive index of the optical medium layer 210 .
  • the material of the protection structure 400 is quartz glass doped with modified ions, and the modified ions include fluorine ions or boron ions.
  • the modified ions are used to reduce the refractive index of the protective structure 400 .
  • the material of the protection structure 400 is magnesium fluoride.
  • the thickness of the protective structure 400 in contact with the surface of the light coupling region A is 300-800 microns.
  • the protection structure 400 in contact with the surface of the light coupling region A is less than 300 ⁇ m, the protection structure 400 does not have sufficient limiting effect on the light coupling region A, and it is difficult for the protection structure 400 to fix the optical fiber and to couple the light.
  • the support function of the area A is insufficient; if the thickness of the protection structure 400 in contact with the surface of the optical coupling area A is greater than 800 microns, the package thickness is too large, which is not conducive to improving the integration of the optoelectronic chip package structure.
  • the protection structure 400 protrudes from the side wall of the light coupling area A; the protection structure 400 has a positioning groove, and the positioning groove is used for positioning and assembling the optical fiber.
  • the shape of the positioning groove includes a "V" shape.
  • the shape of the positioning groove may also be other shapes.
  • the positioning groove has a first side wall and a second side wall connected with the first side wall, the first side wall is flush with the side wall of the light coupling region and is suitable for being opposite to a part of the end face of the optical fiber,
  • the second sidewall is adapted to be in contact with the sidewall of the optical fiber.
  • the advantage of the shape of the positioning groove including the "V" shape is that after the optical fiber is positioned in the positioning groove, the second side wall of the positioning groove is in tangential contact with part of the side wall of the optical fiber, and the first side wall of the positioning groove is in tangential contact.
  • the two sidewalls are in contact with the optical fiber, so that the optical fiber can be precisely positioned and coupled with the mode spot converter to achieve efficient coupling.
  • the positioning groove may be single, or a plurality of positioning grooves may be arranged side by side.
  • Part of the optical core redistribution layer 240 is connected 300 to the first conductive plug 230 and the first electrical chip, respectively.
  • a plastic encapsulation layer 500 is formed, and the plastic encapsulation layer 500 integrally encapsulates the front surface of the optical chip 200 , the first electrical chip 300 and the protection structure 400 .
  • the optical core semiconductor substrate 220 is thinned from the back side of the optical core semiconductor substrate 220 so that the first conductive plugs 230 are exposed from the back side of the optical core semiconductor substrate 220 .
  • the process of thinning the optical core semiconductor substrate 220 includes chemical mechanical polishing, etching process or mechanical polishing process.
  • a first redistribution layer structure is formed on the backside of the optical core semiconductor substrate 220 , and the first redistribution layer structure includes a first redistribution layer 251 , the first redistribution layer 251 and the The first conductive plug 230 is connected.
  • the first redistribution layer structure includes a first insulating layer 252 and a first redistribution layer 251 located in the first insulating layer 252 .
  • the material of the first redistribution layer 251 is metal.
  • the first redistribution layer 251 is connected to the first conductive plug 230 .
  • the first redistribution layer structure is formed on the backside of the optical core semiconductor substrate 220 , and then the first redistribution layer structure at the bottom of the light coupling region A is removed by etching.
  • the optical core semiconductor substrate 220 at the bottom of the light coupling region A is removed by etching, and the light coupling region A is exposed.
  • the optical core semiconductor substrate 220 at the bottom of the light coupling region A is removed by etching, so that the bottom surface of the light coupling region A is suspended, and the bottom surface of the light coupling region A is not in direct contact with other film layers.
  • the medium suspended at the bottom of the optical coupling area A is air, so the refractive index of the suspended area at the bottom of the optical coupling area A is smaller than the refractive index of the optical medium layer, so that the light in the optical coupling area A is not easily directed
  • the bottom of the light coupling region A leaks.
  • the optical medium layer 210 is etched to expose the coupling end face of the light coupling region A; first solder balls 260 are formed on the surface of the first redistribution layer structure.
  • the optical medium layer 210 at the bottom of the positioning groove in the protective structure 400 is removed by etching, while the optical medium layer 210 in contact with the protective structure 400 is retained.
  • balls are implanted on the surface of the first redistribution layer 251 to form first solder balls 260 .
  • the protection structure 400 and the plastic sealing layer 500 are cut.
  • the structure in which the optical chip 200 and the first electrical chip 300 are packaged together is mounted on the substrate 600 ; after that, the optical fiber structure 700 is positioned and assembled in the positioning groove middle.
  • FIG. 12 is used to illustrate the positional relationship between the optical fiber structure 700 and the protection structure 400 more clearly.
  • FIG. 12 is a cross-sectional view of the optical fiber structure 700 in FIG. The cross-sectional view of FIG. 12 is obtained.
  • this embodiment also provides an optoelectronic chip packaging structure, please refer to FIG. 11 , including: an optical chip 200 (refer to FIG. 2 ), the optical chip 200 includes an optical medium layer 210 , and a part of the optical medium layer 210 The side edge region is the light coupling region A (refer to FIG. 2 ); the protective structure 400 located on the front surface of the optical chip 200 and contacting the surface of the light coupling region A, the refractive index of the protective structure 400 is smaller than that of the optical medium layer 210 index of refraction.
  • the refractive index of the protective structure 400 is 94% ⁇ 99% of the refractive index of the optical medium layer 210 .
  • the material of the protection structure 400 is quartz glass doped with modified ions, and the modified ions include fluorine ions or boron ions.
  • the material of the protective structure is magnesium fluoride.
  • the modified ions are used to reduce the refractive index of the protective structure 400 .
  • the thickness of the protective structure 400 in contact with the surface of the light coupling region A is 300-800 microns.
  • the protection structure 400 protrudes from the side wall of the light coupling area A; the protection structure 400 has a positioning groove, and the positioning groove is used for positioning and assembling the optical fiber.
  • the shape of the positioning groove includes a "V" shape.
  • the positioning groove has a first side wall and a second side wall connected with the first side wall, the first side wall is flush with the side wall of the light coupling area A and is suitable for being opposite to a part of the end face of the optical fiber , the second side wall is adapted to be in contact with the side wall of the optical fiber.
  • the optoelectronic chip packaging structure further includes: an optical fiber structure 700 located in the positioning groove; the optical fiber structure 700 is a single optical fiber; or the optical fiber structure 700 is an optical fiber array.
  • the optoelectronic chip packaging structure further includes: a first electrical chip 300 disposed on the front side of the optoelectronic chip, the first electrical chip 300 is electrically connected to the optoelectronic chip 200, and the first electrical chip 300 is located in the The side portion of the protection structure 400 ; the plastic encapsulation layer 500 , the plastic encapsulation layer 500 integrally encapsulates the front surface of the optical chip 200 , the first electrical chip 300 and the protection structure 400 .
  • the optical chip 200 further includes an optical core semiconductor substrate 220 located at the bottom of the optical medium layer 210 , and the optical core semiconductor substrate 220 exposes the light coupling region A. As shown in FIG.
  • the optoelectronic chip package structure further includes: a first conductive plug 230 penetrating the optical medium layer 210 and the optical core semiconductor substrate 220; a first redistribution layer 251 located on the back of the optical chip 200; the One end of the first conductive plug 230 is electrically connected to the first electrical chip 300 , and the other end of the first conductive plug 230 is connected to the first redistribution layer 251 ; and is electrically connected to the first redistribution layer 251
  • the first solder ball 260 is connected.
  • Another embodiment of the present application further provides a packaging method for an optoelectronic chip packaging structure. Please refer to FIGS. 13 to 24 on the basis of FIG. 2 .
  • FIG. 13 which is a schematic diagram based on FIG. 2 , a first conductive plug 230 ′ is formed in the optical medium layer 210 , and an optical core redistribution layer 240 ′ is formed on the front surface of the optical chip 200 .
  • the first conductive plug 230' only penetrates the optical medium layer 210, but is not located in the optical core semiconductor substrate 220.
  • Part of the optical core redistribution layer 240' is connected to the first conductive plug 230', and part of the optical core redistribution layer 240' is connected to the lead wire.
  • a second conductive plug 241 is formed over the front surface of the optical chip 200 .
  • the second conductive plug 241 is connected to part of the optical core redistribution layer 240'.
  • the method for forming the second conductive plug 241 over the front surface of the optical chip 200 includes: providing the second conductive plug 241, crimping the second conductive plug 241 or Soldered on the part of the optical core redistribution layer 240'.
  • the method for forming the second conductive plug 241 over the front surface of the optical chip 200 includes: forming a patterned photoresist over the front surface of the optical chip 200; using an electroplating process A second conductive plug 241 is formed in the patterned photoresist; after that, the patterned photoresist is removed.
  • a first electrical chip 300 ′ is provided on the front side of the optical chip 200 , and the first electrical chip 300 ′ is electrically connected to the optical chip 200 ;
  • the protective structure 400 ′ in contact with the surface of the coupling region A, the refractive index of the protective structure 400 ′ is smaller than the refractive index of the optical medium layer 210 .
  • the front side of the first electrical chip 300 ′ has cell pads, the surface of the cell pads has cell solder balls, and the first electrical chip 300 ′ is connected to part of the optical core through the cell solder balls.
  • the wiring layer 240' is connected.
  • a protective structure 400' is provided, and the protective structure 400' and the surface of the light coupling region A are mounted together. After the protection structure 400' is mounted, the first electrical chip 300' is located at the side of the protection structure 400'.
  • Part of the optical core redistribution layer 240' is connected to the first conductive plug 230' and the first electrical chip 300', respectively.
  • a first electrical chip 300' is disposed above the front surface of the optical chip 200.
  • the protection structure 400' is formed on the front surface of the optical chip 200.
  • the refractive index of the protective structure 400' is 94%-99% of the refractive index of the optical medium layer 210.
  • the material of the protection structure 400' is quartz glass doped with modified ions, and the modified ions include fluorine ions or boron ions.
  • the material of the protective structure is magnesium fluoride.
  • the thickness of the protection structure 400' in contact with the surface of the light coupling region A is 300-800 microns.
  • the protection structure 400' protrudes relative to the sidewall of the light coupling area A; the protection structure 400' has a positioning groove, and the positioning groove is used for positioning and assembling the optical fiber.
  • the shape of the positioning groove includes a "V" shape.
  • the positioning groove has a first side wall and a second side wall connected with the first side wall, the first side wall is flush with the side wall of the light coupling region and is suitable for being opposite to a part of the end face of the optical fiber,
  • the second sidewall is adapted to be in contact with the sidewall of the optical fiber.
  • the positioning groove may be single, or a plurality of positioning grooves may be arranged side by side.
  • a plastic encapsulation layer 500' is formed, and the plastic encapsulation layer 500' integrally encapsulates the front surface of the optical chip 200, the first electrical chip 300', the protection structure 400' and the second conductive plug 241.
  • the molding layer 500 ′ is thinned until the top surface of the second conductive plug 241 is exposed.
  • the plastic sealing layer 500' Since the second conductive plug 241 is higher than the top surface of the first electrical chip 300' and the top surface of the protection structure 400', after the plastic sealing layer 500' is thinned, the plastic sealing layer 500' is still The top surface of the first electrical chip 300' and the top surface of the protection structure 400' are completely covered.
  • a second redistribution layer 242 is formed on the surface of the plastic sealing layer 500 ′, and the second redistribution layer 242 is connected to the second conductive plug 241 .
  • the optical core semiconductor substrate 220 is removed.
  • a first redistribution structure is formed on the backside of the optical medium layer 210, the first redistribution structure includes a first redistribution layer 244, the first redistribution structure The redistribution layer 244 is connected to the first conductive plug 230'.
  • the first redistribution layer structure includes a first insulating layer and a first redistribution layer 244 in the first insulating layer.
  • the material of the first redistribution layer 244 is metal.
  • a temporary bonding layer 243 is also formed on the second redistribution layer 242;
  • the backside of the optical medium layer 210 forms a first redistribution structure.
  • the temporary bonding layer 243 provides a better process platform for forming the first redistribution structure.
  • the first redistribution structure at the bottom of the optical coupling region A is removed by exposure and development, or the bottom of the optical coupling region A is removed by etching. the first redistribution structure to expose the light coupling region A;
  • the first redistribution structure at the bottom of the light coupling region A is removed by etching, so that the bottom surface of the light coupling region A is suspended, and the bottom surface of the light coupling region A is not in direct contact with other film layers.
  • the medium suspended at the bottom of the optical coupling area A is air, so the refractive index of the suspended area at the bottom of the optical coupling area A is smaller than the refractive index of the optical medium layer, so that the light in the optical coupling area A is not easily directed
  • the bottom of the light coupling region A leaks.
  • the optical medium layer 210 is etched to expose the coupling end face of the light coupling region A. As shown in FIG. 21 , the optical medium layer 210 is etched to expose the coupling end face of the light coupling region A. As shown in FIG. 21 , the optical medium layer 210 is etched to expose the coupling end face of the light coupling region A. As shown in FIG. 21 , the optical medium layer 210 is etched to expose the coupling end face of the light coupling region A. As shown in FIG.
  • the optical medium layer 210 at the bottom of the positioning groove in the protective structure 400' is removed by etching, while the optical medium layer 210 in contact with the protective structure 400' is retained.
  • the temporary bonding layer 243 is removed; after the temporary bonding layer 243 is removed, second solder balls 245 are formed on the surface of the second redistribution layer 242 .
  • the protective structure 400' and the plastic encapsulation layer 500' are cut.
  • the protection structure 400' protrudes relative to the sidewall of the light coupling region; the protection structure 400' has positioning grooves therein.
  • the second electrical chip 800 is mounted on the first redistribution layer 244 through the first solder balls 801; after that, the optical fiber structure 700' is positioned and assembled in the positioning concave in the slot.
  • the second electrical chip 800 implements data processing and storage.
  • the structure in which the optical chip 200 and the first electrical chip 300 ′ are packaged together is mounted on the substrate 600 ′.
  • the second redistribution layer 242 is soldered to the substrate 600 ′ through the second solder balls 245 . together; after that, the optical fiber structure 700' is positioned and assembled in the positioning groove.
  • the positioning concave in the protective structure 400 ′ is upward, so during the process of positioning and assembling the optical fiber structure 700' in the positioning groove, the operating end can directly place the optical fiber structure 700' in the positioning groove from top to bottom , which is conducive to the smooth completion of the operation, and in the process of the operation, the operator can intuitively see the internal structure of the positioning groove, thus facilitating the accurate positioning of the optical fiber structure 700 ′.
  • the first electrical chip 300' is packaged with the optical chip 200
  • the second electrical chip 800 is packaged with the optical chip 200, which improves the integration degree of the optoelectronic chip packaging structure.
  • this embodiment also provides an optoelectronic chip packaging structure, please refer to FIG. 24 , including: an optical chip, the optical chip includes an optical medium layer 210 , and an edge area of one side of the optical medium layer 210 is an optical coupling area A (refer to FIG. 2 ): a protective structure 400 ′ located on the front surface of the optical chip and in contact with the surface of the light coupling region A, the protective structure 400 ′ has a refractive index smaller than that of the optical medium layer.
  • the refractive index of the protective structure 400' is 94%-99% of the refractive index of the optical medium layer.
  • the material of the protection structure 400' is quartz glass doped with modified ions, and the modified ions include fluoride ions or boron ions; or, the material of the protection structure is magnesium fluoride.
  • the thickness of the protective structure in contact with the surface of the light coupling region is 300 micrometers to 800 micrometers.
  • the protection structure 400' protrudes relative to the sidewall of the light coupling region; the protection structure 400' has a positioning groove, and the positioning groove is used for positioning and assembling the optical fiber.
  • the shape of the positioning groove includes a "V" shape.
  • the positioning groove has a first side wall and a second side wall connected with the first side wall, the first side wall is flush with the side wall of the light coupling region and is suitable for being opposite to a part of the end face of the optical fiber,
  • the second sidewall is adapted to be in contact with the sidewall of the optical fiber.
  • the optoelectronic chip packaging structure further includes: an optical fiber structure 700' located in the positioning groove; the optical fiber structure 700' is a single optical fiber; or the optical fiber structure 700' is an optical fiber array.
  • the optoelectronic chip packaging structure further includes: a first electrical chip 300' disposed on the front side of the optoelectronic chip, the first electrical chip 300' is electrically connected to the optoelectronic chip, and the first electrical chip 300' is located in the The side portion of the protection structure 400 ′; the plastic sealing layer 500 ′, the plastic sealing layer 500 ′ integrally plastic-encapsulates the front side of the optical chip, the first electrical chip 300 ′ and the protection structure 400 ′.
  • the optoelectronic chip packaging structure further includes: a first redistribution structure located on the back of the optical chip, the first redistribution structure is located on the surface of the optical medium layer 210 , and the first redistribution structure exposes the optical coupling Region A, the first redistribution structure includes a first insulating layer and a first redistribution layer 244 in the first insulating layer.
  • the optoelectronic chip packaging structure further includes: a first conductive plug 230' penetrating the optical medium layer 210; one end of the first conductive plug 230' is electrically connected to the first electrical chip 300', and the first conductive plug 230' The other end of a conductive plug 230' is connected to the first redistribution layer 244; the first solder ball 801 is electrically connected to the first redistribution layer 244; the second electrical chip 800 is located on the back of the optical chip , the second electrical chip 800 is connected to the first solder ball 801 .
  • the optoelectronic chip packaging structure further includes: a second redistribution layer 242 located on the surface of the plastic sealing layer 500' and facing the back of the first electrical chip 300'; a second conductive plug penetrating the plastic sealing layer 500' 241, one end of the second conductive plug 241 is electrically connected to the first electrical chip 300', and the other end of the second conductive plug 241 is connected to the second redistribution layer 242;
  • the wiring layer 242 is electrically connected to the second solder balls 245 .

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Abstract

一种光电芯片封装结构及其封装方法，光电芯片封装结构包括：光芯片，所述光芯片包括光介质层，所述光介质层的一侧边缘区域为光耦合区；位于所述光芯片的正面且接触所述光耦合区表面的保护结构，所述保护结构的折射率小于所述光介质层的折射率。所述光电芯片封装结构的封装可靠性提高且光泄露降低。

Description

一种光电芯片封装结构及其封装方法 技术领域
本申请涉及封装领域，具体涉及一种光电芯片封装结构及其封装方法。
背景技术
光通信是以光波为载波的通信方式。随着技术的发展，通信数据量越来越大，因此对光通信模块的传输速率要求越来越高。光电芯片集成结构是光通信模块的核心组成部分。光电芯片集成结果将光芯片与其外围电路的电芯片集成在一起，实现光信号和电信号之间转换的功能。
光芯片的一侧边缘具有光耦合区，光耦合区中一般具有模斑转换器，模斑转换器的一端具有较大的模斑尺寸而与光纤的模斑尺寸相匹配，模斑转换器的另一端具有较小的模斑尺寸而与光芯片中波导的模斑尺寸相匹配，模斑转换器用于降低光纤与光芯片中波导之间的光连接损耗。即使采用模斑转换器，模斑转换器的区域向外(光芯片硅衬底)的光信号泄露还是存在的。因此对于降低光耦合区向外的光信号泄露是需要解决的问题。另一方面，光耦合区需要避免污染，增加耦合区域强度，以保证封装可靠性。
目前，对于如何兼顾封装可靠性且降低光泄露是急需解决的问题。
发明内容
因此，本申请要解决的技术问题在于克服现有技术中如何同时提高封装可靠性且降低光泄露。
本申请还提供一种光电芯片封装结构，包括：光芯片，所述光芯片包括光介质层，所述光介质层的一侧边缘区域为光耦合区；位于所述光芯片的正面且接触所述光耦合区表面的保护结构，所述保护结构的折射率小于所述光介质层的折射率。
可选的，所述保护结构的折射率为所述光介质层的折射率的94％～99％。
可选的，所述保护结构的材料为掺杂有改性离子的石英玻璃，所述改性离子包括氟离子或者硼离子；或者，所述保护结构的材料为氟化镁。
可选的，与所述光耦合区表面接触的所述保护结构的厚度为300微米～800微米。
可选的，所述保护结构相对于所述光耦合区的侧壁凸出；所述保护结构中具有定位凹槽，所述定位凹槽用于对光纤进行定位组装。
可选的，所述定位凹槽的形状包括“V”形。
可选的，所述定位凹槽具有第一侧壁和与第一侧壁连接的第二侧壁，所述第一侧壁与所述光耦合区的侧壁齐平且适于与光纤的部分端面相对，所述第二侧壁适于与光纤的侧壁接触。
可选的，还包括：位于所述定位凹槽中的光纤结构；所述光纤结构为单个的光纤；或者所述光纤结构为光纤阵列。
可选的，还包括：设置在所述光芯片的正面的第一电芯片，所述第一电芯片与所述光芯片电学连接，所述第一电芯片位于所述保护结构的侧部；塑封层，所述塑封层一体塑封所述光芯片的正面、所述第一电芯片和所述保护结构。
可选的，还包括：所述光芯片还包括位于所述光介质层底部的光芯半导体衬底，所述光芯半导体衬底暴露出所述光耦合区。
可选的，还包括：贯穿所述光介质层和所述光芯半导体衬底的第一导电插塞；位于所述光芯片背面的第一重布线层；所述第一导电插塞的一端电学连接所述第一电芯片，所述第一导电插塞的另一端与所述第一重布线层连接；与所述第一重布线层电学连接的第一焊球。
可选的，还包括：位于所述光芯片背面的第一重布线结构，所述第一重布线结构位于光介质层的表面，所述第一重布线结构暴露出所述光耦合区，所述第一重布线结构包括第一绝缘层和位于第一绝缘层中的第一重布线层。
可选的，还包括：贯穿所述光介质层的第一导电插塞；所述第一导电插塞的一端电学连接所述第一电芯片，所述第一导电插塞的另一端与所述第一重布线层连接；与所述第一重布线层电学连接的第一焊球；位于所述光芯片背面的第二电芯片，所述第二电芯片与所述第一焊球连接。
可选的，还包括：位于所述塑封层表面且朝向所述第一电芯片的背面的第二重布线层；贯穿所述塑封层的第二导电插塞，所述第二导电插塞的一端与所述第一电芯片电学连接，所述第二导电插塞的另一端与第二重布线层连接；与所述第二重布线层电学连接的第二焊球。
本申请还提供一种光电芯片封装结构的封装方法，包括：提供光芯片，所述光芯片包括光介质层，所述光介质层的一侧边缘区域为光耦合区；在所述光芯片的正面形成与所述光耦合区表面接触的保护结构，所述保护结构的折射率小于所述光介质层的折射 率。
可选的，还包括：在所述光芯片的正面设置第一电芯片，所述第一电芯片与所述光芯片电学连接；形成所述保护结构之后，所述第一电芯片位于所述保护结构的侧部；形成塑封层，所述塑封层一体塑封所述光芯片的正面、所述第一电芯片和所述保护结构。
可选的，所述光芯片还包括位于所述光介质层底部的光芯半导体衬底；所述封装方法还包括：在设置所述第一电芯片和形成所述保护结构之前，在所述光介质层和光芯半导体衬底中形成第一导电插塞；在所述光芯片的正面形成光芯重布线层，所述光芯重布线层分别与第一导电插塞和第一电芯片连接；形成所述塑封层之后，在所述光芯半导体衬底的背面形成第一重布线层结构，所述第一重布线层结构包括第一重布线层，所述第一重布线层与所述第一导电插塞连接；在所述第一重布线层结构表面形成第一焊球；形成第一焊球之后，进行划片切割。
可选的，还包括：刻蚀去除光耦合区底部的光芯半导体衬底，以暴露出所述光耦合区。
可选的，在形成所述保护结构之前，所述光芯片还包括位于所述光介质层底部的光芯半导体衬底；所述封装方法还包括：在设置所述第一电芯片和形成所述保护结构之前，在所述光介质层中形成第一导电插塞，在所述光芯片的正面形成光芯重布线层，所述光芯重布线层分别与第一导电插塞和第一电芯片连接；在形成所述塑封层之前，在所述光芯片的正面上方形成第二导电插塞；形成所述塑封层之后，所述塑封层还一体塑封所述第二导电插塞，且所述塑封层暴露出所述第二导电插塞的顶面；在所述塑封层表面形成第二重布线层，所述第二重布线层与第二导电插塞连接；形成所述第二重布线层之后，去除所述光芯半导体衬底；去除所述光芯半导体衬底之后，在所述光介质层背面形成第一重布线结构，所述第一重布线结构包括第一重布线层，所述第一重布线层与所述第一导电插塞连接。
可选的，还包括：去除所述光耦合区底部的第一重布线结构，以暴露出所述光耦合区。
可选的，还包括：在形成所述第一重布线结构之后，在所述第二重布线层表面形成第二焊球；形成第二焊球之后，进行划片切割；划片切割之后，将第二电芯片通过第一焊球贴装在所述第一重布线层上。
可选的，所述保护结构相对于所述光耦合区的侧壁凸出；所述保护结构中具有定位凹槽；提供光纤结构，将所述光纤结构定位组装在所述定位凹槽中。
本申请技术方案，具有如下优点：
本申请技术方案提供的光电芯片封装结构，所述光芯片的正面具有与所述光耦合区表面接触的保护结构，这样使得光耦合区和保护结构之间没有空腔，光耦合区的正面被保护结构限制，因此光耦合区不容易发生曲翘，封装的可靠性提高。由于所述保护结构的折射率小于所述光介质层的折射率，这样光耦合区内的光不易向保护结构泄露。因此，提高了光电芯片封装结构的性能。
本申请技术方案提供的光电芯片封装结构的封装方法，在所述光芯片的正面形成与所述光耦合区表面接触的保护结构，这样使得光耦合区和保护结构之间没有空腔，光耦合区的正面被保护结构限制，因此光耦合区不容易发生曲翘，封装的可靠性提高。由于所述保护结构的折射率小于所述光介质层的折射率，这样光耦合区内的光不易向保护结构泄露。因此，提高了光电芯片封装结构的性能。
附图说明
为了更清楚地说明本申请具体实施方式或现有技术中的技术方案，下面将对具体实施方式或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图是本申请的一些实施方式，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是一种光电芯片封装结构；
图2至图12是本申请一实施例提供的光电芯片封装结构形成过程的结构示意图；
图13至图24是本申请另一实施例提供的光电芯片封装结构形成过程的结构示意图。
具体实施方式
正如背景技术所述，现有的光电芯片封装结构的性能较差。
一种光电芯片封装结构，如图1，包括：光芯片，所述光芯片包括光芯半导体衬底110和光互连结构111；电芯片150(150-1、150-2)；盖板160；塑封层170；导电连接件120；第一布线层130；第二布线层140；焊球180。
上述光电芯片封装结构中，光互连结构111的一侧具有光耦合区，光光耦合区中具有模斑转换器，盖板160的材料通常为玻璃，且盖板160与光耦合区不接触，而是盖板160与光耦合区之间悬空形成空腔。盖板160与光耦合区之间具有空腔，空腔内部的折射率小于光互连结构111的介质层的折射率，这样光耦合区内的光不容易向盖板160与光耦合区之间的空腔内部泄露。
上述结构中，为了降低光向光耦合区和底部泄露，将光耦合区下方的半导体衬底110 去除部分厚度，具体的，在光互连结构111的光耦合区中形成刻蚀孔，刻蚀位于刻蚀孔底部的光芯半导体衬底110，使得光耦合区底部的部分厚度的半导体衬底110刻蚀去除，这样半导体衬底110和光互连结构111的光耦合区之间形成底部空腔。半导体衬底110和光互连结构111的光耦合区之间形成底部空腔，且由于盖板160与光耦合区之间也没有有效支撑，加之光耦合区的厚度较薄，厚度在4微米-10微米之间，因此在温度改变时光耦合区上方没有被其他结构限制而容易曲翘，影响封装的可靠性。
为了解决上述技术问题，本申请实施例提供一种光电芯片封装结构，包括：光芯片，所述光芯片包括光介质层，所述光介质层的一侧边缘区域为光耦合区；位于所述光芯片的正面且接触所述光耦合区表面的保护结构，所述保护结构的折射率小于所述光介质层的折射率。所述光电芯片封装结构使得封装可靠性提高且降低了光泄露。
下面参考图2至图13具体介绍形成光电芯片封装结构的各个步骤。
参考图2，提供光芯片200，所述光芯片200包括光介质层210和位于所述光介质层210底部的光芯半导体衬底220，所述光介质层210的一侧边缘区域为光耦合区A。
所述光介质层210中具有若干光学单元，所述光学单元包括光波导、调制器、探测器和模斑转换器，其中，所述模斑转换器位于所述光耦合区A中，所述光波导、调制器和探测器位于光耦合区A的侧部。
所述光介质层210的主体材料包括氧化硅。
所述光芯半导体衬底220的材料为半导体材料，例如硅、碳化硅、或者铟、镓、砷、磷化合物半导体材料。
形成所述光芯片200的方法包括：提供绝缘体上半导体层，所述绝缘体上半导体层包括底层半导体层、顶层半导体层和位于底层半导体层和顶层半导体层之间的掩埋层；在所述顶层半导体层中形成若干光学单元；形成所述光学单元之后，形成覆盖所述光学单元的主介质层，所述主介质层和所述掩埋层构成了光介质层210，所述底层半导体层构成了光芯半导体衬底220。
在一个具体的实施例中，所述绝缘体上半导体层为绝缘体上硅(SOI)，所述底层半导体层和顶层半导体层的材料均为单晶硅，所述掩埋层的材料为氧化硅。所述主介质层的材料包括氧化硅。
继续参考图2，在所述光介质层210中形成引出线(未标示)，所述引出线位于部分光学单元上。
所述引出线用于引出光学单元中的有源器件。
参考图3，在所述光介质层210和光芯半导体衬底220中形成第一导电插塞230；在所述光芯片200的正面形成光芯重布线层240。
具体的，在所述光介质层210和光芯半导体衬底220中形成第一通孔，在所述第一通孔中形成第一导电插塞；形成第一导电插塞230之后，在所述光芯片200的正面形成光芯重布线层240，所述光芯重布线层240与第一导电插塞230的一端连接。
部分光芯重布线层240与第一导电插塞230的一端连接，部分光芯重布线层240与所述引出线连接。
参考图4，在所述光芯片200的正面设置第一电芯片300，所述第一电芯片300与所述光芯片200电学连接；在所述光芯片200的正面形成与所述光耦合区A表面接触的保护结构400，所述保护结构400的折射率小于所述光介质层210的折射率。
具体的，第一电芯片300的正面具有电芯焊盘，所述电芯焊盘表面具有电芯焊球，所述第一电芯片300通过所述电芯焊球与部分光芯重布线层240连接。
具体的，提供保护结构400，将所述保护结构400与所述光耦合区A的表面贴装在一起。贴装所述保护结构400之后，所述第一电芯片300位于所述保护结构400的侧部。
所述第一电芯片300为激光器或调制器的驱动芯片，也可以是探测器的放大芯片。
在一个具体的实施例中，在所述光芯片200的正面形成所述保护结构400之后，在所述光芯片200的正面上方设置第一电芯片300。在另一个具体的实施例中，在所述光芯片200的正面上方设置第一电芯片300之后，在所述光芯片200的正面形成所述保护结构400。
在一个具体的实施例中，所述保护结构400的折射率为所述光介质层210的折射率的94％～99％。
所述保护结构400的材料为掺杂有改性离子的石英玻璃，所述改性离子包括氟离子或者硼离子。所述改性离子用于降低所述保护结构400的折射率。
或者，所述保护结构400的材料为氟化镁。
与所述光耦合区A表面接触的所述保护结构400的厚度为300微米～800微米。
若与所述光耦合区A表面接触的所述保护结构400的厚度小于300微米，所述保护结构400对光耦合区A的限定作用不充分，所述保护结构400难以固定光纤而且对光耦合区A的支撑作用不充分；若与所述光耦合区A表面接触的所述保护结构400的厚度大于800微米，封装厚度过大，不利于光电芯片封装结构的集成度的提高。
所述保护结构400相对于所述光耦合区A的侧壁凸出；所述保护结构400中具有定位凹槽，所述定位凹槽用于对光纤进行定位组装。
所述定位凹槽的形状包括“V”形。
在其他实施例中，所述定位凹槽的形状还可以为其他形状。
所述定位凹槽具有第一侧壁和与第一侧壁连接的第二侧壁，所述第一侧壁与所述光耦合区的侧壁齐平且适于与光纤的部分端面相对，所述第二侧壁适于与光纤的侧壁接触。
所述定位凹槽的形状包括“V”形的好处在于：光纤定位在定位凹槽中之后，所述定位凹槽的第二侧壁与光纤的部分侧壁相切接触，定位凹槽的第二侧壁与光纤呈现接触的方式，这样使得光纤能够精确定位与模斑转换器实现高效耦合。
所述定位凹槽可以为单个，或者定位凹槽为并列排布的多个。
部分所述光芯重布线层240分别与第一导电插塞230和第一电芯片连接300。
参考图5，形成塑封层500，所述塑封层500一体塑封所述光芯片200的正面、所述第一电芯片300和所述保护结构400。
参考图6，从光芯半导体衬底220的背面对光芯半导体衬底220进行减薄，使得光芯半导体衬底220的背面暴露出第一导电插塞230。
对光芯半导体衬底220进行减薄的工艺包括化学机械研磨、刻蚀工艺或者机械研磨工艺。
参考图7，在所述光芯半导体衬底220的背面形成第一重布线层结构，所述第一重布线层结构包括第一重布线层251，所述第一重布线层251与所述第一导电插塞230连接。
所述第一重布线层结构包括第一绝缘层252和位于第一绝缘层252中的第一重布线层251。所述第一重布线层251的材料为金属。
所述第一重布线层251与所述第一导电插塞230连接。
具体的，在所述光芯半导体衬底220的背面形成第一重布线层结构，之后，刻蚀去除光耦合区A底部的第一重布线层结构。
参考图8，刻蚀去除光耦合区A底部的光芯半导体衬底220，暴露出所述光耦合区A。
刻蚀去除光耦合区A底部的光芯半导体衬底220，这样使得光耦合区A底面悬空， 光耦合区A的底面不与其他膜层直接接触。在光传输的过程中，光耦合区A底部悬空的介质为空气，因此光耦合区A底部悬空的区域的折射率小于所述光介质层的折射率，这样光耦合区A内的光不易向光耦合区A底部泄露。
参考图9，刻蚀光介质层210，以暴露出光耦合区A的耦合端面；在所述第一重布线层结构表面形成第一焊球260。
具体的，将保护结构400中的定位凹槽底部的光介质层210刻蚀去除，而与保护结构400接触的光介质层210是保留的。
具体的，在所述第一重布线层251的表面植球，形成第一焊球260。
参考图10，进行划片切割。
具体的，沿着图9中虚线的位置，对保护结构400和塑封层500进行切割。
参考图11，进行划片切割之后，将所述光芯片200和第一电芯片300封装在一起的结构贴装在基板600上；之后，将所述光纤结构700定位组装在所述定位凹槽中。
采用图12更加清楚的示意出光纤结构700和保护结构400的位置关系，图12为图11中光纤结构700的剖面图，具体的，沿着垂直与图11中光纤结构700中光纤的延伸方向获得图12的剖面图。
相应的，本实施例还提供一种光电芯片封装结构，请参考图11，包括：光芯片200(参考图2)，所述光芯片200包括光介质层210，所述光介质层210的一侧边缘区域为光耦合区A(参考图2)；位于所述光芯片200的正面且接触所述光耦合区A表面的保护结构400，所述保护结构400的折射率小于所述光介质层210的折射率。
所述保护结构400的折射率为所述光介质层210的折射率的94％～99％。
所述保护结构400的材料为掺杂有改性离子的石英玻璃，所述改性离子包括氟离子或者硼离子。或者，所述保护结构的材料为氟化镁。所述改性离子用于降低所述保护结构400的折射率。
与所述光耦合区A表面接触的所述保护结构400的厚度为300微米～800微米。
所述保护结构400相对于所述光耦合区A的侧壁凸出；所述保护结构400中具有定位凹槽，所述定位凹槽用于对光纤进行定位组装。
所述定位凹槽的形状包括“V”形。
所述定位凹槽具有第一侧壁和与第一侧壁连接的第二侧壁，所述第一侧壁与所述光耦合区A的侧壁齐平且适于与光纤的部分端面相对，所述第二侧壁适于与光纤的侧壁接 触。
所述光电芯片封装结构还包括：位于所述定位凹槽中的光纤结构700；所述光纤结构700为单个的光纤；或者所述光纤结构700为光纤阵列。
所述光电芯片封装结构还包括：设置在所述光芯片的正面的第一电芯片300，所述第一电芯片300与所述光芯片200电学连接，所述第一电芯片300位于所述保护结构400的侧部；塑封层500，所述塑封层500一体塑封所述光芯片200的正面、所述第一电芯片300和所述保护结构400。
所述光芯片200还包括位于所述光介质层210底部的光芯半导体衬底220，所述光芯半导体衬底220暴露出所述光耦合区A。
所述光电芯片封装结构还包括：贯穿所述光介质层210和所述光芯半导体衬底220的第一导电插塞230；位于所述光芯片200背面的第一重布线层251；所述第一导电插塞230的一端电学连接所述第一电芯片300，所述第一导电插塞230的另一端与所述第一重布线层251连接；与所述第一重布线层251电学连接的第一焊球260。
本申请另一实施例还提供一种光电芯片封装结构的封装方法，请在图2的基础上参考图13～图24。
参考图13，图13为在图2基础上的示意图，在所述光介质层210中形成第一导电插塞230’，在所述光芯片200的正面形成光芯重布线层240’。
所述第一导电插塞230’仅贯穿所述光介质层210，但是并不位于光芯半导体衬底220中。
部分光芯重布线层240’与第一导电插塞230’连接，部分光芯重布线层240’与所述引出线连接。
参考图14，在所述光芯片200的正面上方形成第二导电插塞241。
具体的，所述第二导电插塞241与部分光芯重布线层240’连接。
在一个具体的实施例中，在所述光芯片200的正面上方形成所述第二导电插塞241的方法包括：提供第二导电插塞241，将所述第二导电插塞241压接或焊接在所述部分光芯重布线层240’上。
在另一个具体的实施例中，在所述光芯片200的正面上方形成所述第二导电插塞241的方法包括：在所述光芯片200的正面上方形成图案化的光阻；采用电镀工艺在所述图案化的光阻中形成第二导电插塞241；之后，去除所述图案化的光阻。
参考图15，在所述光芯片200的正面设置第一电芯片300’，所述第一电芯片300’与所述光芯片200电学连接；在所述光芯片200的正面形成与所述光耦合区A表面接触的保护结构400’，所述保护结构400’的折射率小于所述光介质层210的折射率。
具体的，第一电芯片300’的正面具有电芯焊盘，所述电芯焊盘表面具有电芯焊球，所述第一电芯片300’通过所述电芯焊球与部分光芯重布线层240’连接。
具体的，提供保护结构400’，将所述保护结构400’与所述光耦合区A的表面贴装在一起。贴装所述保护结构400’之后，所述第一电芯片300’位于所述保护结构400’的侧部。
部分的所述光芯重布线层240’分别与第一导电插塞230’和第一电芯片300’连接。
在一个具体的实施例中，在所述光芯片200的正面形成所述保护结构400’之后，在所述光芯片200的正面上方设置第一电芯片300’。在另一个具体的实施例中，在所述光芯片200的正面上方设置第一电芯片300’之后，在所述光芯片200的正面形成所述保护结构400’。
在一个具体的实施例中，所述保护结构400’的折射率为所述光介质层210的折射率的94％～99％。
所述保护结构400’的材料为掺杂有改性离子的石英玻璃，所述改性离子包括氟离子或者硼离子。或者，所述保护结构的材料为氟化镁。
与所述光耦合区A表面接触的所述保护结构400’的厚度为300微米～800微米。
所述保护结构400’相对于所述光耦合区A的侧壁凸出；所述保护结构400’中具有定位凹槽，所述定位凹槽用于对光纤进行定位组装。
所述定位凹槽的形状包括“V”形。
所述定位凹槽具有第一侧壁和与第一侧壁连接的第二侧壁，所述第一侧壁与所述光耦合区的侧壁齐平且适于与光纤的部分端面相对，所述第二侧壁适于与光纤的侧壁接触。
所述定位凹槽可以为单个，或者定位凹槽为并列排布的多个。
参考图16，形成塑封层500’，所述塑封层500’一体塑封所述光芯片200的正面、所述第一电芯片300’、所述保护结构400’和第二导电插塞241。
参考图17，减薄所述塑封层500’，直至暴露出所述第二导电插塞241的顶面。
由于第二导电插塞241的高于所述第一电芯片300’的顶面和所述保护结构400’的 顶面，因此减薄所述塑封层500’之后，所述塑封层500’还完全覆盖所述第一电芯片300’的顶面和所述保护结构400’的顶面。
参考图18，在所述塑封层500’表面形成第二重布线层242，所述第二重布线层242与第二导电插塞241连接。
参考图19，形成所述第二重布线层242之后，去除所述光芯半导体衬底220。
参考图20，去除所述光芯半导体衬底220之后，在所述光介质层210的背面形成第一重布线结构，所述第一重布线结构包括第一重布线层244，所述第一重布线层244与所述第一导电插塞230’连接。
所述第一重布线层结构包括第一绝缘层和位于第一绝缘层中的第一重布线层244。所述第一重布线层244的材料为金属。
需要说明的是，本实施例中，在去除所述光芯半导体衬底220之后，还在所述第二重布线层242上形成临时键合层243；形成临时键合层243之后，在所述光介质层210的背面形成第一重布线结构。
所述临时键合层243为形成第一重布线结构提供较好的工艺平台。
具体的，在所述光介质层210的背面形成第一重布线结构的过程中，通过曝光和显影去除光耦合区A底部的第一重布线结构，或通过刻蚀去除光耦合区A底部的第一重布线结构，以暴露出所述光耦合区A。
刻蚀去除光耦合区A底部的第一重布线结构，这样使得光耦合区A底面悬空，光耦合区A的底面不与其他膜层直接接触。在光传输的过程中，光耦合区A底部悬空的介质为空气，因此光耦合区A底部悬空的区域的折射率小于所述光介质层的折射率，这样光耦合区A内的光不易向光耦合区A底部泄露。
参考图21，刻蚀光介质层210，以暴露出光耦合区A的耦合端面。
具体的，将保护结构400’中的定位凹槽底部的光介质层210刻蚀去除，而与保护结构400’接触的光介质层210是保留的。
参考图22，去除所述临时键合层243；去除所述临时键合层243之后，在所述第二重布线层242表面形成第二焊球245。
参考图23，形成第二焊球245之后，进行划片切割。
具体的，沿着图22中虚线的位置，对保护结构400’和塑封层500’进行切割。
所述保护结构400’相对于所述光耦合区的侧壁凸出；所述保护结构400’中具有 定位凹槽。
参考图24，划片切割之后，将第二电芯片800通过第一焊球801贴装在所述第一重布线层244上；之后，将所述光纤结构700’定位组装在所述定位凹槽中。
所述第二电芯片800实现数据处理和存储。
将所述光芯片200和第一电芯片300’封装在一起的结构贴装在基板600’上，具体的，将所述第二重布线层242通过第二焊球245与基板600’焊接在一起；之后，将所述光纤结构700’定位组装在所述定位凹槽中。
本实施例中，由于将所述光芯片200、第一电芯片300’和第二电芯片800封装在一起的结构置于所述基板600’上之后，所述保护结构400’中的定位凹槽的是朝上的，因此在将光纤结构700’定位组装在所述定位凹槽中的过程中，操作端可直接将光纤结构700’从上至下的方向放置在所述定位凹槽中，利于操作的顺利完成，且在操作的过程中，操作人员可直观的看到所述定位凹槽的内部结构，因此利于准确的定位光纤结构700’。
本实施例中，不仅将第一电芯片300’与所述光芯片200封装在一起，还将第二电芯片800与所述光芯片200封装在一起，提高了光电芯片封装结构的集成度。
相应的，本实施例还提供一种光电芯片封装结构，请参考图24，包括：光芯片，所述光芯片包括光介质层210，所述光介质层210的一侧边缘区域为光耦合区A(参考图2)；位于所述光芯片的正面且接触所述光耦合区A表面的保护结构400’，所述保护结构400’的折射率小于所述光介质层的折射率。
所述保护结构400’的折射率为所述光介质层的折射率的94％～99％。
所述保护结构400’的材料为掺杂有改性离子的石英玻璃，所述改性离子包括氟离子或者硼离子；或者，所述保护结构的材料为氟化镁。
与所述光耦合区表面接触的所述保护结构的厚度为300微米～800微米。
所述保护结构400’相对于所述光耦合区的侧壁凸出；所述保护结构400’中具有定位凹槽，所述定位凹槽用于对光纤进行定位组装。
所述定位凹槽的形状包括“V”形。
所述定位凹槽具有第一侧壁和与第一侧壁连接的第二侧壁，所述第一侧壁与所述光耦合区的侧壁齐平且适于与光纤的部分端面相对，所述第二侧壁适于与光纤的侧壁接触。
所述光电芯片封装结构还包括：位于所述定位凹槽中的光纤结构700’；所述光纤结构700’为单个的光纤；或者所述光纤结构700’为光纤阵列。
所述光电芯片封装结构还包括：设置在所述光芯片的正面的第一电芯片300’，所述第一电芯片300’与所述光芯片电学连接，所述第一电芯片300’位于所述保护结构400’的侧部；塑封层500’，所述塑封层500’一体塑封所述光芯片的正面、所述第一电芯片300’和所述保护结构400’。
所述光电芯片封装结构还包括：位于所述光芯片背面的第一重布线结构，所述第一重布线结构位于光介质层210的表面，所述第一重布线结构暴露出所述光耦合区A，所述第一重布线结构包括第一绝缘层和位于第一绝缘层中的第一重布线层244。
所述光电芯片封装结构还包括：贯穿所述光介质层210的第一导电插塞230’；所述第一导电插塞230’的一端电学连接所述第一电芯片300’，所述第一导电插塞230’的另一端与所述第一重布线层244连接；与所述第一重布线层244电学连接的第一焊球801；位于所述光芯片背面的第二电芯片800，所述第二电芯片800与所述第一焊球801连接。
所述光电芯片封装结构还包括：位于所述塑封层500’表面且朝向所述第一电芯片300’的背面的第二重布线层242；贯穿所述塑封层500’的第二导电插塞241，所述第二导电插塞241的一端与所述第一电芯片300’电学连接，所述第二导电插塞241的另一端与第二重布线层242连接；与所述第二重布线层242电学连接的第二焊球245。
显然，上述实施例仅仅是为清楚地说明所作的举例，而并非对实施方式的限定。对于所属领域的普通技术人员来说，在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引伸出的显而易见的变化或变动仍处于本申请的保护范围之中。

Claims (22)

  1. 一种光电芯片封装结构，其特征在于，包括：
    光芯片，所述光芯片包括光介质层，所述光介质层的一侧边缘区域为光耦合区；
    位于所述光芯片的正面且接触所述光耦合区表面的保护结构，所述保护结构的折射率小于所述光介质层的折射率。
  2. 根据权利要求1所述的光电芯片封装结构，其特征在于，所述保护结构的折射率为所述光介质层的折射率的94％～99％。
  3. 根据权利要求1所述的光电芯片封装结构，其特征在于，所述保护结构的材料为掺杂有改性离子的石英玻璃，所述改性离子包括氟离子或者硼离子；
    或者，所述保护结构的材料为氟化镁。
  4. 根据权利要求1所述的光电芯片封装结构，其特征在于，与所述光耦合区表面接触的所述保护结构的厚度为300微米～800微米。
  5. 根据权利要求1所述的光电芯片封装结构，其特征在于，所述保护结构相对于所述光耦合区的侧壁凸出；所述保护结构中具有定位凹槽，所述定位凹槽用于对光纤进行定位组装。
  6. 根据权利要求5所述的光电芯片封装结构，其特征在于，所述定位凹槽的形状包括“V”形。
  7. 根据权利要求5所述的光电芯片封装结构，其特征在于，所述定位凹槽具有第一侧壁和与第一侧壁连接的第二侧壁，所述第一侧壁与所述光耦合区的侧壁齐平且适于与光纤的部分端面相对，所述第二侧壁适于与光纤的侧壁接触。
  8. 根据权利要求5所述的光电芯片封装结构，其特征在于，还包括：位于所述定位凹槽中的光纤结构；
    所述光纤结构为单个的光纤；或者所述光纤结构为光纤阵列。
  9. 根据权利要求1所述的光电芯片封装结构，其特征在于，还包括：设置在所述光芯片的正面的第一电芯片，所述第一电芯片与所述光芯片电学连接，所述第一电芯片位于所述保护结构的侧部；塑封层，所述塑封层一体塑封所述光芯片的正面、所述第一电芯片和所述保护结构。
  10. 根据权利要求9所述的光电芯片封装结构，其特征在于，还包括：所述光芯片还包括位于所述光介质层底部的光芯半导体衬底，所述光芯半导体衬底暴露出所述光耦合 区。
  11. 根据权利要求10所述的光电芯片封装结构，其特征在于，还包括：贯穿所述光介质层和所述光芯半导体衬底的第一导电插塞；位于所述光芯片背面的第一重布线层；所述第一导电插塞的一端电学连接所述第一电芯片，所述第一导电插塞的另一端与所述第一重布线层连接；与所述第一重布线层电学连接的第一焊球。
  12. 根据权利要求9所述的光电芯片封装结构，其特征在于，还包括：位于所述光芯片背面的第一重布线结构，所述第一重布线结构位于光介质层的表面，所述第一重布线结构暴露出所述光耦合区，所述第一重布线结构包括第一绝缘层和位于第一绝缘层中的第一重布线层。
  13. 根据权利要求12所述的光电芯片封装结构，其特征在于，还包括：贯穿所述光介质层的第一导电插塞；所述第一导电插塞的一端电学连接所述第一电芯片，所述第一导电插塞的另一端与所述第一重布线层连接；与所述第一重布线层电学连接的第一焊球；位于所述光芯片背面的第二电芯片，所述第二电芯片与所述第一焊球连接。
  14. 根据权利要求12所述的光电芯片封装结构，其特征在于，还包括：位于所述塑封层表面且朝向所述第一电芯片的背面的第二重布线层；贯穿所述塑封层的第二导电插塞，所述第二导电插塞的一端与所述第一电芯片电学连接，所述第二导电插塞的另一端与第二重布线层连接；与所述第二重布线层电学连接的第二焊球。
  15. 一种光电芯片封装结构的封装方法，用于形成权要1～9任意一项所述的光电芯片封装结构，其特征在于，包括：
    提供光芯片，所述光芯片包括光介质层，所述光介质层的一侧边缘区域为光耦合区；
    在所述光芯片的正面形成与所述光耦合区表面接触的保护结构，所述保护结构的折射率小于所述光介质层的折射率。
  16. 根据权利要求15所述的光电芯片封装结构的封装方法，其特征在于，还包括：在所述光芯片的正面设置第一电芯片，所述第一电芯片与所述光芯片电学连接；形成所述保护结构之后，所述第一电芯片位于所述保护结构的侧部；形成塑封层，所述塑封层一体塑封所述光芯片的正面、所述第一电芯片和所述保护结构。
  17. 根据权利要求16所述的光电芯片封装结构的封装方法，其特征在于，所述光芯片还包括位于所述光介质层底部的光芯半导体衬底；
    所述封装方法还包括：在设置所述第一电芯片和形成所述保护结构之前，在所述光介质层和光芯半导体衬底中形成第一导电插塞；在所述光芯片的正面形成光芯重布线层，所 述光芯重布线层分别与第一导电插塞和第一电芯片连接；形成所述塑封层之后，在所述光芯半导体衬底的背面形成第一重布线层结构，所述第一重布线层结构包括第一重布线层，所述第一重布线层与所述第一导电插塞连接；在所述第一重布线层结构表面形成第一焊球；形成第一焊球之后，进行划片切割。
  18. 根据权利要求17所述的光电芯片封装结构的封装方法，其特征在于，还包括：刻蚀去除光耦合区底部的光芯半导体衬底，以暴露出所述光耦合区。
  19. 根据权利要求16所述的光电芯片封装结构的封装方法，其特征在于，在形成所述保护结构之前，所述光芯片还包括位于所述光介质层底部的光芯半导体衬底；
    所述封装方法还包括：在设置所述第一电芯片和形成所述保护结构之前，在所述光介质层中形成第一导电插塞，在所述光芯片的正面形成光芯重布线层，所述光芯重布线层分别与第一导电插塞和第一电芯片连接；在形成所述塑封层之前，在所述光芯片的正面上方形成第二导电插塞；形成所述塑封层之后，所述塑封层还一体塑封所述第二导电插塞，且所述塑封层暴露出所述第二导电插塞的顶面；在所述塑封层表面形成第二重布线层，所述第二重布线层与第二导电插塞连接；形成所述第二重布线层之后，去除所述光芯半导体衬底；去除所述光芯半导体衬底之后，在所述光介质层背面形成第一重布线结构，所述第一重布线结构包括第一重布线层，所述第一重布线层与所述第一导电插塞连接。
  20. 根据权利要求19所述的光电芯片封装结构的封装方法，其特征在于，还包括：去除所述光耦合区底部的第一重布线结构，以暴露出所述光耦合区。
  21. 根据权利要求19或20所述的光电芯片封装结构的封装方法，其特征在于，还包括：在形成所述第一重布线结构之后，在所述第二重布线层表面形成第二焊球；形成第二焊球之后，进行划片切割；划片切割之后，将第二电芯片通过第一焊球贴装在所述第一重布线层上。
  22. 根据权利要求15所述的光电芯片封装结构的封装方法，其特征在于，所述保护结构相对于所述光耦合区的侧壁凸出；所述保护结构中具有定位凹槽；提供光纤结构，将所述光纤结构定位组装在所述定位凹槽中。
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