WO2022041962A1 - 数据传输电路和存储器 - Google Patents

数据传输电路和存储器 Download PDF

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Publication number
WO2022041962A1
WO2022041962A1 PCT/CN2021/100853 CN2021100853W WO2022041962A1 WO 2022041962 A1 WO2022041962 A1 WO 2022041962A1 CN 2021100853 W CN2021100853 W CN 2021100853W WO 2022041962 A1 WO2022041962 A1 WO 2022041962A1
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Prior art keywords
data
redundant
read
module
unit
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PCT/CN2021/100853
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English (en)
French (fr)
Inventor
冀康灵
李红文
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21859806.8A priority Critical patent/EP4030435B1/en
Priority to US17/467,547 priority patent/US11687402B2/en
Publication of WO2022041962A1 publication Critical patent/WO2022041962A1/zh
Priority to US17/736,154 priority patent/US11860734B2/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44—Indication or identification of errors, e.g. for repair
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/52—Protection of memory contents; Detection of errors in memory contents
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits

Definitions

  • the present invention relates to a data transmission circuit and a memory.
  • DRAM Dynamic Random Access Memory
  • a first aspect of the present application provides a data transmission circuit, the data transmission circuit comprising:
  • a normal reading module connected to the normal storage array, for reading data from the normal storage array and outputting;
  • a redundant read module connected to the redundant storage array, for reading data from the redundant storage array and outputting;
  • the error detection operation module is respectively connected with the normal reading module and the redundant reading module, and is used for synchronously receiving the read data output by the normal reading module and the redundant reading module, and for all The read data is used for error detection operation.
  • a second aspect of the present application provides a memory, including:
  • a plurality of data pin areas, the data pin areas are in one-to-one correspondence with the normal storage array;
  • the data transmission circuit is respectively connected to the redundant memory array, the normal memory array and the data pin area.
  • FIG. 1 is a structural block diagram of a data transmission circuit according to an embodiment.
  • FIG. 2 is a structural diagram of a data transmission circuit according to another embodiment.
  • FIG. 3 is a structural diagram of a data transmission circuit according to another embodiment.
  • FIG. 4 is a structural diagram of a data transmission circuit according to still another embodiment.
  • Normal read module 100; Data bit read unit: 111; Flag bit read unit: 112; Redundant read module: 113; Data bit write unit: 121; Flag bit write unit: 122; Redundant write Input module: 123; logic operation unit: 131; first multiplexer: 141; normal error correction unit: 151; redundant error correction unit: 152; write operation unit: 161; second multiplexer: 171 ;Normal storage array: 200; Data bit storage array: 210; Flag bit storage array: 220; Redundant storage array: 230; Data pin area: 240; Error detection operation module: 300; Redundant data bus: 400; Bit coding module: 500; Enable control module: 600
  • the current data transmission circuit takes a long time to read the redundant memory array, thus greatly reducing the processing speed of the dynamic random access memory.
  • the data transmission circuit includes a normal reading module 100 , a redundant reading module 113 and an error detection operation module 300 .
  • the normal reading module 100 is connected to the normal storage array 200 for reading and outputting data from the normal storage array 200 .
  • the normal storage array 200 refers to a storage array used when the memory operates normally, and the memory includes a plurality of normal storage arrays 200 .
  • the redundant read module 113 is connected to the redundant storage array 230, and is used for reading data from the redundant storage array 230 and outputting the data.
  • the redundant storage array 230 refers to a storage array used for replacement when the normal storage array 200 is damaged.
  • the damage of the normal storage array 200 includes the damage caused during the preparation of the memory, and also includes the damage during the use of the memory.
  • the normal storage array 200 and the redundant storage array 230 are prepared at the same time. Usually, multiple normal storage arrays 200 correspond to one redundant storage array 230.
  • the redundant storage array is repaired through a repair process. 230 replaces the damaged normal storage array 200, thereby realizing the repair of the storage array.
  • the data to be stored in the damaged normal storage array 200 will be stored in the redundant storage array 230, and if the data in the damaged normal storage array 200 needs to be read, it will be stored from the corresponding redundant storage array 200.
  • Memory array 230 reads.
  • the error detection operation module 300 is respectively connected with the normal reading module 100 and the redundant reading module 113, and is used for synchronously receiving the reading data output by the normal reading module 100 and the redundant reading module 113, and checking the reading data. wrong operation.
  • both the normal read module 100 and the redundant read module 113 are connected to the error detection operation module 300, and transmit the read data to the error detection operation module 300 in parallel, that is, regardless of whether the normal memory array 200 occurs or not damaged, the normal reading module 100 reads the normal storage array 200, and the redundant reading module 113 reads the redundant storage array 230 synchronously. After the reading is completed, the normal reading module 100 and the redundant reading module 113 synchronously read The read data is sent to the error detection operation module 300 . Therefore, the step of querying the address of the damaged normal memory array 200 does not need to be performed first, thereby simplifying the serial steps of data reading and realizing a data transmission circuit with a faster reading speed.
  • the normal storage array 200 includes a flag bit storage array 220 and a plurality of data bit storage arrays 210
  • the normal read module 100 includes a flag bit read unit 112 and a plurality of data bit read units unit 111.
  • the data bit reading unit 111 is connected to the data bit storage array 210 in a one-to-one correspondence, and is used for reading data information from the corresponding data bit storage array 210 .
  • the flag bit reading unit 112 is connected to the flag bit storage array 220 for reading the flag information from the flag bit storage array 220 .
  • the flag information corresponds to the data information, that is, unique flag information can be generated according to the data information, and according to the flag information, it can also be reversely judged whether the corresponding data information is in error. That is, if the data information changes, the flag information also changes accordingly. Therefore, by comparing the flag information corresponding to the written data information and the flag information corresponding to the read data information, it can be determined whether the written data information and the read data information are the same.
  • the read data information needs to be the same as the written data information to be an effective data read and write process, otherwise the read data information will be wrong. Therefore, if the two flag information when writing and reading are the same, it means that the written data information is the same as the read data information, and the data reading and writing process is valid; if the two flags of writing and reading are valid If the information is different, it means that the written data information is different from the read data information, that is, the data information changes during the writing and/or reading process, and the changed data needs to be error-corrected to generate a correct read Get data information.
  • the error detection operation circuit judges whether it is necessary to perform error correction on the read data information by comparing the flag information corresponding to the written data information with the flag information corresponding to the read data information, thereby improving the Accuracy of reading data.
  • the multiple data bit storage arrays 210 correspond to one flag bit storage array 220 , that is, one flag bit storage array 220 is used to store the flag information corresponding to the data information of the multiple data bit storage arrays 210 .
  • 16 data bit storage arrays 210 may correspond to one flag bit storage array 220 , and correspondingly, 16 data bit reading units 111 correspond to one flag bit reading unit 112 .
  • the data transmission circuit further includes an enabling control module 600, and the enabling control module 600 is connected to the redundant reading module 113 and the plurality of data bit reading units 111, respectively.
  • the enable control module 600 is used to generate redundant read enable signal Read Repair and multiple data bit read enable signals Read killn, wherein n is the same as the number of data bit storage arrays, and the data bit read enable signal Read killn is the same as the data bit read enable signal Read killn.
  • the bit reading units 111 are in one-to-one correspondence
  • the redundant read enable signal Read Repair corresponds to the redundant read module 113
  • the enable control module 600 is also used to send the redundant read enable signal Read Repair and the data bits in one-to-one correspondence respectively.
  • the read enable signal Read killn is sent to the data bit read unit 111 or the redundant read module 113. Among them, when the redundant read enable signal Read Repair is valid, one of the multiple data bit read enable signals Read Killn is invalid; when the redundant read enable signal Read Repair is invalid, the multiple data bit read enable signals Read killn is valid.
  • the data bit read enable signal is named Read killn
  • the redundant read enable signal Read Repair is named Read Repair. Since the data bit read enable signal Read killn corresponds to the data bit read unit 111 one-to-one, the number of the data bit read enable signal Read killn is the same as that of the data bit read unit 111. For example, if the data bit read unit If the number of 111 is 16, the number of data bit read enable signals Read killn is also 16, and the 16 data bit read enable signals Read killn can be named Read kill0 ⁇ Read kill15 respectively.
  • enable control module 600 is also connected with the flag bit reading unit 112, and the enable control module 600 is also used to generate the flag bit read enable signal Read killcc, thereby realizing the control of the flag bit reading unit 112.
  • each data bit storage array 210 of the memory is inspected to determine the damaged data bit storage array 210, and then each data bit storage array 210 is marked according to the inspection result, and is generated for storage.
  • Each data bit stores a look-up table of tags for array 210 . Therefore, the flag determines the data bit read enable signal Read killn of the corresponding data bit storage array 210. For example, when the data bit storage array 210 is damaged, it is marked as 0, and the corresponding generated data bit read enable signal Read killn is invalid; when the data bit storage array 210 is not damaged, it is marked as 1, corresponding to the generated data bit The read enable signal Read killn is valid.
  • the control module 600 is enabled to read the above lookup table synchronously to Obtain information on whether damage occurs to each data bit storage array 210, thereby generating redundant read enable signals Read Repair and multiple data bit read enable signals Read killn according to the queried information.
  • FIG. 2 is a structural diagram of a data transmission circuit according to another embodiment, and FIG. 2 shows a plurality of modules and units related to a data reading process.
  • the memory includes a plurality of data bit storage arrays 210, for example, 8, 16, or 32, etc. However, in order to simplify the drawing, only two data bit storage arrays 210 and their storage arrays 210 are shown in FIG. 2 .
  • the corresponding data transmission structure similarly, the drawings of other embodiments of the present application are also simplified, and will not be repeated in other drawings.
  • the data transmission circuit further includes a plurality of logic operation units 131 , and one input end of the logic operation units 131 corresponds to the data bit reading unit 111 , the flag bit reading unit 112 and the redundant reading unit 111 .
  • One of the modules 113 is connected, the other input terminal of the logic operation unit 131 is connected to the enable signal, the output terminal of the logic operation unit 131 is connected to the error detection operation module 300, and the logic operation unit 131 is used to input the two input terminals. Perform a preset operation on the data obtained, and send the operation result to the error detection operation module 300 .
  • the logic operation unit 131 performs preliminary processing on the received data according to the enable signal, and then sends the processed data to the error detection operation module 300 , thereby simplifying the operation complexity of the error detection operation module 300 , the operation speed of the error detection operation module 300 is improved.
  • the logic operation unit 131 is a logic AND unit, and one input of the logic AND unit is connected to one of the data bit reading unit 111 , the flag bit reading unit 112 and the redundant reading module 113 correspondingly , the other input terminal of the logical AND unit is connected to the enable signal, the output terminal of the logical AND unit is connected to the error detection operation module 300, and the logical operation unit 131 is used to perform a logical AND operation on the data input from the two input terminals, and connect the The operation result is sent to the error detection operation module 300 .
  • the data output by the first data bit read unit 111 and the data bit read enable signal Read kill0 perform a logical AND operation .
  • the data bit read enable signal Read kill0 When the data bit read enable signal Read kill0 is 0, it indicates that the corresponding data bit storage array 210 is damaged, and the data output by the data bit read unit 111 is logically ANDed with 0, and the data output by the logical AND unit is all 0. For example, if it is 8-bit data, the logical AND unit corresponding to the data bit reading unit 111 outputs 00000000. At the same time, under the control of the flag read enable signal Read killcc, the logical AND unit corresponding to the flag read unit 112 also outputs 0. Based on the above-mentioned arithmetic processing of the logical AND unit, the data information can be matched with the flag information, and error detection can be performed. The detection result of the operation module 300 is "no error", so the error detection operation module 300 does not need to further obtain the information of the erroneous data bits, thereby simplifying the operation steps and complexity of the error detection operation module 300 .
  • the logic operation unit 131 of this embodiment does not affect the data transmission and error detection functions of the undamaged data bit storage array 210, and can also reduce the difficulty of data transmission and error detection of the damaged data bit storage array 210, thereby realizing A fast data transmission circuit is developed.
  • the logic operation unit 131 is not limited to the AND unit provided in the above embodiments, and may also be a NAND unit or the like. As long as the logical operation unit 131 can satisfy the following conditions: when the data bit read enable signal Read killn takes effect, the data read by the data bit read unit 111 is output; when the data bit read enable signal Read killn fails, the output preset data.
  • the preset data output by the logic operation unit 131 corresponding to the data bit reading unit 111 may also be, for example, 11111111, 01010101, etc.
  • the preset data output by the logic operation unit 131 corresponding to the flag bit reading unit 112 may be, for example, 0.
  • the error detection operation module 300 is configured to output a plurality of error detection information, and the error detection information is in one-to-one correspondence with the data bit reading unit 111 , and the data transmission circuit further includes a normal error correction unit 151 and a redundant data bus. 400 and a plurality of first multiplexers 141.
  • the error detection information includes whether the read data information is the same as the written data information. When the two are different, the error detection information further includes specific error data bits. For example, if the written data information is 10000000, read The fetched data information is 11000000, then the error data bit is the second bit.
  • the normal error correction unit 151 is connected to the data bit reading unit 111 in a one-to-one correspondence, and is also connected to the error detection operation module 300.
  • the normal error correction unit 151 is used to receive error detection information, and update the corresponding data bit reading according to the error detection information Data information output by unit 111. Since the data in the memory is stored in binary, when there is an error in reading the data, error correction can be performed directly according to the error detection information. For example, if the data information output by the data bit reading unit 111 is 11000000, and the second bit is marked as an error data bit in the error detection information, then the written data information must be 10000000, and the normal error correction unit 151 can correct the data information Updates are made to complete error correction.
  • the redundant data bus 400 is connected to the redundant reading module 113 for receiving data output by the redundant reading module 113 . Specifically, after reading the data from the redundant storage array 230, the redundant reading module 113 transmits the read data to the redundant data bus 400, so that the first multiplexing corresponding to the damaged data bit storage array 210 is selected.
  • the controller 141 can obtain the read data from the redundant data bus 400 .
  • the first multiplexer 141 has a one-to-one correspondence with the normal error correction unit 151, one input terminal of the first multiplexer 141 is connected to the corresponding normal error correction unit 151, and the other input terminal of the first multiplexer is connected to the redundant unit.
  • the remaining data bus 400 is connected, and the first multiplexer 141 is used to receive the data bit read enable signal Read killn, and select and output the data input by any input terminal under the control of the data bit read enable signal Read killn.
  • the first A multiplexer 141 selects and outputs data from the redundant data bus 400, that is, the redundant storage array 230 replaces the data bit storage array 210; when the data bit read enable signal Read kill0 is 1, the corresponding If the data bit storage array 210 is not damaged, the first multiplexer 141 selects and outputs the data from the normal error correction unit 151 , that is, the data read by the data bit reading unit 111 is normally output.
  • the normal error correction unit 151 is configured to directly send the data information output by the data bit reading unit 111 to the first multiplexer 141 when the error detection information is invalid.
  • "error detection information is invalid" means that the read data information is the same as the written data information, and it is not necessary to perform error correction on the read data information.
  • the normal error correction unit 151 is configured to perform error correction on the data information output by the data bit reading unit 111 according to the error detection information when the error detection information is valid, so as to update the data information, and update the updated data information.
  • the data information is sent to the first multiplexer 141 .
  • "the error detection information is valid" means that the read data information is different from the written data information, and it is necessary to correct the read data information according to the error detection information, so as to realize the correct output of the data information.
  • the normal error correction unit 151 is further configured to send the updated data information to the corresponding data bit storage array 210 when the error detection information is valid, so as to update the data information stored in the normal storage array 200 .
  • the data information stored in the corresponding data bit storage array 210 also has the risk of error. Therefore, in this embodiment, the data information stored in the data bit storage array 210 is The update can improve the accuracy of the stored data information, thereby reducing the error correction amount of the normal error correction unit 151 and improving the running speed of the data transmission circuit.
  • the redundant read module 113 is configured to send the data read by the redundant read module 113 to the redundant data bus 400 when the redundant read enable signal Read Repair is valid; the first multiplexing The device 141 is used to select and output the data on the redundant data bus 400 when the data bit read enable signal Read kill0 is invalid.
  • the error detection operation module 300 is further configured to output error detection information corresponding to the redundant read module 113
  • the data transmission circuit further includes: a redundant error correction unit 152, which is respectively connected to the redundant error correction unit 152.
  • the redundant read module 113, the error detection operation module 300 are connected to the redundant data bus 400, and the redundant error correction unit 152 is used for updating according to the error detection information when the error detection information is valid and the redundant read enable signal Read Repair is valid
  • the data output by the redundant read module 113 is read, and the updated data is sent to the redundant data bus 400 .
  • the redundant error correction unit 152 is configured to perform error correction on the data read by the redundant reading module 113 , so as to achieve the reading accuracy of the redundant reading module 113 .
  • FIG. 3 is a structural diagram of a data transmission circuit according to another embodiment, and FIG. 3 shows a plurality of modules and units related to a data writing process.
  • the data transmission circuit further includes a flag bit writing unit 122 , a redundant writing module 123 and a plurality of data bit writing units 121 .
  • the plurality of data bit writing units 121 are connected to the plurality of data bit storage arrays 210 in one-to-one correspondence, and are also connected to the redundant data bus 400 for sending data information to the data bit storage array 210 or the redundant data bus 400;
  • the flag bit writing unit 122 is respectively connected with the flag bit storage array 220 and the redundant data bus 400, and is used for sending the flag information to the flag bit storage array 220 or the redundant data bus 400;
  • the redundant write module 123 is connected to the redundant storage array 230 and the redundant data bus 400 respectively, and is used for writing data on the redundant data bus 400 into the redundant storage array 230 .
  • the data bit write enable signal Write killn matches the aforementioned data bit read enable signal Read killn, that is, if the data bit storage array 210 is damaged, its read and write functions are all performed by the redundant storage array 230 instead.
  • the data bit writing unit 121 sends the received data information to the redundant data bus 400, and sends the preset data to the flag bit encoding module 500 through the writing operation unit 161, so as to reduce the coding complexity of the flag bit encoding module 500, and the redundancy is reduced.
  • the redundant writing module 123 obtains the data information from the redundant data bus 400 and writes the data to the redundant storage array 230 .
  • the data bit write enable signal Write kill0 is 1, it means that the corresponding data bit storage array 210 is not damaged, then the data bit writing unit 121 sends the received data information to the corresponding data bit storage array 210, thereby realizing data Normal storage of information.
  • the data transmission circuit further includes: a flag bit encoding module 500, which is connected to the data bit writing unit 121 and the flag bit writing unit 122 respectively, and is used for receiving the data information output by the data bit writing unit 121, The data is encoded to generate flag information, and the flag information is sent to the flag bit writing unit 122 .
  • the flag bit encoding module 500 encodes the written data information according to the preset rules to generate unique flag information, and sends the generated flag information to the flag bit writing unit 122, so as to store the flag information for storing in the flag bit information. Error detection is performed when data information is read.
  • FIG. 4 is a structural diagram of a data transmission circuit according to still another embodiment, and FIG. 4 shows a plurality of modules and units related to data writing and reading processes.
  • the data transmission circuit further includes a second multiplexer 171 , and the two input terminals of the second multiplexer 171 are respectively connected to the data bit reading unit 111 and the data bit writing unit 121 connection, the second multiplexer 171 is used to turn on the data transmission path between any input terminal and the output terminal in time-division under the control of the read/write enable signal Wr/Rd, so as to realize the time-division writing of data and read function.
  • the error detection operation module 300 and the flag bit encoding module 500 are integrated to improve the integration degree of the memory. In other embodiments, the error detection operation module 300 and the flag bit encoding module 500 can also be set separately. .
  • the data bit writing unit 121 acquires the data information to be written from the data pin area 240 .
  • the corresponding data bit write enable signal Write kill0 is 1, and the data bit writing unit 121 sends the data information to the data bit storage array 210 and the flag bit encoding module 500 respectively, so as to Data information is stored and encoded.
  • the flag bit encoding module 500 is configured to encode the received data information according to a preset encoding rule to generate flag information, and send the flag information to the flag bit writing unit 122 for storage.
  • the redundant write enable signal Write Repair is 1, the data transmission path between the redundant data bus 400 and the redundant write module 123 is turned on, and the redundant write enable signal Write Repair is 1.
  • the writing module 123 obtains the data information to be written from the redundant data bus 400 and stores it.
  • the data bit reading unit 111 reads the data information from the corresponding data bit storage array 210, and sends The read data information is sent to the normal error correction unit 151, the flag bit encoding module 500 and the error detection operation module 300, and at the same time, the logic operation unit 131 sends preset data to the first under the control of the redundant read enable signal Read Repair.
  • Two multiplexers 171 Two multiplexers 171 .
  • the flag bit encoding module 500 encodes according to the received data information to generate the flag information corresponding to the read data information
  • the error detection operation module 300 receives the flag information corresponding to the read data information, and obtains from the flag bit reading unit 112
  • the flag information corresponding to the written data information the error detection operation module 300 compares the two flag information to generate error detection information
  • the normal error correction unit 151 corrects the read data information according to the error detection information and outputs it to Data pin area 240 .
  • the redundant read enable signal Read Repair is 1
  • the redundant read module 113 sends the read data to the redundant correction
  • the error unit 152, the flag bit encoding unit and the error detection operation module 300 are used to perform error detection and error correction steps.
  • the computational complexity of the error detection operation module 300 after the redundant error correction unit 152 processes the received data information, the data information is sent to the redundant data bus 400, and the data bit read enable signal Read kill0 makes the damaged data bits
  • the data transmission path between the first multiplexer 141 corresponding to the storage array 210 and the redundant data bus 400 is turned on, and the first multiplexer 141 corresponding to the damaged data bit storage array 210 is obtained from the redundant data bus 400
  • the data information is sent to the data pin area 240 under the control of the data bit read enable signal Read kill0.
  • the embodiment of the present application also provides a memory, including: a plurality of normal storage arrays 200; a redundant storage array 230; The data transmission circuit is connected to the redundant storage array 230, the normal storage array 200 and the data pin area 240 respectively. Regardless of whether the normal storage array 200 is damaged or not, the memory of this embodiment does not need to perform the step of querying the address of the damaged normal storage array 200 first, which simplifies the serial steps of data reading, thereby realizing a faster reading speed of memory.

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Abstract

一种数据传输电路和存储器，数据传输电路包括：正常读取模块，与正常存储阵列连接，用于从所述正常存储阵列中读取数据并输出；冗余读取模块，与冗余存储阵列连接，用于从所述冗余存储阵列中读取数据并输出；以及检错运算模块，分别与所述正常读取模块和所述冗余读取模块连接，用于同步接收所述正常读取模块和所述冗余读取模块输出的读取数据，并对所述读取数据进行检错运算。

Description

数据传输电路和存储器
相关申请交叉引用
本申请要求2020年08月27日递交的、标题为“数据传输电路和存储器”、申请号为2020108778613的中国申请，其公开内容通过引用全部结合在本申请中。
技术领域
本发明涉及一种数据传输电路和存储器。
背景技术
半导体存储器是一种利用半导体电路进行存取的存储器，其中，动态随机存取存储器(Dynamic Random Access Memory，DRAM)以其快速的存储速度和高集成度被广泛应用于各个领域。
为了获得更高的灵活性和可靠性，通常会在动态随机存储器中设置一定数量的冗余存储阵列，以在正常存储阵列发生损坏时作为替代。
发明内容
根据多个实施例，本申请第一方面提供一种数据传输电路，所述数据传输电路包括：
正常读取模块，与正常存储阵列连接，用于从所述正常存储阵列中读取数据并输出；
冗余读取模块，与冗余存储阵列连接，用于从所述冗余存储阵列中读取数据并输出；以及
检错运算模块，分别与所述正常读取模块和所述冗余读取模块连接，用于同步接收所述正常读取模块和所述冗余读取模块输出的读取数据，并对所述读取数据进行检错运算。
对应地与对应地与根据多个实施例，本申请第二方面提供一种存储器，包括：
多个正常存储阵列；
冗余存储阵列；
多个数据引脚区，所述数据引脚区与所述正常存储阵列一一对应；以及
如上述的数据传输电路，所述数据传输电路分别与所述冗余存储阵列、所述正常存储阵列和所述数据引脚区连接。
本申请的一个或多个实施例的细节在下面的附图和描述中提出。本申请的其它特征和 优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本申请实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一实施例的数据传输电路的结构框图。
图2为另一实施例的数据传输电路的结构图。
图3为又一实施例的数据传输电路的结构图。
图4为再一实施例的数据传输电路的结构图。
元件标号说明：
正常读取模块：100；数据位读取单元：111；标志位读取单元：112；冗余读取模块：113；数据位写入单元：121；标志位写入单元：122；冗余写入模块：123；逻辑运算单元：131；第一多路选择器：141；正常纠错单元：151；冗余纠错单元：152；写入运算单元：161；第二多路选择器：171；正常存储阵列：200；数据位存储阵列：210；标志位存储阵列：220；冗余存储阵列：230；数据引脚区：240；检错运算模块：300；冗余数据总线：400；标志位编码模块：500；使能控制模块：600
具体实施方式
目前的数据传输电路在对冗余存储阵列进行读取时的处理时间较长，因此大大降低了动态随机存储器的处理速度。
为了便于理解本发明，下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是，本发明可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
在本发明的描述中，需要理解的是，术语“上”、“下”、“竖直”、“水平”、“内”、 “外”等指示的方位或位置关系为基于附图所示的方法或位置关系，仅是为了便于描述本发明和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本发明的限制。
在现有技术中，当需要采用冗余存储阵列代替损坏的正常存储阵列进行数据读取时，需要先查询当前访问的正常存储阵列是否为被修复的存储阵列，若当前访问地址对应的正常存储阵列是被修复的存储阵列，则不去访问被修复的地址，而是去访问作为替代的冗余存储阵列的地址，从而实现数据的读取。可以理解的是，现有技术中被修复地址的查询和冗余存储阵列的读取是串行的，从而导致处理速度较慢。
进一步地，如果列冗余的修复不是局限在一个较小的范围内，而是在相对较大的范围内，例如，在整个一次读写操作的范围内进行全局修复(global repair)，那么需要先查询损坏的正常存储阵列的地址，然后再去读取对应的冗余存储阵列从而进行替换，因此所需要的操作时长会大大增加，而且后续进行检错操作也需要较长时间，从而共同导致存储器的访问速度降低。
图1为一实施例的数据传输电路的结构框图，参考图1，在本实施例中，数据传输电路包括正常读取模块100、冗余读取模块113和检错运算模块300。
正常读取模块100与正常存储阵列200连接，用于从正常存储阵列200中读取数据并输出。正常存储阵列200是指存储器正常运行时使用的存储阵列，存储器中包括多个正常存储阵列200。
冗余读取模块113与冗余存储阵列230连接，用于从冗余存储阵列230中读取数据并输出。冗余存储阵列230是指，当正常存储阵列200发生损坏时用于替代的存储阵列，正常存储阵列200的损坏包括存储器制备过程中导致的损坏，也包括存储器使用过程中的损坏。正常存储阵列200和冗余存储阵列230同时制备，通常多个正常存储阵列200与一个冗余存储阵列230相对应，当通过检测手段发现正常存储阵列200损坏时，通过修复工艺使冗余存储阵列230代替损坏的正常存储阵列200，从而实现存储阵列的修复。在存储阵列被修复后，待存储至损坏的正常存储阵列200的数据会被存储至冗余存储阵列230，而若需要读取损坏的正常存储阵列200中的数据，则将从对应的冗余存储阵列230读取。
检错运算模块300分别与正常读取模块100和冗余读取模块113连接，用于同步接收正常读取模块100和冗余读取模块113输出的读取数据，并对读取数据进行检错运算。
在本实施例中，正常读取模块100和冗余读取模块113均与检错运算模块300连接，且并行向检错运算模块300发送读取到的数据，即不论正常存储阵列200是否发生损坏， 正常读取模块100都读取正常存储阵列200，且冗余读取模块113同步读取冗余存储阵列230，读取完成后，正常读取模块100和冗余读取模块113同步将读取到的数据发送至检错运算模块300。因此，无需先执行查询损坏的正常存储阵列200的地址的步骤，从而简化了数据读取的串行步骤，实现了一种读取速度更快的数据传输电路。
在其中一个实施例中，继续参考图1，正常存储阵列200包括标志位存储阵列220和多个数据位存储阵列210，正常读取模块100包括标志位读取单元112和多个数据位读取单元111。
数据位读取单元111与数据位存储阵列210一一对应连接，用于从对应的数据位存储阵列210中读取数据信息。
标志位读取单元112与标志位存储阵列220连接，用于从标志位存储阵列220中读取标志信息。标志信息与数据信息相对应，即根据数据信息可以生成唯一的标志信息，且根据标志信息，也可以反向判断对应的数据信息是否出错。即，若数据信息发生变化，则标志信息也会相应地变化。因此，通过比对写入的数据信息对应的标志信息和读取的数据信息对应的标志信息，即可确定写入的数据信息和读取的数据信息是否相同。
需要说明的是，对于数据位存储阵列210而言，需要使读取的数据信息与写入的数据信息相同，才是有效的数据读写过程，否则会导致读取到的数据信息错误。因此，若写入和读取时的两个标志信息相同，则说明写入的数据信息与读取的数据信息相同，该数据读写过程是有效的；若写入和读取的两个标志信息不同，则说明写入的数据信息与读取的数据信息不同，即数据信息在写入和/或读取的过程中发生的变化，需要对变化的数据进行纠错，以生成正确的读取数据信息。在本实施例中，检错运算电路即通过比对写入的数据信息对应的标志信息和读取的数据信息对应的标志信息，来判断是否需要对读取的数据信息进行纠错，从而提高读取数据的准确性。
进一步地，多个数据位存储阵列210与一个标志位存储阵列220相对应，即一个标志位存储阵列220用于存储多个数据位存储阵列210的数据信息所对应的标志信息。例如，可以是16个数据位存储阵列210与一个标志位存储阵列220相对应，相应地，16个数据位读取单元111与一个标志位读取单元112相对应。
在其中一个实施例中，数据传输电路还包括使能控制模块600，使能控制模块600分别与冗余读取模块113和多个数据位读取单元111连接。使能控制模块600用于生成冗余读使能信号Read Repair和多个数据位读使能信号Read killn，其中，n与数据位存储阵列的数量相同，数据位读使能信号Read killn与数据位读取单元111一一对应，冗余读使能 信号Read Repair与冗余读取模块113对应，使能控制模块600还用于分别一一对应发送冗余读使能信号Read Repair和数据位读使能信号Read killn至数据位读取单元111或冗余读取模块113。其中，当冗余读使能信号Read Repair有效时，多个数据位读使能信号Read killn中的一个无效；当冗余读使能信号Read Repair无效时，多个数据位读使能信号Read killn均有效。
为了便于说明，在本申请实施例中将数据位读使能信号命名为Read killn，并将冗余读使能信号Read Repair命名为Read Repair。由于数据位读使能信号Read killn与数据位读取单元111一一对应，所以数据位读使能信号Read killn的数量与数据位读取单元111的数量相同，例如，若数据位读取单元111的数量为16，则数据位读使能信号Read killn的数量也为16，并可以将16个数据位读使能信号Read killn分别命名为Read kill0～Read kill15。
进一步地，使能控制模块600还与标志位读取单元112连接，使能控制模块600还用于生成标志位读使能信号Read killcc，从而实现对标志位读取单元112的控制。
存储器出厂之前，会对存储器的每个数据位存储阵列210进行检测，以从中确定出损坏的数据位存储阵列210，再根据检测结果对每个数据位存储阵列210进行标记，并生成用于保存每个数据位存储阵列210的标记的查询表。因此，标记即决定了对应的数据位存储阵列210的数据位读使能信号Read killn。例如，当数据位存储阵列210损坏时，则标记为0，对应生成的数据位读使能信号Read killn则失效；当数据位存储阵列210未损坏时，则标记为1，对应生成的数据位读使能信号Read killn则有效。
进一步地，数据位读取单元111和冗余读取模块113从对应的存储阵列读取数据需要占用约2ns的时长，在该时间段内，使能控制模块600同步读取上述查询表，以获取每个数据位存储阵列210是否发生损坏的信息，从而根据查询到的信息生成冗余读使能信号Read Repair和多个数据位读使能信号Read killn。
图2为另一实施例的数据传输电路的结构图，图2中示出了数据读取过程相关的多个模块和单元。需要说明的是，存储器中包括多个数据位存储阵列210，例如可以为8个、16个或32个等，但为了简化附图，图2中仅示出两个数据位存储阵列210及其对应的数据传输结构，相似地，本申请其他实施例的附图也进行了简化，在其他附图中将不再进行赘述。
参考图2，在本实施例中，数据传输电路还包括多个逻辑运算单元131，逻辑运算单元131的一个输入端对应地与数据位读取单元111、标志位读取单元112和冗余读取模块113中的一个连接，逻辑运算单元131的另一个输入端与使能信号连接，逻辑运算单元131 的输出端与检错运算模块300连接，逻辑运算单元131用于对两个输入端输入的数据进行预设运算，并将运算结果发送至检错运算模块300。在本实施例中，逻辑运算单元131根据使能信号对接收到的数据先进行初步处理，再将处理后的数据发送至检错运算模块300，从而简化了检错运算模块300的运算复杂度，提高了检错运算模块300的运算速度。
在其中一个实施例中，逻辑运算单元131为逻辑与单元，逻辑与单元的一个输入端对应地与数据位读取单元111、标志位读取单元112和冗余读取模块113中的一个连接，逻辑与单元的另一个输入端与使能信号连接，逻辑与单元的输出端与检错运算模块300连接，逻辑运算单元131用于对两个输入端输入的数据进行逻辑与运算，并将运算结果发送至检错运算模块300。
具体地，以第一个数据位读取单元111和数据位读使能信号Read kill0为例，第一个数据位读取单元111输出的数据与数据位读使能信号Read kill0进行逻辑与运算。
当数据位读使能信号Read kill0为0时，说明对应的数据位存储阵列210损坏，数据位读取单元111输出的数据与0进行逻辑与运算，则逻辑与单元输出的数据均为0。例如，若为8位数据，则数据位读取单元111对应的逻辑与单元输出00000000。同时，在标志位读使能信号Read killcc的控制下，标志位读取单元112对应的逻辑与单元也输出0，基于逻辑与单元的上述运算处理，数据信息可以与标志信息相匹配，检错运算模块300的检测结果为“不存在错误”，因此不需要通过检错运算模块300进一步获取错误数据位的信息，从而简化了检错运算模块300的运算步骤和复杂度。
当数据位读使能信号Read kill0为1时，说明对应的数据位存储阵列210未损坏，数据位读取单元111输出的数据与1进行逻辑与运算，逻辑与单元输出的数据为数据位读取单元111输出的数据。因此，本实施例的逻辑运算单元131既不影响未损坏的数据位存储阵列210的数据传输和检错功能，又可以降低损坏的数据位存储阵列210的数据传输和检错的难度，从而实现了一种运行速度较快的数据传输电路。
需要明确的是，逻辑运算单元131不局限于上述实施例中提供的与单元，也可以是与非单元等。逻辑运算单元131只要能够满足以下条件：当数据位读使能信号Read killn生效时，输出数据位读取单元111读取到的数据；当数据位读使能信号Read killn失效时，输出预设数据即可。数据位读取单元111对应的逻辑运算单元131输出的预设数据例如也可以为11111111、01010101等，标志位读取单元112对应的逻辑运算单元131输出的预设数据例如可以为0。
在其中一个实施例中，检错运算模块300用于输出多个检错信息，检错信息与数据位 读取单元111一一对应，数据传输电路还包括正常纠错单元151、冗余数据总线400和多个第一多路选择器141。其中，检错信息包括读取的数据信息与写入的数据信息是否相同，当二者不同时，检错信息还进一步包括具体的错误数据位，例如，若写入的数据信息为10000000，读取的数据信息为11000000，则错误数据位为第2位。
正常纠错单元151与数据位读取单元111一一对应连接，还与检错运算模块300连接，正常纠错单元151用于接收检错信息，并根据检错信息更新对应的数据位读取单元111输出的数据信息。由于在存储器中的数据以二进制进行保存，所以当存在读取数据的错误时，可以根据检错信息直接进行纠错。例如，若数据位读取单元111输出的数据信息为11000000，且检错信息中标示第2位为错误数据位，则写入的数据信息必然为10000000，正常纠错单元151即可对数据信息进行更新从而完成纠错。
冗余数据总线400与冗余读取模块113连接，用于接收冗余读取模块113输出的数据。具体地，冗余读取模块113从冗余存储阵列230读取到数据后，将读取的数据传输至冗余数据总线400，以使损坏的数据位存储阵列210对应的第一多路选择器141可以从冗余数据总线400上获取读取的数据。
第一多路选择器141与正常纠错单元151一一对应，第一多路选择器141的一个输入端与对应的正常纠错单元151连接，第一多路选择的另一个输入端与冗余数据总线400连接，第一多路选择器141用于接收数据位读使能信号Read killn，并在数据位读使能信号Read killn的控制下选择输出任一输入端输入的数据。具体地，以第一个数据位读取单元111和数据位读使能信号Read kill0为例，当数据位读使能信号Read kill0为0时，说明对应的数据位存储阵列210损坏，则第一多路选择器141选择输出来自冗余数据总线400的数据，即实现了冗余存储阵列230对数据位存储阵列210的替代；当数据位读使能信号Read kill0为1时，说明对应的数据位存储阵列210未损坏，则第一多路选择器141选择输出来自正常纠错单元151的数据，即将数据位读取单元111读取到的数据正常输出。
在其中一个实施例中，正常纠错单元151用于当检错信息无效时，将数据位读取单元111输出的数据信息直接发送至第一多路选择器141。其中，“检错信息无效”即读取的数据信息和写入的数据信息相同，不需要对读取的数据信息进行纠错。
在其中一个实施例中，正常纠错单元151用于当检错信息有效时，根据检错信息对数据位读取单元111输出的数据信息进行纠错，以更新数据信息，并将更新后的数据信息发送至第一多路选择器141。其中，“检错信息有效”即读取的数据信息和写入的数据信息不同，需要根据检错信息对读取的数据信息进行纠错，从而实现数据信息的正确输出。
在其中一个实施例中，正常纠错单元151还用于当检错信息有效时，将更新后的数据信息发送至对应的数据位存储阵列210，以更新正常存储阵列200中存储的数据信息。当读取的数据信息和写入的数据信息不同时，对应的数据位存储阵列210中存储的数据信息也存在错误的风险，因此，本实施例通过对数据位存储阵列210中存储的数据信息进行更新，可以提高存储的数据信息的准确性，从而减少正常纠错单元151的纠错量，提高数据传输电路的运行速度。
在其中一个实施例中，冗余读取模块113用于当冗余读使能信号Read Repair有效时，发送冗余读取模块113读取的数据至冗余数据总线400；第一多路选择器141用于当数据位读使能信号Read kill0无效时，选择输出冗余数据总线400上的数据。通过上述读取方式，即可实现冗余存储阵列230对损坏的数据存储阵列的替换。
在其中一个实施例中，检错运算模块300还用于输出与冗余读取模块113对应的检错信息，数据传输电路还包括：冗余纠错单元152，冗余纠错单元152分别与冗余读取模块113、检错运算模块300和冗余数据总线400连接，冗余纠错单元152用于当检错信息有效且冗余读使能信号Read Repair有效时，根据检错信息更新冗余读取模块113输出的数据，并将更新后的数据发送至冗余数据总线400。在本实施例中，冗余纠错单元152用于对冗余读取模块113读取到的数据进行纠错，从而实现冗余读取模块113的读取准确性。
图3为又一实施例的数据传输电路的结构图，图3中示出了数据写入过程相关的多个模块和单元。参考图3，在本实施例中，在其中一个实施例中，数据传输电路还包括标志位写入单元122、冗余写入模块123和多个数据位写入单元121。
多个数据位写入单元121与多个数据位存储阵列210一一对应连接，还与所冗余数据总线400连接，用于向数据位存储阵列210或冗余数据总线400发送数据信息；
标志位写入单元122分别与标志位存储阵列220和冗余数据总线400连接，用于向标志位存储阵列220或冗余数据总线400发送标志信息；
冗余写入模块123分别与冗余存储阵列230和冗余数据总线400连接，用于将冗余数据总线400上的数据写入冗余存储阵列230中。
其中，数据位写使能信号Write killn与前述数据位读使能信号Read killn相匹配，即若数据位存储阵列210损坏，其读写功能均由冗余存储阵列230代替执行。
具体地，以第一个数据位读取单元111和数据位写使能信号Write kill0为例，当数据位写使能信号Write kill0为0时，说明对应的数据位存储阵列210损坏，则数据位写入单元121将接收到的数据信息发送至冗余数据总线400，并通过写入运算单元161发送预设 数据至标志位编码模块500，以降低标志位编码模块500的编码复杂度，冗余写入模块123从冗余数据总线400上获取该数据信息并写入至冗余存储阵列230。当数据位写使能信号Write kill0为1时，说明对应的数据位存储阵列210未损坏，则数据位写入单元121将接收到的数据信息发送至对应的数据位存储阵列210，从而实现数据信息的正常存储。
在其中一个实施例中，数据传输电路还包括：标志位编码模块500，分别与数据位写入单元121、标志位写入单元122连接，用于接收数据位写入单元121输出的数据信息，对数据进行编码以生成标志信息，并将标志信息发送至标志位写入单元122。标志位编码模块500根据预设规则对写入的数据信息进行编码，以生成唯一的标志信息，并将生成的标志信息发送至标志位写入单元122，从而进行标志信息的存储，用于在数据信息读取时进行检错。
图4为再一实施例的数据传输电路的结构图，图4中示出了数据写入和读取过程相关的多个模块和单元。参考图4，在本实施例中，数据传输电路还包括第二多路选择器171，第二多路选择器171的两个输入端分别与数据位读取单元111和数据位写入单元121连接，第二多路选择器171用于在读/写使能信号Wr/Rd的控制下，分时导通任一输入端与输出端之间的数据传输路径，以实现数据的分时写入和读取功能。在图4的实施例中，检错运算模块300与标志位编码模块500相集成，以提升存储器的集成度，在其他实施例中，检错运算模块300与标志位编码模块500也可以分别设置。
具体地，以第一个数据位读取单元111和数据位读使能信号Read kill0为例进行具体说明。在数据写入时，数据位写入单元121从数据引脚区240获取待写入的数据信息。当数据位存储阵列210为未损坏时，对应的数据位写使能信号Write kill0为1，数据位写入单元121将数据信息分别发送至数据位存储阵列210和标志位编码模块500，以对数据信息进行存储和编码。
当数据位存储阵列210损坏时，对应的数据位写使能信号Write kill0为0，使数据位写入单元121与冗余数据总线400之间的数据传输路径导通，因此，数据位写入单元121会还将数据信息发送至冗余数据总线400。标志位编码模块500用于根据预设编码规则对接收到的数据信息进行编码，以生成标志信息，并将标志信息发送至标志位写入单元122以进行存储。当存在一个数据位写使能信号Write kill0为0时，冗余写使能信号Write Repair即为1，冗余数据总线400与冗余写入模块123之间的数据传输路径导通，冗余写入模块123从冗余数据总线400获取待写入的数据信息并进行存储。
在数据读取时，当数据位存储阵列210未损坏时，对应的数据位读使能信号Read kill0 为1，数据位读取单元111从对应的数据位存储阵列210读取数据信息，并将读取到的数据信息发送至正常纠错单元151、标志位编码模块500和检错运算模块300，同时，逻辑运算单元131在冗余读使能信号Read Repair的控制下发送预设数据至第二多路选择器171。标志位编码模块500根据接收的数据信息进行编码，以生成读取的数据信息对应的标志信息，检错运算模块300接收读取的数据信息对应的标志信息，并从标志位读取单元112获取写入的数据信息对应的标志信息，检错运算模块300对两个标志信息进行比对以生成检错信息，正常纠错单元151根据检错信息对读取的数据信息进行纠错并输出至数据引脚区240。
当数据位存储阵列210损坏时，对应的数据位读使能信号Read kill0为0，冗余读使能信号Read Repair为1，冗余读取模块113将读取到的数据发送至冗余纠错单元152、标志位编码单元和检错运算模块300，以执行检错纠错步骤，同时，损坏的数据位存储阵列210对应的逻辑运算模块发送预设数据值检错运算模块300，从而简化检错运算模块300的运算复杂度，冗余纠错单元152对接收到的数据信息进行处理后，将数据信息发送至冗余数据总线400，数据位读使能信号Read kill0使损坏的数据位存储阵列210对应的第一多路选择器141与冗余数据总线400之间的数据传输路径导通，损坏的数据位存储阵列210对应的第一多路选择器141从冗余数据总线400获取数据信息，并在数据位读使能信号Read kill0的控制下将数据信息发送至数据引脚区240。
本申请实施例还提供了一种存储器，包括：多个正常存储阵列200；冗余存储阵列230；多个数据引脚区240，数据引脚区240与正常存储阵列200一一对应；如上述的数据传输电路，数据传输电路分别与冗余存储阵列230、正常存储阵列200和数据引脚区240连接。本实施例的存储器不论正常存储阵列200是否发生损坏，都无需先执行查询损坏的正常存储阵列200的地址的步骤，简化了数据读取的串行步骤，从而实现了一种读取速度更快的存储器。
以上实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例中的各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上实施例仅表达了本发明的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对发明专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本发明构思的前提下，还可以做出若干变形和改进，这些都属于本发明的保护范围。因此，本发明专利的保护范围应以所附权利要求为准。

Claims (16)

  1. 一种数据传输电路，所述数据传输电路包括：
    正常读取模块，与正常存储阵列连接，用于从所述正常存储阵列中读取数据并输出；
    冗余读取模块，与冗余存储阵列连接，用于从所述冗余存储阵列中读取数据并输出；以及
    检错运算模块，分别与所述正常读取模块和所述冗余读取模块连接，用于同步接收所述正常读取模块和所述冗余读取模块输出的读取数据，并对所述读取数据进行检错运算。
  2. 根据权利要求1所述的数据传输电路，其中所述正常存储阵列包括标志位存储阵列和多个数据位存储阵列，所述正常读取模块包括：
    多个数据位读取单元，所述数据位读取单元与所述数据位存储阵列一一对应连接，用于从对应的所述数据位存储阵列中读取数据信息；以及
    标志位读取单元，与所述标志位存储阵列连接，用于从标志位存储阵列中读取标志信息。
  3. 根据权利要求2所述的数据传输电路，还包括：
    多个逻辑运算单元，所述逻辑运算单元的一个输入端对应地与所述数据位读取单元、所述标志位读取单元和所述冗余读取模块中的一个连接，所述逻辑运算单元的另一个输入端与使能信号连接，所述逻辑运算单元的输出端与所述检错运算模块连接，所述逻辑运算单元用于对两个输入端输入的数据进行预设运算，并将运算结果发送至所述检错运算模块。
  4. 根据权利要求3所述的数据传输电路，其中所述逻辑运算单元为逻辑与单元，所述逻辑与单元的一个输入端对应地与所述数据位读取单元、所述标志位读取单元和所述冗余读取模块中的一个连接，所述逻辑与单元的另一个输入端与所述使能信号连接，所述逻辑与单元的输出端与所述检错运算模块连接，所述逻辑运算单元用于对两个输入端输入的数据进行逻辑与运算，并将运算结果发送至所述检错运算模块。
  5. 根据权利要求3所述的数据传输电路，还包括：
    使能控制模块，分别与多个所述逻辑与单元连接，所述使能控制模块用于生成冗余读使能信号和多个数据位读使能信号，所述数据位读使能信号与所述数据位读取单元一一对应，所述冗余读使能信号与所述冗余读取模块对应，所述使能控制模块还用于将所述冗余读使能信号和所述数据位读使能信号分别一一对应发送至所述逻辑与单元；
    其中，当所述冗余读使能信号有效时，多个所述数据位读使能信号中的一个无效；当 所述冗余读使能信号无效时，多个所述数据位读使能信号均有效。
  6. 根据权利要求5所述的数据传输电路，其中所述检错运算模块用于输出多个检错信息，所述检错信息与所述数据位读取单元一一对应，所述数据传输电路还包括：
    正常纠错单元，与所述数据位读取单元一一对应连接，还与所述检错运算模块连接，所述正常纠错单元用于接收所述检错信息，并根据所述检错信息更新对应的所述数据位读取单元输出的数据信息；
    冗余数据总线，与所述冗余读取模块连接，用于接收所述冗余读取模块输出的数据；以及
    多个第一多路选择器，所述第一多路选择器与所述正常纠错单元一一对应，所述第一多路选择器的一个输入端与对应的所述正常纠错单元连接，所述第一多路选择的另一个输入端与所述冗余数据总线连接，所述第一多路选择器用于接收数据位读使能信号，并在所述数据位读使能信号的控制下选择输出任一所述输入端输入的数据。
  7. 根据权利要求6所述的数据传输电路，其中所述正常纠错单元用于当所述检错信息无效时，将所述数据位读取单元输出的数据信息发送至所述第一多路选择器。
  8. 根据权利要求6所述的数据传输电路，其中所述正常纠错单元用于当所述检错信息有效时，根据所述检错信息对所述数据位读取单元输出的数据信息进行纠错，以更新所述数据信息，并将更新后的所述数据信息发送至所述第一多路选择器。
  9. 根据权利要求8所述的数据传输电路，其中所述正常纠错单元还用于当所述检错信息有效时，将更新后的所述数据信息发送至对应的所述数据位存储阵列，以更新所述正常存储阵列中存储的数据信息。
  10. 根据权利要求6所述的数据传输电路，其中所述冗余读取模块用于当所述冗余读使能信号有效时，发送所述冗余读取模块读取的数据至所述冗余数据总线；
    所述第一多路选择器用于当所述数据位读使能信号无效时，选择输出冗余数据总线上的数据。
  11. 根据权利要求6所述的数据传输电路，其中所述检错运算模块还用于输出与所述冗余读取模块对应的检错信息，所述数据传输电路还包括：
    冗余纠错单元，所述冗余纠错单元分别与所述冗余读取模块、所述检错运算模块和所述冗余数据总线连接，所述冗余纠错单元用于当所述检错信息有效且所述冗余读使能信号有效时，根据所述检错信息更新所述冗余读取模块输出的数据，并将更新后的数据发送至所述冗余数据总线。
  12. 根据权利要求6所述的数据传输电路，还包括：
    多个数据位写入单元，与多个所述数据位存储阵列一一对应连接，还与所冗余数据总线连接，用于向所述数据位存储阵列或所述冗余数据总线发送数据信息；
    标志位写入单元，分别与所述标志位存储阵列和所述冗余数据总线连接，用于向所述标志位存储阵列或所述冗余数据总线发送标志信息；以及
    冗余写入模块，分别与所述冗余存储阵列和所述冗余数据总线连接，用于将所述冗余数据总线上的数据写入所述冗余存储阵列中。
  13. 根据权利要求12所述的数据传输电路，还包括：
    标志位编码模块，分别与所述数据位写入单元、所述标志位写入单元连接，用于接收所述数据位写入单元输出的所述数据信息，对所述数据进行编码以生成所述标志信息，并将所述标志信息发送至所述标志位写入单元。
  14. 根据权利要求7所述的数据传输电路，其中所述“检错信息无效”即读取的所述数据信息和写入的所述数据信息相同，不需要对读取的所述数据信息进行纠错。
  15. 根据权利要求8所述的数据传输电路，其中所述“检错信息有效”即读取的所述数据信息和写入的所述数据信息不同，需要根据检错信息对读取的所述数据信息进行纠错，从而实现所述数据信息的正确输出。
  16. 一种存储器，包括：
    多个正常存储阵列；
    冗余存储阵列；
    多个数据引脚区，所述数据引脚区与所述正常存储阵列一一对应；以及
    如权利要求1至15任一项所述的数据传输电路，所述数据传输电路分别与所述冗余存储阵列、所述正常存储阵列和所述数据引脚区连接。
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