WO2022041944A1 - 存储器 - Google Patents

存储器 Download PDF

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Publication number
WO2022041944A1
WO2022041944A1 PCT/CN2021/099868 CN2021099868W WO2022041944A1 WO 2022041944 A1 WO2022041944 A1 WO 2022041944A1 CN 2021099868 W CN2021099868 W CN 2021099868W WO 2022041944 A1 WO2022041944 A1 WO 2022041944A1
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WIPO (PCT)
Prior art keywords
memory
command
port
clock signal
chip
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Application number
PCT/CN2021/099868
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English (en)
French (fr)
Inventor
寗树梁
何军
应战
刘杰
Original Assignee
长鑫存储技术有限公司
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Application filed by 长鑫存储技术有限公司 filed Critical 长鑫存储技术有限公司
Priority to EP21859788.8A priority Critical patent/EP4033490A4/en
Priority to US17/445,658 priority patent/US11886357B2/en
Publication of WO2022041944A1 publication Critical patent/WO2022041944A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
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    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N

Definitions

  • the embodiments of the present application relate to the field of semiconductor technology, and in particular, to a memory.
  • DRAM Dynamic Random Access Memory
  • Each memory cell usually includes a capacitor and a transistor.
  • the gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor.
  • the voltage signal on the word line can control the opening or closing of the transistor, and then through the bit line
  • the data information stored in the capacitor is read, or the data information is written into the capacitor through the bit line for storage.
  • DRAM is applied in more and more fields, such as DRAM is more and more used in various fields, users have higher and higher requirements for DRAM performance indicators, and will have different requirements for DRAM due to different application fields.
  • the technical problem solved by the embodiments of the present application is to provide a memory that solves the problems of high power consumption and high cost of the memory.
  • an embodiment of the present application provides a memory, including: a control chip; A chipset and a second storage chipset, the storage chips in the first storage chipset are configured to use a first clock signal to exchange information with the control chip, and the storage chips in the second storage chipset are configured In order to use the second clock signal to exchange information with the control chip, the phases of the first clock signal and the second clock signal are different.
  • the first storage chip set includes a first storage chip and a second storage chip, the first storage chip performs information interaction with the control chip at the rising edge of the first clock signal, and the second storage chip The chip exchanges information with the control chip at the falling edge of the first clock signal;
  • the second storage chip set includes a third storage chip and a fourth storage chip, and the third storage chip is at the second clock
  • the rising edge of the signal exchanges information with the control chip, and the fourth memory chip exchanges information with the control chip at the falling edge of the second clock signal.
  • the frequencies of the first clock signal and the second clock signal are the same.
  • phase difference between the first clock signal and the second clock signal is an odd multiple of 90 degrees.
  • each of the memory chips includes at least one channel, and the channel includes: a plurality of memory blocks, each of the memory blocks includes a plurality of memory cells, and the plurality of the memory blocks are configured to alternately perform read and write operations;
  • Command port the command port is configured to receive a command signal on the corresponding clock edge of receiving a data signal to be written into the memory block or sending a data signal; wherein the corresponding clock edge includes the clock edge of the first clock signal or the clock edge of the second clock signal;
  • the command port includes A row address port and a column address port, the row address port is used to receive the row address signal of the location of the target storage unit, the column address port is used to receive the column address signal of the location of the target storage unit, and the target storage unit is The selected storage unit from the plurality of storage units.
  • the command signal includes an activation command and a read command corresponding to each activation command; the channel is further configured to, after the command port receives the activation command for one of the memory blocks, the The command port receives the read command corresponding to the activation command.
  • the channel is further configured such that the data port transmits the data signal after the command port receives the read command.
  • the command signal includes an activation command and a plurality of read commands corresponding to each activation command; the channel is further configured to, after the command port receives the activation command for one of the memory blocks, The command port receives one of the read commands corresponding to the active command on a plurality of corresponding clock edges, so that the command port receives a plurality of the read commands corresponding to the active command on a plurality of consecutive corresponding clock edges Order.
  • the channel is also configured such that the data port respectively transmits a plurality of the data signals on a plurality of consecutive corresponding clock edges, and the number of the data signals is the same as the number of the received read commands .
  • the command signal includes an activation command and a read command corresponding to the activation command; the channel is further configured such that after the command port alternately receives activation commands for different memory blocks, the command port alternately The read command corresponding to the activate command is received.
  • the channel is further configured such that after the command port receives the read command, the data port alternately transmits the data signals corresponding to different memory blocks.
  • the command signal includes an active command and a plurality of read commands corresponding to each of the active commands; the channel is further configured such that the command port alternately receives the active commands for different memory blocks, and all The command port alternately receives a plurality of the read commands corresponding to each of the active commands.
  • the activate command includes the row address signal
  • the read command includes the column address signal
  • the channel is further configured such that the activate command and the read command pass through different ones of the command ports take over.
  • the memory chip includes a plurality of the channels, and the memory chip further includes a common circuit shared by the channels.
  • the memory chip further includes: a test port, and in the test mode, a plurality of the channels share the same test port for testing.
  • the common circuit includes a test control circuit, and the test control circuit is used for test control of a plurality of the channels.
  • a plurality of the memory chips are sequentially stacked on the control chip, and the channel includes a through-silicon via structure.
  • Embodiments of the present application provide a memory with superior structure and performance, wherein a plurality of memory chips share a channel and are electrically connected to a control chip, and the plurality of memory chips include a first memory chip group and a second memory chip group, and the memory chips in the first memory chip group
  • the chip is configured to use the first clock signal to exchange information with the control chip
  • the memory chips in the second memory chipset are configured to use the second clock signal to exchange information with the control chip
  • the difference between the first clock signal and the second clock signal is Phase is different.
  • the row address port is separated from the column address port, the row address signal and the column address signal can be transmitted at the same time, avoiding the problem that the activation command signal can only be transmitted after the read command transmission is completed, so it is beneficial to avoid the need for certain time periods.
  • the problem that the data line is not full ensures that the data line is always full of data, thereby increasing the storage speed of the memory and improving the storage performance of the memory.
  • FIG. 1 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • FIG. 2 is two different waveform diagrams of the first clock signal and the second clock signal
  • Fig. 3 is the timing chart of the working signal corresponding to each memory chip in the memory provided by an embodiment of the application;
  • FIG. 4 is a schematic structural diagram of a memory provided by another embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of a memory chip in FIG. 4;
  • FIG. 6 is a timing diagram of the operation of each memory chip in the memory provided by another embodiment of the present application.
  • FIG. 7 is another timing diagram of the operation of each memory chip in the memory according to another embodiment of the present application.
  • the implementation of the present application provides a memory, a plurality of memory chips, the plurality of memory chips are electrically connected to a control chip through a common channel, and the plurality of memory chips include a first memory chip group and a second memory chip group, and the first memory chip.
  • the memory chip of the chipset is configured to use the first clock signal to exchange information with the control chip
  • the memory chips in the second memory chipset are configured to use the second clock signal to exchange information with the control chip
  • the first clock signal communicates with the first clock signal.
  • the phases of the two clock signals are different.
  • the number of channels required by the memory can be saved without affecting the quality of the information interaction between the multiple memory chips and the control chip, thereby saving the area of the memory, reducing the cost of the memory, and reducing the size of the memory. power consumption.
  • FIG. 1 is a schematic structural diagram of a memory provided by an embodiment of the present application.
  • the memory includes: a control chip 114; a plurality of memory chips, the plurality of memory chips share a channel 01 and are electrically connected to the control chip 114, and the plurality of memory chips include a first memory chip set 110 and a second memory chip Chip set 120, the memory chips in the first memory chip set 110 are configured to use a first clock signal to exchange information with the control chip 114, and the memory chips in the second memory chip set 120 are configured to use a second clock signal and control
  • the chip 114 performs information exchange, and the phases of the first clock signal and the second clock signal are different.
  • the memory may be a dynamic random access memory.
  • a plurality of memory chips can be stacked on the control chip 114 in sequence, which is beneficial to improve the storage density and reduce the distance between the memory chip and the control chip 114; It is beneficial to reduce the longitudinal thickness of the memory.
  • a plurality of memory chips are stacked on the control chip 114 in sequence, and the channel 01 includes a through silicon via (TSV, Through Silicon Via).
  • the timing of the clock edge of the first clock signal and the clock edge of the second clock signal can be distinguished, and the clock edge includes a rising edge and a falling edge.
  • the first storage chipset 110 and the second storage chipset 120 share the channel 01, the storage chips in the first storage chipset 110 and the second storage chipset 120 can exchange information with the control chip 114 at different times.
  • the first memory chip set 110 includes a first memory chip 111 and a second memory chip 112 , and the first memory chip exchanges information with the control chip 114 at the rising edge of the first clock signal,
  • the second memory chip 112 exchanges information with the control chip 114 at the falling edge of the first clock signal.
  • the second memory chip set 120 includes a third memory chip 121 and a fourth memory chip 122.
  • the third memory chip 121 exchanges information with the control chip 114 at the rising edge of the second clock signal
  • the fourth memory chip 122 exchanges information with the control chip 114 at the rising edge of the second clock signal.
  • the falling edge of exchanges information with the control chip 114 .
  • first memory chip 111 and the second memory chip 112 may be in adjacent layers, and may also be separated by other memory chips.
  • the third memory chip 121 and the fourth memory chip 122 may be in adjacent layers, or they may be separated by other memory chips.
  • the overall macro operating mode of the first memory chip 111 and the second memory chip 112 is: when the first clock signal Data is transmitted on both the rising and falling edges of the . Therefore, for a single memory chip, it suffices to transmit data on either the rising edge or the falling edge of the first clock signal, but for the memory as a whole, it can achieve data transmission on both the rising edge and the falling edge of the first clock signal Effect.
  • the third memory chip 121 and the fourth memory chip 122 also work in different clock states of the same second clock signal, and also have the ability to transmit the data on both the rising and falling edges of the second clock signal for the memory as a whole. effect of the data.
  • the first clock signal includes a first command clock and a first data clock
  • the second clock signal includes a second command clock and a second data clock.
  • the first memory chip 111 exchanges information with the control chip 114 at the rising edge of the first command clock and/or the first data clock
  • the second memory chip 112 exchanges information at the first command clock and/or the first data clock
  • the falling edge of the first data clock performs information interaction with the control chip 114 .
  • the third memory chip 121 exchanges information with the control chip 114 at the rising edge of the second command clock and/or the second data clock; Or the falling edge of the second data clock performs information exchange with the control chip 114 .
  • the first memory chip 111 is configured to receive a command signal at the rising edge of the first command clock, and the command signal is used to control the read and write operations of the first memory chip 111, and the command signal is used to control the read and write operations of the first memory chip 111.
  • the rising edge receives a data signal to be written into the first memory chip 111 or transmits a data signal.
  • the second memory chip 112 the third memory chip 121 and the fourth memory chip 122 , reference may be made to the first memory chip 111 .
  • the first command clock and the first data clock use the same first clock signal
  • the second command clock and the second data clock use the same second clock signal.
  • the data reception or transmission error caused by the error improves the storage accuracy of the memory.
  • first command clock and the first data clock may also use different first clock signals
  • second command clock and the second data clock may also use different second clock signals
  • the frequencies of the first clock signal and the second clock signal are the same.
  • the rising edge of the first clock signal and the rising edge of the second clock signal at the same time during the memory operation can be effectively avoided, or the falling edge of the first clock signal and the falling edge of the second clock signal appearing at the same time, It is ensured that the clocks of the first clock signal and the second clock signal can be accurately identified by the corresponding memory chips, thereby improving the reading and writing accuracy of the memory.
  • the absolute value of the difference between the frequency of the first clock signal and the frequency of the second clock signal is within the allowable value, it may also be considered that the frequencies of the first clock signal and the second clock signal are same.
  • the frequency of the first clock signal and the frequency of the second clock signal may also be in a multiple relationship, as long as the above requirement of being able to distinguish clock edges can be met.
  • the phase difference between the first clock signal and the second clock signal is an odd multiple of 90 degrees, for example, the phase difference is 3 times, 5 times, 7 times, etc., of 90 degrees.
  • FIG. 2 shows two different waveform diagrams of the first clock signal and the second clock signal, the first clock signal is illustrated by CK1, and the second clock signal is illustrated by CK21.
  • the first clock signal and the second clock signal The phase difference of the signals is 90 degrees; CK22 shows another second clock signal, and the phase difference between the first clock signal and the second clock signal is 270 degrees.
  • CK1 is a first clock signal
  • CK2 is a second clock signal
  • DATA1 is a timing diagram of data transmission by the first memory chip 111
  • DATA2 is The second memory chip 112 transmits the data sequence diagram
  • DATA3 is the third memory chip 121 transmits the data sequence diagram
  • DATA4 is the fourth memory chip 122 transmits the data sequence diagram
  • DATA is the DATA1, DATA2, DATA3, DATA4 time sequence merged picture.
  • the first memory chip 111 On the first rising edge of the first clock signal, the first memory chip 111 receives the activation command signal; on the mth rising edge of the clock signal, the first memory chip 111 receives the read command signal; on the nth rising edge of the first clock signal, the first memory chip 111 receives the read command signal; A rising edge, the first memory chip 111 transmits data.
  • the second memory chip 112 On the first falling edge of the first clock signal, the second memory chip 112 receives the activation command signal; on the mth falling edge of the first clock signal, the second memory chip 112 receives the read command signal; On the nth falling edge, the second memory chip 112 transmits data. In this way, the first storage chip 111 transmits data at different rising edges of the first clock signal, and the second storage chip 112 transmits data at different falling edges of the first clock signal, until the data transmission is completed.
  • the third memory chip 121 receives the activation command signal; on the mth rising edge of the clock signal, the third memory chip 121 receives the read command signal; on the nth rising edge of the second clock signal, the third memory chip 121 receives the read command signal; A rising edge, the third memory chip 121 transmits data.
  • the fourth memory chip 122 On the first falling edge of the second clock signal, the fourth memory chip 122 receives the activation command signal; on the mth falling edge of the second clock signal, the fourth memory chip 122 receives the read command signal; On the nth falling edge, the fourth memory chip 122 transmits data. In this way, the third storage chip 121 transmits data at different rising edges of the second clock signal, and the fourth storage chip 122 transmits data at different falling edges of the second clock signal, until the data transmission is completed.
  • the above description takes the memory read operation as an example.
  • the first memory chip 111 and the second memory chip 112 also transmit data alternately, and the third memory chip 121 and the fourth memory chip 121 and the fourth memory chip.
  • the chip 122 also transmits data alternately.
  • the first storage chipset 110 includes two storage chips
  • the second storage chipset 120 includes two storage chips.
  • the first storage chipset may be a single storage chip, and the storage chip may perform information interaction with the control chip at the rising or falling edge of the first clock signal; the second storage chipset may For a single memory chip, the memory chip can exchange information with the control chip at the rising edge or the falling edge of the second clock signal.
  • the number of channels 01 in the memory is reduced without affecting the bandwidth of the information interaction between the control chip 114 and the plurality of memory chips, thereby reducing the manufacturing cost of the memory and power consumption.
  • Another embodiment of the present application further provides a memory, which is substantially the same as the foregoing embodiment, and the main differences include a more detailed description of each memory chip.
  • the memory provided in this embodiment will be described in detail below with reference to the accompanying drawings. It should be noted that for the same or corresponding parts as those of the foregoing embodiments, reference may be made to the descriptions of the foregoing embodiments, which will not be repeated below.
  • FIG. 4 is a schematic structural diagram of a memory provided by another embodiment of the present application
  • FIG. 5 is a schematic structural diagram of a memory chip in FIG. 4 .
  • the memory includes: a control chip 214; a plurality of storage chips, the plurality of storage chips include a first storage chip set 210 and a second storage chip set 220, the aforementioned information exchange includes reading and writing operation; each memory chip includes at least one channel 20, the channel 20 includes: a plurality of storage blocks 201, each storage block 201 includes a plurality of storage units, and the plurality of storage blocks 201 are configured to alternately perform read and write operations; a command port 202 , the command port 202 is configured to receive a command signal at the corresponding clock edge of The data signal of block 201 or the transmission data signal; wherein, the corresponding clock edge includes the clock edge of the first clock signal or the clock edge of the second clock signal; the command port 202 includes a row address port 212 and a column address port 222, and the row address port 212
  • the column address port 222 is used to receive the row address signal of the location of the target memory unit, and the column address port 222 is used to receive the column address
  • the corresponding clock edge refers to the first rising edge or falling edge corresponding to the information exchange performed by the memory chip, and the rising edge or falling edge of the data clock corresponding to the information exchange performed by the memory chip.
  • command port referred to in this embodiment includes a port for transmitting command signals and address signals, but is not limited thereto.
  • each channel 20 includes four memory blocks 201 as an example.
  • bank10 , bank11 , bank12 and bank13 are used to illustrate four memory blocks 201 in a channel 20 . It can be understood that, in other embodiments, the number of memory blocks included in each channel may also be any other number, such as 2, 6, and so on.
  • the data port 203 is used for receiving data to be stored in the storage unit or sending data read out from the storage unit.
  • the memory chip includes a plurality of channels 20 , and the memory chip further includes a common circuit 204 shared by the plurality of channels 20 .
  • the shared circuit 204 may be a test control circuit, and the test control circuit is used for test control of the multiple channels 20 .
  • the shared circuit may also be at least one of a temperature sensor circuit, an analog circuit or a charge pump circuit.
  • the memory may further include: a test port, and in the test mode, a plurality of channels 20 share the same test port for testing. Due to the setting of the shared test port, it is beneficial to reduce the number of ports in the memory, thereby reducing the difficulty of using the probe card to test the memory, and reducing the difficulty of manufacturing the probe card.
  • the corresponding clock edge is the clock edge of the first clock signal; for the memory chips in the second memory chip set 220, the corresponding clock edge is the clock edge of the second clock signal.
  • the command signals include an activation command and a read command corresponding to each activation command.
  • Channel 20 is also configured such that, after command port 202 receives an activate command for a memory block, command port 202 receives a read command corresponding to the activate command.
  • the activate command includes row address signals, which are received through row address port 212 ;
  • the read command includes column address signals, which are received through column address port 222 .
  • the activation command and the read command may also contain other control signals other than the row address signal or the column address signal. These other control signals are used to help or assist the memory chip to identify whether the command is an activation command or a read command.
  • channel 20 is further configured such that the activation command and the read command are received through different ports in the command port 202, so that the activation command and the read command can be received simultaneously.
  • channel 20 is also configured such that after command port 202 receives a read command, data port 203 transmits a data signal.
  • the command signal includes an activation command and a read command corresponding to the activation command; the channel is further configured such that after the command port 202 alternately receives activation commands for different memory blocks 201, the command port 202 alternately receives the read commands corresponding to the activation commands. Order. Specifically, after the row address ports 212 alternately receive activation commands for different memory blocks 201, the column address ports 222 alternately receive read commands corresponding to the activation commands.
  • the channel is also configured such that after the command port 202 receives the read command, the data port 203 alternately transmits data signals corresponding to different memory blocks 201 .
  • first storage chipset 210 For a detailed description of the difference between the first storage chipset 210 and the second storage chipset 220, reference may be made to the foregoing embodiments. The following will take the storage chips in the first storage chipset 210 as an example to describe the working mode of the command port 202 in detail. .
  • the first memory chip group 210 includes a first memory chip 211 and a second memory chip 212 ; the second memory chip group 220 includes a third memory chip 221 and a fourth memory chip 222 .
  • the command port 202 of the first memory chip 211 uses the rising edge of the first clock signal to receive or send signals, and the data port 203 uses the rising edge of the first clock signal to receive or send signals, and the memory chip is denoted as memory chip C1;
  • the command port 202 of the chip 212 uses the falling edge of the first clock signal to receive or send signals, and the data port 203 uses the falling edge of the first clock signal to receive or send signals.
  • the memory chip is denoted as memory chip C2.
  • the command port 202 of the third memory chip 221 uses the rising edge of the second clock signal to receive or send signals, and the data port 203 uses the rising edge of the second clock signal to receive or send signals, and the memory chip is denoted as memory chip C3;
  • the command port 202 of the chip 222 uses the falling edge of the second clock signal to receive or send signals, and the data port 203 uses the falling edge of the second clock signal to receive or send signals, and the memory chip is marked as C4.
  • FIG. 6 is a working timing diagram of the memory chips C1/C2/C3/C4. The working principle of the memory will be described below with reference to the timing diagram.
  • CK1 shows the first clock signal
  • CK2 shows the second clock signal
  • ACT1/ACT2/ACT3/ACT4 correspondingly shows the timing diagram of the activation command signal for the memory chips C1/C2/C3/C
  • RD1/ RD2/RD3/RD4 shows the timing diagram of the read command signal for the memory chips C1/C2/C3/C
  • DATA1/DATA2/DATAA3/DATA4 shows the data signals of the data ports of the memory chips C1/C2/C3/C4. Timing diagram.
  • the memory chip C1 includes four memory blocks 201 of bank10, bank11, and bank12 as an example, and the activation command signal ACT1 includes A10/A11/A12/A13, A10 and bank10 for activating bank10, bank11, and bank12, respectively, and bank13.
  • A11 corresponds to bank11, and so on;
  • the read command signal RD1 includes R10/R11/R12/R13 corresponding to bank10, bank11, and bank12 one-to-one with bank13, and the data signal DATA1 includes D10/D11/D12/D13;
  • the activation command A10 Corresponding to bank10, one read command R10 and data signal D10, the activation command A11 corresponds to bank11, one read command R11 and data signal D11, the active command A12 corresponds to bank12, one read command R12 and data signal D12, the activation command A13 corresponds to bank13, one read command R13 and data signal D13, that is, one activation command corresponds to one read command.
  • R43 and the data signal D40/D41/D42/D43 please refer to the foregoing description.
  • the command port 202 and the data port 203 use the rising edge of the first clock to receive or send signals as an example: the command port 202 receives a signal for a memory block at the rising edge of the first clock signal. After the activation command A10, the command port 202 receives a read command R10 corresponding to the activation command A10 on the rising edge; after the command port 202 receives the read command R10, the data port 203 sends the data signal D10 on the rising edge of the first clock signal. .
  • the process after the command port 202 receives the activation command A11/A12/A13 is similar to that described above.
  • the row address port 212 in the command port 202 receives the activation command A10 to activate bank10 at the first rising edge of the first clock signal, and the row address port 212 in the command port 202 is at the second rising edge of the first clock signal.
  • Receive the activation command A11 that activates bank11 along the edge receive the activation command A12 that activates bank12 at the third rising edge of the first clock signal, and receive the activation command A12 that activates bank13 at the fourth rising edge of the first clock signal; command port 202
  • the column address port 222 in the nth rising edge receives the read command R10 corresponding to the activation command A10, and the command port 202 receives the read command R11 corresponding to the activation command A11 at the n+1th rising edge, and at the n+2th
  • the read command R12 corresponding to the activation command A2 is received at the first rising edge
  • the read command R13 corresponding to the activation command A13 is received at the n+3th rising edge, where n is
  • the data port 203 sends the data signal D10 corresponding to the memory block bank10 on the mth rising edge of the clock signal, and the data port 203 sends the data corresponding to the memory block bank11 on the m+1th rising edge of the first clock signal.
  • Signal D11, the data signal D12 corresponding to bank12 is sent on the m+2th rising edge, and the data signal D13 corresponding to bank13 is sent on the m+3th rising edge, where m is any natural number, and for each memory block For example, the corresponding m is greater than n.
  • the activation commands A10, A11, A12, and A13 are respectively received at successive rising edges as an example, that is, activation commands corresponding to different memory blocks are respectively received at successive rising edges. In other embodiments, It is also possible to receive activation commands corresponding to different memory blocks on non-consecutive rising edges.
  • the row address port 212 can receive the activation command A12 during the period when the column address port 222 receives the read command R10, so that there is no need to wait for all the read commands.
  • the activation command can only be received after all the command signals are received, so that the data bus can be filled, that is, the data port 203 can continuously transmit data to avoid the idle problem of the data bus within a certain period of time, thereby helping to improve the storage speed of the memory.
  • the command port 202 and the data port 203 use the falling edge of the first clock signal to receive or send signals: the command port 202 receives a signal for a memory chip at the falling edge of the first clock signal. After the activation command A0 of the block 201, the command port 202 receives a read command R20 corresponding to the activation command A20 on the rising edge; after the command port 202 receives the read command R20, the data port 203 sends data on the falling edge of the first clock signal Signal D20. The process of sending the data signals D21/D22/D23 by the memory chip C2 will not be described in detail.
  • the working process of the memory chip C3 and the memory chip C4 is similar to that of the foregoing memory chips C1/C2, and the foregoing description may be referred to, and will not be repeated. It can be understood that, because the phases of the first clock signal and the second clock signal are different, the memory chips C1/C2/C3/C4 receive or transmit at different clock edges of the first clock signal and different clock edges of the second clock signal respectively. Therefore, the four memory chips sharing the channel 02 transmit data without interfering with each other.
  • the command signal includes an activation command and a plurality of read commands corresponding to each activation command; the channel 20 is further configured such that, after the command port 202 receives an activation command for a memory block 201, the command port 202 is in multiple Each corresponding clock edge receives a read command corresponding to the active command, so that the command port 202 receives a plurality of read commands corresponding to the active command at a plurality of consecutive corresponding clock edges.
  • the channel 20 is also configured such that the data port 203 respectively transmits a plurality of data signals on a plurality of consecutive corresponding clock edges, and the number of the data signals is the same as the number of the received read commands.
  • the activation command includes a row address signal
  • the read command includes the column address signal
  • the channel 20 is further configured such that the activation command and the read command are received through different ones of the command ports.
  • the command signal may include an activation command and a plurality of read commands corresponding to each activation command; the channel 20 may also be configured such that after the command port 202 alternately receives activation commands for different memory blocks 201, the command port 202 alternately receives and Each of the activation commands corresponds to a plurality of the read commands. Specifically, after the command port 202 alternately receives the activation commands for different memory blocks 201, the command port 202 receives a read command corresponding to the activation command at each clock edge of the plurality of corresponding clock edges, so that the command port 202 is in continuous operation. Multiple clock edges receive multiple read commands corresponding to the active command until the command port 202 receives multiple read commands corresponding to the active command, after which the command port 202 receives multiple read commands corresponding to the active command for another memory block 201. Order.
  • FIG. 7 is another working timing diagram of the first memory chip set 210 and the second memory chip set 220 .
  • the working principle of the memory will be described below with reference to FIG. 7 , taking one activation command corresponding to four read commands as an example.
  • each signal in FIG. 7 please refer to the description corresponding to 6.
  • the main differences corresponding to FIG. 6 include: the activation command A10 for activating bank10 corresponds to 4 read commands R10 and 4 data signals D10, which are used to activate bank11
  • the activation command A11 corresponds to four read commands R11 and data signals D11, and so on, that is, one activation command corresponds to multiple different read commands.
  • the command port 202 Take the memory chip C1 that receives or transmits signals at the rising edge of the first clock signal as an example: as shown in FIG. 7 , after the command port 202 receives the activation command A10 for a memory block at the rising edge of the first clock signal, the command The port 202 receives four read commands R10 corresponding to the active command A10 on four consecutive rising edges. After the command port 202 receives the read command R10, the data port 203 sends four data signals D10 on the rising edge of the first clock signal.
  • the command port 202 After receiving the activation command A11 for another memory block, the command port 202 receives 4 read commands R11 corresponding to the activation command A11 at 4 consecutive rising edges, and after the command port 202 receives the read command R11, the data port 203 The four data signals D11 are sent on the rising edge of the clock signal, and the process after the command port 202 receives the activation commands A12 and A13 is similar to that described above.
  • the memory chip C2 sends or receives signals on the falling edge of the first clock signal, that is, the memory chip C2 exchanges information with the control chip 214 on the falling edge of the first clock signal; the memory chip C3 communicates with the control chip on the rising edge of the second clock signal 214 performs information exchange, and the memory chip C4 performs information exchange with the control chip 214 at the falling edge of the second clock signal.
  • the working principle of memory chip C2/C3/C4 please refer to the working principle of memory chip C1.
  • the channel is also configured such that: for any memory block, the time difference between the received command signal and the corresponding read command signal is greater than or equal to tRCD, where tRCD is the memory block that can be processed after receiving the command signal.
  • Minimum preparation time required for a read operation is: the interval from the row valid to the read/write command is defined as tRCD, that is, the delay from RAS to CAS, RAS is the row address strobe signal, referred to as the row address signal, and CAS is the column address signal.
  • the address strobe pulse signal is referred to as the column address signal, and tRCD can be understood as the row strobe period.
  • the time difference between A10 and R10 is tRCD; for bank11, the time difference between A11 and R11 can be greater than or equal to tRCD,
  • the situations of bank12 and bank13 are not listed one by one here. Regardless of whether an activation command corresponds to one read command or to multiple read commands, reasonable settings can be used to ensure that for any memory block, the time difference between the received command signal and the corresponding read command signal is greater than or equal to tRCD.
  • different storage blocks use the same command port and data port. In other embodiments, different memory blocks may also use different command ports and different data ports.
  • the row address port is separated from the column address port, the row address signal and the column address signal can be transmitted simultaneously, avoiding data reception or transmission caused by errors caused by the handshake or synchronization of the command clock and the data clock. Therefore, it is beneficial to avoid the problem that the data line is not full in certain time periods, and to ensure that the data line is always full of data, thereby increasing the storage speed of the memory and improving the storage performance of the memory.

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Abstract

本申请实施例提供一种存储器，包括：控制芯片；多个存储芯片，多个所述存储芯片共用信道与所述控制芯片电连接，多个所述存储芯片包括第一存储芯片组和第二存储芯片组，所述第一存储芯片组中的存储芯片被配置为采用第一时钟信号与所述控制芯片进行信息交互，所述第二存储芯片组中的存储芯片被配置为采用第二时钟信号与所述控制芯片进行信息交互，所述第一时钟信号和所述第二时钟信号的相位不同。

Description

存储器
相关申请的交叉引用
本申请基于申请号为202010873263.9、申请日为2020年08月26日的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及半导体技术领域，特别涉及一种存储器。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)是计算机中常用的半导体存储器件，由许多重复的存储单元组成。每个存储单元通常包括电容器和晶体管，晶体管的栅极与字线相连、漏极与位线相连、源极与电容器相连，字线上的电压信号能够控制晶体管的打开或关闭，进而通过位线读取存储在电容器中的数据信息，或者通过位线将数据信息写入到电容器中进行存储。
随着DRAM应用的领域越来越多，如DRAM越来越多地应用于各种领域，用户对于DRAM性能指标的要求越来越高，且会由于应用领域不同而对DRAM有着不同的要求。
发明内容
本申请实施例解决的技术问题为提供一种存储器，解决存储器功耗大、成本高的问题。
为解决上述问题，本申请实施例提供一种存储器，包括：控制芯片；多个存储芯片，多个所述存储芯片共用信道与所述控制芯片电连接，多个所述存储芯片包括第一存储芯片组和第二存储芯片组，所述第一存储芯片 组中的存储芯片被配置为采用第一时钟信号与所述控制芯片进行信息交互，所述第二存储芯片组中的存储芯片被配置为采用第二时钟信号与所述控制芯片进行信息交互，所述第一时钟信号和所述第二时钟信号的相位不同。
另外，所述第一存储芯片组包括第一存储芯片和第二存储芯片，所述第一存储芯片在所述第一时钟信号的上升沿与所述控制芯片进行信息交互，所述第二存储芯片在所述第一时钟信号的下降沿与所述控制芯片进行信息交互；所述第二存储芯片组包括第三存储芯片和第四存储芯片，所述第三存储芯片在所述第二时钟信号的上升沿与所述控制芯片进行信息交互，所述第四存储芯片在所述第二时钟信号的下降沿与所述控制芯片进行信息交互。
另外，所述第一时钟信号和所述第二时钟信号的频率相同。
另外，所述第一时钟信号和所述第二时钟信号的相位差为90度的奇数倍。
另外，每一所述存储芯片包括至少一个通道，所述通道包括：多个存储块，每一所述存储块包括多个存储单元，多个所述存储块被配置为交替进行读写操作；命令端口，所述命令端口被配置为在的对应时钟沿接收命令信号，所述命令信号用于控制所述存储块的读写操作；数据端口，所述数据端口被配置为，在对应时钟沿接收待写入到所述存储块的数据信号或者发送数据信号；其中，所述对应时钟沿包括所述第一时钟信号的时钟沿或者所述第二时钟信号的时钟沿；所述命令端口包括行地址端口和列地址端口，所述行地址端口用于接收目标存储单元所在位置的行地址信号，所述列地址端口用于接收目标存储单元所在位置的列地址信号，所述目标存储单元为所述多个存储单元中选中的存储单元。
另外，所述命令信号包括激活命令以及与每一所述激活命令对应的读命令；所述通道还被配置为，所述命令端口接收针对一所述存储块的所述激活命令后，所述命令端口接收与所述激活命令对应的所述读命令。
另外，所述通道还被配置为，在所述命令端口接收所述读命令之后，所述数据端口发送所述数据信号。
另外，所述命令信号包括激活命令以及与每一所述激活命令对应的多个读命令；所述通道还被配置为，所述命令端口接收针对一所述存储块的所述激活命令后，所述命令端口在多个对应时钟沿接收一与所述激活命令对应的所述读命令，以使所述命令端口在连续多个对应时钟沿接收多个与所述激活命令对应的所述读命令。
另外，所述通道还被配置为，所述数据端口在连续多个所述对应时钟沿分别发送多个所述数据信号，所述数据信号的数量与所接收到的所述读命令的数量相同。
另外，所述命令信号包括激活命令和与所述激活命令对应的读命令；所述通道还被配置为，所述命令端口交替接收针对不同所述存储块的激活命令后，所述命令端口交替接收与所述激活命令对应的所述读命令。
另外，所述通道还被配置为，在所述命令端口接收所述读命令之后，所述数据端口交替发送与不同所述存储块对应的所述数据信号。
另外，所述命令信号包括激活命令以及与每一所述激活命令对应的多个读命令；所述通道还被配置为，所述命令端口交替接收针对不同存储块的所述激活命令，且所述命令端口交替接收与每一所述激活命令对应的多个所述读命令。
另外，所述激活命令包括所述行地址信号，所述读命令包括所述列地址信号；所述通道还被配置为：所述激活命令和所述读命令通过所述命令端口中的不同端口接收。
另外，所述存储芯片包括多个所述通道，所述存储芯片还包括多个所述通道共用的共用电路。
另外，所述存储芯片还包括：测试端口，在测试模式下，多个所述通道共用同一所述测试端口进行测试。
另外，所述共用电路包括测试控制电路，所述测试控制电路用于对多个所述通道的测试控制。
另外，多个所述存储芯片依次堆叠于所述控制芯片上，所述信道包括硅通孔结构。
与现有技术相比，本申请实施例提供的技术方案具有以下优点：
本申请实施例提供一种结构性能优越的存储器，多个存储芯片共用信道与控制芯片电连接，多个存储芯片包括第一存储芯片组和第二存储芯片组，第一存储芯片组中的存储芯片被配置为采用第一时钟信号与控制芯片进行信息交互，第二存储芯片组中的存储芯片被配置为采用第二时钟信号与控制芯片进行信息交互，第一时钟信号和第二时钟信号的相位不同。由于多个存储芯片共用信道与控制芯片电连接，因此无需为每个存储芯片分别设置一个与控制芯片电连接的信道，有利于减少存储器所需的信道的数量，从而降低存储器的成本以及功耗。
另外，由于行地址端口与列地址端口分开，因而可以实现行地址信号和列地址信号同时传输，避免了读命令传输完成后才能传输激活命令信号的问题，因此有利于避免在某些时间段上数据线未被占满的问题，保证数据线始终被数据占满，从而提高存储器的存储速度，改善存储器的存储性能。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，这些示例性说明并不构成对实施例的限定，附图中具有相同参考数字标号的元件表示为类似的元件，除非有特别申明，附图中的图不构成比例限制。
图1为本申请一实施例提供的存储器的结构示意图；
图2为第一时钟信号以及第二时钟信号的两种不同的波形图；
图3为本申请一实施例提供的存储器中各存储芯片对应的工作信号的 时序图；
图4为本申请另一实施例提供的存储器的结构示意图；
图5为图4中一存储芯片的结构示意图；
图6为本申请另一实施例提供的存储器中各存储芯片工作的一种时序图；
图7为本申请另一实施例提供的存储器中各存储芯片工作的另一种时序图。
具体实施方式
由背景技术可知，现有技术的存储器的性能有待提高。
为解决上问题，本申请实施提供一种存储器，多个存储芯片，多个存储芯片共用信道与控制芯片电连接，多个存储芯片包括第一存储芯片组和第二存储芯片组，第一存储芯片组的存储芯片被配置为采用第一时钟信号与控制芯片进行信息交互，第二存储芯片组中的存储芯片被配置为采用第二时钟信号与控制芯片进行信息交互，第一时钟信号与第二时钟信号的相位不同。由于多个存储芯片共用信道，因而在不影响多个存储芯片与控制芯片信息交互的质量的前提下，节省存储器所需的信道数量，从而节省存储器的面积，降低存储器的成本，减小存储器的功耗。
为使本申请实施例的目的、技术方案和优点更加清楚，下面将结合附图对本申请的各实施例进行详细的阐述。然而，本领域的普通技术人员可以理解，在本申请各实施例中，为了使读者更好地理解本申请而提出了许多技术细节。但是，即使没有这些技术细节和基于以下各实施例的种种变化和修改，也可以实现本申请所要求保护的技术方案。
图1为本申请一实施例提供的存储器的结构示意图。
参考图1，本实施例中，存储器包括：控制芯片114；多个存储芯片，多个存储芯片共用信道01与控制芯片114电连接，多个存储芯片包括第一 存储芯片组110和第二存储芯片组120，第一存储芯片组110中的存储芯片被配置为采用第一时钟信号与控制芯片114进行信息交互，第二存储芯片组120中的存储芯片被配置为采用第二时钟信号与控制芯片114进行信息交互，第一时钟信号和第二时钟信号的相位不同。
以下将结合附图对本实施例提供的存储器进行详细说明。
本实施例中，存储器可以为动态随机存储器。
具体地，多个存储芯片可以在控制芯片114上依次层叠设置，有利于提高存储密度且减小存储芯片与控制芯片114的距离；或者，多个存储芯片也可以在控制芯片114上并排设置，有利于减小存储器的纵向厚度。本实施例中，多个存储芯片依次堆叠于控制芯片114上，且信道01包括硅通孔结构(TSV，Through Silicon Via)。
由于第一时钟信号与第二时钟信号的相位不同，因此第一时钟信号的时钟沿的时刻与第二时钟信号的时钟沿能够被区分开，时钟沿包括上升沿和下降沿。如此，虽然第一存储芯片组110与第二存储芯片组120共用信道01，第一存储芯片组110与第二存储芯片组120中的存储芯片能够与控制芯片114在不同的时刻进行信息交互。
本实施例中，如图1所示，第一存储芯片组110包括第一存储芯片111和第二存储芯片112，第一存储芯片在第一时钟信号的上升沿与控制芯片114进行信息交互，第二存储芯片112在第一时钟信号的下降沿与控制芯片114进行信息交互。第二存储芯片组120包括第三存储芯片121和第四存储芯片122，第三存储芯片121在第二时钟信号的上升沿与控制芯片114进行信息交互，第四存储芯片122在第二时钟信号的下降沿与控制芯片114进行信息交互。
需要说明的是，第一存储芯片111与第二存储芯片112可以处于相邻层，二者之间也可以被其他存储芯片间隔开。第三存储芯片121与第四存储芯片122可以处于相邻层，二者之间也可以被其他存储芯片间隔开。
由于第一存储芯片111和第二存储芯片112工作在同一第一时钟信号的不同时钟状态下，使得第一存储芯片111和第二存储芯片112整体上的宏观工作模式为：在第一时钟信号的上升沿以及下降沿均传输数据。因此，对于单个存储芯片而言满足在第一时钟信号的上升沿或者下降沿中的一者传输数据，但是对于存储器整体而言即可达到在第一时钟信号的上升沿和下降沿均传输数据的效果。同样的，第三存储芯片121和第四存储芯片122也工作在同一第二时钟信号的不同时钟状态下，同样具有对于存储器整体而言可达到在第二时钟信号的上升沿和下降沿均传输数据的效果。
此外，第一时钟信号包括第一命令时钟和第一数据时钟，第二时钟信号包括第二命令时钟和第二数据时钟。对于第一存储芯片组110而言，第一存储芯片111在第一命令时钟和/或第一数据时钟的上升沿与控制芯片114进行信息交互；第二存储芯片112在第一命令时钟和/或第一数据时钟的下降沿与控制芯片114进行信息交互。对于第二存储芯片组120而言，第三存储芯片121在第二命令时钟和/或第二数据时钟的上升沿与控制芯片114进行信息交互；第四存储芯片122在第二命令时钟和/或第二数据时钟的下降沿与控制芯片114进行信息交互。
以第一存储芯片111作为示例，第一存储芯片111被配置为，在第一命令时钟的上升沿接收命令信号，命令信号用于控制第一存储芯片111的读写操作，在对于数据时钟的上升沿接收待写入到第一存储芯片111的数据信号或者发送数据信号。有关第二存储芯片112、第三存储芯片121以及第四存储芯片122的相关描述，可参考第一存储芯片111。
本实施例中，为了降低存储器的复杂度，第一命令时钟和第一数据时钟采用同一第一时钟信号，第二命令时钟和第二数据时钟采用同一第二时钟信号。如此，有利于简化电路设计，避免由于第一命令时钟和第一数据时钟握手或同步产生的错误而导致的数据接收或发送错误，避免由于第二命令时钟和第二数据时钟握手或同步产生的错误而导致的数据接收或者发 送错误，提高存储器的存储正确率。
需要说明的是，在其他实施例中，第一命令时钟和第一数据时钟也可以采用不同的第一时钟信号，第二命令时钟和第二数据时钟也可以采用不同的第二时钟信号。
此外，本实施例中，第一时钟信号和第二时钟信号的频率相同。如此，可以有效的避免存储器工作期间在同一时刻出现第一时钟信号的上升沿以及第二时钟信号的上升沿，或者在同一时刻出现第一时钟信号的下降沿以及第二时钟信号的下降沿，保证第一时钟信号以及第二时钟信号时钟能够被相应的存储芯片准确的识别出，提高存储器的读写准确性。可以理解的是，在其他实施例中，第一时钟信号的频率与第二时钟信号的频率的差值的绝对值在容许值内时，也可以认为第一时钟信号与第二时钟信号的频率相同。需要说明的是，第一时钟信号的频率与第二时钟信号的频率也可成倍数关系，只要能够满足上述能区分时钟沿的要求即可。
相应的，第一时钟信号和第二时钟信号的相位差为90度的奇数倍，例如，相位差为90度的3倍、5倍、7倍等。如此，有利于进一步地避免存储器工作期间在同一时刻出现第一时钟信号的上升沿以及第二时钟信号的上升沿，避免在同一时刻出现第一时钟信号的下降沿以及第二时钟信号的下降沿，从而进一步地提高存储器的读写准确性。
具体地，图2为第一时钟信号以及第二时钟信号的两种不同的波形图，以CK1示意出第一时钟信号，CK21示意出一种第二时钟信号，第一时钟信号与第二时钟信号的相位差为90度；CK22示意出另一种第二时钟信号，第一时钟信号与第二时钟信号的相位差为270度。
图3为本实施例提供的存储器中各存储芯片对应的工作信号的时序图，CK1为第一时钟信号，CK2为第二时钟信号，DATA1为第一存储芯片111传输数据的时序图，DATA2为第二存储芯片112传输数据的时序图，DATA3为第三存储芯片121传输数据的时序图，DATA4为第四存储芯片122传输 数据的时序图，DATA为将DATA1、DATA2、DATA3、DATA4合并的时序图。
以下将结合图3对本实施例提供的存储器的工作原理进行说明。
在第一时钟信号的第一个上升沿，第一存储芯片111接收激活命令信号；在时钟信号的第m个上升沿，第一存储芯片111接收读命令信号；在第一时钟信号的第n个上升沿，第一存储芯片111传输数据。在第一时钟信号的第一个下降沿，第二存储芯片112接收激活命令信号；在第一时钟信号的第m个下降沿，第二存储芯片112接收读命令信号；在第一时钟信号的第n个下降沿，第二存储芯片112传输数据。如此，在第一时钟信号的不同上升沿第一存储芯片111传输数据，在第一时钟信号的不同下降沿第二存储芯片112传输数据，直至完成数据的传输。
在第二时钟信号的第一个上升沿，第三存储芯片121接收激活命令信号；在时钟信号的第m个上升沿，第三存储芯片121接收读命令信号；在第二时钟信号的第n个上升沿，第三存储芯片121传输数据。在第二时钟信号的第一个下降沿，第四存储芯片122接收激活命令信号；在第二时钟信号的第m个下降沿，第四存储芯片122接收读命令信号；在第二时钟信号的第n个下降沿，第四存储芯片122传输数据。如此，在第二时钟信号的不同上升沿第三存储芯片121传输数据，在第二时钟信号的不同下降沿第四存储芯片122传输数据，直至完成数据的传输。
可以理解的是，上述是以存储器进行读取操作为例进行说明的，存储器进行写入操作期间第一存储芯片111以及第二存储芯片112也是交替传输数据，第三存储芯片121以及第四存储芯片122也是交替传输数据。
本实施例中，第一存储芯片组110包括两个存储芯片，第二存储芯片组120包括两个存储芯片。需要说明的是，在其他实施例中，第一存储芯片组可以为单个存储芯片，该存储芯片可以在第一时钟信号的上升沿或者下降沿与控制芯片进行信息交互；第二存储芯片组可以为单个存储芯片， 该存储芯片可以在第二时钟信号的上升沿或者下降沿与控制芯片进行信息交互。
本实施例提供的存储器，由于多个存储芯片共用信道01，在不影响控制芯片114与多个存储芯片信息交互的带宽的前提下，减少了存储器的信道01数量，从而降低了存储器的制造成本以及功耗。
本申请另一实施例还提供一种存储器，该存储器与前述实施例大致相同，主要区别包括对每一存储芯片进行了更详细的说明。以下将结合附图对本实施例提供的存储器进行详细说明，需要说明的是，与前述实施例相同或者相应的部分，可参考前述实施例的说明，以下将不做赘述。
图4为本申请另一实施例提供的存储器的结构示意图，图5为图4中一存储芯片的结构示意图。
参考图4及图5，本实施例中，存储器包括：控制芯片214；多个存储芯片，多个存储芯片包括第一存储芯片组210和第二存储芯片组220，前述的信息交互包括读写操作；每一存储芯片包括至少一个通道20，通道20包括：多个存储块201，每一存储块201包括多个存储单元，多个存储块201被配置为交替进行读写操作；命令端口202，命令端口202被配置为在的对应时钟沿接收命令信号，命令信号用于控制存储块201的读写操作；数据端口203，数据端口203被配置为，在对应时钟沿接收待写入到存储块201的数据信号或者发送数据信号；其中，对应时钟沿包括第一时钟信号的时钟沿或者第二时钟信号的时钟沿；命令端口202包括行地址端口212和列地址端口222，行地址端口212用于接收目标存储单元所在位置的行地址信号，列地址端口222用于接收目标存储单元所在位置的列地址信号，目标存储单元为多个存储单元中选中的存储单元。
可以理解的是，对应时钟沿指的是，该存储芯片进行信息交互对应的第一的上升沿或者下降沿，该存储芯片进行信息交互对应的数据时钟的上升沿或者下降沿。
需要注意的是，本实施例所称的命令端口包括传输命令信号和地址信号的端口，但也不限于此。
以下将结合附图对本实施例提供的存储器进行详细说明。
每一存储块201中的多个存储单元可以呈阵列式分布。本实施例中，以每一通道(channel)20包括4个存储块201作为示例，图5中以bank10、bank11、bank12以bank13示意出一通道20中的4个存储块201。可以理解的是，在其他实施例中，每一通道包括的存储块的数量也可以为其他任意数量个，例如为2个、6个等。
数据端口203用于接收待存入存储单元中的数据或发送从存储单元中读出的数据。
存储芯片包括多个通道20，且存储芯片还包括多个通道20共用的共用电路204。本实施例中，该共用电路204可以为测试控制电路，测试控制电路用于对多个通道20的测试控制。在其他实施例中，该共用电路也可以为温度传感器电路、模拟电路或者电荷泵电路中的至少一种。
存储器还可以包括：测试端口，且在测试模式下多个通道20共用同一测试端口进行测试。由于共用测试端口的设置，有利于减少存储器中端口的数量，从而降低采用探针卡对存储器进行测试的难度，且降低探针卡的制造难度。
对于第一存储芯片组210中的存储芯片而言，对应时钟沿为第一时钟信号的时钟沿；对于第二存储芯片组220中的存储芯片，对应时钟沿为第二时钟信号的时钟沿。
命令信号包括激活命令以及与每一激活命令对应的读命令。通道20还被配置为，命令端口202接收针对一存储块的激活命令后，命令端口202接收与激活命令对应的读命令。更具体地，激活命令包括行地址信号，其中行地址信号通过行地址端口212接收；读命令包括列地址信号，其中列地址信号通过列地址端口222接收。需要注意的是，激活命令和读命令中 还可能包含除行地址信号或列地址信号以外的其他控制信号，这些其他控制信号用于帮助或辅助存储芯片识别该命令是否是激活命令或读命令，且这些其他控制信号可通过除行地址端口212和列地址端口222之外的其他命令端口接收；如此，行地址端口212可以连续地接收行地址信号，列地址端口222可以连续地接收列地址信号。相应的，通道20还被配置为：激活命令和读命令通过命令端口202中的不同端口接收，从而可以实现激活命令和读命令的同时接收。此外，通道20还被配置为，在命令端口202接收读命令之后，数据端口203发送数据信号。
本实施例中，命令信号包括激活命令和与激活命令对应的读命令；通道还被配置为，命令端口202交替接收针对不同存储块201的激活命令后，命令端口202交替接收激活命令对应的读命令。具体地，行地址端口212交替接收针对不同存储块201的激活命令后，列地址端口222交替接收激活命令对应的读命令。
此外，通道还被配置为，在命令端口202接收读命令之后，数据端口203交替发送与不同存储块201对应的数据信号。
有关第一存储芯片组210与第二存储芯片组220的区别详细说明，可参考前述实施例，以下将以第一存储芯片组210中存储芯片作为示例，对命令端口202的工作方式进行详细说明。
第一存储芯片组210包括第一存储芯片211和第二存储芯片212；第二存储芯片组220包括第三存储芯片221和第四存储芯片222。
第一存储芯片211的命令端口202采用第一时钟信号的上升沿接收或者发送信号，数据端口203采用第一时钟信号的上升沿接收或者发送信号，该存储芯片记为存储芯片C1；第二存储芯片212的命令端口202采用第一时钟信号的下降沿接收或者发送信号，数据端口203采用第一时钟信号的下降沿接收或者发送信号，该存储芯片记为存储芯片C2。第三存储芯片221的命令端口202采用第二时钟信号的上升沿接收或者发送信号，数据端口 203采用第二时钟信号的上升沿接收或者发送信号，该存储芯片记为存储芯片C3；第四存储芯片222的命令端口202采用第二时钟信号的下降沿接收或者发送信号，数据端口203采用第二时钟信号的下降沿接收或者发送信号，该存储芯片记为C4。
图6为存储芯片C1/C2/C3/C4的一种工作时序图，以下将结合时序图对该存储器的工作原理进行说明。
图6中以CK1示意出第一时钟信号，CK2示意出第二时钟信号，ACT1/ACT2/ACT3/ACT4对应示意出针对存储芯片C1/C2/C3/C4的激活命令信号的时序图，RD1/RD2/RD3/RD4示意出针对存储芯片C1/C2/C3/C4的读命令信号的时序图，DATA1/DATA2/DATAA3/DATA4示意出存储芯片C1/C2/C3/C4的数据端口的数据信号的时序图。
其中，以存储芯片C1包括bank10、bank11、bank12以bank13四个存储块201作为示例，激活命令信号ACT1包括分别用于激活bank10、bank11、bank12以bank13的A10/A11/A12/A13，A10与bank10对应，A11与bank11对应，依次类推；读命令信号RD1包括与bank10、bank11、bank12以bank13一一对应的R10/R11/R12/R13，数据信号DATA1包括D10/D11/D12/D13；激活命令A10与bank10、1个读命令R10以及数据信号D10对应，激活命令A11与bank11、1个读命令R11以及数据信号D11对应，激活命令A12与bank12、1个读命令R12以及数据信号D12对应，激活命令A13与bank13、与1个读命令R13以及数据信号D13对应，即一激活命令对应一读命令。
有关存储芯片C2对应的激活命令信号A20/A21/A22/A23、读命令信号R20/R21/R22/R23、数据信号D20/D21/D22/D23，存储芯片C3对应的激活命令信号A30/A31/A32/A33、读命令信号R30/R31/R32/R33、数据信号D30/D31/D32/D33，存储芯片C4对应的激活命令信号A40/A41/A42/A43、读命令信号R40/R41/R42/R43、数据信号D40/D41/D42/D43的详细说明可参考前述说明。
如图6所示，对于存储芯片C1，以命令端口202和数据端口203采用第一时钟的上升沿接收或者发送信号作为示例：命令端口202在第一时钟信号的上升沿接收到针对一存储块的激活命令A10后，命令端口202在上升沿接收与激活命令A10对应的1个读命令R10；在命令端口202接收读命令R10之后，数据端口203在第一时钟信号的上升沿发送数据信号D10。关于命令端口202接收到激活命令A11/A12/A13后的流程与前述类似。
具体地，命令端口202中的行地址端口212在第一时钟信号的第一个上升沿接收激活bank10的激活命令A10，命令端口202中的行地址端口212在第一时钟信号的第二个上升沿接收激活bank11的激活命令A11，在第一时钟信号的第三个上升沿接收激活bank12的激活命令A12，在第一时钟信号的第四个上升沿接收激活bank13的激活命令A12；命令端口202中的列地址端口222在第n个上升沿接收与激活命令A10对应的读命令R10，命令端口202在第n+1个上升沿接收与激活命令A11对应的读命令R11，在第n+2个上升沿接收与激活命令A2对应的读命令R12，在第n+3个上升沿接收与激活命令A13对应的读命令R13，其中，n为任意自然数。相应的，数据端口203在时钟信号的第m个上升沿发送与存储块bank10对应的数据信号D10，数据端口203在第一时钟信号的第m+1个上升沿发送与存储块bank11对应的数据信号D11，在第m+2个上升沿发送与bank12对应的数据信号D12，在第m+3个上升沿发送与bank13对应的数据信号D13，其中，m为任意自然数，且对于每一存储块而言，对应的m大于n。
需要说明的是，图6中以在连续的上升沿分别接收激活命令A10、A11、A12、A13作为示例，即在连续的上升沿分别接收不同存储块对应的激活命令，在其他实施例中，也可以在非连续的上升沿分别接收不同存储块对应的激活命令。
从图6中不难发现，由于行地址端口212与列地址端口222不共用，因此在列地址端口222接收读命令R10期间，行地址端口212可以接收激 活命令A12，如此，无需等待所有的读命令信号都接收完毕之后才能接收激活命令，使得数据总线能够被填满，即数据端口203可以连续传输数据，避免数据总线在一定时间段内出现的空闲问题，从而有利于提升存储器的存储速度。
此外，如图6所示，对于存储芯片C2，以命令端口202和数据端口203采用第一时钟信号的下降沿接收或者发送信号：命令端口202在第一时钟信号的下降沿接收到针对一存储块201的激活命令A0后，命令端口202在上升沿接收与激活命令A20对应的1个读命令R20；在命令端口202接收读命令R20之后，数据端口203在第一时钟信号的下降沿发送数据信号D20。有关发存储芯片C2发送数据信号D21/D22/D23的过程将不做详细赘述。
有关存储芯片C3以及存储芯片C4的工作过程，与前述存储芯片C1/C2的工作方式类似，可参考前述说明，将不做赘述。可以理解的是，由于第一时钟信号与第二时钟信号的相位不同，存储芯片C1/C2/C3/C4分别在第一时钟信号的不同时钟沿以及第二时钟信号的不同时钟沿接收或者发送信号，因此共用信道02的四个存储芯片传输数据互不干扰。
在另一个例子中，命令信号包括激活命令以及与每一激活命令对应的多个读命令；通道20还被配置为，命令端口202接收针对一存储块201的激活命令后，命令端口202在多个对应时钟沿接收一与激活命令对应的读命令，以使命令端口202在连续多个对应时钟沿接收多个与激活命令对应的读命令。通道20还被配置为，数据端口203在连续多个对应时钟沿分别发送多个数据信号，数据信号的数量与所接收到的读命令的数量相同。具体地，激活命令包括行地址信号，读命令包括所述列地址信号；通道20还被配置为：激活命令和读命令通过命令端口中的不同端口接收。
此外，命令信号可以包括激活命令以及与每一激活命令对应的多个读命令；通道20还可以被配置为，命令端口202交替接收针对不同存储块201 的激活命令后，命令端口202交替接收与每一所述激活命令对应的多个所述读命令。具体地，命令端口202交替接收针对不同存储块201的激活命令后，命令端口202在多个对应时钟沿中的每一时钟沿接收一与激活命令对应的读命令，以使命令端口202在连续多个时钟沿接收多个与激活命令对应的读命令，直至命令端口202接收与激活命令对应的多个读命令，之后，命令端口202接收针对另一存储块201的激活命令对应的多个读命令。
图7为第一存储芯片组210以及第二存储芯片组220的另一种工作时序图，以下将结合图7对该存储器的工作原理进行说明，以一个激活命令对应4个读命令作为示例。
有关图7中各信号的说明可参考6对应的说明，与图6对应的主要区别包括：用于激活bank10的激活命令A10与4个读命令R10以及4个数据信号D10对应，用于激活bank11的激活命令A11与4个读命令R11以及数据信号D11对应，依此类推，即一激活命令对应多个不同的读命令。
以在第一时钟信号的上升沿接收或发送信号的存储芯片C1作为示例：如图7所示，命令端口202在第一时钟信号的上升沿接收到针对一存储块的激活命令A10后，命令端口202在4个连续的上升沿接收与激活命令A10对应的4个读命令R10，在命令端口202接收读命令R10之后，数据端口203在第一时钟信号的上升沿发送四个数据信号D10。在接收到针对另一存储块的激活命令A11后，命令端口202在4个连续的上升沿接收与激活命令A11对应的4个读命令R11，在命令端口202接收读命令R11之后，数据端口203在时钟信号的上升沿发送四个数据信号D11，关于命令端口202接收到激活命令A12以及A13之后的流程与前述类似。
存储芯片C2在第一时钟信号的下降沿发送或者接收信号，即存储芯片C2在第一时钟信号的下降沿与控制芯片214进行信息交互；存储芯片C3在第二时钟信号的上升沿与控制芯片214进行信息交互，存储芯片C4在第二时钟信号的下降沿与控制芯片214进行信息交互。有关存储芯片 C2/C3/C4的工作原理可参考存储芯片C1的工作原理。
需要说明的是，本实施例中，通道还被配置为：对于任意存储块，接收命令信号与接收对应的读命令信号的时间差大于或等于tRCD，tRCD为存储块在接收到命令信号之后可进行读操作所需的最短准备时间。具体地，关于tRCD的定义为：从行有效到读/写命令发出之间的间隔被定义为tRCD，即RAS到CAS的延迟，RAS为行地址选通脉冲信号简称行地址信号，CAS为列地址选通脉冲信号简称列地址信号，tRCD可理解为行选通周期。如此，可以保证存储块在接收到读命令之前或接收到读命令时已经被完全激活，在接收到读命令时即可进行读操作，从而进一步地提高存储器的存储速度。
具体地，以存储芯片C1作为示例，如图6及图7，对于bank10而言，A10与R10之间的时间差为tRCD；对于bank11而言，A11与R11之间的时间差可以大于或等于tRCD，关于bank12以及bank13的情形在此不再一一列举。不管一个激活命令对应一个读命令还是对应多个读命令，均可以通过合理的设置保证对于任意存储块，接收命令信号与接收对应的读命令信号的时间差大于或等于tRCD。
本实施例提供的存储器中，不同的存储块采用相同的命令端口以及数据端口。在其他实施例中，不同的存储块也可以采用不同的命令端口以及不同的数据端口。
本实施例提供的存储器，由于行地址端口与列地址端口分开，因而可以实现行地址信号和列地址信号同时传输，避免由于命令时钟和数据时钟握手或同步产生的错误而导致的数据接收或发送错误，因此有利于避免在某些时间段上数据线未被占满的问题，保证数据线始终被数据占满，从而提高存储器的存储速度，改善存储器的存储性能。
本领域的普通技术人员可以理解，上述各实施方式是实现本申请的具体实施例，而在实际应用中，可以在形式上和细节上对其作各种改变，而不偏离本申请的精神和范围。任何本领域技术人员，在不脱离本申请的精 神和范围内，均可作各自更动与修改，因此本申请的保护范围应当以权利要求限定的范围为准。

Claims (17)

  1. 一种存储器，包括：
    控制芯片；
    多个存储芯片，多个所述存储芯片共用信道与所述控制芯片电连接，多个所述存储芯片包括第一存储芯片组和第二存储芯片组，所述第一存储芯片组中的存储芯片被配置为采用第一时钟信号与所述控制芯片进行信息交互，所述第二存储芯片组中的存储芯片被配置为采用第二时钟信号与所述控制芯片进行信息交互，所述第一时钟信号和所述第二时钟信号的相位不同。
  2. 如权利要求1所述的存储器，其中，所述第一存储芯片组包括第一存储芯片和第二存储芯片，所述第一存储芯片在所述第一时钟信号的上升沿与所述控制芯片进行信息交互，所述第二存储芯片在所述第一时钟信号的下降沿与所述控制芯片进行信息交互；所述第二存储芯片组包括第三存储芯片和第四存储芯片，所述第三存储芯片在所述第二时钟信号的上升沿与所述控制芯片进行信息交互，所述第四存储芯片在所述第二时钟信号的下降沿与所述控制芯片进行信息交互。
  3. 如权利要求2所述的存储器，其中，所述第一时钟信号和所述第二时钟信号的频率相同。
  4. 如权利要求3所述的存储器，其中，所述第一时钟信号和所述第二时钟信号的相位差为90度的奇数倍。
  5. 如权利要求1所述的存储器，其中，每一所述存储芯片包括至少一个通道，所述通道包括：多个存储块，每一所述存储块包括多个存储单元，多个所述存储块被配置为交替进行读写操作；命令端口，所述命令端口被配置为在的对应时钟沿接收命令信号，所述命令信号用于控制所述存储块的读写操作；数据端口，所述数据端口被配置为，在对应时钟沿接收待写 入到所述存储块的数据信号或者发送数据信号；其中，所述对应时钟沿包括所述第一时钟信号的时钟沿或者所述第二时钟信号的时钟沿；所述命令端口包括行地址端口和列地址端口，所述行地址端口用于接收目标存储单元所在位置的行地址信号，所述列地址端口用于接收目标存储单元所在位置的列地址信号，所述目标存储单元为所述多个存储单元中选中的存储单元。
  6. 如权利要求5所述的存储器，其中，所述命令信号包括激活命令以及与每一所述激活命令对应的读命令；所述通道还被配置为，所述命令端口接收针对一所述存储块的所述激活命令后，所述命令端口接收与所述激活命令对应的所述读命令。
  7. 如权利要求6所述的存储器，其中，所述通道还被配置为，在所述命令端口接收所述读命令之后，所述数据端口发送所述数据信号。
  8. 如权利要求5所述的存储器，其中，所述命令信号包括激活命令以及与每一所述激活命令对应的多个读命令；所述通道还被配置为，所述命令端口接收针对一所述存储块的所述激活命令后，所述命令端口在多个对应时钟沿接收一与所述激活命令对应的所述读命令，以使所述命令端口在连续多个对应时钟沿接收多个与所述激活命令对应的所述读命令。
  9. 如权利要求8所述的存储器，其中，所述通道还被配置为，所述数据端口在连续多个所述对应时钟沿分别发送多个所述数据信号，所述数据信号的数量与所接收到的所述读命令的数量相同。
  10. 如权利要求5所述的存储器，其中，所述命令信号包括激活命令和与所述激活命令对应的读命令；所述通道还被配置为，所述命令端口交替接收针对不同所述存储块的激活命令后，所述命令端口交替接收与所述激活命令对应的所述读命令。
  11. 如权利要求10所述的存储器，其中，所述通道还被配置为，在所述命令端口接收所述读命令之后，所述数据端口交替发送与不同所述存储块 对应的所述数据信号。
  12. 如权利要求5所述的存储器，其中，所述命令信号包括激活命令以及与每一所述激活命令对应的多个读命令；所述通道还被配置为，所述命令端口交替接收针对不同存储块的所述激活命令，且所述命令端口交替接收与每一所述激活命令对应的多个所述读命令。
  13. 如权利要求6、8、10或12所述的存储器，其中，所述激活命令包括所述行地址信号，所述读命令包括所述列地址信号；所述通道还被配置为：所述激活命令和所述读命令通过所述命令端口中的不同端口接收。
  14. 如权利要求5所述的存储器，其中，所述存储芯片包括多个所述通道，所述存储芯片还包括多个所述通道共用的共用电路。
  15. 如权利要求14所述的存储器，其中，所述存储芯片还包括：测试端口，在测试模式下，多个所述通道共用同一所述测试端口进行测试。
  16. 如权利要求14所述的存储器，其中，所述共用电路包括测试控制电路，所述测试控制电路用于对多个所述通道的测试控制。
  17. 如权利要求1所述的存储器，其中，多个所述存储芯片依次堆叠于所述控制芯片上，所述信道包括硅通孔结构。
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