WO2022041232A1 - 芯片测试电路及电路测试方法 - Google Patents

芯片测试电路及电路测试方法 Download PDF

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Publication number
WO2022041232A1
WO2022041232A1 PCT/CN2020/112660 CN2020112660W WO2022041232A1 WO 2022041232 A1 WO2022041232 A1 WO 2022041232A1 CN 2020112660 W CN2020112660 W CN 2020112660W WO 2022041232 A1 WO2022041232 A1 WO 2022041232A1
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WIPO (PCT)
Prior art keywords
test
circuit
scan
data distribution
bus
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PCT/CN2020/112660
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English (en)
French (fr)
Inventor
崔昌明
黄俊林
黄宇
付海涛
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/112660 priority Critical patent/WO2022041232A1/zh
Priority to EP20950901.7A priority patent/EP4194865A4/en
Priority to CN202080100077.XA priority patent/CN115443413A/zh
Publication of WO2022041232A1 publication Critical patent/WO2022041232A1/zh
Priority to US18/175,306 priority patent/US20230204660A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318558—Addressing or selecting of subparts of the device under test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3172—Optimisation aspects, e.g. using functional pin as test pin, pin multiplexing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31722—Addressing or selecting of test units, e.g. transmission protocols for selecting test units
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/31723—Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318544—Scanning methods, algorithms and patterns
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318572—Input/Output interfaces
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836—Fault-finding or characterising
    • G01R31/2844—Fault-finding or characterising using test interfaces, e.g. adapters, test boxes, switches, PIN drivers

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a test circuit in a chip and a circuit test method.
  • a small number of chip pins are multiplexed with multiplexers (MUX), which can realize the test of a circuit with a larger number of test scan channels. If the number of scan channels of the circuit to be tested is If it continues to increase, there will be more serious routing congestion problems, and the test cost will be high.
  • the test scan data is transmitted through the bus, and during the transmission process, the test data is exchanged between the bus and the test compression logic of the circuit under test through a more complex hardware circuit. , the hardware circuit for data exchange will also increase, resulting in a larger scale of the hardware circuit.
  • various configurations of complex hardware circuits are also required, the configuration process is complicated, and the test efficiency is low.
  • the embodiments of the present application provide a chip test circuit and a circuit test method, which can optimize the problems of wire routing congestion and complex test configuration in the current test scheme, so as to reduce the test cost and improve the test efficiency.
  • a test circuit in a first aspect, includes: a plurality of sub-test circuits respectively corresponding to the plurality of tested circuits, and the plurality of sub-test circuits are used to respectively connect the corresponding tested circuits to the test bus.
  • Each circuit under test corresponds to a sub-test circuit, and each sub-test circuit can transmit the data required for the test scan to the scan input channel of the corresponding circuit under test through the test bus, and transmit the test result data of the corresponding circuit under test to the scan input channel of the corresponding circuit under test. Transfer to the test bus output.
  • Each sub-test circuit can also dynamically assign the test bus to the corresponding circuit under test.
  • the jth sub-test circuit among the plurality of sub-test circuits includes Nj data distribution circuits and M first selectors, wherein Nj and M are both positive integers, M is equal to the bit width of the test bus, and M is greater than or equal to Nj.
  • the jth sub-test circuit may be any one of the multiple sub-test circuits.
  • the data distribution circuit is used to receive the scan test data of the test bus and transmit it to the scan input channel of the circuit under test, and receive the test result data of the scan output channel of the circuit under test, and transmit it to the test bus output.
  • the connection relationship between the data distribution circuit and the test bus and the circuit under test is: the first input terminals of the Nj data distribution circuits are respectively connected to the Nj inputs of the test bus, and are used for receiving the test of the test bus.
  • the first output terminals of the Nj data distribution circuits are connected to the scan input channel of the circuit under test corresponding to the jth sub-test circuit, and are used to transmit the test scan data received by the data distribution circuit to the scan input of the circuit under test In the channel;
  • the second input end of the Nj data distribution circuits is connected to the scan output channel of the circuit under test corresponding to the jth sub-test circuit, and is used to transmit the test result data of the circuit under test to the data distribution circuit, and then pass the data through the data distribution circuit.
  • the distribution circuit transmits to the output of the test bus.
  • the first selector may be a selector for selecting one of two, and is used to select the test bus used by the j+1 th sub-test circuit, so as to realize the dynamic allocation of the test bus.
  • the output terminals of the M first selectors in each sub-test circuit are respectively connected to the M outputs of the test bus, and the M first selectors in each sub-test circuit are respectively connected to the M bits of the test bus one by one.
  • the first input ends of Nj first selectors in the M first selectors are respectively connected to the second output ends of the Nj data distribution circuits, and the first input ends of the remaining M-Nj first selectors are respectively Connect to the input of M-Nj test buses without data distribution circuits.
  • the second input ends of Nj first selectors among the M first selectors are respectively connected to the second output ends of the Nj data distribution circuits, and the second input ends of the remaining M-Nj first selectors are respectively connected to M - Inputs of Nj test buses not provided with data distribution circuits.
  • the test buses connected to the first input terminal and the second input terminal of each first selector are different.
  • the test bus connected to the first input terminal and the second input terminal of the first selector is different, and the test bus used by the j+1th sub-test circuit can be configured through the first selector.
  • the test circuit transmits the input data of the test vector, that is, the scan test data, to the data distribution circuit through the input of the test bus, and to the scan input channel of the circuit under test through the data distribution circuit.
  • the output data of the test vector of the output channel of the circuit under test that is, the test result data
  • the dynamic correspondence between the data distribution circuit and the test bus is realized by configuring the first selector, so that the test resources can be dynamically allocated.
  • the bit width of the test bus is 8 bits
  • the number of data distribution circuits used in the first sub-test circuit is 3, and the number of the second data distribution circuit is 5.
  • the three data distribution circuits in the first sub-test circuit are respectively connected to the [0], [1], and [2] bits of the test bus
  • the four data distribution circuits in the second sub-test circuit are respectively connected to the test bus
  • the outputs of the eight first selectors are respectively connected to the eight outputs of the test bus.
  • the first input ends of the first 3 first selectors can be connected to the second output ends of the 3 data distribution circuits in the first sub-test circuit;
  • the first input terminals of the last five first selectors can be connected to the inputs of bits [3], [4], [5], [6], and [7] of the test bus.
  • the second input terminals of the first five first selectors can be connected to the inputs of bits [3], [4], [5], [6], and [7] of the test bus;
  • the two input terminals can be connected to the second output terminals of the three data distribution circuits in the first sub-test circuit.
  • the test bus allocated in the second sub-test circuit is the test bus Bits [0], [1], [2], [3], [4].
  • the test bus allocated in the second sub-test circuit is the test bus [3], [4], [5], [6], [7] bits. That is, through the configuration of the first selector in the first sub-test circuit through the above solution, the test bus used in the second sub-test circuit can be dynamically allocated, and only the first selector needs to be configured during configuration.
  • the data distribution circuit and the first selector realize the dynamic distribution of the test bus used by the circuit under test, which can greatly optimize the problem of winding congestion, so as to reduce the test cost , and can simplify the configuration process and improve the test efficiency.
  • the first input terminals of the Nj data distribution circuits are sequentially connected to the first Nj tests The input of the bus; the first input ends of the first Nj first selectors are sequentially connected to the second output ends of the Nj data distribution circuits, and the first input ends of the M-Nj first selectors are sequentially connected to the second output ends of the test bus.
  • the first selector is configured so that when the first input end of the first selector is connected to the output end, the output of the first selector is the same as the test bus corresponding to the input, That is, the direct connection mode.
  • the second input ends of the first M-Nj first selectors are sequentially connected to the last M-Nj inputs of the test bus; the second input ends of the last Nj first selectors are sequentially connected to the second output ends of the Nj data distribution circuits , that is, in the jth sub-test circuit, when the first selector is configured so that the second input end of the first selector is connected to the output end, the output of the first selector is different from the test bus corresponding to the input, that is, the shift connection model.
  • the data distribution circuit is allocated to the bus resources in a preset order according to the established rules, so that the test circuit can simplify the circuit design under the condition of ensuring the dynamic allocation of test resources, thereby improving the efficiency of the test circuit. Test efficiency.
  • the preset test bus sequence is the sequence or reverse sequence of the test bus sequence.
  • the preset test bus sequence is a specific sequence, such as the test bus sequence or the reverse sequence, in this way, the circuit structure of the test circuit can be further simplified, thereby simplifying the test to a certain extent The structure of the circuit in order to quickly realize the wiring requirements of the test circuit.
  • the first output terminals of the CI j data distribution circuits in the Nj data distribution circuits are respectively connected with the CI j scan input channels of the circuit under test corresponding to the jth sub-test circuit, that is, the first output terminal of the data distribution circuit is used for
  • the test scan data received from the test bus is transmitted to the scan input channel of the corresponding circuit under test.
  • the second input terminals of the CO j data distribution circuits in the Nj data distribution circuits are respectively connected with the CO j scan output channels of the circuit under test corresponding to the jth sub-test circuit, that is, the second input terminal of the data distribution circuit is used for
  • the test result data output by the scan output channel of the corresponding circuit under test is received, and the test result data is output to the test bus through the second output terminal of the data distribution circuit.
  • each data distribution circuit may include a fourth selector, a register and a fifth selector.
  • the fourth selector is used to realize that the data distribution circuit selects whether to receive data from the test bus or to receive data from the scan output channel of the corresponding circuit under test. That is, the first input terminal and the second input terminal of the fourth selector are respectively connected to the first input terminal and the second input terminal of the data distribution circuit, and the control terminal of the fourth selector is connected to the first control terminal of the data distribution circuit.
  • the register is used to temporarily store the data received by the data distribution circuit, so the input end of the register is connected to the output end of the fourth selector, and the output end of the register is connected to the first input end of the fifth selector.
  • the fifth selector is used to realize the configuration of whether the input data of the test bus passes through the register, that is, the second input end of the fifth selector is connected to the first input end of the data distribution circuit, and the output end of the fifth selector is connected to the data distribution circuit.
  • the second output end, the control end of the fifth selector is connected to the second control end of the data distribution circuit.
  • the first output end of the data distribution circuit is connected to the first input end of the data distribution circuit or the output end of the register or the second output end of the data distribution circuit.
  • the data distribution circuit has two inputs, respectively receiving test scan data from the test bus and receiving test output data from the corresponding scan output channel of the circuit under test;
  • the configuration of the device realizes the selection of the input, so that the test scan data and the test output data are transmitted in different time periods respectively, and in the case of a simpler circuit structure, data transmission conflicts can be avoided.
  • the data distribution circuit also controls whether the second output of the data distribution circuit passes through the register inside the data distribution circuit through the configuration of the fifth selector, so that the circuit under test corresponding to the sub-test circuit where the data distribution circuit is located does not participate in the test. At the time, the first input to the second output of the data distribution circuit do not pass through the internal register, so as to reduce the test time and further improve the test efficiency.
  • each sub-test circuit may further include a controller, wherein the controller may include: a first signal interface, the first signal interface and each first selection in the sub-test circuit
  • the control end of the selector is connected to control the first input end of the first selector to communicate with the output end or the second input end of the first selector to communicate with the output end.
  • the second signal interface is connected to the second control terminal of each data distribution circuit in the sub-test circuit, and is used to control the first input terminal and the second output terminal of the data distribution circuit to be directly connected or connected through a register.
  • the dynamic allocation of test resources is realized by configuring the first selector, and the circuit under test that does not participate in the test is realized by configuring the fifth selector when the circuit under test does not participate in the test.
  • the data distribution circuit in the corresponding sub-test circuit is configured in a bypass state, even though the first input to the second output of the data distribution circuit do not pass through the internal register, so as to reduce the test time. Therefore, in this optional solution, the first selector is configured by outputting the shift selection control signal through the first signal interface of the controller, and the data is configured by outputting the bypass enable signal through the second signal interface of the controller.
  • a fifth selector in the distribution circuit is configured.
  • the data distribution circuit passes through the scan input channel of the circuit under test corresponding to the jth sub-test circuit by the first gating circuit
  • the connection is used to control whether the data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the jth sub-test circuit.
  • the data distribution circuit is connected between the second gate control circuit and the scan output channel of the circuit under test corresponding to the jth sub-test circuit, and is used to control the data of the scan output channel of the circuit under test corresponding to the jth sub-test circuit Whether to output to the data distribution circuit.
  • corresponding gate control circuits are provided between the scan input channel of the circuit under test and the data distribution circuit, as well as between the scan output channel of the circuit under test and the data distribution circuit, so that only when the corresponding Only when the gating circuit of the test circuit is turned on, data can be transmitted between the data distribution circuit and the scan input channel of the circuit under test, or between the scan output channel of the circuit under test and the data distribution circuit, thereby avoiding the transmission of invalid data.
  • each sub-test circuit may further include a state machine, and the state machine may include: a first state control interface, which communicates with the first control interface of each data distribution circuit in the sub-test circuit The terminal is connected to generate an output capture enable signal to control whether each data distribution circuit in the sub-test circuit receives the scan output data of the circuit under test.
  • the second state control interface is connected to the control terminal of the first gating circuit, and is used to generate a first gating enable signal to control whether the data of each data distribution circuit in the sub-test circuit is transmitted to the corresponding sub-test circuit.
  • the scan input channel of the circuit under test is used to generate a first gating enable signal to control whether the data of each data distribution circuit in the sub-test circuit is transmitted to the corresponding sub-test circuit.
  • the third state control interface is connected to the control terminal of the second gating circuit, and is used to generate a second gating enable signal to control whether the data of the scan output channel of the circuit under test corresponding to the sub-test circuit is transmitted to the under test.
  • the fourth state control interface is connected to the scan enable terminal of the scan structure of the circuit under test, and is used for generating a scan enable signal for controlling whether the scan structure of the circuit under test corresponding to the sub-test circuit performs test scan.
  • the output capture enable signal is generated through the first state control interface of the state machine, which is used to configure the fourth selector in the data distribution circuit to control the data distribution circuit to receive the test of the test bus at the current time
  • the scan data is also the scan output data of the received circuit under test.
  • the first gate control enable signal is generated through the second state interface of the state machine to control whether the test scan data of the data distribution circuit is transmitted to the scan input channel of the circuit under test.
  • a third gating enable signal is generated through the third state interface of the state machine to control whether the scan data of the scan output channel of the circuit under test is transmitted to the data distribution circuit corresponding to the circuit under test.
  • a scan enable signal is generated through the fourth state interface to control whether the scan structure of the circuit under test starts the test scan.
  • the test circuit is provided inside or outside the circuit under test. In the above possible implementation manner, whether the test circuit is arranged inside or outside the circuit under test, it has no influence on the test circuit and the circuit operation of the circuit under test.
  • a test circuit in a second aspect, includes: a plurality of sub-test circuits respectively corresponding to the plurality of tested circuits, and the plurality of sub-test circuits are used to connect the corresponding tested circuits to the test bus.
  • Each circuit under test corresponds to a sub-test circuit, and each sub-test circuit can transmit the data required for the test scan to the scan input channel of the corresponding circuit under test through the test bus, and transmit the test result data of the corresponding circuit under test to the scan input channel of the corresponding circuit under test. Transfer to the test bus output.
  • Each sub-test circuit can also dynamically assign the test bus to the corresponding circuit under test.
  • the j-th sub-test circuit among the plurality of sub-test circuits includes M data distribution circuits, M second selectors and CI j third selectors.
  • the jth sub-test circuit may be any one of the multiple sub-test circuits.
  • the number of data distribution circuits in the jth sub-test circuit and the number M of second selectors are both equal to the bit width of the test bus.
  • the number CI j of third selectors in the jth sub-test circuit is equal to the number of scan input channels of the circuit under test corresponding to the jth sub-test circuit.
  • the first input terminals of the M data distribution circuits are respectively connected to the M inputs of the test bus, that is, the first input terminals of the data distribution circuits are used to receive the test scan data of the test bus, and the second output terminals of the M data distribution circuits are respectively connected to The M outputs of the test bus, that is, the second output end of the data distribution circuit, are used for outputting test result data to the test bus.
  • the CO j input terminals of each of the M second selectors are respectively connected to CO j scan output channels of the circuit under test corresponding to the jth sub-test circuit.
  • the output terminals of the M second selectors are respectively connected to the second input terminals of the M data distribution circuits in the sub-test circuit.
  • the second selector is a multiple-select-one multiplexer.
  • the number of input terminals of the second selector is related to the number of scan output channels of the circuit under test corresponding to the jth sub-test circuit. For example, the number of scan output channels of the circuit under test is: If three, the second selector can select one of three multiplexers for selecting the data distribution circuit corresponding to each scan output channel of the circuit under test and the corresponding test bus.
  • the M input terminals of each of the CI j third selectors are respectively connected to the first output terminals of the M data distribution circuits.
  • the output ends of the CI j third selectors are respectively connected to the CI j scan input channels of the circuit under test corresponding to the jth sub-test circuit.
  • the third selector is also a multiple-select-one multiplexer.
  • the number of input terminals of the third selector is related to the number of data distribution circuits corresponding to the jth sub-test circuit, and the number of data distribution circuits is related to the bit width of the test bus. For example, if the bit width of the test bus is eight bits, the third selector can be an eight-to-one multiplexer, which is used to select the data distribution circuit corresponding to the scan input channel of the circuit under test and the corresponding test bus.
  • the test circuit transmits the input data of the test vector, that is, the scan test data, to the data distribution circuit through the input of the test bus, and to the scan input channel of the circuit under test through the data distribution circuit.
  • the output data of the test vector of the output channel of the circuit under test is transmitted to the output of the test bus through the data distribution circuit to complete the test of the circuit under test.
  • the scan output channel of the circuit under test is configured by the second selector to select the connected data distribution circuit
  • the scan input channel of the circuit under test is configured by the third selector to select the connected data distribution circuit.
  • each bit of the test bus is provided with a data distribution circuit, so through the configuration of the second selector and the third selector, the problem of bus resource planning and routing congestion can be optimized, and the problem of routing congestion can also be realized.
  • the assignment of each scan channel of the circuit under test to any bus resource makes the assignment of bus resources more flexible.
  • each data distribution circuit may include a fourth selector, a register and a fifth selector; the internal structure of the data distribution circuit and the technical effects that can be produced may be Referring to the internal structure and technical effects of the data distribution circuit of the test circuit provided in the first aspect above, details are not repeated here.
  • each sub-test circuit may further include a controller.
  • the controller may include: a second signal interface for configuring the fifth selector of the data distribution circuit in each sub-test circuit, for controlling the first input end and the second output end of the data distribution circuit to be directly connected or Connected through registers; a plurality of third signal interfaces for configuring a plurality of second selectors in each sub-test circuit, for controlling the scan output channel of the circuit under test corresponding to the sub-test circuit and the sub-test circuit One of the data distribution circuits is connected; a plurality of fourth signal interfaces are used to configure a plurality of third selectors in each sub-test circuit, and are used to control the sub-test circuit to select one of the data distribution circuits corresponding to the sub-test circuit The scan input channel of the circuit under test is connected.
  • the bypass enable signal is output through the second signal interface of the controller to configure the fifth selector in the data distribution circuit, so that when the circuit under test does not participate in the test, the The data distribution circuit in the sub-test circuit corresponding to the circuit under test participating in the test is configured in a bypass state, even if the first input to the second output of the data distribution circuit do not pass through the internal register, thereby reducing the test time period.
  • the scan output selection signal is output through the third signal interface of the controller, the second selector is configured by the scan output selection signal, and the corresponding data distribution circuit is selected to receive the scan output data of the circuit under test.
  • the scan input selection signal is output through the fourth signal interface of the controller, the third selector is configured by the scan input selection signal, and the corresponding data distribution circuit is selected to transmit the test scan data to the scan input channel of the circuit under test.
  • the third selector scans the circuit under test corresponding to the jth sub-test circuit by the first gating circuit
  • the input channel is connected to control whether the data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the jth sub-test circuit.
  • the scan output channel of the circuit under test corresponding to the jth sub-test circuit is connected to the second selector through the second gate control circuit, and is used to control whether the data of the scan output channel of the circuit under test corresponding to the jth sub-test circuit is not. output to the data distribution circuit.
  • corresponding gate control circuits are provided between the scan input channel of the circuit under test and the data distribution circuit, as well as between the scan output channel of the circuit under test and the data distribution circuit, so that only when the corresponding Only when the gating circuit of the test circuit is turned on, data can be transmitted between the data distribution circuit and the scan input channel of the circuit under test, or between the scan output channel of the circuit under test and the data distribution circuit, thereby avoiding the transmission of invalid data.
  • each sub-test circuit may further include a state machine, and for the state machine, reference may be made to the state machine in the test circuit provided in the above-mentioned first aspect, and details are not repeated here.
  • test circuit includes: a plurality of sub-test circuits respectively corresponding to the plurality of circuits under test, and the sub-test circuits are used to connect the circuits under test to a test bus.
  • Each circuit under test corresponds to a sub-test circuit, and each sub-test circuit can transmit the data required for the test scan to the scan input channel of the corresponding circuit under test through the test bus, and transmit the test result data of the corresponding circuit under test to the scan input channel of the corresponding circuit under test. Transfer to the test bus output.
  • Each sub-test circuit can also dynamically assign the test bus to the corresponding circuit under test.
  • the jth sub-test circuit among the plurality of sub-test circuits includes Nj groups of data distribution circuits and CI j OR gates.
  • the CI j OR gates respectively correspond to the CI j groups of data distribution circuits in the Nj groups of data distribution circuits, and the CI j OR gates respectively correspond to the CI j scan input channels of the circuit under test.
  • the CO j groups of data distribution circuits in the Nj groups of data distribution circuits respectively correspond to the CO j scan output channels of the circuit under test.
  • the number of scan channels of the circuit under test is four, and the number of scan channels is the maximum of the number of scan input channels and the number of scan output channels.
  • the number of groups of data distribution circuits in the sub-test circuit corresponding to the circuit under test is four groups, and each group of data distribution circuits may correspond to one scan input channel and one scan output channel.
  • the number of OR gates in this sub-test circuit is the number of scan input channels, that is, three, so each OR gate also corresponds to a group of data distribution circuits and corresponds to one scan input channel of the circuit under test.
  • each group of data distribution circuits includes M data distribution circuits, and the M data distribution circuits are respectively connected to M-bit test buses.
  • Each group of data distribution circuits in the Nj groups of data distribution circuits is sequentially connected in series on the corresponding test bus through the first input terminal and the second output terminal of each data distribution circuit, that is, multiple data distribution circuits on the same test bus, according to They are connected to the same test bus through the first input terminal and the second output terminal in sequence.
  • the first output terminals of the M data distribution circuits in each group of data distribution circuits are connected to the corresponding M input terminals of the OR gate, and the output terminals of the OR gate are connected to the corresponding scan input channels of the circuit under test.
  • the second input ends of the M data distribution circuits in each group of data distribution circuits are connected to the scan output channels of the corresponding circuit under test.
  • Each data distribution circuit is also configured to control the reset of the data distribution circuit. When the data distribution circuit is reset, the output of the data distribution circuit is zero, which can be implemented in each group of data distribution circuits.
  • the output value of the OR gate is It is the value output by the first output terminal of the selected data distribution circuit, that is, the input value of the selected test bus.
  • the test circuit transmits the input data of the test vector, that is, the scan test data, to the data distribution circuit through the input of the test bus, and transmits it to the scan input channel of the circuit under test through the data distribution circuit.
  • the output data of the test vector of the output channel of the circuit under test that is, the test result data, is transmitted to the output of the test bus through the data distribution circuit to complete the test of the circuit under test.
  • the area overhead can be reduced as much as possible , as well as optimizing the routing congestion problem, thereby reducing the cost of test.
  • the output value of each OR gate can be the value output by the first output terminal of the selected data distribution circuit, thereby realizing correct test bus resource allocation, It further simplifies the configuration process and improves the test efficiency.
  • each data distribution circuit may include a fourth selector, a register and a fifth selector.
  • the internal structure of the data distribution circuit reference may be made to the internal structure of the data distribution circuit in the test circuit provided in the first aspect, which will not be repeated here. The difference is that the second control terminal of the data distribution circuit is also connected to the reset terminal of the register for controlling the reset of the register.
  • the bypass enable signal can be used to control the register in the data distribution circuit to perform bypass selection. Reset, the structure is simpler.
  • each sub-test circuit may further include a controller.
  • the controller may include: a second signal interface, the second signal interface is connected to the second control terminal of each data distribution circuit in the sub-test circuit, and is used to control the first input terminal and the second output terminal of the data distribution circuit to directly Connect or connect through registers, and control register reset.
  • the bypass enable signal is output through the second signal interface of the controller, which is used to configure the fifth selector in the data distribution circuit to distribute the unselected data in the sub-test circuit.
  • the circuit is set to bypass, and the register of the control data distribution circuit is reset, so as to meet the requirements of the scan input channel of the circuit under test to select the data distribution circuit, the configuration process is simple, and the test efficiency is further improved.
  • the OR gate is connected to the scan input channel of the circuit under test corresponding to the jth sub-test circuit through the first gating circuit , which is used to control whether the data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the jth sub-test circuit.
  • the scan output channel of the circuit under test corresponding to the jth sub-test circuit is connected to the data distribution circuit through the second gate control circuit, and is used to control whether the data of the scan output channel of the circuit under test corresponding to the jth sub-test circuit is output into the data distribution circuit.
  • corresponding gate control circuits are provided between the scan input channel of the circuit under test and the data distribution circuit, as well as between the scan output channel of the circuit under test and the data distribution circuit, so that only when the corresponding Only when the gating circuit of the test circuit is turned on, data can be transmitted between the data distribution circuit and the scan input channel of the circuit under test, or between the scan output channel of the circuit under test and the data distribution circuit, thereby avoiding the transmission of invalid data.
  • each sub-test circuit may further include a state machine, and for the state machine, reference may be made to the state machine in the test circuit provided in the above-mentioned first aspect, and details are not repeated here.
  • test circuit includes: a plurality of sub-test circuits respectively corresponding to the plurality of circuits under test, and the plurality of sub-test circuits are used to respectively connect the corresponding circuits under test to the test bus.
  • Each circuit under test corresponds to a sub-test circuit, and each sub-test circuit can transmit the data required for the test scan to the scan input channel of the corresponding circuit under test through the test bus, and transmit the test result data of the corresponding circuit under test to the scan input channel of the corresponding circuit under test. Transfer to the test bus output.
  • Each sub-test circuit can also dynamically assign the test bus to the corresponding circuit under test.
  • the jth sub-test circuit among the plurality of sub-test circuits includes Nj data distribution circuits and M first selectors.
  • the jth sub-test circuit can be any sub-test circuit among multiple sub-test circuits, and the number Nj of data distribution circuits in the j-th sub-test circuit is the number of scan channels of the corresponding circuit under test, that is, the corresponding test circuit.
  • the maximum value among the number of scan input channels CI j and the number of scan output channels CO j of the circuit, ie Nj max(CI j , CO j ).
  • the data distribution circuit is used to receive the scan test data of the test bus and transmit it to the scan input channel of the circuit under test, and receive the test result data of the scan output channel of the circuit under test, and transmit it to the test bus output.
  • the first selector may be a selector for selecting one from two, and is used to select the test bus used by the j+1th sub-test circuit.
  • the first input ends of the Nj data distribution circuits are respectively connected to the Nj inputs of the test bus, that is, the first input end of the data distribution circuit is used to receive the test scan data of the test bus;
  • the first output terminals of the CI j data distribution circuits in the circuit are respectively connected to the CI j scan input channels of the circuit under test corresponding to the jth sub-test circuit, that is, the first input terminal of the data distribution circuit is used to send data from the test bus.
  • the received test scan data is transmitted to the scan input channel of the corresponding circuit under test; the second input terminals of the CO j data distribution circuits in the Nj data distribution circuits are respectively connected to the circuit under test corresponding to the jth sub-test circuit
  • the CO j scan output channels that is, the second input end of the data distribution circuit is used to receive the test result data output by the scan output channel of the corresponding circuit under test, and the test result data is output to the test through the second output end of the data distribution circuit. bus.
  • the number M of first selectors of each sub-test circuit in the plurality of sub-test circuits is equal to the bit width of the test bus, and the output ends of the M first selectors in each sub-test circuit are respectively connected to the M outputs of the test bus, and the The M first selectors in each sub-test circuit are in one-to-one correspondence with the M bits of the test bus. Wherein, the first input ends of the M first selectors are respectively connected to the M inputs of the test bus.
  • the second input ends of Nj first selectors among the M first selectors are respectively connected to the second output ends of the Nj data distribution circuits, and the second input ends of the remaining M-Nj first selectors are respectively connected to M - Inputs of Nj test buses not provided with data distribution circuits.
  • the busses to which the first input terminal and the second output terminal of each first selector are connected are different.
  • the test bus connected to the first input terminal and the second input terminal of the first selector is different, and the test bus used by the j+1th sub-test circuit can be selected by the first selector.
  • the test circuit transmits the input data of the test vector to the data distribution circuit through the input of the test bus, and transmits it to the scanning input channel of the circuit under test through the data distribution circuit.
  • the output data of the test vector of the scan output channel of the circuit under test is transmitted to the output of the test bus through the data distribution circuit to complete the test of the circuit under test, and the dynamic correspondence between the data distribution circuit and the test bus is realized by configuring the first selector. , so that test resources can be dynamically allocated.
  • the test bus allocated in the j+1th sub-test circuit is the test bus bus A.
  • the test bus allocated in the j+1th sub-test circuit for B is the test bus allocated in the j+1th sub-test circuit for B.
  • the data distribution circuit in the j+1th sub-test circuit will correspond to a group of first selectors in the jth sub-test circuit, which is denoted as the first selector X, so the test bus A is configured for the first selector X In order to select the test bus connected to the first selector X when the first input end of the first selector is connected to the output end; the test bus B is the second input end of the first selector X that is configured to select the first selector When connected to the output terminal, the test bus to which the first selector X is connected.
  • the test circuit provided by the fourth aspect can greatly optimize the problem of routing congestion, so as to reduce the test cost, simplify the configuration process, and improve the test efficiency.
  • the first input end of the first selector is directly connected to the input of the test bus, so that when the circuit under test corresponding to the jth sub-test circuit does not participate in the test, the j+1th sub-test circuit The input data of the test circuit does not pass through the data distribution circuit in the jth sub-test circuit, thereby reducing the test time.
  • the first input terminals of the Nj data distribution circuits are sequentially connected to the inputs of the first Nj buses. .
  • the first input terminals of the M first selectors are sequentially connected to the M inputs of the test bus.
  • the second input terminals of the first M-Nj first selectors are sequentially connected to the last M-Nj inputs of the test bus.
  • the second input terminals of the last Nj first selectors are sequentially connected to the second output terminals of the Nj data distribution circuits.
  • the data distribution circuit is allocated to the bus resources in a preset order according to the established rules, so that the test circuit can make the circuit design simpler under the condition of ensuring the dynamic allocation of the test resources. Easy wiring.
  • the preset bus sequence is the sequence or reverse sequence of the number of bus bits.
  • the preset test bus sequence is a specific sequence, such as the test bus sequence or the reverse sequence, in this way, the circuit structure of the test circuit can be further simplified and effective, so that to a certain extent Simplify the structure of the test circuit in order to quickly realize the wiring requirements of the test circuit.
  • each data distribution circuit may include a fourth selector and a register.
  • the first input end and the second input end of the fourth selector are respectively connected to the first input end and the second input end of the data distribution circuit, and the control end of the fourth selector is connected to the first control end of the data distribution circuit.
  • the input end of the register is connected to the output end of the fourth selector, and the output end of the register is connected to the second output end of the data distribution circuit.
  • the first output terminal of the data distribution circuit is connected to the first input terminal of the data distribution circuit or the output terminal of the register.
  • the data distribution circuit has two inputs, respectively receiving test scan data from the test bus and receiving test output data from the corresponding scan output channel of the circuit under test;
  • the configuration of the device realizes the selection of the input, so that the test scan data and the test output data are transmitted in different time periods respectively, and in the case of a simpler circuit structure, data transmission conflicts can be avoided.
  • each sub-test circuit may further include a controller, and the controller may include a first signal interface, the first signal interface and the control of the M first selectors in the sub-test circuit
  • the terminal is connected to control the first input terminal in the first selector to communicate with the output terminal or the second input terminal in the first selector to communicate with the output terminal.
  • the shift selection control signal is output through the first signal interface of the controller to configure the first selector, and the configuration is simple and easy.
  • the first selector When the first selector is configured such that the first input terminal and the output terminal of the first selector are connected, all the test bus resources in the sub-test circuit corresponding to the first selector will not pass through the data distribution circuit, Therefore, when the circuit under test corresponding to the sub-test circuit does not participate in the test, configuring the first selector so that the first input end and the output end of the first selector are connected to each other can reduce the test time.
  • the data distribution circuit passes through the scan input channel of the circuit under test corresponding to the jth sub-test circuit by the first gating circuit
  • the connection is used to control whether the data in the data distribution circuit is output to the scan input channel of the circuit under test corresponding to the jth sub-test circuit.
  • the data distribution circuit is connected between the second gate control circuit and the scan output channel of the circuit under test corresponding to the jth sub-test circuit, and is used to control the data of the scan output channel of the circuit under test corresponding to the jth sub-test circuit Whether to output to the data distribution circuit.
  • corresponding gate control circuits are provided between the scan input channel of the circuit under test and the data distribution circuit, as well as between the scan output channel of the circuit under test and the data distribution circuit, so that only when the corresponding Only when the gating circuit of the test circuit is turned on, data can be transmitted between the data distribution circuit and the scan input channel of the circuit under test, or between the scan output channel of the circuit under test and the data distribution circuit, thereby avoiding the transmission of invalid data.
  • each sub-test circuit may further include a state machine.
  • state machine reference may be made to the state machine in the test circuit provided in the above-mentioned first aspect, which will not be repeated here.
  • each sub-test circuit in the above-mentioned first aspect to the fourth aspect may further include a frequency dividing circuit, and the frequency dividing circuit is respectively connected to the bus clock interface and the scan clock interface of the circuit under test, and is used for dividing the clock of the test bus.
  • the frequency division is the scan clock of the circuit under test.
  • the high-speed scan clock of the test bus is divided into a low-speed scan clock in the circuit under test, so as to facilitate the scan test of the circuit under test.
  • an integrated circuit in a fifth aspect, includes: a plurality of circuits under test, a test bus, and any possible test circuit according to any one of the first to fourth aspects above.
  • a plurality of tested circuits are connected to the test bus through a plurality of sub-test circuits in the test circuit corresponding to the tested circuits.
  • an electronic device in a sixth aspect, includes a printed circuit board and the integrated circuit provided in the fifth aspect above; the integrated circuit is arranged on the printed circuit board.
  • a method for designing a test circuit includes: acquiring the number of scan-in channels, the number of scan-out channels of each circuit under test, and the bus bit width of the test bus. According to the bus bit width of the test bus, and the number of scan input channels and scan output channels of each circuit under test, configure the data distribution circuit in the sub-test circuit corresponding to each circuit under test on the test bus to generate the above Any one of the possible test circuits of the one aspect to the fourth aspect.
  • the number of data distribution circuits in the sub-test circuit corresponding to each circuit under test is determined by the bus bit width of the test bus, or the number of scan input channels and scan output channels of each circuit under test.
  • a circuit testing method is provided.
  • the circuit testing method can be used in EDA software, and is suitable for testing a circuit under test using a test circuit, wherein the test circuit is any one of the possible test circuits in the first aspect to the fourth aspect above.
  • the circuit testing method includes: generating configuration information and a test vector; wherein, the configuration information is used to configure the test circuit; the test vector is test excitation data of the circuit under test and is determined by the circuit structure of the circuit under test.
  • the circuit testing method may further include: configuring the testing circuit according to the configuration information.
  • the test vector is transmitted to the test bus, and is transmitted to the scan input channel of the circuit under test through the test circuit.
  • the test result data of the circuit under test is transmitted to the output of the test bus through the circuit under test.
  • the shift selection control signal can be configured through the first signal interface of the controller to control the connection relationship between the input and output selected by the first selector.
  • the first selector in the sub-test circuit corresponding to the circuit under test is placed in the direct connection mode, that is, the first selector is configured so that the first input end is connected to the output end.
  • the bypass enable signal can be configured through the second signal interface of the controller, so that the data distribution circuit in the sub-test circuit corresponding to the circuit under test that does not participate in the test is placed in the bypass state, that is, the first data distribution circuit in the corresponding data distribution circuit. There is no register between an input terminal and a second output terminal.
  • the scan-out selection signal and the scan-in selection signal may be configured by the controller.
  • the scan output selection signal is output by the third signal interface and is used to configure the second selector so that the scan output channel of the circuit under test corresponding to the sub-test circuit is connected to a data distribution circuit in the sub-test circuit.
  • the scan-in selection signal is output by the fourth signal interface, and is used to configure the third selector, so that the sub-test circuit selects one of the data distribution circuits and communicates with the scan-in channel of the circuit under test corresponding to the sub-test circuit.
  • the bypass enable signal can be configured through the second signal interface of the controller, and the bypass enable signal can be used as the reset signal of the data distribution circuit.
  • the data distribution circuit is reset, it means The data distribution circuit is not selected, so the value output by the first output terminal of the selected data distribution circuit is the input value of the selected test bus, thereby realizing the integration of the test bus, the data distribution circuit and the scanning channel of the circuit under test. One-to-one correspondence between them.
  • the shift selection control signal can be configured through the first signal interface of the controller to control the connection relationship between the input and output selected by the first selector.
  • the first selector in the sub-test circuit corresponding to the circuit under test is placed in the direct connection mode, that is, the first selector is configured so that the first input end is connected to the output end.
  • the output capture enable signal is also configured through the first state control interface of the state machine, and the first gating enable signal is configured through the second state control interface of the state machine , the second gating enable signal is configured through the third state control interface of the state machine, and the scan enable signal is configured through the fourth state control interface of the state machine.
  • the functions of outputting the capture enable signal, the first gating enable signal, the second gating enable signal, and the scan enable signal please refer to the description of the state machine in the first aspect, which will not be repeated here.
  • transmitting the test vector to the scan input channel of the circuit under test through the test circuit includes: according to the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus, by The input of the test bus corresponding to the scan input channel of the circuit under test transmits the test vector to the scan input channel of the circuit under test.
  • the correspondence between the scan input channel of the circuit under test and the input of the test bus is determined by the data distribution circuit in the sub-test circuit corresponding to the circuit under test.
  • the scan input channels of the circuit under test and the data distribution circuits in the corresponding sub-test circuits belong to a one-to-one correspondence.
  • the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus is actually the actual connection relationship between the data distribution circuit in the sub-test circuit corresponding to the circuit under test and the test bus.
  • the scan input channel of the circuit under test and the data distribution circuit in the sub-test circuit corresponding to the circuit under test belong to a one-to-many relationship. Therefore, the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus can be configured by the scan input selection signal configured by the controller. After configuration, the test bus connected to the data distribution circuit selected by the scan input channel of the circuit under test, That is, the scan input channel corresponding to the circuit under test.
  • the scan input channel of the circuit under test and the data distribution circuit in the sub-test circuit corresponding to the circuit under test belong to a one-to-many relationship. Therefore, the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus can be controlled by the bypass enable signal, which can control the data distribution circuit to reset.
  • the data distribution circuit is not reset, then The data distribution circuit is selected by the scan input channel of the corresponding circuit under test. That is, the correspondence between the scan input channel of the circuit under test and the input of the test bus is determined by the data distribution circuit that is not reset.
  • transmitting the test result data of the circuit under test to the output of the test bus through the circuit under test includes: according to the corresponding relationship between the scan output channel of the circuit under test and the output of the test bus , the test result data output by the scan output channel of the circuit under test is transmitted to the output of the test bus corresponding to the scan output channel of the circuit under test; wherein, the corresponding relationship between the scan output channel of the circuit under test and the output of the test bus, Determined by the data distribution circuit in the sub-test circuit corresponding to the circuit under test.
  • the method for determining the correspondence between the scan output channel of the circuit under test and the output of the test bus is similar to the above method for determining the correspondence between the scan input channel of the circuit under test and the input of the test bus, and will not be repeated here.
  • the test vector is transmitted to the scan input channel of the circuit under test through the input of the test bus corresponding to the scan input channel of the circuit under test, Including: the test bus sequentially transmits the test vector to the scan input channel of the circuit under test in multiple bus clock cycles; wherein, the number of scan input channels of the circuit under test corresponding to one of the inputs of the test bus exceeds one .
  • test bus when testing the circuit under test, there may be multiple circuits under test that are tested at the same time.
  • bit width of the test bus is limited, so the test bus will be multiplexed, that is, the test bus will transmit data to the scan input channels of multiple circuits under test by means of timing splitting. In one bus clock cycle, the test bus can only transmit data to one scan-in channel, so if one of the inputs of the test bus needs to transmit data to multiple scan-in channels, it will be split and transmitted sequentially in multiple bus clock cycles.
  • the test result data output by the scan output channel of the circuit under test is transmitted to the output of the test bus corresponding to the scan output channel of the circuit under test.
  • the test bus sequentially transmits the test result data in the scan output channel of the circuit under test to the output of the test bus in multiple clock cycles, wherein one of the outputs of the test bus corresponds to the circuit under test The number of scan output channels exceeds one.
  • the test result data is transmitted to the test bus, and similarly the scan test data, that is, the test vector, is transmitted to the scan input channel of the circuit under test, which will not be repeated here.
  • a computer-readable storage medium includes a program or an instruction, when the program or instruction is executed on a computer, the computer can execute any one of the possible circuit testing methods in the eighth aspect.
  • a tenth aspect provides a computer program product, the computer program product comprising: computer program code, when the computer program code is run on a computer, the computer program code enables the computer to execute any one of the possible circuit testing methods in the eighth aspect.
  • any of the above-mentioned integrated circuits, electronic devices, test circuit design methods, circuit test methods, computer-readable storage media and computer program products, etc. can be obtained from the corresponding test circuits provided above. It is implemented or associated with the corresponding test circuit provided above. Therefore, the beneficial effects that can be achieved can be referred to the beneficial effects in the test circuit provided above, which will not be repeated here.
  • FIG. 1 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application.
  • Fig. 2 is the structural schematic diagram 1 of the circuit under test, the test bus and the test circuit in Fig. 1;
  • FIG. 3 is a schematic structural diagram of a data distribution circuit in a test circuit provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a gate control circuit in a test circuit provided by an embodiment of the present application.
  • Fig. 5 is the structural schematic diagram 2 of the circuit under test, the test bus and the test circuit in Fig. 1;
  • Fig. 6 is the structural schematic diagram three of the circuit under test, the test bus and the test circuit in Fig. 1;
  • FIG. 7 is a schematic diagram 4 of the structure of the circuit under test, the test bus and the test circuit in FIG. 1;
  • FIG. 8 is a schematic structural diagram of the data distribution circuit in FIG. 7;
  • Fig. 9 is the structural schematic diagram five of the circuit under test, the test bus and the test circuit in Fig. 1;
  • FIG. 10 is a schematic structural diagram of the data distribution circuit in FIG. 9;
  • FIG. 11 is a flowchart of a circuit testing method provided by an embodiment of the application.
  • Fig. 12 is the structural representation of a kind of test scheme corresponding to Fig. 2;
  • FIG. 13 is a schematic structural diagram of another test scheme corresponding to FIG. 2;
  • FIG. 14 is a schematic waveform diagram of the scanning process of the test scheme corresponding to FIG. 13;
  • FIG. 15 is a flowchart of a test circuit design method provided by an embodiment of the present application.
  • first”, second, etc. are only used for descriptive purposes, and should not be understood as indicating or implying relative importance or implying the number of indicated technical features.
  • a feature defined as “first”, “second”, etc. may expressly or implicitly include one or more of that feature.
  • connection should be understood in a broad sense.
  • connection may refer to a physical direct connection or an electrical connection through an intermediate medium, such as through Connections made by resistors, inductors, capacitors, or other electronic devices.
  • test circuit 03 (as shown in FIG. 1 ).
  • the test circuit 03 is used to test a plurality of functional modules of the integrated circuit, so that the integrated circuit can complete a predetermined function.
  • Different integrated circuits can achieve different functions, so their functional modules are also different.
  • a mobile phone chip includes a processor module, a touch screen control module, a storage module, and a power management module.
  • FIG. 1 is a schematic structural diagram of an integrated circuit provided by an embodiment of the present application. Please refer to FIG. 1 .
  • the integrated circuit includes a plurality of circuits under test 01 , a test bus 02 and a test circuit 03 . Among them, different circuits under test in each integrated circuit can realize the same function or completely different functions.
  • the test circuit 03 includes a plurality of sub-test circuits 30 corresponding to the plurality of tested circuits 01 , that is, each of the tested circuits 01 corresponds to one sub-test circuit 30 .
  • the multiple circuits under test 01 are connected to the test bus 02 through multiple sub-test circuits 30 , so that the integrated circuit can perform functional tests on the multiple circuits under test 01 according to the planned test rules.
  • the embodiment of the present application also provides an electronic device.
  • the electronic device includes a printed circuit board and the integrated circuit provided in the above embodiment, wherein the integrated circuit provided in the above embodiment is arranged on the printed circuit board.
  • the electronic devices include mobile phones (mobile phones), tablet computers (pads), computers, smart wearable products (eg, smart watches, smart bracelets), virtual reality (virtual reality, VR) terminal devices, augmented reality (augmented reality, AR) ) electronic products such as terminal equipment.
  • the embodiments of the present application do not specifically limit the specific form of the above electronic device.
  • test circuit 03 provided by some embodiments of the present application will be described in detail below with reference to the accompanying drawings.
  • Fig. 2 is a schematic diagram of the structure of the circuit under test, the test bus and the test circuit in Fig. 1;
  • Fig. 5 is a schematic diagram of the structure of the circuit under test, the test bus and the test circuit in Fig. 1;
  • Fig. 6 is the circuit under test in Fig. 1, Schematic diagram three of the structure of the test bus and test circuit;
  • Figure 7 is a schematic diagram of the structure of the circuit under test, test bus and test circuit four in Figure 1;
  • Figure 9 is a schematic diagram of the structure of the circuit under test, the test bus and the test circuit five in Figure 1. Please refer to Fig. 2, Fig. 5, Fig. 6, Fig. 7 and Fig. 9, in conjunction with Fig.
  • an integrated circuit may include multiple functional modules that implement different functions or the same function, and all functional modules need to pass the test
  • the circuit tests it in order to know whether the function of the functional module can be performed normally, and the functional module at this time can be referred to as the circuit under test 01 in the process of testing. Therefore, a test circuit in this embodiment of the present application may include: a plurality of sub-test circuits 30 as shown in FIG. 1 corresponding to a plurality of circuits under test 01 respectively, and a plurality of sub-test circuits 30 as shown in FIG. 1 .
  • test bus 02 Used to connect the corresponding circuit under test 01 to the test bus 02, wherein the test bus 02 corresponds to the scanbus in Figure 2, Figure 5, Figure 6, Figure 7 and Figure 9, where scanbus_in is the input channel of the test bus 02 , scanbus_out is the output channel of test bus 02.
  • each sub-test circuit 30 shown in FIG. 1 is used to connect the corresponding circuit under test 01 to the test bus, wherein each sub-test circuit 30 shown in FIG. 1 may include multiple
  • the number of data distribution circuits 301 in each sub-test circuit 30 shown in FIG. 1 is related to the number of scan channels in the circuit under test 01 corresponding to the sub-test circuit. For example, in the example shown in FIG. 2 , the number of data distribution circuits 301 in each sub-test circuit 30 shown in FIG. 1 is equal to the number of scan channels in the corresponding circuit under test 01 , and the number of scan channels in the circuit under test 01 is equal.
  • each sub-test circuit 30 shown in FIG. 1 can connect the circuit under test 01 to the test bus through a plurality of data distribution circuits 301 .
  • the data distribution circuit 301 which may also be called a dynamic routing unit (DRU), has two input terminals and two output terminals in the data distribution circuit 301.
  • the input terminal is connected to the input channel scanbus_in of the test bus 02
  • the second input terminal is connected to the scan output channel channel_out of the circuit under test 01
  • the first output terminal is connected to the scan input channel channel_in of the circuit under test 01
  • the second output terminal is connected to the test bus 02.
  • Output channel scanbus_out is also be called a dynamic routing unit
  • the data distribution circuit 301 receives the data of the input channel scanbus_in of the test bus 02 , and the data input in the input channel scanbus_in of the test bus 02 is the test vector required by the circuit under test 01 .
  • the data distribution circuit 301 transmits the received data in the input channel scanbus_in of the test bus 02 to the scan structure (scanstucture) of the circuit under test 01 through the scan input channel channel_in of the circuit under test 01 .
  • the scan structure of the circuit under test 01 is a structural block in the circuit under test 01 used to perform a scan test on the circuit under test 01 , and the scan input channel and scan output channel of the circuit under test 01 are both connected to the circuit under test 01 On the scan structure of the scan structure, when the scan structure receives the input data of the scan input channel channel_in, it will perform a scan test on the circuit under test. After the test is completed, the test result data is output through the scan output channel channel_out on the scan structure.
  • the data distribution circuit 301 When the scan structure of the circuit under test 01 completes the scan test, the data distribution circuit 301 outputs the test result data from the scan output channel channel_out of the circuit under test 01, and transmits the test result data to the output channel scanbus_out of the test bus 02, and transmits it to Compare with the expected test result data in the test software, or directly compare with the expected test result data in the test machine, to judge whether there is a fault in the circuit under test 01, wherein the test software is EDA software.
  • the role of the data distribution circuit 301 is to distribute and transmit the test data.
  • the data distribution circuit 301 is used to receive the input data of the input channel scanbus_in of the test bus and transmit it to the scan input channel channel_in of the circuit under test 01 .
  • the data distribution circuit 301 receives the test result data of the scan output channel channel_out of the circuit under test 01, and transmits it to the output channel scanbus_out of the test bus 02 for output to complete the test.
  • the corresponding relationship between the data distribution circuit 301 and the test bus 02 can be dynamically distributed.
  • a data distribution circuit can be connected to multiple inputs or outputs of the test bus, and the data distribution circuit 301 and the test bus can be dynamically configured in the form of a multiplexer.
  • the actual connection relationship of multiple inputs or outputs of 02 is used to achieve the purpose of dynamic connection between the data distribution circuit 301 and the test bus 02.
  • the test bus 02 is dynamically allocated to meet the requirements of testing a larger number of tested circuits 01, thereby optimizing the line connection, reducing line congestion, and Reduce area overhead.
  • Example 1 please refer to FIG. 2.
  • the j-th sub-test circuit includes Nj data distribution circuits 301 and M first selection circuits.
  • the first selector 302 referring to the shift selector SHIFT_MUX in FIG.
  • the connection relationship between the first selector 302 and the test bus 02 can be set according to the following relationship: the first input of the first Nj first selectors 302 The terminals are sequentially connected to the second output terminals of the Nj data distribution circuits 301; the first input terminals of the last M-Nj first selectors 302 are sequentially connected to the last M-Nj input channels scanbus_in of the test bus 02, that is, in the jth sub
  • the first selector is configured such that when the first input end of the first selector is connected to the output end, the output and the input of the first selector correspond to the same test bus, that is, the direct connection mode.
  • the second input terminals of the first M-Nj first selectors 302 are sequentially connected to the last M-Nj input channels scanbus_in of the test bus; the second input terminals of the last Nj first selectors 302 are sequentially connected to the Nj data distribution circuits 301
  • the second output terminal of , that is, in the jth sub-test circuit, the first selector is configured so that when the second input terminal of the first selector is connected to the output terminal, the output of the first selection is different from the test bus corresponding to the input , that is, the shift connection mode.
  • the preset test bus sequence may be the sequence or reverse sequence of the test bus sequence. It can also be any other preset or specified bus sequence, which is not limited here.
  • the preset test bus sequence is [0][2][4][6][1][3][5][ 7], [0] is the [0]th bit (bit) of the test bus 02, namely scanbus_in[0] and scanbus_out[0].
  • connection relationship between the first selector 302 and the test bus and the data distribution circuit 301 is connected according to the order of the test bus sequence.
  • circuits under test 01 are exemplarily drawn as circuit A (core_A) under test, circuit B under test (core_B) and circuit C under test (core_C); three circuits as shown in FIG. 1
  • the sub-test circuits 30 are respectively a first sub-test circuit corresponding to the circuit A under test, a second sub-test circuit corresponding to the circuit B under test, and a third sub-test circuit corresponding to the circuit B under test.
  • circuit B under test and circuit C under test are set in the tested circuit A, the tested circuit B, and the tested circuit C respectively.
  • circuit B under test and circuit C under test may not include the corresponding sub-test circuits, that is, circuit under test A, circuit under test.
  • the sub-test circuits corresponding to the circuit B and the circuit C under test are only arranged inside the circuit A under test, the circuit B under test, and the circuit C under test in the circuit positional relationship.
  • the sub-test circuits corresponding to the tested circuit A, the tested circuit B and the tested circuit C can be set outside the tested circuit A, the tested circuit B and the tested circuit C, for example, as shown in Figure 5 circuit structure.
  • the sub-test circuit 30 shown in FIG. 1 is disposed inside or outside the circuit under test 01 , it has no effect on the test circuit and the circuit operation of the circuit under test 01 . Therefore, this embodiment does not limit whether the test circuit 03 shown in FIG. 1 and the sub-test circuit 30 shown in FIG. 1 are arranged inside the circuit under test 01 .
  • the scan structure of the circuit A under test has three scan input channels channel_in, respectively channel_in[0], channel_in[1], channel_in[2]; three scan output channels channel_out, respectively channel_out[0 ], channel_out[1], channel_out[2] (please refer to channel_in/out in the scanning structure A in FIG. 2, the detailed correspondence is not shown in FIG. 2).
  • the scan structure of circuit B under test has five scan input channels channel_in, namely channel_in[0], channel_in[1], channel_in[2], channel_in[3], channel_in[4]; and five scan output channels channel_out , respectively channel_out[0], channel_out[1], channel_out[2], channel_out[3], channel_out[4] (not shown in FIG. 2).
  • the scan structure of the circuit C under test has four scan input channels channel_in, respectively channel_in[0], channel_in[1], channel_in[2], channel_in[3]; and four scan output channels channel_out, respectively channel_out [0], channel_out[1], channel_out[2], channel_out[3] (not shown in Figure 2).
  • the first sub-test circuit corresponding to circuit A under test has three data distribution circuits 301
  • the second sub-test circuit corresponding to circuit B under test has five data distribution circuits 301
  • the third sub-test circuit corresponding to circuit C under test has five data distribution circuits 301.
  • the test circuit has four data distribution circuits 301 .
  • the bit width of the test bus in FIG. 2 is eight bits, and the first input terminals of the three data distribution circuits 301 in the first sub-test circuit are respectively connected to the first three bits of the test bus, that is, scanbus_in[ 0], scanbus_in[1], scanbus_in[2]; and so on, the first input terminals of the five data distribution circuits 301 in the second sub-test circuit are respectively connected to the first five bits of the test bus, that is, scanbus_in[0 ], scanbus_in[1], scanbus_in[2], scanbus_in[3], scanbus_in[4]; the first input terminals of the four data distribution circuits 301 of the third sub-test circuit are respectively connected to the first four bits of the test bus , that is, on scanbus_in[0], scanbus_in[1], scanbus_in[2], and scanbus_in[3].
  • the number of the first selectors 302 corresponding to each sub-test circuit is equal to the bit width of the test bus, that is, the number of the first selectors 302 of each sub-test circuit is eight.
  • the first input ends of the first three first selectors 302 are connected to the second output ends of the three data distribution circuits 301, and the last five first selectors
  • the first input terminal of 302 is connected to the input scanbus_in of the last five bits of the test bus, namely scanbus_in[3], scanbus_in[4], scanbus_in[5], scanbus_in[6], scanbus_in[7] connected to the test bus.
  • the second input terminals of the first five first selectors 302 are connected to the input scanbus_in of the last five test buses, namely scanbus_in[3], scanbus_in[4], scanbus_in[5], scanbus_in[6], scanbus_in[ of the test bus. 7], the second input terminals of the last three first selectors 302 are connected to the second input terminals of the three data distribution circuits 301 .
  • the first input terminals of the first five first selectors 302 are connected to the second output terminals of the five data distribution circuits 301, and the last three first selection
  • the first input terminal of the device 302 is connected to the input scanbus_in of the last three test buses, namely scanbus_in[5], scanbus_in[6], scanbus_in[7] of the test bus.
  • the second input terminals of the first three first selectors 302 are connected to the input scanbus_in of the last three test buses, namely scanbus_in[5], scanbus_in[6], scanbus_in[7] of the test bus, and the last five first selectors
  • the second input terminals of 302 are connected to the second input terminals of the five data distribution circuits 301 .
  • the first input terminals of the first four first selectors 302 are connected to the second output terminals of the four data distribution circuits 301, and the second output terminals of the last four first selectors 302 are connected to An input terminal is connected to the input scanbus_in of the back four test bus, namely scanbus_in[4], scanbus_in[5], scanbus_in[6], scanbus_in[7] of the connection bus.
  • the second input terminals of the first four first selectors 302 are connected to the input scanbus_in of the last four-bit test bus, namely scanbus_in[4], scanbus_in[5], scanbus_in[6], scanbus_in[7] of the test bus, and the last four The second input terminals of the first selectors 302 are connected to the second input terminals of the four data distribution circuits 301 .
  • the shift selection control is received through the control terminal of the first selector 302 Signal bus_shift to control.
  • the shift selection control signal bus_shift is configured and generated by the controller 303, that is, corresponding to the first signal interface of the controller 303, and the controller 303 can be configured by the IEEE 1687 standard (Internal JTAG, IJTAG) protocol pins.
  • the shift selection control signal bus_shift instructs the first selector 302 to select the first input terminal to be connected to the output terminal
  • the input scanbus_in and output scanbus_out of the test bus in the sub-test circuit are in a direct connection mode, such as scanbus_in of the test bus [0] corresponds to scanbus_out[0] of the test bus, and so on.
  • the shift selection control signal bus_shift instructs the first selector 302 to select the second input terminal to connect with the output terminal
  • the input scanbus_in and output scanbus_out of the test bus in the sub-test circuit are in the shift connection mode, which corresponds to FIG. 2
  • scanbus_in[0] of the test bus corresponds to scanbus_out[5] of the test bus
  • scanbus_in[3] of the test bus corresponds to scanbus_in[0] of the test bus, so that By analogy, I will not repeat them.
  • the shift selection control signal bus_shift in the sub-test circuit corresponding to the circuit B under test is controlled to instruct the first selector 302 to select the first input
  • the terminal is connected to the output terminal, that is, the direct connection mode.
  • the input channels of the test bus used by the circuit A under test are scanbus_in[0], scanbus_in[1], scanbus_in[2] of the test bus 02, and the output channels are scanbus_out[1], scanbus_out[2], scanbus_out[3], the input channel of the test bus occupied by the circuit B under test is scanbus_in[3], scanbus_in[4], scanbus_in[5], scanbus_in[6] of test bus 02, and the output channel is scanbus_out of test bus 02 [4], scanbus_out[5], scanbus_out[6], scanbus_out[7].
  • FIG. 3 shows a schematic structural diagram of a data distribution circuit 301 in a test circuit provided in this embodiment, which is applicable to the first example shown in FIG. 2 .
  • each data distribution circuit 301 includes a fourth option 3011, a register 3012 and a fifth selector 3013.
  • the fourth selector 3011 is used to implement the data distribution circuit 301 to select whether to receive data from the test bus 02 or to receive data from the scan output channel channel_out of the corresponding circuit under test 01 . That is, the first input terminal and the second input terminal of the fourth selector 3011 are respectively connected to the first input terminal and the second input terminal of the data distribution circuit 301 .
  • the control terminal of the fourth selector 3011 is connected to the first control terminal of the data distribution circuit 301, and is used to control the selection of input bus data to the data distribution circuit 301, or to select and input the scan output data of the corresponding circuit under test 01 to the data distribution circuit 301 .
  • the register 3012 is used to temporarily store the data received by the data distribution circuit 301, so the input end of the register 3012 is connected to the output end of the fourth selector 3011, and the output end of the register 3012 is connected to the first input end of the fifth selector 3013.
  • the fifth selector 3012 is used to realize the configuration of whether the input data of the test bus 02 passes through the register 3012, that is, the second input end of the fifth selector 3013 is connected to the first input end of the data distribution circuit 301, and the The output terminal is connected to the second output terminal of the data distribution circuit 301 , and the control terminal of the fifth selector 3013 is connected to the second control terminal of the data distribution circuit 301 .
  • the first output terminal of the data distribution circuit 301 is connected to the first input terminal of the data distribution circuit 301 or the output terminal of the register 3012 or the second output terminal of the data distribution circuit 301 .
  • a fifth selector 3013 is provided in the above-mentioned data distribution circuit 301 .
  • the fifth selector 3013 is a selector for selecting one of two, and the bypass enable signal dru_bp is generated through the configuration of the controller 303, that is, corresponding to the second signal interface of the controller 303, and controls the first signal of the fifth selector 3013.
  • the input terminal is connected to its output terminal, or the second input terminal that controls the fifth selector 3013 is connected to its output terminal.
  • the bypass enable signal dru_bp instructs the fifth selector 3013 to select the first input terminal to connect its output terminal
  • the data distribution circuit 301 is in the bypass state, that is, the first input terminal and the second output terminal of the data distribution circuit 301 are directly connected. Therefore, when a circuit under test 01 does not participate in the test, all the data distribution circuits 301 in the sub-test circuit corresponding to the circuit under test 01 are set to the bypass state, and no extra data is occupied during the data transmission process. time period, thereby reducing test time.
  • Example 2 please refer to FIG. 6.
  • the j-th sub-test circuit in the plurality of sub-test circuits 30 shown in FIG. 1 includes M data distribution circuits 301, M second selection circuits 308 and CI j third selectors 309, wherein the jth sub-test circuit can be any one of the multiple sub-test circuits.
  • the second selector 308 please refer to the scan output selector SO_MUX in FIG.
  • the three selectors 309 please refer to the scan input selector SI_MUX in FIG. 6 .
  • the number of data distribution circuits 301 and the number M of second selectors 308 in the j-th sub-test circuit are both equal to the bit width of the test bus, and the number CI j of the third selectors 309 in the j-th sub-test circuit is the same as the j-th sub-test
  • the number of scan input channels channel_in corresponding to the circuit under test 01 is equal.
  • the first input terminals of the M data distribution circuits 301 are respectively connected to the M input channels scanbus_in of the test bus 02, that is, the first input terminals of the data distribution circuits 301 are used to receive the test scan data of the test bus 02, and the M data distribution circuits 301
  • the second output ends of the test bus are respectively connected to the M output channels scanbus_out of the test bus.
  • the CO j input terminals of each of the M second selectors 308 are respectively connected to the CO j scans of the circuit under test 01 corresponding to the jth sub-test circuit Output channel channel_out; the output ends of the M second selectors 308 are respectively connected to the second input ends of the M data distribution circuits 301 in the sub-test circuit.
  • the second selector 308 is a multiple-to-one multiplexer. The number of input terminals of the second selector 308 is related to the number of scan output channels channel_out of the circuit under test 01 corresponding to the jth sub-test circuit.
  • the second selector 308 can select one of three multiplexers for selecting the data distribution circuit 301 corresponding to each scan output channel channel_out of the circuit under test 01, and the corresponding The input channel scanbus_in or output channel scanbus_out of the test bus 02.
  • each third selector 309 of the CI j third selectors 309 is respectively connected to the first output terminals of the M data distribution circuits 301, and the CI j third selectors 309 are respectively connected to the first output terminals of the M data distribution circuits 301.
  • the output terminals of the selector 309 are respectively connected to the CI j scan input channel channel_in of the circuit under test 01 corresponding to the jth sub-test circuit.
  • the third selector 309 is also a multiple-to-one multiplexer.
  • the number of input terminals of the third selector 309 is related to the number of data distribution circuits 301 corresponding to the jth sub-test circuit, and the number of data distribution circuits 301 is related to the test bus.
  • the bit width of 02 is related. If the bit width of the test bus 02 is eight bits, the third selector 309 can be an eight-to-one multiplexer, which is used to select the data corresponding to the scan input channel channel_in of the circuit under test 01
  • the distribution circuit 301 and the corresponding input channel scanbus_in or output channel scanbus_out of the test bus 02 are examples of the third selector 309 .
  • the second selector 308 is used to configure the scan output channel channel_out of the circuit under test 01 to select the connected data distribution circuit 301
  • the third selector 309 is used to configure the scan input channel channel_in of the circuit under test 01 to select the connected data distribution circuit 301.
  • Data distribution circuit 301 Since corresponding to each sub-test circuit 30 shown in FIG. 1 , a data distribution circuit 301 is provided on each bit of the test bus, so through the configuration of the second selector 308 and the third selector 309 , the bus can be optimized. To solve the problem of congestion in resource planning and routing, it can also realize the allocation of each scan channel of the circuit under test 01 to any bus resource, thereby making the allocation of bus resources more flexible.
  • both the second selector 308 and the third selector 309 are multiplexers that select one from many, and the controller 303 is used to generate a signal for the configuration of the second selector 308 and the third selector 309
  • the second selector 308 corresponds to the scan output selection signal so_select
  • the third selector 309 corresponds to the scan input selection signal si_select.
  • the scan-out selection signal so_select is generated by the third signal interface
  • the scan-in select signal si_select is generated by the fourth signal interface.
  • the scan output selection signal so_select is output through the third signal interface of the controller 303
  • the second selector 308 is configured through the scan output selection signal so_select
  • the corresponding data distribution circuit 301 is selected to receive the scan output of the circuit under test 01 data.
  • the scan input selection signal si_select is output through the fourth signal interface of the controller 303
  • the third selector 309 is configured through the scan input selection signal si_select
  • the corresponding data distribution circuit 301 is selected to transmit the test scan data to the circuit under test.
  • the second selector 308 is a three-to-one selector, so the scan output selection signal so_select should actually be a two-bit signal, The output values are 00, 01 and 10 respectively, and these signals correspond to a scan output channel of circuit A under test respectively.
  • the third selector 309 is an eight-to-one selector, so the scan input selection signal si_select should actually be a three-bit signal, and the output values are 000, 001, 010, 011, 100, 101, 110, and 111, respectively.
  • the signals respectively correspond to a data distribution circuit in the sub-test circuit corresponding to the circuit A under test.
  • Example 3 please refer to FIG. 7.
  • the j-th sub-test circuit in the plurality of sub-test circuits 30 shown in FIG. 1 includes Nj groups of data distribution circuits 301 and CI j OR gates 310. .
  • the CI j OR gates 310 respectively correspond to the CI j groups of data distribution circuits 301 in the Nj groups of data distribution circuits 301
  • the CI j OR gates 310 respectively correspond to the CI j scan input channels channel_in of the circuit under test 01
  • the CO j groups of data distribution circuits 301 in the Nj groups of data distribution circuits 301 respectively correspond to the CO j scan output channels channel_out of the circuit under test 01 .
  • the number of scan channels of the circuit under test 01 is four, and the number of scan channels is the maximum of the number of scan input channels channel_in and the number of scan output channels channel_out, then the data distribution in the sub-test circuit corresponding to the circuit under test 01
  • the number of groups of the circuits 301 is four, and each group of the data distribution circuits 301 may correspond to one scan input channel channel_in and one scan output channel channel_out.
  • the number of OR gates in this sub-test circuit is the number of scan input channels channel_in, that is, three, so each OR gate 301 also corresponds to a group of data distribution circuits 301 and corresponds to a scan input channel channel_in of the circuit under test 01 .
  • each group of data distribution circuits 301 includes M data distribution circuits 301, and the M data distribution circuits 301 are respectively connected to M-bit test buses.
  • Each group of data distribution circuits 301 in the Nj groups of data distribution circuits 301 is sequentially connected in series on the corresponding test bus through the first input terminal and the second output terminal of each data distribution circuit 301 . That is, multiple data distribution circuits 301 on the same test bus 02 are connected to the same test bus 02 through the first input terminal and the second output terminal in sequence.
  • the first output terminals of the M data distribution circuits 301 in each group of data distribution circuits 301 are connected to the M input terminals of the corresponding OR gate 310, and the output terminal of the OR gate 310 is connected to the corresponding scan input channel channel_in of the circuit under test 01.
  • the second input terminals of the M data distribution circuits 301 in each group of data distribution circuits 301 are connected to the scan output channel channel_out of the corresponding circuit under test 01 .
  • Each data distribution circuit 301 is also configured to control the data distribution circuit 301 to reset, when the data distribution circuit 301 is reset, the output of the data distribution circuit 301 is zero, which can be implemented in each group of data distribution circuits 301, or
  • the output value of the gate 310 is the value output by the first output terminal of the selected data distribution circuit 301 , that is, the value input by the input channel scanbus_in of the selected test bus 02 .
  • the OR gate 310 is set between the scan input channel channel_in of the circuit under test 01 and the data distribution circuit 301 connected to the test bus, and the scan input channel channel_in entering the circuit under test 01 is transmitted through the OR gate 310.
  • the data can be selected by selecting one, which can reduce the area overhead as much as possible and solve the problem of routing congestion.
  • the output value of each OR gate 310 can be the value output by the first output terminal of the selected data distribution circuit 301, thereby realizing more flexible testing. Bus resource allocation.
  • a reset signal needs to be configured. Since the reset signal and the bypass enable signal dru_bp are associated signals, the reset signal and the bypass enable signal dru_bp can be shared. , that is, generated by the second signal interface of the controller 303 .
  • bypass enable signal dru_bp is output through the second signal interface of the controller 303 to configure the fifth selector 3013 in the data distribution circuit 301 to distribute the unselected data in the sub-test circuit
  • the circuit 301 is set to bypass, and the register 3012 of the control data distribution circuit 301 is reset to meet the requirements of the scan input channel channel_in of the circuit under test 01 to select the data distribution circuit 301, and the configuration operation is simple.
  • bypass enable signal dru_bp in the example shown in FIG. 7 is a multi-bit signal, and each data distribution circuit in each sub-test module corresponds to one of the bypass enable signals dru_bp. Signal.
  • FIG. 8 shows a schematic structural diagram of the data distribution circuit 301 corresponding to FIG. 7 .
  • the data distribution circuit 301 shown in FIG. 7 is different from the data distribution circuit 301 shown in FIG.
  • the two control terminals are also connected to the reset terminal of the register 3012 for controlling the register 3012 to reset.
  • the reset signal and the bypass enable signal may belong to opposite signals. If the trigger level of the reset signal and the bypass enable signal are opposite, the bypass enable signal can be negated and then transmitted to the register 301.
  • the control terminal is reset.
  • Example 4 please refer to FIG. 9.
  • the circuit under test 01 is connected to the test bus.
  • the jth sub-test circuit among the plurality of sub-test circuits 30 shown in FIG. 1 includes Nj data distribution circuits 301 and M first selectors 302, and the first selectors 302 refer to the shift selector in FIG. 2 SHIFT_MUX.
  • the jth sub-test circuit may be any one of the multiple sub-test circuits 30 shown in FIG. 1 .
  • the number Nj of data distribution circuits in the jth sub-test circuit is the number of scan channels of the corresponding circuit under test, that is, the number of scan input channels CI j and the number of scan output channels CO j of the corresponding circuit under test.
  • the maximum value, ie Nj max(CI j , CO j ).
  • the first input terminals of the Nj data distribution circuits 301 are respectively connected to the Nj input channels scanbus_in of the test bus, that is, the first input terminal of the data distribution circuit 301 is used to receive the input channel of the test bus 02 Test scan data entered by scanbus_in.
  • the first output terminals of the CI j data distribution circuits 301 in the Nj data distribution circuits 301 are respectively connected with the CI j scan input channels channel_in of the circuit under test 01 corresponding to the jth sub-test circuit, that is, the data distribution circuit 301
  • the first output terminal is used for transmitting the test scan data received from the test bus 02 to the scan input channel channel_in of the corresponding circuit under test 01 .
  • the second input terminals of the CO j data distribution circuits 301 in the Nj data distribution circuits 301 are respectively connected to the CO j scan output channels channel_out of the circuit under test 01 corresponding to the jth sub-test circuit, that is, the data distribution circuit 301
  • the two input terminals are used to receive the test result data output by the scan output channel channel_out of the corresponding circuit under test 01 .
  • the test result data is output to the output channel scanbus_out of the test bus 02 through the second output terminal of the data distribution circuit 301 .
  • the number M of the first selectors 302 of each sub-test circuit in the plurality of sub-test circuits shown in FIG. 1 is equal to the bit width of the test bus 02, and the output ends of the M first selectors 302 in each sub-test circuit
  • the M output channels scanbus_out of the test bus 02 are respectively connected, that is, the M first selectors 302 in each sub-test circuit are in a one-to-one correspondence with the M bits of the test bus 02 .
  • the first input terminals of the M first selectors 302 are respectively connected to the M input channels scanbus_in of the test bus 02 .
  • the second input terminals of the Nj first selectors 302 in the M first selectors 302 are respectively connected to the second output terminals of the Nj data distribution circuits 301, and the second inputs of the remaining M-Nj first selectors 302
  • the terminals are respectively connected to the input channels scanbus_in of the M-Nj test buses not provided with the data distribution circuit 301 .
  • the busses to which the first input terminal and the second output terminal of each first selector 302 are connected are different.
  • the circuit structure of the sub-test circuit 30 shown in FIG. 1 in this example is similar to the first example shown in FIG. 2 , the difference is that the first input terminals of the M first selectors 302 are all connected to the test bus. M inputs.
  • the first input terminal of the first selector is directly connected to the input of the test bus, so that when the circuit under test corresponding to the jth sub-test circuit does not participate in the test, the j+1th sub-test circuit The input data does not pass through the data distribution circuit in the jth sub-test circuit, thereby reducing the test time.
  • the data distribution circuit 301 allocates and transmits the test resources, and through the configuration of the first selector 302, the test resources can be dynamically allocated, which greatly solves the problem of winding The problem of congestion, the configuration process is simpler.
  • the first input terminals of the Nj data distribution circuits 301 are sequentially connected to the first Nj busses. Input channel scanbus_in.
  • the first input terminals of the M first selectors 302 are sequentially connected to the M inputs of the test bus.
  • the second input terminals of the first M-Nj first selectors 302 are sequentially connected to the last M-Nj inputs of the test bus.
  • the second input terminals of the last Nj first selectors 302 are sequentially connected to the second output terminals of the Nj data distribution circuits 301 .
  • the data distribution circuit 301 is allocated to the bus resources in a preset order according to the established rules, so that the test circuit can simplify the circuit design under the condition of ensuring the dynamic allocation of the test resources, which is convenient for wiring.
  • the first selector 302 since the first input end of the first selector 302 is directly connected to the input scanbus_in of the bus, the first selector 302 is configured to select the first input end and When the output end is connected, the test bus connected to the first selector 302 is actually in a state of direct connection, and does not pass through the data distribution circuit 301 .
  • each data distribution circuit 301 includes a fourth selector 3011 and a register 3012 .
  • the first input end and the second input end of the fourth selector 3011 are respectively connected to the first input end and the second input end of the data distribution circuit 301 , and the control end of the fourth selector 3011 is connected to the first control end of the data distribution circuit 301 .
  • the input end of the register 3012 is connected to the output end of the fourth selector 3011 , and the output end of the register 3012 is connected to the second output end of the data distribution circuit 301 .
  • the first output terminal of the data distribution circuit 301 is connected to the first input terminal of the data distribution circuit 301 or the output terminal of the register 3012 .
  • the configuration of the first selector 302 can still be controlled by using the controller 303 to generate a shift selection control signal bus_shift.
  • the controller 303 can still be controlled by using the controller 303 to generate a shift selection control signal bus_shift.
  • a shift selection control signal bus_shift please refer to Example 1 shown in FIG. 2 , which will not be repeated here.
  • FIG. 4 shows a schematic structural diagram of a gate control circuit in a test circuit provided by an embodiment of the present application, and the gate control circuit may correspond to FIG. 2 , FIG. 5 , FIG. 6 , FIG. 7 and The gate control unit gate in Figure 9.
  • gates are provided when the data distribution circuit 301 transmits data to the scan input channel channel_in of the circuit under test 01 and when the scan output channel channel_out of the circuit under test 01 transmits data to the data distribution circuit 301
  • the control circuits are respectively a first gating circuit 306 and a second gating circuit 307 .
  • the first gating circuit 306 and the second gating circuit 307 are integrated together. In an actual circuit, the first gating circuit 306 and the second gating circuit 307 can also be separated into two circuit modules. .
  • the data distribution circuit 301 passes through the first gating circuit 306
  • the scan input channel channel_in of the circuit under test 01 corresponding to the jth sub-test circuit is connected to control whether the data in the data distribution circuit 301 is output to the scan input channel of the circuit under test 01 corresponding to the jth sub-test circuit in channel_in.
  • the data distribution circuit 301 is connected with the scan output channel channel_out of the circuit under test 01 corresponding to the jth sub-test circuit through the second gate control circuit 307, and is used to control the circuit under test 01 corresponding to the jth sub-test circuit. Whether the data of the scan output channel channel_out is output to the data distribution circuit 301 is checked.
  • the first output terminals of the CI j data distribution circuits 301 in the Nj data distribution circuits 301 are respectively connected to the input terminals of the CI j first gating circuits 306, and the CI j first gating circuits 306 are respectively connected.
  • the output terminals of the gate control circuit 306 are respectively connected to the CI j scan input channels channel_in of the circuit under test 01 corresponding to the jth sub-test circuit.
  • the CO j scan output channels channel_out of the circuit under test 01 corresponding to the j th sub-test circuit are respectively connected to the input ends of the CO j second gating circuits 307, and the CO j second gating circuits
  • the output terminals of the circuit 307 are respectively connected to the second input terminals of the CO j data distribution circuits 301 in the Nj data distribution circuits 301 .
  • the third selector 309 corresponds to the j-th sub-test circuit through the first gating circuit 306 .
  • the scan input channel channel_in of the circuit under test 01 is connected to control whether the data in the data distribution circuit 301 is output to the scan input channel channel_in of the circuit under test 01 corresponding to the jth sub-test circuit.
  • the scan output channel channel_out of the circuit under test 01 corresponding to the jth sub-test circuit is connected to the second selector 308 through the second gate control circuit 307 to control the scan of the circuit under test 01 corresponding to the jth sub-test circuit Whether the data of the output channel channel_out is output to the data distribution circuit 301 .
  • the CO j scan output channels channel_out of the circuit under test 01 corresponding to the j th sub-test circuit are respectively connected to the input ends of the CO j second gating circuits 307, and the output ends of the CO j second gating circuits 307 are respectively The CO j inputs of each of the M second selectors 308 are connected.
  • the output terminals of the CI j third selectors 309 are respectively connected to the input terminals of the CI j first gating circuits 306, and the output terminals of the CI j first gating circuits 306 are respectively connected to the tested test circuits corresponding to the j th sub-test circuit.
  • CI j scan input channels channel_in of circuit 01.
  • the scan input channel channel_in of the circuit 01 is connected to control whether the data in the data distribution circuit 301 is output to the scan input channel channel_in of the circuit under test 01 corresponding to the jth sub-test circuit.
  • the scan output channel channel_out of the circuit under test 01 corresponding to the jth sub-test circuit is connected to the data distribution circuit 301 through the second gate control circuit 307, and is used to control the scan output of the circuit under test 01 corresponding to the jth sub-test circuit Whether the data of the channel channel_out is output to the data distribution circuit 301 .
  • the output terminals of the CI j OR gates 310 are respectively connected to the input terminals of the CI j first gating circuits 306 , and the output terminals of the CI j first gating circuits 306 are respectively connected to the under test corresponding to the j th sub-test circuit.
  • CI j scan input channels channel_in of circuit 01.
  • the CO j scan output channels channel_out of the circuit under test 01 corresponding to the j th sub-test circuit are respectively connected to the input ends of the CO j second gating circuits 307, and the CO j second gating circuits 307 correspond to the CO j groups of data respectively.
  • the second input end of each data distribution circuit 301 in each group of data distribution circuits 301 is connected to the output end of the corresponding second gate control circuit 307 .
  • the circuit 30 further includes a state machine 304, where the state machine 304 is a finite state machine (FSM), and the state machine 304 may include: a first state control interface, a second state control interface, and a third state control interface and the fourth state control interface.
  • FSM finite state machine
  • the state machine 304 applies to the examples described in FIGS. 2 , 5 , 6 , 7 and 9 .
  • the first state control interface is used to generate the output capture enable signal so_cap_en, and transmit the output capture enable signal so_cap_en to the data distribution circuit 301 of each sub-test circuit 30 shown in FIG. 1 .
  • the first control terminal configures the fourth selector 3011 to control whether the data distribution circuit 301 receives the test scan data of the test bus or the scan output data of the circuit under test 01 at the current time.
  • the second state control interface is used to generate the first gating enable signal ch_in_gate_en, and use the first gating enable signal ch_in_gate_en to configure the first gating circuit 306 to control the sub-test circuit 30 shown in FIG. 1 Whether the test scan data of each data distribution circuit 301 is transmitted to the scan input channel channel_in of the circuit under test 01 corresponding to the sub-test circuit 30 shown in FIG. 1 .
  • the third state control interface is used to generate the second gating enable signal ch_out_gate_en, and use the second gating enable signal ch_out_gate_en to configure the second gating circuit, so as to control the sub-test circuit 30 shown in FIG. 1 .
  • the signal on the FSM side of the state machine in FIGS. 2 , 5 , 6 , 7 and 9 is identified as gate_en, which may correspond to ch_in_gate_en in the first gate control circuit 306 and ch_in_gate_en in the second gate control circuit 307 ch_out_gate_en).
  • the fourth state control interface is used to generate the scan enable signal scan_enable, and use the scan enable signal to configure the scan structure of the circuit under test 01, thereby controlling the circuit under test corresponding to the sub-test circuit 30 shown in FIG. 1 Whether the scan structure of 01 performs a test scan.
  • the above four kinds of signals are generated by the finite state machine 304 to configure the test process of the test circuit, and the configuration is simple and easy to implement.
  • each sub-test circuit 30 shown in FIG. 1 may further include a frequency dividing circuit 305 , and the frequency dividing circuit 305 may Use dividers (dividers, DIV).
  • the frequency dividing circuit 305 is respectively connected to the bus clock interface and the scan clock interface of the circuit under test 01 , and is used for dividing the frequency of the clock scanbus_clk of the test bus into the scan clock scan_clock of the circuit under test 01 .
  • the high-speed scan clock of the test bus is divided into a low-speed scan clock in the circuit under test 01, so as to facilitate the scan test of the circuit under test 01.
  • FIG. 11 is a flowchart of a circuit testing method provided by an embodiment of the present application.
  • the circuit test method can be used to test the circuit under test in EDA software, and is suitable for testing the circuit under test using any of the test circuits shown in Figure 2, Figure 5, Figure 6, Figure 7 and Figure 9.
  • the circuit test method includes:
  • configuration information and test vectors can be generated by the EDA software.
  • the EDA software can generate the configuration information and test stimulus data according to some test parameters given by the tester.
  • the configuration information can be used to configure the test circuit; the test vector is the test excitation data of the circuit under test and is determined by the circuit structure of the circuit under test.
  • the circuit under test Before configuring the test circuit, it is necessary to identify the circuit under test that will be tested at the same time. Therefore, during the test, the circuit under test can be tested in groups, and the grouping principle can generally be based on the principle of the shortest total test time.
  • the specific configuration method and configuration content are different according to different test circuit structures.
  • the shift selection control signal bus_shift can be configured through the first signal interface of the controller 303 to control the connection relationship between the input and the output selected by the first selector 302,
  • the first selector in the sub-test circuit corresponding to the circuit under test is placed in the direct connection mode, that is, the first selector 302 is configured so that the first input end is connected to the output end.
  • the bypass enable signal dru_bp can be configured through the second signal interface of the controller 303, so that the data distribution circuit in the sub-test circuit corresponding to the circuit under test that does not participate in the test is placed in the bypass state, that is, the corresponding data distribution circuit 301. There is no register between the first input terminal and the second output terminal in .
  • the scan output selection signal so_select and the scan input selection signal si_select can be configured by the controller 303 .
  • the scan output selection signal so_select is output by the third signal interface, and is used to configure the second selector 308, so that the scan output channel channel_out of the circuit under test 01 corresponding to the sub-test circuit 30 shown in FIG.
  • a data distribution circuit 301 in the circuit 30 is connected.
  • the scan-in selection signal is output from the fourth signal interface, and is used to configure the third selector 309, so that the sub-test circuit 30 selects one of the data distribution circuits 301 and is connected to the scan-in channel channel_in of the circuit under test 01 corresponding to the sub-test circuit 30 .
  • the bypass enable signal dru_bp can be configured through the second signal interface of the controller 303, and the bypass enable signal dru_bp can be used as the reset signal of the data distribution circuit.
  • reset it means that the data distribution circuit 301 is not selected, so the value output by the first output terminal of the selected data distribution circuit 301 is the input value of the selected test bus 02, thereby realizing the test bus 02 and data distribution.
  • the shift selection control signal bus_shift can be configured through the first signal interface of the controller 303 to control the connection relationship between the input and the output selected by the first selector 302.
  • the first selector 302 in the sub-test circuit 30 shown in FIG. 1 corresponding to the circuit under test 01 is placed in the direct connection mode, that is, the first selector 302 is The output is connected.
  • the output capture enable signal so_cap_en is also configured through the first state control interface of the state machine 304 .
  • the second state control interface of the state machine 304 configures the first gating enable signal ch_in_gate_en
  • the third state control interface of the state machine 304 configures the second gate enable signal ch_out_gate_en
  • the fourth state control interface of the state machine 304 configures Scan enable signal scan_enable.
  • the output capture enable signal so_cap_en the first gating enable signal ch_in_gate_en, the second gating enable signal ch_out_gate_en, and the scan enable signal scan_enable, please refer to the description of the state machine in the example corresponding to FIG. Repeat.
  • the frequency dividing ratio of the frequency dividing circuit 305 needs to be configured during the configuration process, wherein the frequency dividing ratio of the frequency dividing circuit 305 is determined by the number of scan input channels channel_in, scan output channels channel_out and test bus 02 of the circuit under test 01 Determined by the bit width of the frequency dividing circuit 305, the calculation formula of the frequency dividing ratio Rdiv of the frequency dividing circuit 305 is:
  • CI i is the number of scan input channels of the i-th circuit under test to be tested
  • CO i is the number of scan output channels of the i-th circuit under test to be tested
  • B is the bus bit width.
  • test vector transmits the test vector to the test bus, and transmit it to the scan input channel of the circuit under test through the test circuit.
  • the test vector is the test excitation data of the circuit under test and is determined by the circuit structure of the circuit under test.
  • the test vector is transmitted to the scan input channel of the circuit under test through the test circuit, including: according to the corresponding relationship between the scan input channel of the circuit under test and the input of the test bus, through the scan input channel of the circuit under test corresponding to the test bus. input to transmit the test vector to the scan-in channel of the circuit under test.
  • the correspondence between the scan input channel channel_in of the circuit under test and the input channel scanbus_in of the test bus 02 is determined by the data distribution circuit 301 in the sub-test circuit 30 shown in FIG. 1 corresponding to the circuit under test 01 .
  • the scan input channel channel_in of the circuit under test and the corresponding data distribution circuit 301 in the sub-test circuit 30 shown in FIG. 1 belong to a one-to-one correspondence. Therefore, the correspondence between the scan input channel channel_in of the circuit under test and the input channel scanbus_in of the test bus 02 is actually the data distribution circuit 301 and the test bus 02 in the sub-test circuit 30 shown in FIG. 1 corresponding to the circuit under test 01 the actual connection relationship.
  • the scan input channel channel_in of the circuit under test 01 and the data distribution circuit 301 in the sub-test circuit 30 shown in FIG. 1 corresponding to the circuit under test 01 belong to a one-to-many relationship . Therefore, the corresponding relationship between the scan input channel channel_in of the circuit under test and the input channel scanbus_in of the test bus can be configured by the scan input selection signal si_select configured by the controller 303. After the configuration, the data distribution selected by the scan input channel channel_in of the circuit under test 01 The test bus 02 to which the circuit 301 is connected corresponds to the scan input channel channel_in of the circuit 01 under test.
  • the scan input channel channel_in of the circuit under test 01 and the data distribution circuit 301 in the sub-test circuit 30 shown in FIG. 1 corresponding to the circuit under test 01 belong to a one-to-many relationship . Therefore, the correspondence between the scan input channel channel_in of the circuit under test 01 and the input channel scanbus_in of the test bus 02 can be controlled by the bypass enable signal dru_bp.
  • the bypass enable signal dru_bp can control the data distribution circuit 301 to reset.
  • the data distribution circuit 301 is selected by the scan input channel channel_in of the corresponding circuit under test 01 . That is, the corresponding relationship between the scan input channel channel_in of the circuit under test 01 and the input channel scanbus_in of the test bus 02 is determined by the data distribution circuit 301 that is not reset.
  • test result data of the circuit under test to the output of the test bus through the circuit under test. Specifically, according to the corresponding relationship between the scan output channel of the circuit under test and the output of the test bus, the test result data output by the scan output channel of the circuit under test is transmitted to the test bus corresponding to the scan output channel of the circuit under test. output.
  • the correspondence between the scan output channel of the circuit under test and the output channel of the test bus is determined by the data distribution circuit in the sub-test circuit corresponding to the circuit under test.
  • the method for determining the correspondence between the scan output channel channel_out of the circuit under test 01 and the output channel scanbus_out of the test bus 02 is similar to the method for determining the correspondence between the scan input channel of the circuit under test and the input of the test bus in step S1103, It will not be repeated here.
  • test bus when the test circuit tests the circuit under test, there may be a plurality of circuits under test that are tested at the same time.
  • bit width of the test bus is limited, so the test bus will be multiplexed, that is, the test bus will transmit data to the scan input channels of multiple circuits under test by means of timing splitting.
  • the test bus can only transmit data to one scan-in channel or output data from one scan-out channel, so if one of the inputs of the test bus needs to transmit data to multiple scan-in channels channel_in, or one of the outputs If data needs to be output from multiple scan output channels channel_out, the transmitted data is divided into multiple bus clock cycles and transmitted in sequence.
  • test scheme shown in Figure 13 please refer to the test scheme shown in Figure 13.
  • test bus clock cycle each time the test bus transmits one cycle of scan data, one bus clock cycle will be added to transmit the test vector data in the data distribution circuit to the scan input channel channel_in of the circuit under test 01, and the scan output channel of the circuit under test 01 will be transmitted.
  • the test result data of channel_out is transmitted to the data distribution circuit.
  • the scan data of one cycle refers to the test scan data of one scan of all the circuits under test to be tested.
  • test circuit shown in FIG. 2 is used as an example for description below.
  • core_A circuit under test A
  • core_C circuit under test C
  • core_B circuit under test B
  • the first selector 302 in the sub-test circuit corresponding to the circuit B under test is configured to be in a direct connection state through the shift selection control signal bus_shift, that is, in this example, the shift selection The control signal bus_shift is set to 0, and the bypass enable signal dru_bp that controls the bypass of the data distribution circuit 301 in the sub-test circuit corresponding to the circuit B under test is set to 0, so that the first input terminal and the second output of the data distribution circuit 301 are set to 0. connected directly.
  • FIG. 12 is a schematic structural diagram of a test scheme corresponding to FIG. 2 in this embodiment.
  • the scan test is performed on the circuit A and the circuit C under test at the same time, while the circuit B under test is not tested temporarily, the scan channel of the test bus 02 and the circuit under test 01
  • Table 1 for the corresponding relationship.
  • the test vector is transmitted to the scan input channel of the circuit under test through the input channel scanbus_in of the test bus, and the test result data is sent from the circuit under test.
  • the scan output channel is transmitted to the output channel scanbus_out of the test bus. Since each input or output of the test bus corresponds to only one scan channel of the circuit under test, the test vector and test result data can be transmitted in one cycle.
  • Figure 13 is a A schematic structural diagram of another test solution corresponding to FIG. 2 in this embodiment.
  • the bus width of the test bus 02 is 8 bits
  • the circuit A under test has 3 scan channels
  • the circuit B under test has 5 scan channels
  • the circuit C under test has 4 scan channels, among which the The number is the maximum value among the number of scan-in channels and the number of scan-out channels of the circuit under test. Therefore, for the allocation of the test bus, the circuit A under test needs to allocate 3 bits of input and output of the test bus, and the circuit B under test needs to allocate 5 bits of input and output of the test bus, that is, the circuit A and the circuit B under test have connected the test bus All resources are occupied.
  • the test bus only the test bus can be multiplexed, and the test vector input data and test result data are input or output in two different clock cycles respectively.
  • channel[x] in Table 2 can represent channel_in[x] or channel_out[x] in Figure 2, and x is Integer representing the number of bits.
  • channel[x] in Table 2 represents channel_in[x]; for example, when the test result data is transmitted, channel[x] in Table 2 represents channel_out[x] .
  • test waveform diagram is shown in FIG. 14 .
  • the above test scheme shown in Figure 13 is only an example.
  • the number of scan channels of one of the circuits under test may also exceed the bit width of the test bus.
  • the number of scan input channels channel_in of the circuit under test 01 corresponding to one input channel scanbus_in of the test bus 02 may exceed one
  • the number of scan input channels channel_out of the circuit under test 01 corresponding to one output channel scanbus_out of the test bus 02 may also be If there is more than one, in this case, it is also necessary to perform data transmission in multiple bus clock cycles by means of timing splitting.
  • FIG. 15 is a flowchart of a method for designing a test circuit according to an embodiment of the present application.
  • the design method of the test circuit includes:
  • test circuit S1502 according to the bus bit width of the test bus and the number of scan input channels and scan output channels of each circuit under test, configure the data distribution circuit in the sub-test circuit corresponding to each circuit under test on the test bus, and generate Any of the test circuits shown in Figures 2, 5, 6, 7 and 9 above.
  • the number of data distribution circuits in the sub-test circuit corresponding to each circuit under test is determined by the bus bit width of the test bus, or the number of scan input channels and scan output channels of each circuit under test.
  • the number of data distribution circuits 301 in the sub-test circuit 30 shown in FIG. 1 corresponding to each circuit under test 01 is related to the scan input channel channel_in in the circuit under test 01 . It is associated with the number of scan output channels channel_out, which is equal to the maximum of the number of scan input channels channel_in and scan output channel channel_out in the corresponding circuit under test.
  • Embodiments of the present application further provide a computer-readable storage medium, where computer-readable instructions are stored in the computer storage medium, and when the computer reads and executes the computer-readable instructions, the computer is made to execute the above-mentioned instructions as shown in FIG. 11 .
  • the circuit testing method in the method embodiment
  • Embodiments of the present application further provide a computer program product, which, when the computer reads and executes the computer program product, enables the computer to execute the circuit testing method in the method embodiment shown in FIG. 11 .
  • processors in the embodiments of the present application may be a central processing unit (central processing unit, CPU), and the processor may also be other general-purpose processors, digital signal processors (digital signal processors, DSP), dedicated integrated Circuit (application specific integrated circuit, ASIC), off-the-shelf programmable gate array (field programmable gate array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
  • the memory in the embodiments of the present application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory.
  • the non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically programmable Erase programmable read-only memory (electrically EPROM, EEPROM) or flash memory.
  • Volatile memory may be random access memory (RAM), which acts as an external cache.
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • DRAM synchronous dynamic random access memory
  • SDRAM synchronous dynamic random access memory
  • DDR SDRAM double data rate synchronous dynamic random access memory
  • enhanced SDRAM enhanced synchronous dynamic random access memory
  • SLDRAM synchronous connection dynamic random access memory Fetch memory
  • direct memory bus random access memory direct rambus RAM, DR RAM
  • the above embodiments may be implemented in whole or in part by software, hardware (eg, circuits), firmware, or any other combination.
  • the above-described embodiments may be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server or data center Transmission to another website site, computer, server or data center by wire (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, a data center, or the like containing one or more sets of available media.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVDs), or semiconductor media.
  • the semiconductor medium may be a solid state drive.

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Abstract

一种芯片测试电路及电路测试方法，可用于EDA软件中对芯片电路进行测试，用于解决目前的测试方案中的绕线拥塞和测试配置复杂的问题。该测试电路将测试向量的输入数据通过测试总线的输入传输至数据分发电路(301)中，通过数据分发电路(301)传输至被测电路(01)的扫描输入通道，被测电路(01)扫描结束后，被测电路(01)的扫描输出通道的测试向量的输出数据通过数据分发电路(301)传输至测试总线的输出完成被测电路(01)的测试，通过对第一选择器(302)的配置实现数据分发电路(301)与测试总线(02)的动态对应关系，使得测试资源能够得以动态分配，极大程度地优化了绕线拥塞的问题，以便降低测试成本，并且可以简化配置过程，从而提高测试效率。

Description

芯片测试电路及电路测试方法 技术领域
本申请涉及电子技术领域，尤其涉及一种芯片中的测试电路及电路测试方法。
背景技术
随着半导体技术的发展，系统级芯片(system on a chip,SoC)的规模越来越大，其内部的电路模块越来越多，在对系统级芯片中的电路模块进行测试时，由于可用于测试的资源有限，例如芯片管脚有限，因此需要对有限的资源进行合理规划复用，以便实现大规模的测试需求。为解决上述问题，目前所采用的方案有扫描路由结构(scan routing fabric,SRF)和扫描流水网络结构(scan streaming network,SSN)。
在SRF方案中，通过少量的芯片管脚利用多路选择器(multiplexers,MUX)对其进行复用，可以实现具有更大数量的测试扫描通道的电路的测试，如果待测电路的扫描通道数量持续增加，就会出现较严重的绕线拥塞问题，测试成本高。在SSN方案中，测试扫描数据通过总线进行传输，在传输过程中通过较复杂的硬件电路使测试数据在总线与待测电路的测试压缩逻辑之间进行数据交换，在待测电路增加的情况下，作为数据交换的硬件电路也会增加，导致硬件电路规模较大。另外，在SSN方案中，还需要对复杂的硬件电路进行各项配置，配置过程比较复杂，测试效率低下。
发明内容
本申请实施例提供一种芯片测试电路及电路测试方法，能够优化目前的测试方案中的绕线拥塞和测试配置复杂的问题，以降低测试成本，提高测试效率。
为达到上述目的，本申请采用如下技术方案：
第一方面，提供一种测试电路。该测试电路包括：与多个被测电路分别对应的多个子测试电路，多个子测试电路用于分别将对应的被测电路连接在测试总线上。每一个被测电路对应一个子测试电路，每个子测试电路可以将测试扫描所需的数据通过测试总线传输至对应的被测电路的扫描输入通道中，并将对应的被测电路的测试结果数据传输至测试总线输出。每个子测试电路还可以将测试总线动态分配给对应的被测电路。多个子测试电路中第j个子测试电路包括Nj个数据分发电路和M个第一选择器，其中Nj和M均为正整数，M等于所述测试总线的位宽，并且M大于或等于Nj。第j个子测试电路可以为多个子测试电路中的任意一个子测试电路。数据分发电路用于接收测试总线的扫描测试数据并传输至被测电路的扫描输入通道中，并接收被测电路的扫描输出通道的测试结果数据，传输至测试总线输出。在第j个子测试电路中，数据分发电路与测试总线和被测电路的连接关系为：Nj个数据分发电路的第一输入端分别与测试总线的Nj个输入连接，用于接收测试总线的测试扫描数据；Nj个数据分发电路的第一输出端，与第j个子测试电路对应的被测电路的扫描输入通道连接，用于将数据分发电路接收的测试扫描数据传输至被测电路的扫描输入通道中；Nj个数据分发电路的第二输入端，与第j个子测试电路对应的被测电路的扫描输出通道连接，用于 将被测电路的测试结果数据传输至数据分发电路后，通过数据分发电路传输至测试总线的输出。第一选择器可以为二选一的选择器，用于对第j+1个子测试电路所使用的的测试总线进行选择，来实现测试总线的动态分配。具体来说，每个子测试电路中的M个第一选择器的输出端分别连接测试总线的M个输出，将每个子测试电路中的M个第一选择器分别与测试总线的M位一一对应。其中，M个第一选择器中的Nj个第一选择器的第一输入端分别连接Nj个数据分发电路的第二输出端，其余的M-Nj个第一选择器的第一输入端分别连接M-Nj个未设置数据分发电路的测试总线的输入。M个第一选择器中的Nj个第一选择器的第二输入端分别连接Nj个数据分发电路的第二输出端，其余的M-Nj个第一选择器的第二输入端分别连接M-Nj个未设置数据分发电路的测试总线的输入。并且，每个第一选择器的第一输入端和第二输入端连接的测试总线不同。在第j个子测试电路中，第一选择器的第一输入端和第二输入端连接的测试总线不同，可以通过第一选择器配置第j+1个子测试电路所使用的测试总线。
基于第一方面提供的测试电路，该测试电路将测试向量的输入数据，即扫描测试数据通过测试总线的输入传输至数据分发电路中，通过数据分发电路传输至被测电路的扫描输入通道。被测电路扫描结束后，被测电路的扫描输出通道的测试向量的输出数据，即测试结果数据通过数据分发电路传输至测试总线的输出完成被测电路的测试。通过对第一选择器的配置实现数据分发电路与测试总线的动态对应关系，使得测试资源能够得以动态分配。例如，假设测试总线的位宽为8位，第1个子测试电路中用到的数据分发电路数量为3，第二个数据分发电路的数量为5。第1个子测试电路中的3个数据分发电路分别连接在测试总线的第[0]、[1]、[2]位上，第2个子测试电路中的4个数据分发电路分别连接在测试总线的第[0]、[1]、[2]、[3]、[4]位上，8个第一选择器的输出分别连接测试总线的8个输出。那么在第一个子测试电路中的8个第一选择器中，前3个第一选择器的第一输入端可以连接第1个子测试电路中的3个数据分发电路的第二输出端；后5个第一选择器的第一输入端可以连接测试总线的第[3]、[4]、[5]、[6]、[7]位的输入。前5个第一选择器的第二输入端可以连接测试总线的第[3]、[4]、[5]、[6]、[7]位的输入；后3个第一选择器的第二输入端可以连接第1个子测试电路中的3个数据分发电路的第二输出端。当第1个子测试电路中的8个第一选择器被配置为，第一选择器的第一输入端与输出端连通时，那么在第2个子测试电路中分配到的测试总线为测试总线的第[0]、[1]、[2]、[3]、[4]位。当第1个子测试电路中的8个第一选择器被配置为，第一选择器的第二输入端与输出端连通时，那么在第2个子测试电路中分配到的测试总线为测试总线的[3]、[4]、[5]、[6]、[7]位。即，通过上述方案对第1个子测试电路中的第一选择器的配置，可以对第2个子测试电路中的所使用的测试总线进行动态分配，配置时只需要对第一选择器进行配置即可实现动态分配，配置过程简单。因此在该第一方面提供的测试电路，通过数据分发电路和第一选择器实现对被测电路所使用的测试总线进行动态分配，能够极大程度地优化绕线拥塞的问题，以便降低测试成本，并且可以简化配置过程，而提高测试效率。
在第一方面的一种可能的实现方式中，在多个子测试电路的第j个子测试电路中，按照预设的测试总线顺序，Nj个数据分发电路的第一输入端依次连接前Nj个测试总线的输入；前Nj个第一选择器的第一输入端依次连接Nj个数据分发电路的第二输出 端后M-Nj个第一选择器的第一输入端依次连接测试总线的后M-Nj个输入，即在第j个子测试电路中，第一选择器被配置为第一选择器的第一输入端与输出端连通时，第一选择器的输出和输入所对应的测试总线相同，即直连模式。前M-Nj个第一选择器的第二输入端依次连接测试总线的后M-Nj个输入；后Nj个第一选择器的第二输入端依次连接Nj个数据分发电路的第二输出端，即在第j个子测试电路中，第一选择器被配置为第一选择器的第二输入端与输出端连通时，第一选择的输出与输入所对应的测试总线不同，即移位连接模式。在上述可能的实现方式中，以一种预设的顺序将数据分发电路按照既定的规则分配到总线资源上，能够使该测试电路在保证测试资源动态分配的情况下，简化线路设计，从而提高测试效率。
进一步地，预设的测试总线顺序为测试总线位序的顺序或倒序。在上述可能的实现方式中，预设的测试总线顺序是以一种特定的顺序，例如测试总线的顺序或倒序，以此种方式可进一步简化测试电路的线路结构，从而在一定程度上简化测试电路的结构，以便快速实现测试电路的接线要求。
在第一方面的另一种可能的实现方式中，第j个子测试电路中的数据分发电路的数量Nj为对应的被测电路的扫描通道的数量，其中对应的被测电路的扫描通道数量为被测电路的扫描输入通道的数量CI j和扫描输出通道CO j的数量中的最大值，即Nj＝max(CI j,CO j)。Nj个数据分发电路中的CI j个数据分发电路的第一输出端，分别与第j个子测试电路对应的被测电路的CI j个扫描输入通道连接，即数据分发电路的第一输出端用于将从测试总线接收的测试扫描数据传输至对应的被测电路的扫描输入通道中。Nj个数据分发电路中的CO j个数据分发电路的第二输入端分别与第j个子测试电路对应的被测电路的CO j个扫描输出通道连接，即数据分发电路的第二输入端用于接收对应的被测电路的扫描输出通道输出的测试结果数据，测试结果数据通过数据分发电路的第二输出端输出至测试总线。通过该方案，实现被测电路的扫描输入通道和扫描输出通道与数据分发电路的一一对应关系，方便测试数据的传输，从而避免输出输出，进一步提高测试效率，降低测试时间。
在第一方面的另一种可能的实现方式中，每个数据分发电路均可以包括第四选择器、寄存器和第五选择器。其中，第四选择器用于实现数据分发电路选择从测试总线接收数据，还是从对应的被测电路的扫描输出通道接收数据。即第四选择器的第一输入端和第二输入端分别连接数据分发电路的第一输入端和第二输入端，第四选择器的控制端连接数据分发电路的第一控制端。寄存器用于将数据分发电路接收的数据暂存，因此寄存器的输入端连接第四选择器的输出端，寄存器的输出端连接第五选择器的第一输入端。第五选择器用于实现对测试总线的输入数据是否经过寄存器的配置，即第五选择器的第二输入端连接数据分发电路的第一输入端，第五选择器的输出端连接数据分发电路的第二输出端，第五选择器的控制端连接数据分发电路的第二控制端。数据分发电路的第一输出端连接数据分发电路的第一输入端或寄存器的输出端或数据分发电路的第二输出端。在上述可能的实现方式中，数据分发电路具有两路输入，分别为从测试总线接收测试扫描数据，从相对应的被测电路的扫描输出通道接收测试输出数据；数据分发电路通过对第四选择器的配置实现输入的选择，以便使测试扫描数据和测试输出数据分别于不同的时间周期进行传输，在电路结构更简化的情况下，避免 数据的传输冲突。此外，数据分发电路还通过第五选择器的配置，控制数据分发电路的第二输出是否经过数据分发电路内部的寄存器，使得该数据分发电路所在的子测试电路对应的被测电路在不参与测试时，该数据分发电路的第一输入至第二输出不经过其内部的寄存器，以降低测试时间，从而进一步提高测试效率。
在第一方面的一种可能的实现方式中，每个子测试电路还可以包括控制器，其中该控制器可以包括：第一信号接口，第一信号接口与子测试电路中的每个第一选择器的控制端连接，用于控制第一选择器中的第一输入端与输出端连通或第一选择器中的第二输入端与输出端连通。第二信号接口，第二信号接口与子测试电路中的每个数据分发电路的第二控制端连接，用于控制数据分发电路的第一输入端和第二输出端直接连通或通过寄存器连通。在上述可能的实现方式中，通过对第一选择器的配置实现测试资源的动态分配，通过对第五选择器的配置实现被测电路在不参与测试时，将该不参与测试的被测电路所对应的子测试电路中的数据分发电路配置为旁路状态，即使数据分发电路的第一输入至第二输出不经过其内部的寄存器，以降低测试时间。因此，在该可选的方案中，通过控制器的第一信号接口输出移位选择控制信号来对第一选择器进行配置，通过控制器的第二信号接口输出旁路使能信号来对数据分发电路中的第五选择器进行配置。
在第一方面的一种可能的实现方式中，多个子测试电路的第j个子测试电路中，数据分发电路通过第一门控电路与第j个子测试电路相对应的被测电路的扫描输入通道连接，用于控制数据分发电路中的数据是否输出到与第j个子测试电路相对应的被测电路的扫描输入通道中。数据分发电路通过第二门控电路与第j个子测试电路相对应的被测电路的扫描输出通道之间连接，用于控制与第j个子测试电路相对应的被测电路的扫描输出通道的数据是否输出到数据分发电路中。在上述可能的实现方式中，通过在被测电路的扫描输入通道与数据分发电路之间，以及在被测电路的扫描输出通道与数据分发电路之间设置相应的门控电路，使得只有在相应的门控电路开启时，数据才能够在数据分发电路与被测电路的扫描输入通道之间传递，或在被测电路的扫描输出通道与数据分发电路之间传递，从而避免无效数据的传输。
在第一方面的一种可能的实现方式中，每个子测试电路还可以包括状态机，该状态机可以包括：第一状态控制接口，与子测试电路中的每个数据分发电路的第一控制端连接，用于生成输出捕获使能信号，控制子测试电路中的每个数据分发电路是否接收被测电路的扫描输出数据。第二状态控制接口，与第一门控电路的控制端连接，用于生成第一门控使能信号，控制子测试电路中的每个数据分发电路的数据是否传输至与子测试电路中对应的被测电路的扫描输入通道。第三状态控制接口，与第二门控电路的控制端连接，用于生成第二门控使能信号，控制与子测试电路中对应的被测电路的扫描输出通道的数据是否传输至被测电路对应的数据分发电路中。第四状态控制接口，与被测电路的扫描结构的扫描使能端连接，用于生成扫描使能信号，用于控制与子测试电路对应的被测电路的扫描结构是否进行测试扫描。在上述可能的实现方式中，通过状态机的第一状态控制接口生成输出捕获使能信号，用于配置数据分发电路中的第四选择器，来控制在当前时间数据分发电路接收测试总线的测试扫描数据还是接收被测电路的扫描输出数据。通过状态机的第二状态接口生成第一门控使能信号，来控 制数据分发电路的测试扫描数据是否传输至被测电路的扫描输入通道。通过状态机的第三状态接口生成第三门控使能信号，来控制被测电路的扫描输出通道的扫描数据是否传输至该被测电路对应的数据分发电路中。通过第四状态接口生成扫描使能信号，来控制被测电路的扫描结构是否开启测试扫描。通过状态机生成如上四种信号，来对测试电路的测试过程进行配置，简化配置过程。
在第一方面的一种可能的实现方式中，测试电路设置于被测电路的内部或外部。在上述可能的实现方式中，无论测试电路设置于被测电路的内部还是外部，对测试电路以及被测电路的电路运行均没有影响。
第二方面，提供一种测试电路。该测试电路包括：与多个被测电路分别对应的多个子测试电路，多个子测试电路用于将对应被测电路连接在测试总线上。每一个被测电路对应一个子测试电路，每个子测试电路可以将测试扫描所需的数据通过测试总线传输至对应的被测电路的扫描输入通道中，并将对应的被测电路的测试结果数据传输至测试总线输出。每个子测试电路还可以将测试总线动态分配给对应的被测电路。其中，多个子测试电路中的第j个子测试电路包括M个数据分发电路、M个第二选择器和CI j个第三选择器。第j个子测试电路可以为多个子测试电路中的任意一个子测试电路。第j个子测试电路中数据分发电路的数量以及第二选择器的数量M均与测试总线的位宽相等。第j个子测试电路中第三选择器的数量CI j与第j个子测试电路对应的被测电路的扫描输入通道的数量相等。M个数据分发电路的第一输入端分别连接测试总线的M个输入，即数据分发电路的第一输入端用于接收测试总线的测试扫描数据，M个数据分发电路的第二输出端分别连接测试总线的M个输出，即数据分发电路的第二输出端用于将测试结果数据输出至测试总线。在第j个子测试电路中，M个第二选择器中的每个第二选择器的CO j个输入端均分别连接与第j个子测试电路对应的被测电路的CO j个扫描输出通道。M个第二选择器的输出端分别连接子测试电路中的M个数据分发电路的第二输入端。第二选择器为多选一的多路选择器，第二选择器的输入端的数量与第j个子测试电路对应的被测电路的扫描输出通道数量有关，如被测电路的扫描输出通道数量为三个，则第二选择器可以选择三选一的多路选择器，用于选择被测电路的每个扫描输出通道所对应的数据分发电路，以及对应的测试总线。在第j个子测试电路中，CI j个第三选择器中的每个第三选择器的M个输入端均分别连接M个数据分发电路的第一输出端。CI j个第三选择器的输出端分别连接与第j个子测试电路对应的被测电路的CI j扫描输入通道。第三选择器也为多选一的多路选择器，第三选择器的输入端的数量与第j个子测试电路对应的数据分发电路的数量有关，数据分发电路的数量与测试总线的位宽有关，如测试总线的位宽为八位，则第三选择器可以为八选一的多路选择器，用于选择被测电路的扫描输入通道所对应的数据分发电路，以及对应的测试总线。
基于第二方面提供的测试电路，该测试电路将测试向量的输入数据，即扫描测试数据通过测试总线的输入传输至数据分发电路中，通过数据分发电路传输至被测电路的扫描输入通道。被测电路扫描结束后，被测电路的扫描输出通道的测试向量的输出数据，即测试结果数据通过数据分发电路传输至测试总线的输出完成被测电路的测试。通过第二选择器来配置被测电路的扫描输出通道选择连通的数据分发电路，通过第三 选择器来配置被测电路的扫描输入通道选择连通的数据分发电路。由于对应于每个子测试电路，测试总线的每位上均设置有数据分发电路，因此通过第二选择器和第三选择器的配置，既能够优化总线资源规划绕线拥塞的问题，还能够实现被测电路的每个扫描通道到任意总线资源的分配，从而使得总线资源的分配更加灵活。
在第二方面的一种可能的实现方式中，每个数据分发电路内均可以包括第四选择器、寄存器和第五选择器；该数据分发电路中的内部结构以及能够产生的技术效果，可参考上述第一方面中提供的测试电路的数据分发电路的内部结构以及技术效果，此处不再赘述。
在第二方面的一种可能的实现方式中，每个子测试电路还可以包括控制器。该控制器可以包括：第二信号接口，用于对每个子测试电路中的数据分发电路的第五选择器进行配置，用于控制数据分发电路的第一输入端和第二输出端直接连通或通过寄存器连通；多个第三信号接口，用于对每个子测试电路中的多个第二选择器进行配置，用于控制与子测试电路对应的被测电路的扫描输出通道与该子测试电路中的一个数据分发电路连通；多个第四信号接口，用于对每个子测试电路中的多个第三选择器进行配置，用于控制子测试电路选择其中一个数据分发电路与子测试电路对应的被测电路的扫描输入通道连通。在上述可能的实现方式中，通过控制器的第二信号接口输出旁路使能信号用来对数据分发电路中的第五选择器进行配置，实现被测电路在不参与测试时，将该不参与测试的被测电路所对应的子测试电路中的数据分发电路配置为旁路状态，即使数据分发电路的第一输入至第二输出不经过其内部的寄存器，而降低测试时间周期。通过控制器的第三信号接口输出扫描输出选择信号，通过扫描输出选择信号对第二选择器进行配置，选择对应的数据分发电路接收被测电路的扫描输出数据。同理，通过控制器的第四信号接口输出扫描输入选择信号，通过扫描输入选择信号对第三选择器进行配置，选择对应的数据分发电路来传输测试扫描数据至被测电路的扫描输入通道。通过该实现方式，简化配置过程，从而提高测试效率。
在第二方面的一种可能的实现方式中，在多个子测试电路的第j个子测试电路中，第三选择器通过第一门控电路与第j个子测试电路相对应的被测电路的扫描输入通道连接，用于控制数据分发电路中的数据是否输出到与第j个子测试电路相对应的被测电路的扫描输入通道中。与第j个子测试电路对应的被测电路的扫描输出通道通过第二门控电路与第二选择器连接，用于控制与第j个子测试电路相对应的被测电路的扫描输出通道的数据是否输出到数据分发电路中。在上述可能的实现方式中，通过在被测电路的扫描输入通道与数据分发电路之间，以及在被测电路的扫描输出通道与数据分发电路之间设置相应的门控电路，使得只有在相应的门控电路开启时，数据才能够在数据分发电路与被测电路的扫描输入通道之间，或被测电路的扫描输出通道与数据分发电路之间传递，从而避免无效数据的传输。
在第二方面的一种可能的实现方式中，每个子测试电路还可以包括状态机，该状态机可参考上述第一方面提供的测试电路中的状态机，此处不再赘述。
第三方面，提供另一种测试电路，该测试电路包括：与多个被测电路分别对应的多个子测试电路，子测试电路用于将被测电路连接在测试总线上。每一个被测电路对应一个子测试电路，每个子测试电路可以将测试扫描所需的数据通过测试总线传输至 对应的被测电路的扫描输入通道中，并将对应的被测电路的测试结果数据传输至测试总线输出。每个子测试电路还可以将测试总线动态分配给对应的被测电路。多个子测试电路中第j个子测试电路包括Nj组数据分发电路和CI j个或门。其中，第j个子测试电路可以为多个子测试电路中的任意一个子测试电路，第j个子测试电路中的数据分发电路的组数量Nj为对应的被测电路的扫描通道的数量，即为对应的被测电路的扫描输入通道的数量CI j和扫描输出通道的数量CO j中的最大值，即Nj＝Max(CI j,CO j)。CI j个或门分别对应Nj组数据分发电路中的CI j组数据分发电路，并且CI j个或门分别对应被测电路的CI j个扫描输入通道。Nj组数据分发电路中的CO j组数据分发电路分别对应被测电路的CO j个扫描输出通道。例如，被测电路的扫描通道数量为四个，该扫描通道数量为扫描输入通道数量和扫描输出通道数量中的最大值。则与被测电路对应的子测试电路中的数据分发电路的组数为四组，每一组数据分发电路可能会对应一个扫描输入通道，对应一个扫描输出通道。在该子测试电路中或门的数量为扫描输入通道数量，即三个，因此每个或门也会对应一组数据分发电路，并对应被测电路的一个扫描输入通道。在第j个子测试电路中，每组数据分发电路包括M个数据分发电路，M个数据分发电路分别连接在M位的测试总线上。Nj组数据分发电路中的每组数据分发电路通过每个数据分发电路的第一输入端和第二输出端依次串联在对应的测试总线上，即同一测试总线上的多个数据分发电路，按照先后顺序依次通过第一输入端和第二输出端连接在同一测试总线上。每组数据分发电路中的M个数据分发电路的第一输出端连接对应的或门的M个输入端，或门的输出端连接对应的被测电路的扫描输入通道。每组数据分发电路中的M个数据分发电路的第二输入端连接对应的被测电路的扫描输出通道。每个数据分发电路还被配置为用于控制数据分发电路复位，当数据分发电路被复位时，数据分发电路的输出为零，可以实现在每一组数据分发电路中，或门的输出值即为被选中的数据分发电路的第一输出端输出的值，也即为被选中的测试总线的输入的值。
基于第三方面提供的测试电路，该测试电路将测试向量的输入数据，即扫描测试数据通过测试总线的输入传输至数据分发电路中，通过数据分发电路传输至被测电路的扫描输入通道。被测电路扫描结束后，被测电路的扫描输出通道的测试向量的输出数据，即测试结果数据通过数据分发电路传输至测试总线的输出完成被测电路的测试。通过在被测电路的扫描输入通道与测试总线上连接的数据分发电路之间设置或门，通过或门对传输进入被测电路的扫描输入通道的数据进行择一选择，能够尽可能降低面积开销，以及优化绕线拥塞问题，从而降低测试成本。并且，通过对未被选择的数据分发电路进行复位操作，可以使得每个或门的输出值即为被选中的数据分发电路的第一输出端输出的值，从而实现正确的测试总线资源分配，更进一步简化了配置过程，提高测试效率。
在第三方面的一种可能的实现方式中，每个数据分发电路均可以包括第四选择器、寄存器和第五选择器。该数据分发电路的内部结构可参考上述第一方面提供的测试电路中的数据分发电路的内部结构，此处不再赘述。不同之处在于，数据分发电路的第二控制端还连接寄存器的复位端，用于控制寄存器复位。在上述可能的实现方式中，由于需要对数据分发电路进行复位，因此在数据分发电路需要通过第五选择器进行旁 路选择时，通过旁路使能信号即可控制数据分发电路中的寄存器进行复位，结构更加简单。
在第三方面的一种可能的实现方式中，每个子测试电路还可以包括控制器。该控制器可以包括：第二信号接口，第二信号接口与子测试电路中的每个数据分发电路的第二控制端连接，用于控制数据分发电路的第一输入端和第二输出端直接连通或通过寄存器连通，以及控制寄存器复位。在上述可能的实现方式中，通过控制器的第二信号接口输出旁路使能信号，用来对数据分发电路中的第五选择器进行配置，将该子测试电路中未被选择的数据分发电路置为旁路，并且控制数据分发电路的寄存器复位，满足被测电路的扫描输入通道对数据分发电路进行择一选择的要求，配置过程简单，进一步提高测试效率。
在第三方面的一种可能的实现方式中，多个子测试电路的第j个子测试电路中，或门通过第一门控电路与第j个子测试电路相对应的被测电路的扫描输入通道连接，用于控制数据分发电路中的数据是否输出到与第j个子测试电路相对应的被测电路的扫描输入通道中。与第j个子测试电路对应的被测电路的扫描输出通道通过第二门控电路与数据分发电路连接，用于控制与第j个子测试电路相对应的被测电路的扫描输出通道的数据是否输出到数据分发电路中。在上述可能的实现方式中，通过在被测电路的扫描输入通道与数据分发电路之间，以及在被测电路的扫描输出通道与数据分发电路之间设置相应的门控电路，使得只有在相应的门控电路开启时，数据才能够在数据分发电路与被测电路的扫描输入通道之间，或被测电路的扫描输出通道与数据分发电路之间传递，从而避免无效数据的传输。
在第三方面的一种可能的实现方式中，每个子测试电路还可以包括状态机，该状态机可参考上述第一方面提供的测试电路中的状态机，此处不再赘述。
第四方面，提供另一种测试电路，该测试电路包括：与多个被测电路分别对应的多个子测试电路，多个子测试电路用于分别将对应的被测电路连接在测试总线上。每一个被测电路对应一个子测试电路，每个子测试电路可以将测试扫描所需的数据通过测试总线传输至对应的被测电路的扫描输入通道中，并将对应的被测电路的测试结果数据传输至测试总线输出。每个子测试电路还可以将测试总线动态分配给对应的被测电路。其中，多个子测试电路中第j个子测试电路包括Nj个数据分发电路和M个第一选择器。第j个子测试电路可以为多个子测试电路中的任意一个子测试电路，第j个子测试电路中的数据分发电路的数量Nj为对应的被测电路的扫描通道的数量，即为对应的被测电路的扫描输入通道的数量CI j和扫描输出通道CO j的数量中的最大值，即Nj＝max(CI j,CO j)。数据分发电路用于接收测试总线的扫描测试数据并传输至被测电路的扫描输入通道中，并接收被测电路的扫描输出通道的测试结果数据，传输至测试总线输出。第一选择器可以为二选一的选择器，用于对第j+1个子测试电路所使用的的测试总线进行选择。在第j个子测试电路中，Nj个数据分发电路的第一输入端分别连接测试总线的Nj个输入，即数据分发电路的第一输入端用于接收测试总线的测试扫描数据；Nj个数据分发电路中的CI j个数据分发电路的第一输出端分别连接与第j个子测试电路对应的被测电路的CI j个扫描输入通道，即数据分发电路的第一输入端用于将从测试总线接收的测试扫描数据传输至对应的被测电路的扫描输入通道中；Nj个 数据分发电路中的CO j个数据分发电路的第二输入端，分别连接与第j个子测试电路对应的被测电路的CO j个扫描输出通道，即数据分发电路的第二输入端用于接收对应的被测电路的扫描输出通道输出的测试结果数据，测试结果数据通过数据分发电路的第二输出端输出至测试总线。多个子测试电路中的每个子测试电路的第一选择器数量M均等于测试总线的位宽，每个子测试电路中的M个第一选择器的输出端分别连接测试总线的M个输出，将每个子测试电路中的M个第一选择器分别与测试总线的M位一一对应。其中，M个第一选择器的第一输入端分别连接测试总线的M个输入。M个第一选择器中的Nj个第一选择器的第二输入端分别连接Nj个数据分发电路的第二输出端，其余的M-Nj个第一选择器的第二输入端分别连接M-Nj个未设置数据分发电路的测试总线的输入。每个第一选择器的第一输入端和第二输出端连接的总线不同。在第j个子测试电路中，第一选择器的第一输入端和第二输入端连接的测试总线不同，可以通过第一选择器选择第j+1个子测试电路所使用的测试总线。
基于第四方面提供的测试电路，该测试电路将测试向量的输入数据通过测试总线的输入传输至数据分发电路中，通过数据分发电路传输至被测电路的扫描输入通道，被测电路扫描结束后，被测电路的扫描输出通道的测试向量的输出数据通过数据分发电路传输至测试总线的输出完成被测电路的测试，通过对第一选择器的配置实现数据分发电路与测试总线的动态对应关系，使得测试资源能够得以动态分配。例如，将第j个子测试电路中的M个第一选择器配置为选择第一选择器的第一输入端与输出端连通，则第j+1个子测试电路中所分配到的测试总线为测试总线A。同理，如果将第j个子测试电路中的M个第一选择器配置为选择第一选择器的第二输入端与输出端连通，则第j+1个子测试电路中所分配到的测试总线为B。其中，第j+1个子测试电路中的数据分发电路会对应第j个子测试电路中的一组第一选择器，记做第一选择器X，因此测试总线A为第一选择器X被配置为选择第一选择器的第一输入端与输出端连通时，第一选择器X所连接的测试总线；测试总线B为第一选择器X被配置为选择第一选择器的第二输入端与输出端连通时，第一选择器X所连接的测试总线。通过该第四方面提供的测试电路能够极大程度地优化绕线拥塞的问题，以便降低测试成本，并且可以简化配置过程，而提高测试效率。此外，在第j个子测试电路中，第一选择器的第一输入端直接连接测试总线的输入，即可使第j个子测试电路所对应的被测电路不参与测试时，第j+1个子测试电路的的输入数据不经过第j个子测试电路中的数据分发电路，从而减少测试时间。
在第四方面的一种可能的实现方式中，多个子测试电路中第j个子测试电路中，按照预设的总线顺序，Nj个数据分发电路的第一输入端依次连接前Nj个总线的输入。M个第一选择器的第一输入端依次连接测试总线的M个输入。前M-Nj个第一选择器的第二输入端依次连接测试总线的后M-Nj个输入。后Nj个第一选择器的第二输入端依次连接Nj个数据分发电路的第二输出端。在上述可能的实现方式中，以一种预设的顺序将数据分发电路按照既定的规则分配到总线资源上，能够使该测试电路在保证测试资源动态分配的情况下，使得线路设计更加简单，便于接线。
在第四方面的一种可能的实现方式中，预设的总线顺序为总线位数的顺序或者倒序。在上述可能的实现方式中，预设的测试总线顺序是以一种特定的顺序，例如测试 总线的顺序或倒序，以此种方式可进一步使测试电路的线路结构简单有效，从而在一定程度上简化测试电路的结构，以便快速实现测试电路的接线要求。
在第四方面的一种可能的实现方式中，每个数据分发电路均可以包括第四选择器和寄存器。第四选择器的第一输入端和第二输入端分别连接数据分发电路的第一输入端和第二输入端，第四选择器的控制端连接数据分发电路的第一控制端。寄存器的输入端连接第四选择器的输出端，寄存器的输出端连接数据分发电路的第二输出端。数据分发电路的第一输出端连接数据分发电路的第一输入端或寄存器的输出端。在上述可能的实现方式中，数据分发电路具有两路输入，分别为从测试总线接收测试扫描数据，从相对应的被测电路的扫描输出通道接收测试输出数据；数据分发电路通过对第四选择器的配置实现输入的选择，以便使测试扫描数据和测试输出数据分别于不同的时间周期进行传输，在电路结构更简化的情况下，避免数据的传输冲突。
在第四方面的一种可能的实现方式中，每个子测试电路还可以包括控制器，控制器可以包括第一信号接口，第一信号接口与子测试电路中的M个第一选择器的控制端连接，用于控制第一选择器中的第一输入端与输出端连通或第一选择器中的第二输入端与输出端连通。在上述可能的实现方式中，通过控制器的第一信号接口输出移位选择控制信号用来对第一选择器进行配置，配置简单易行。当第一选择器被配置为第一选择器的第一输入端和输出端连通时，则该第一选择器所对应的子测试电路中，所有的测试总线资源均不会经过数据分发电路，因此在该子测试电路对应的被测电路不参与测试时，将第一选择器配置为第一选择器的第一输入端和输出端进行连通，可以降低测试时间。
在第四方面的一种可能的实现方式中，多个子测试电路的第j个子测试电路中，数据分发电路通过第一门控电路与第j个子测试电路相对应的被测电路的扫描输入通道连接，用于控制数据分发电路中的数据是否输出到与第j个子测试电路相对应的被测电路的扫描输入通道中。数据分发电路通过第二门控电路与第j个子测试电路相对应的被测电路的扫描输出通道之间连接，用于控制与第j个子测试电路相对应的被测电路的扫描输出通道的数据是否输出到数据分发电路中。在上述可能的实现方式中，通过在被测电路的扫描输入通道与数据分发电路之间，以及在被测电路的扫描输出通道与数据分发电路之间设置相应的门控电路，使得只有在相应的门控电路开启时，数据才能够在数据分发电路与被测电路的扫描输入通道之间，或被测电路的扫描输出通道与数据分发电路之间传递，从而避免无效数据的传输。
在第四方面的一种可能的实现方式中，每个子测试电路还可以包括状态机，该状态机可参考上述第一方面提供的测试电路中的状态机，此处不再赘述。
可选地，在上述第一方面至第四方面中的每个子测试电路还可以包括分频电路，分频电路分别连接总线时钟接口和被测电路的扫描时钟接口，用于将测试总线的时钟分频为被测电路的扫描时钟。在上述可选方案中，将测试总线的高速扫描时钟分频为被测电路中的低速扫描时钟，便于对被测电路进行扫描测试。
第五方面，提供一种集成电路。该集成电路包括：多个被测电路、测试总线以及如上第一方面至第四方面任一种可能的测试电路。多个被测电路通过测试电路中与被测电路对应的多个子测试电路连接在测试总线上。
第六方面，提供一种电子设备。该电子设备包括印刷电路板以及如上第五方面提供的集成电路；该集成电路设置于印刷电路板上。
第七方面，提供一种测试电路的设计方法。该测试电路的设计方法包括：获取每个被测电路的扫描输入通道数量、扫描输出通道数量，以及测试总线的总线位宽。根据测试总线的总线位宽、以及每个被测电路的扫描输入通道数量、扫描输出通道数量，在测试总线上配置每个被测电路所对应的子测试电路中的数据分发电路，生成如上第一方面至第四方面中任一种可能的测试电路。其中，每个被测电路所对应的子测试电路中的数据分发电路的数量，由测试总线的总线位宽，或每个被测电路的扫描输入通道和扫描输出通道数量确定。
第八方面，提供一种电路测试方法。该电路测试方法可用于EDA软件中，并适用于使用测试电路测试被测电路，其中该测试电路为如上第一方面至第四方面中任一种可能的测试电路。该电路测试方法包括：生成配置信息和测试向量；其中，配置信息用于配置所述测试电路；测试向量为被测电路的测试激励数据，并由被测电路的电路结构确定。
在第八方面的一种可能的实现方式中，该电路测试方法还可以包括：根据配置信息，配置测试电路。将测试向量传输至测试总线，并通过测试电路传输至被测电路的扫描输入通道中。将被测电路的测试结果数据，通过被测电路传输至测试总线的输出。
应当理解，在配置测试电路时，根据不同的测试电路结构，具体的配置方法和配置内容并不相同。
例如，在如上第一方面的测试电路中，可通过控制器的第一信号接口配置移位选择控制信号，来控制第一选择器选择的输入与输出的连接关系，当被测电路不参与测试时，将该被测电路所对应的子测试电路中的第一选择器置于直连模式，即第一选择器被配置为第一输入端与输出端连通。可通过控制器的第二信号接口配置旁路使能信号，使不参与测试的被测电路所对应的子测试电路中的数据分发电路置于旁路状态，即对应的数据分发电路中的第一输入端和第二输出端之间不经过寄存器。
在如上第二方面的测试电路中，可通过控制器配置扫描输出选择信号和扫描输入选择信号。其中扫描输出选择信号由第三信号接口输出，用于配置第二选择器，使与子测试电路对应的被测电路的扫描输出通道，与该子测试电路中的一个数据分发电路连通。扫描输入选择信号由第四信号接口输出，用于配置第三选择器，使子测试电路选择其中一个数据分发电路，与子测试电路对应的被测电路的扫描输入通道连通。
在如上第三方面的测试电路中，可通过控制器的第二信号接口配置旁路使能信号，旁路使能信号可以作为数据分发电路的复位信号，当数据分发电路被复位时，则表示数据分发电路未被选中，因此被选中的数据分发电路的第一输出端输出的值即为被选中的测试总线的输入的值，从而实现测试总线、数据分发电路以及被测电路的扫描通道之间的一一对应关系。
在如上第四方面的测试电路中，可通过控制器的第一信号接口配置移位选择控制信号，来控制第一选择器选择的输入与输出的连接关系，当被测电路不参与测试时，将该被测电路所对应的子测试电路中的第一选择器置于直连模式，即第一选择器被配置为第一输入端与输出端连通。
此外，在如上第一方面至第四方面的测试电路中，还通过状态机的第一状态控制接口配置输出捕获使能信号，通过状态机的第二状态控制接口配置第一门控使能信号，通过状态机的第三状态控制接口配置第二门控使能信号，通过状态机的第四状态控制接口配置扫描使能信号。输出捕获使能信号、第一门控使能信号、第二门控使能信号以及扫描使能信号的作用请参考第一方面中关于状态机的描述，此处不再赘述。
在第八方面的一种可能的实现方式中，将测试向量通过测试电路传输至被测电路的扫描输入通道中，包括：根据被测电路的扫描输入通道与测试总线的输入的对应关系，通过与被测电路的扫描输入通道对应的测试总线的输入，将测试向量传输至被测电路的扫描输入通道中。其中，被测电路的扫描输入通道与测试总线的输入的对应关系，由被测电路对应的子测试电路中的数据分发电路确定。例如，在如上第一方面和第四方面中的测试电路中，被测电路的扫描输入通道与对应的子测试电路中的数据分发电路属于一一对应关系。因此被测电路的扫描输入通道与测试总线的输入的对应关系，实际为该被测电路对应的子测试电路中的数据分发电路与测试总线的实际连接关系。在如上第二方面中的测试电路中，被测电路的扫描输入通道与该被测电路对应的子测试电路中的数据分发电路属于一对多的关系。因此被测电路的扫描输入通道与测试总线的输入的对应关系，可以由控制器配置的扫描输入选择信号来配置，配置后被测电路的扫描输入通道选中的数据分发电路所连接的测试总线，即对应于该被测电路的扫描输入通道。在如上第三方面中的测试电路中，被测电路的扫描输入通道与该被测电路对应的子测试电路中的数据分发电路属于一对多的关系。因此被测电路的扫描输入通道与测试总线的输入的对应关系，可以由旁路使能信号来控制，旁路使能信号可以控制数据分发电路进行复位，当数据分发电路未被复位时，则该数据分发电路被对应的被测电路的扫描输入通道选中。即被测电路的扫描输入通道与测试总线的输入的对应关系由未被复位的数据分发电路来确定。
在第八方面的一种可能的实现方式中，将被测电路的测试结果数据，通过被测电路传输至测试总线输出，包括：根据被测电路的扫描输出通道与测试总线的输出的对应关系，将被测电路的扫描输出通道输出的测试结果数据，传输至与被测电路的扫描输出通道对应的测试总线的输出；其中，被测电路的扫描输出通道与测试总线的输出的对应关系，由被测电路对应的子测试电路中的数据分发电路确定。被测电路的扫描输出通道与测试总线的输出的对应关系的确定方法，与上方的被测电路的扫描输入通道与测试总线的输入的对应关系的确定方法相类似，此处不再赘述。
进一步地，根据被测电路的扫描输入通道与测试总线的输入的对应关系，将测试向量通过与被测电路的扫描输入通道对应的测试总线的输入，传输至被测电路的扫描输入通道中，包括：测试总线在多个总线时钟周期，依次将测试向量传输至待测的被测电路的扫描输入通道中；其中，测试总线的其中一个输入对应的被测电路的扫描输入通道的数量超过一个。
应当说明的是，在对被测电路进行测试时，可能会有多个被测电路同时测试。然而测试总线的位宽有限，因此测试总线会被复用，即测试总线会通过时序拆分的方法对多个被测电路的扫描输入通道传输数据。在一个总线时钟周期内，测试总线只能给一个扫描输入通道传输数据，因此如果测试总线的其中一个输入需要给多个扫描输入 通道传输数据，则拆分在多个总线时钟周期内依次传输。
进一步地，根据被测电路的扫描输出通道与测试总线的输出的对应关系，将被测电路的扫描输出通道输出的测试结果数据，传输至与被测电路的扫描输出通道对应的测试总线的输出，包括：测试总线在多个时钟周期，依次将所述被测电路的扫描输出通道中的测试结果数据，传输至所述测试总线的输出，其中，测试总线的其中一个输出对应的被测电路的扫描输出通道的数量超过一个。测试结果数据传输至测试总线，同理扫描测试数据即测试向量传输至被测电路的扫描输入通道，此处不再赘述。
第九方面，提供一种计算机可读存储介质，计算机可读存储介质包括程序或指令，当程序或指令在计算机上运行时，使得计算机执行第八方面中任一种可能的电路测试方法。
第十方面，提供一种计算机程序产品，计算机程序产品包括：计算机程序代码，当计算机程序代码在计算机上运行时，使得计算机执行第八方面中任一种可能的电路测试方法。
可以理解地，上述提供的任一种集成电路、电子设备、测试电路的设计方法、电路测试方法以及计算机可读存储介质和计算机程序产品等，均可以由上文所提供的对应的测试电路来实现或与上文提供的对应的测试电路相关联，因此，其所能达到的有益效果可参考上文所提供的测试电路中的有益效果，此处不再赘述。
附图说明
图1为本申请的实施例提供的一种集成电路的结构示意图；
图2为图1中被测电路、测试总线和测试电路的结构示意图一；
图3为本申请的实施例提供的一种测试电路中的数据分发电路的结构示意图；
图4为本申请的实施例提供的一种测试电路中的门控电路的结构示意图；
图5为图1中被测电路、测试总线和测试电路的结构示意图二；
图6为图1中被测电路、测试总线和测试电路的结构示意图三；
图7为图1中被测电路、测试总线和测试电路的结构示意图四；
图8为图7中的数据分发电路的结构示意图；
图9为图1中被测电路、测试总线和测试电路的结构示意图五；
图10为图9中的数据分发电路的结构示意图；
图11为本申请的实施例提供的一种电路测试方法的流程图；
图12为图2所对应的一种测试方案的结构示意图；
图13为图2所对应的另一种测试方案的结构示意图；
图14为图13所对应的测试方案的扫描流程的波形示意图；
图15为本申请的实施例提供的一种测试电路设计方法的流程图。
附图标记：
01-被测电路；02-测试总线；03-测试电路；30-子测试电路；301-数据分发电路；302-第一选择器；303-控制器；304-状态机；305-分频电路；306-第一门控电路；307-第二门控电路；308-第二选择器；309-第三选择器；310-或门；3011-第四选择器；3012-寄存器；3013-第五选择器。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
以下，术语“第一”、“第二”等仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”等的特征可以明示或者隐含地包括一个或者更多个该特征。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以指物理上的直接连接，也可以指通过中间媒介实现电学上的连接，例如通过电阻、电感、电容，或其他电子器件实现的连接。
本申请一些实施例提供一种测试电路03(如图1所示)。该测试电路03用于对集成电路的多个功能模块进行测试，以便使集成电路能够完成既定的功能。不同的集成电路可实现的功能不一样，因此其功能模块也不一样。例如手机芯片中包括处理器模块、触摸屏控制模块、存储模块、电源管理模块等。
本申请一些实施例提供一种集成电路。图1为本申请的实施例提供的一种集成电路的结构示意图，请参考图1，该集成电路包括多个被测电路01、测试总线02以及测试电路03。其中，每个集成电路中的不同的被测电路可以实现相同的功能，也可以实现完全不同的功能。在该测试电路03中包括有与多个被测电路01相对应的多个子测试电路30，即每个被测电路01即对应一个子测试电路30。多个被测电路01通过多个子测试电路30连接在测试总线02上，使得该集成电路能够根据规划好的测试规则对多个被测电路01进行功能测试。
本申请实施例还提供一种的电子设备。在该电子设备中包括印刷电路板和如上实施例提供的集成电路，其中如上实施例提供的集成电路设置于印刷电路板上。该电子设备包括手机(mobile phone)、平板电脑(pad)、电脑、智能穿戴产品(例如，智能手表、智能手环)、虚拟现实(virtual reality，VR)终端设备、增强现实(augmented reality，AR)终端设备等电子产品。本申请实施例对上述电子设备的具体形式不做特殊限制。
下面结合附图，对本申请一些实施例提供的一种测试电路03进行详细说明。
图2为图1中被测电路、测试总线和测试电路的结构示意图一；图5为图1中被测电路、测试总线和测试电路的结构示意图二；图6为图1中被测电路、测试总线和测试电路的结构示意图三；图7为图1中被测电路、测试总线和测试电路的结构示意图四；图9为图1中被测电路、测试总线和测试电路的结构示意图五。请参考图2、图5、图6、图7和图9，并结合图1，在一个集成电路中可以包括实现不同功能或相同功能的多个功能模块，对于所有的功能模块均需要通过测试电路对其测试，以便知晓该功能模块的功能是否可以正常执行，此时的功能模块可以在测试的过程中称之为被测电路01。因此，本申请实施例中的一种测试电路可以包括：与多个被测电路01分别对应的多个如图1所示的子测试电路30，多个如图1所示的子测试电路30用于分 别将对应的被测电路01连接在测试总线02上，其中测试总线02对应于图2、图5、图6、图7和图9中的scanbus，其中scanbus_in为测试总线02的输入通道，scanbus_out为测试总线02的输出通道。
需要说明的是，如图1所示的子测试电路30用于分别将对应的被测电路01连接在测试总线上，其中，每个如图1所示的子测试电路30中可以包括多个数据分发电路301，每个如图1所示的子测试电路30中的数据分发电路301的数量，与该子测试电路对应的被测电路01中的扫描通道数量有关。例如图2所示的示例中，每个如图1所示的子测试电路30中的数据分发电路301的数量与对应的被测电路01中的扫描通道数量相等，被测电路01的扫描通道数量为该被测电路01的扫描输入通道数量和扫描输出通道数量之中的最大值。因此每个如图1所示的子测试电路30可以通过多个数据分发电路301将被测电路01连接在测试总线上。
具体来说，数据分发电路301，也可以称为动态路由单元(dynamic routing unit,DRU)，在该数据分发电路301中具有两个输入端和两个输出端，该数据分发电路301的第一输入端连接测试总线02的输入通道scanbus_in，第二输入端连接被测电路01的扫描输出通道channel_out，第一输出端连接被测电路01的扫描输入通道channel_in，第二输出端连接测试总线02的输出通道scanbus_out。
在本申请实施例的测试电路中，数据分发电路301接收测试总线02的输入通道scanbus_in的数据，该测试总线02的输入通道scanbus_in中输入的数据为被测电路01所需的测试向量。数据分发电路301将接收到的测试总线02的输入通道scanbus_in中的数据，通过被测电路01的扫描输入通道channel_in传输至被测电路01的扫描结构(scanstucture)中。其中，被测电路01的扫描结构为该被测电路01中用于对被测电路01进行扫描测试的结构块，被测电路01的扫描输入通道和扫描输出通道均连接在被测电路01中的扫描结构上，扫描结构接收到扫描输入通道channel_in的输入数据会对被测电路进行扫描测试，测试完成后测试结果数据通过扫描结构上的扫描输出通道channel_out输出。当被测电路01的扫描结构完成扫描测试时，数据分发电路301从被测电路01的扫描输出通道channel_out输出测试结果数据，并将测试结果数据传输到测试总线02的输出通道scanbus_out，并传输至测试软件中与预期的测试结果数据进行比对，或者直接在测试机台与预期的测试结果数据进行比对，来判断被测电路01是否存在故障，其中测试软件如EDA软件。
在整个测试电路中，数据分发电路301，即DRU承担的角色是将测试数据进行分发和传递。数据分发电路301在数据分发和传递的过程中，用于接收测试总线的输入通道scanbus_in的输入数据并传递至被测电路01的扫描输入通道channel_in中。被测电路01测试扫描结束后，数据分发电路301接收被测电路01的扫描输出通道channe_out的测试结果数据，并传输至测试总线02的输出通道scanbus_out输出完成测试。数据分发电路301与测试总线02的对应关系可以进行动态分配，如一个数据分发电路可以连接测试总线的多个输入或输出，并且可以多路选择器的方式来动态配置数据分发电路301与测试总线02的多个输入或输出的实际连接关系，来达到数据分发电路301与测试总线02动态连接的目的。通过数据分发电路301与测试总线之间02的动态连接关系，对测试总线02进行动态分配，以便满足对较大数量的被测电路01 进行测试的需求，从而优化线路连接，减少线路拥塞，并且降低面积开销。
对于数据分发电路301如何与测试总线进行动态连接，本申请的实施例中提供了多种示例性的实施例。
示例一，请参考图2，在图2中的电路结构示意图中，多个如图1所示的子测试电路30中，第j个子测试电路包括Nj个数据分发电路301和M个第一选择器302，第一选择器302参见图2中的移位选择器SHIFT_MUX对于第一选择器302与测试总线02的连接关系，可以按照如下关系设置：前Nj个第一选择器302的第一输入端依次连接Nj个数据分发电路301的第二输出端；后M-Nj个第一选择器302的第一输入端依次连接测试总线02的后M-Nj个输入通道scanbus_in，即在第j个子测试电路中，第一选择器被配置为第一选择器的第一输入端与输出端连通时，第一选择器的输出和输入所对应的测试总线相同，即直连模式。前M-Nj个第一选择器302的第二输入端依次连接测试总线的后M-Nj个输入通道scanbus_in；后Nj个第一选择器302的第二输入端依次连接Nj个数据分发电路301的第二输出端，即在第j个子测试电路中，第一选择器被配置为第一选择器的第二输入端与输出端连通时，第一选择的输出与输入所对应的测试总线不同，即移位连接模式。
需要说明的是，预设的测试总线顺序可以为测试总线位序的顺序或倒序。也可以为其他任何预设或指定的总线顺序，此处不做任何限定，例如预设的测试总线顺序为[0][2][4][6][1][3][5][7]，[0]为测试总线02的第[0]位(bit)，即scanbus_in[0]以及scanbus_out[0]。
请参考图2，在图2中第一选择器302与测试总线以及数据分发电路301的连接关系是按照测试总线位序的顺序来进行连接的，下面根据图2的示例，对该示例进行详细说明。
在图2中示例性地画出了三个被测电路01分别为被测电路A(core_A)、被测电路B(core_B)和被测电路C(core_C)；三个如图1所示的子测试电路30分别为与被测电路A对应的第一个子测试电路、与被测电路B对应的第二个子测试电路、与被测电路B对应的第三个子测试电路。
值得说明的是，在图2所示的示例中，虽然与被测电路A、被测电路B以及被测电路C分别对应的第一、二、三个子测试电路，设置在被测电路A、被测电路B以及被测电路C的内部，但实际上被测电路A、被测电路B以及被测电路C的电路结构可以不包括对应的子测试电路，即与被测电路A、被测电路B以及被测电路C对应的子测试电路仅仅在电路位置关系上，设置在被测电路A、被测电路B以及被测电路C的内部。
此外，与被测电路A、被测电路B以及被测电路C对应的子测试电路，是可以设置在被测电路A、被测电路B以及被测电路C的外部的，例如图5所示的电路结构。无论如图1所示的子测试电路30设置于被测电路01的内部还是外部，对测试电路以及被测电路01的电路运行均没有影响。因此本实施例不限定如图1所示的测试电路03以及如图1所示的子测试电路30是否设置在被测电路01的内部。
在图2中，被测电路A的扫描结构中具有三个扫描输入通道channel_in，分别为channel_in[0]、channel_in[1]、channel_in[2]；三个扫描输出通道channel_out，分别 为channel_out[0]、channel_out[1]、channel_out[2](请参考图2中的扫描结构A中的channel_in/out，详细对应关系图2中未示出)。
被测电路B的扫描结构中具有五个扫描输入通道channel_in，分别为channel_in[0]、channel_in[1]、channel_in[2]、channel_in[3]、channel_in[4]；以及五个扫描输出通道channel_out，分别为channel_out[0]、channel_out[1]、channel_out[2]、channel_out[3]、channel_out[4](图2中未示出)。
被测电路C的扫描结构中具有四个扫描输入通道channel_in，分别为channel_in[0]、channel_in[1]、channel_in[2]、channel_in[3]；以及，四个扫描输出通道channel_out，分别为channel_out[0]、channel_out[1]、channel_out[2]、channel_out[3](图2中未示出)。
因此被测电路A对应的第一个子测试电路中具有三个数据分发电路301，被测电路B对应的第二个子测试电路具有五个数据分发电路301，被测电路C对应的第三个子测试电路具有四个数据分发电路301。
示例性地，图2中的测试总线的位宽为八位，第一个子测试电路中的三个数据分发电路301的第一输入端分别连接在测试总线的前三位上，即scanbus_in[0]、scanbus_in[1]、scanbus_in[2]上；依次类推，第二个子测试电路中的五个数据分发电路301的第一输入端分别连接在测试总线的前五位上，即scanbus_in[0]、scanbus_in[1]、scanbus_in[2]、scanbus_in[3]、scanbus_in[4]上；第三个子测试电路的四个数据分发电路301的第一输入端分别连接在测试总线的前四位上，即scanbus_in[0]、scanbus_in[1]、scanbus_in[2]、scanbus_in[3]上。
对于第一选择器302，在该示例中，对应于每个子测试电路的第一选择器302的数量均与测试总线的位宽相等，即每个子测试电路的第一选择器302的数量均为八个。
因此，在被测电路A对应的第一个子测试电路中，前三个第一选择器302的第一输入端连接三个数据分发电路301的第二输出端，后五个第一选择器302的第一输入端连接后五位测试总线的输入scanbus_in，即连接测试总线的scanbus_in[3]、scanbus_in[4]、scanbus_in[5]、scanbus_in[6]、scanbus_in[7]。前五个第一选择器302的第二输入端连接后五位测试总线的输入scanbus_in，即连接测试总线的scanbus_in[3]、scanbus_in[4]、scanbus_in[5]、scanbus_in[6]、scanbus_in[7]，后三个第一选择器302的第二输入端连接三个数据分发电路301的第二输入端。
以此类推，在被测电路B对应的第二个子测试电路中，前五个第一选择器302的第一输入端连接五个数据分发电路301的第二输出端，后三个第一选择器302的第一输入端连接后三位测试总线的输入scanbus_in，即连接测试总线的scanbus_in[5]、scanbus_in[6]、scanbus_in[7]。前三个第一选择器302的第二输入端连接后三位测试总线的输入scanbus_in，即连接测试总线的scanbus_in[5]、scanbus_in[6]、scanbus_in[7]，后五个第一选择器302的第二输入端连接五个数据分发电路301的第二输入端。
在被测电路C对应的第三个子测试电路中，前四个第一选择器302的第一输入端连接四个数据分发电路301的第二输出端，后四个第一选择器302的第一输入端连接后四位测试总线的输入scanbus_in，即连接总线的scanbus_in[4]、scanbus_in[5]、scanbus_in[6]、scanbus_in[7]。前四个第一选择器302的第二输入端连接后四位测试总 线的输入scanbus_in，即连接测试总线的scanbus_in[4]、scanbus_in[5]、scanbus_in[6]、scanbus_in[7]，后四个第一选择器302的第二输入端连接四个数据分发电路301的第二输入端。
应当理解，在本示例中，为控制第一选择器302选择第一输入端与输出端连通，还是选择第二输入端与输出端连通，通过第一选择器302的控制端接收移位选择控制信号bus_shift来控制。该移位选择控制信号bus_shift通过控制器303配置生成，即对应于控制器303的第一信号接口，该控制器303可以由IEEE 1687标准(Internal JTAG,IJTAG)协议管脚进行配置。
当移位选择控制信号bus_shift指示第一选择器302选择第一输入端与输出端连通时，该子测试电路中的测试总线的输入scanbus_in和输出scanbus_out为直连的连接模式，例如测试总线的scanbus_in[0]对应测试总线的scanbus_out[0]，以此类推。
当移位选择控制信号bus_shift指示第一选择器302选择第二输入端与输出端连通是，该子测试电路中的测试总线的输入scanbus_in和输出scanbus_out为移位的连接模式，即对应于图2中的示例，在第一个子测试电路中，测试总线的scanbus_in[0]对应的是测试总线scanbus_out[5]；测试总线的scanbus_in[3]对应的是测试总线的scanbus_in[0]，以此类推，不再赘述。
值得说明的是，通过这样的移位连接方式，在某些测试场景中，可能有被测电路01不参与测试，对于不参与测试的被测电路01，其所对应的如图1所示的子测试电路30中的总线采用直连的模式，可以使参与测试的被测电路01在总线资源的分配上能够保持连续，从而降低测试电路配置的复杂度。
在图2所示的示例图中，假设被测电路B不参与测试，则将被测电路B对应的子测试电路中的移位选择控制信号bus_shift控制为指示第一选择器302选择第一输入端与输出端连通，即直连模式。因此对于被测电路A使用的测试总线的输入通道为测试总线02的scanbus_in[0]、scanbus_in[1]、scanbus_in[2]，输出通道为测试总线02的scanbus_out[1]、scanbus_out[2]、scanbus_out[3]，对于被测电路B占用的测试总线的输入通道为测试总线02的scanbus_in[3]、scanbus_in[4]、scanbus_in[5]、scanbus_in[6]，输出通道为测试总线02的scanbus_out[4]、scanbus_out[5]、scanbus_out[6]、scanbus_out[7]。
图3示出了本实施例提供的一种测试电路中的数据分发电路301的结构示意图，适用于图2所示的示例一，请参考图3，每个数据分发电路301均包括第四选择器3011、寄存器3012和第五选择器3013。
其中，第四选择器3011用于实现数据分发电路301选择，是从测试总线02接收数据，还是从对应的被测电路01的扫描输出通道channel_out接收数据。即第四选择器3011的第一输入端和第二输入端分别连接数据分发电路301的第一输入端和第二输入端。第四选择器3011的控制端连接数据分发电路301的第一控制端，用于控制选择输入总线数据至数据分发电路301，或选择输入对应的被测电路01的扫描输出数据至数据分发电路301。
寄存器3012用于将数据分发电路301接收的数据暂存，因此寄存器3012的输入端连接第四选择器3011的输出端，寄存器3012的输出端连接第五选择器3013的第一 输入端。
第五选择器3012用于实现对测试总线02的输入数据是否经过寄存器3012的配置，即第五选择器3013的第二输入端连接数据分发电路301的第一输入端，第五选择器3013的输出端连接数据分发电路301的第二输出端，第五选择器3013的控制端连接数据分发电路301的第二控制端。
数据分发电路301的第一输出端连接数据分发电路301的第一输入端或寄存器3012的输出端或数据分发电路301的第二输出端。
在存在不参与测试的被测电路01的情况下，为了减少测试时间，在上述的数据分发电路301中设置有第五选择器3013。其中，第五选择器3013为二选一的选择器，并通过控制器303配置生成旁路使能信号dru_bp，即对应于控制器303的第二信号接口，控制第五选择器3013的第一输入端连接其输出端，或者控制第五选择器3013的第二输入端连接其输出端。当旁路使能信号dru_bp指示第五选择器3013选择第一输入端连接其输出端时，该数据分发电路301为旁路状态，即数据分发电路301的第一输入端和第二输出端是直接连通的。因此当某被测电路01不参与测试时，将该被测电路01所对应的子测试电路中的所有数据分发电路301均置为旁路状态，在数据传输的过程中则不会占用额外的时间周期，从而可以减少测试时间。
示例二，请参考图6，在图6中的电路结构示意图中，多个如图1所示的子测试电路30中的第j个子测试电路包括M个数据分发电路301、M个第二选择器308和CI j个第三选择器309，其中第j个子测试电路可以为多个子测试电路中的任意一个子测试电路，第二选择器308请参见图6中的扫描输出选择器SO_MUX，第三选择器309请参见图6中的扫描输入选择器SI_MUX。第j个子测试电路中数据分发电路301的数量以及第二选择器308的数量M均与测试总线的位宽相等，第j个子测试电路中第三选择器309的数量CI j与第j个子测试电路对应的被测电路01的扫描输入通道channel_in的数量相等。M个数据分发电路301的第一输入端分别连接测试总线02的M个输入通道scanbus_in，即数据分发电路301的第一输入端用于接收测试总线02的测试扫描数据，M个数据分发电路301的第二输出端分别连接测试总线的M个输出通道scanbus_out。
在第j个子测试电路中，M个第二选择器308中的每个第二选择器308的CO j个输入端均分别连接与第j个子测试电路对应的被测电路01的CO j个扫描输出通道channel_out；M个第二选择器308的输出端分别连接子测试电路中的M个数据分发电路301的第二输入端。第二选择器308为多选一的多路选择器，第二选择器308的输入端的数量与第j个子测试电路对应的被测电路01的扫描输出通道channel_out数量有关，如被测电路01的扫描输出通道channel_out数量为三个，则第二选择器308可以选择三选一的多路选择器，用于选择被测电路01的每个扫描输出通道channel_out所对应的数据分发电路301，以及对应的测试总线02的输入通道scanbus_in或输出通道scanbus_out。
在第j个子测试电路中，CI j个第三选择器309中的每个第三选择器309的M个输入端均分别连接M个数据分发电路301的第一输出端，CI j个第三选择器309的输出端分别连接与第j个子测试电路对应的被测电路01的CI j扫描输入通道channel_in。 第三选择器309也为多选一的多路选择器，第三选择器309的输入端的数量与第j个子测试电路对应的数据分发电路301的数量有关，数据分发电路301的数量与测试总线02的位宽有关，如测试总线02的位宽为八位，则第三选择器309可以为八选一的多路选择器，用于选择被测电路01的扫描输入通道channel_in所对应的数据分发电路301，以及对应的测试总线02的输入通道scanbus_in或输出通道scanbus_out。
在本示例中，通过第二选择器308来配置被测电路01的扫描输出通道channel_out选择连通的数据分发电路301，通过第三选择器309来配置被测电路01的扫描输入通道channel_in选择连通的数据分发电路301。由于对应于每个如图1所示的子测试电路30，测试总线的每位上均设置有数据分发电路301，因此通过第二选择器308和第三选择器309的配置，既能够优化总线资源规划绕线拥塞的问题，还能够实现被测电路01的每个扫描通道到任意总线资源的分配，从而使得总线资源的分配更加灵活。
对应于图6中的示例，第二选择器308和第三选择器309均为多选一的多路选择器，对第二选择器308和第三选择器309的配置采用控制器303生成信号来进行配置，此时第二选择器308对应于扫描输出选择信号so_select，第三选择器309对应于扫描输入选择信号si_select。在控制器303中，扫描输出选择信号so_select由第三信号接口生成，扫描输入选择信号si_select由第四信号接口生成。也就是说，通过控制器303的第三信号接口输出扫描输出选择信号so_select，通过扫描输出选择信号so_select对第二选择器308进行配置，选择对应的数据分发电路301接收被测电路01的扫描输出数据。同理，通过控制器303的第四信号接口输出扫描输入选择信号si_select，通过扫描输入选择信号si_select对第三选择器309进行配置，选择对应的数据分发电路301来传输测试扫描数据至被测电路01的扫描输入通道channel_in。通过该配置方式，使得测试电路的配置简单易行。
应当说明的是，请参考图6，以图6中的被测电路A为例，第二选择器308为三选一的选择器，因此扫描输出选择信号so_select实际应该是一个两位的信号，输出的数值分别为00、01和10，这些信号分别对应被测电路A的一个扫描输出通道。第三选择器309为八选一的选择器，因此扫描输入选择信号si_select实际应该是一个三位的信号，输出的数值分别为000、001、010、011、100、101、110、111，这些信号分别对应被测电路A所对应的子测试电路中的一个数据分发电路。
还需要说明的是，在图6中的示例中，第二选择器308和第三选择器309均为多个，因此对应于每个第二选择器308会有一个扫描输出选择信号so_select(图中仅示例性的画出了一个扫描输出选择信号so_select)，对应于每个第三选择器309会有一个扫描输入选择信号si_select(图中仅示例性的画出了一个扫描输入选择信号si_select)。
另外，对应于图6中的示例，图6中的数据分发电路301的结构可以参考图3中示出的数据分发电路301的结构，此处不再赘述。
示例三，请参考图7，在图7中的电路结构示意图中，多个如图1所示的子测试电路30中第j个子测试电路包括Nj组数据分发电路301和CI j个或门310。其中，第j个子测试电路可以为多个子测试电路中的任意一个子测试电路，第j个子测试电路中的数据分发电路的组数量Nj为对应的被测电路的扫描通道的数量，即为对应的被测电 路的扫描输入通道channel_in数量的数量CI j和扫描输出通道channel_out的数量CO j中的最大值，即Nj＝max(CI j,CO j)。
CI j个或门310分别对应Nj组数据分发电路301中的CI j组数据分发电路301，并且CI j个或门310分别对应被测电路01的CI j个扫描输入通道channel_in。Nj组数据分发电路301中的CO j组数据分发电路301分别对应被测电路01的CO j个扫描输出通道channel_out。例如，被测电路01的扫描通道数量为四个，该扫描通道数量为扫描输入通道channel_in数量和扫描输出通道channel_out数量中的最大值，则与被测电路01对应的子测试电路中的数据分发电路301的组数为四组，每一组数据分发电路301可能会对应一个扫描输入通道channel_in，对应一个扫描输出通道channel_out。在该子测试电路中或门的数量为扫描输入通道channel_in的数量，即三个，因此每个或门301也会对应一组数据分发电路301，并对应被测电路01的一个扫描输入通道channel_in。
在第j个子测试电路中，每组数据分发电路301包括M个数据分发电路301，M个数据分发电路301分别连接在M位的测试总线上。
Nj组数据分发电路301中的每组数据分发电路301通过每个数据分发电路301的第一输入端和第二输出端依次串联在对应的测试总线上。即同一测试总线02上的多个数据分发电路301，按照先后顺序依次通过第一输入端和第二输出端连接在同一测试总线02上。
每组数据分发电路301中的M个数据分发电路301的第一输出端连接对应的或门310的M个输入端，或门310的输出端连接对应的被测电路01的扫描输入通道channel_in。
每组数据分发电路301中的M个数据分发电路301的第二输入端连接对应的被测电路01的扫描输出通道channel_out。
每个数据分发电路301还被配置为用于控制数据分发电路301复位，当数据分发电路301被复位时，数据分发电路301的输出为零，可以实现在每一组数据分发电路301中，或门310的输出值即为被选中的数据分发电路301的第一输出端输出的值，也即为被选中的测试总线02的输入通道scanbus_in输入的值。
在本示例三中，通过在被测电路01的扫描输入通道channel_in与测试总线上连接的数据分发电路301之间设置或门310，通过或门310对传输进入被测电路01的扫描输入通道channel_in的数据进行择一选择，能够尽可能降低面积开销，以及解决绕线拥塞问题。并且，通过对未被选择的数据分发电路301进行复位操作，可以使得每个或门310的输出值即为被选中的数据分发电路301的第一输出端输出的值，从而实现更灵活的测试总线资源分配。
对应于图7中的示例，为了对数据分发电路301进行复位，需要配置一个复位信号，由于该复位信号与旁路使能信号dru_bp属于关联信号，因此复位信号和旁路使能信号dru_bp可以共用，即通过控制器303的第二信号接口生成。也就是说，通过控制器303的第二信号接口输出旁路使能信号dru_bp，用来对数据分发电路301中的第五选择器3013进行配置，将该子测试电路中未被选择的数据分发电路301置为旁路，并且控制数据分发电路301的寄存器3012复位，满足被测电路01的扫描输入通道 channel_in对数据分发电路301进行择一选择的要求，配置操作简单。
值得说明的是，图7中所示的示例中的旁路使能信号dru_bp是一个多位的信号，每个子测试模块中的每个数据分发电路则对应旁路使能信号dru_bp的其中一位信号。
图8示出了对应于图7的数据分发电路301的结构示意图，在图7中所示的数据分发电路301，区别于图3所示的数据分发电路301，该数据分发电路301中的第二控制端还连接寄存器3012的复位端，用于控制寄存器3012进行复位。应当注意的是，复位信号与旁路使能信号可能属于相反的信号，假如复位信号与旁路使能信号的触发电平相反，可以将旁路使能信号进行非运算后再传输给寄存器301的控制端进行复位操作。
示例四，请参考图9，在图9中的电路结构示意图中，与多个被测电路01分别对应的多个子测试电路，多个如图1所示的子测试电路30用于分别将对应的被测电路01连接在测试总线上。其中，多个如图1所示的子测试电路30中第j个子测试电路包括Nj个数据分发电路301和M个第一选择器302，第一选择器302参见图2中的移位选择器SHIFT_MUX。第j个子测试电路可以为多个如图1所示的子测试电路30中的任意一个子测试电路。第j个子测试电路中的数据分发电路的数量Nj为对应的被测电路的扫描通道的数量，即为对应的被测电路的扫描输入通道的数量CI j和扫描输出通道CO j的数量中的最大值，即Nj＝max(CI j,CO j)。
在第j个子测试电路3中，Nj个数据分发电路301的第一输入端分别连接测试总线的Nj个输入通道scanbus_in，即数据分发电路301的第一输入端用于接收测试总线02的输入通道scanbus_in输入的测试扫描数据。Nj个数据分发电路301中的CI j个数据分发电路301的第一输出端，分别与第j个子测试电路对应的被测电路01的CI j个扫描输入通道channel_in连接，即数据分发电路301的第一输出端用于将从测试总线02接收的测试扫描数据传输至对应的被测电路01的扫描输入通道channel_in。Nj个数据分发电路301中的CO j个数据分发电路301的第二输入端分别与第j个子测试电路对应的被测电路01的CO j个扫描输出通道channel_out连接，即数据分发电路301的第二输入端用于接收对应的被测电路01的扫描输出通道channel_out输出的测试结果数据，测试结果数据通过数据分发电路301的第二输出端输出至测试总线02的输出通道scanbus_out。
多个如图1所示的子测试电路中的每个子测试电路的第一选择器302数量M均等于测试总线02的位宽，每个子测试电路中的M个第一选择器302的输出端分别连接测试总线02的M个输出通道scanbus_out，即将每个子测试电路中的M个第一选择器302分别与测试总线02的M位一一对应起来。
其中，M个第一选择器302的第一输入端分别连接测试总线02的M个输入通道scanbus_in。M个第一选择器302中的Nj个第一选择器302的第二输入端分别连接Nj个数据分发电路301的第二输出端，其余的M-Nj个第一选择器302的第二输入端分别连接M-Nj个未设置数据分发电路301的测试总线的输入通道scanbus_in。每个第一选择器302的第一输入端和第二输出端连接的总线不同。
本示例中的如图1所示的子测试电路30的线路结构类似于图2所示的示例一，不同之处在于，M个第一选择器302的第一输入端均连接了测试总线的M个输入。在第 j个子测试电路中，第一选择器的第一输入端直接连接测试总线的输入，即可使第j个子测试电路所对应的被测电路不参与测试时，第j+1个子测试电路的的输入数据不经过第j个子测试电路中的数据分发电路，从而减少测试时间。
在本示例四中，该测试电路中通过数据分发电路301将测试资源进行分配和传递，并通过对第一选择器302的配置，使得测试资源能够得以动态分配，极大程度地解决了绕线拥塞的问题，配置过程更加简单。
可选地，多个如图1所示的子测试电路30中第j个子测试电路中，按照预设的测试总线顺序，Nj个数据分发电路301的第一输入端依次连接前Nj个总线的输入通道scanbus_in。M个第一选择器302的第一输入端依次连接测试总线的M个输入。前M-Nj个第一选择器302的第二输入端依次连接测试总线的后M-Nj个输入。后Nj个第一选择器302的第二输入端依次连接Nj个数据分发电路301的第二输出端。在上述可能的实现方式中，以一种预设的顺序将数据分发电路301按照既定的规则分配到总线资源上，能够使该测试电路在保证测试资源动态分配的情况下，简化线路设计，便于接线。
关于预设的测试总线顺序的解释请参考图2所示的示例一，此处不再赘述。
需要说明的是，对应于图9所示的示例四，由于第一选择器302的第一输入端直接连接了总线的输入scanbus_in，因此在第一选择器302被配置为选择第一输入端和输出端连通时，该第一选择器302所连接的测试总线实际已经属于直连的状态，并且不经过数据分发电路301。
对应于图9中的示例四，图10示出了图9中的数据分发电路的结构示意图。请参考图10，每个数据分发电路301均包括第四选择器3011和寄存器3012。第四选择器3011的第一输入端和第二输入端分别连接数据分发电路301的第一输入端和第二输入端，第四选择器3011的控制端连接数据分发电路301的第一控制端。寄存器3012的输入端连接第四选择器3011的输出端，寄存器3012的输出端连接数据分发电路301的第二输出端。数据分发电路301的第一输出端连接数据分发电路301的第一输入端或寄存器3012的输出端。
此外，对第一选择器302的配置仍然可以采用控制器303生成移位选择控制信号bus_shift来控制，具体具体可参考图2所示的示例一，此处不再赘述。
还应当说明的是，图4示出了本申请的实施例提供的一种测试电路中的门控电路的结构示意图，该门控电路可对应于图2、图5、图6、图7和图9中的门控单元gate。为了使数据能够有效进行传输，在数据分发电路301向被测电路01的扫描输入通道channel_in传输数据时，以及在被测电路01的扫描输出通道channel_out向数据分发电路301传输数据时均设置有门控电路，分别为第一门控电路306和第二门控电路307。如图4所示，第一门控电路306和第二门控电路307集成到一起，在实际的电路中，第一门控电路306和第二门控电路307也可以分开为两个电路模块。
对应于图2和图5中的示例一以及图9中的示例四，多个如图1所示的子测试电路30的第j个子测试电路中，数据分发电路301通过第一门控电路306与第j个子测试电路相对应的被测电路01的扫描输入通道channel_in连接，用于控制数据分发电路301中的数据是否输出到与第j个子测试电路相对应的被测电路01的扫描输入通道 channel_in中。数据分发电路301通过第二门控电路307与第j个子测试电路相对应的被测电路01的扫描输出通道channel_out之间连接，用于控制与第j个子测试电路相对应的被测电路01的扫描输出通道channel_out的数据是否输出到数据分发电路301中。
例如，在第j个子测试电路中，Nj个数据分发电路301中的CI j个数据分发电路301的第一输出端分别连接CI j个第一门控电路306的输入端，CI j个第一门控电路306的输出端分别连接与第j个子测试电路对应的被测电路01的CI j个扫描输入通道channel_in。在第j个子测试电路中，与第j个子测试电路对应的被测电路01的CO j个扫描输出通道channel_out分别连接CO j个第二门控电路307的输入端，CO j个第二门控电路307的输出端分别连接Nj个数据分发电路301中的CO j个数据分发电路301的第二输入端。
对应于图6中的示例二，在多个如图1所示的子测试电路30的第j个子测试电路中，第三选择器309通过第一门控电路306与第j个子测试电路相对应的被测电路01的扫描输入通道channel_in连接，用于控制数据分发电路301中的数据是否输出到，与第j个子测试电路相对应的被测电路01的扫描输入通道channel_in中。与第j个子测试电路对应的被测电路01的扫描输出通道channel_out通过第二门控电路307与第二选择器308连接，用于控制与第j个子测试电路相对应的被测电路01的扫描输出通道channel_out的数据，是否输出到数据分发电路301中。
例如，与第j个子测试电路对应的被测电路01的CO j个扫描输出通道channel_out分别连接CO j个第二门控电路307的输入端，CO j个第二门控电路307的输出端分别连接M个第二选择器308中的每个第二选择器308的CO j个输入。CI j个第三选择器309的输出端分别连接CI j个第一门控电路306的输入端，CI j个第一门控电路306的输出端分别连接与第j个子测试电路对应的被测电路01的CI j个扫描输入通道channel_in。
对应于图7中的示例三，多个如图1所示的子测试电路30的第j个子测试电路中，或门310通过第一门控电路306与第j个子测试电路相对应的被测电路01的扫描输入通道channel_in连接，用于控制数据分发电路301中的数据是否输出到与第j个子测试电路相对应的被测电路01的扫描输入通道channel_in中。与第j个子测试电路对应的被测电路01的扫描输出通道channel_out通过第二门控电路307与数据分发电路301连接，用于控制与第j个子测试电路相对应的被测电路01的扫描输出通道channel_out的数据是否输出到数据分发电路301中。
例如，CI j个或门310的输出端分别连接CI j个第一门控电路306的输入端，CI j个第一门控电路306的输出端分别连接与第j个子测试电路对应的被测电路01的CI j个扫描输入通道channel_in。与第j个子测试电路对应的被测电路01的CO j个扫描输出通道channel_out分别连接CO j个第二门控电路307的输入端，CO j个第二门控电路307分别对应CO j组数据分发电路301，每组数据分发电路301中的每个数据分发电路301的第二输入端均连接对应的第二门控电路307的输出端。
应当理解，通过在被测电路01的扫描输入通道channel_in与数据分发电路301之间，以及在被测电路01的扫描输出通道channel_out与数据分发电路301之间设置相 应的门控电路，使得只有在相应的门控电路开启时，数据才能够在数据分发电路301与被测电路01的扫描输入通道channel_in之间，或被测电路01的扫描输出通道channel_out与数据分发电路301之间传递，从而避免无效数据的传输。
示例性地，为了方便对被测电路01进行测试，在整个测试过程中还需要进行一些参数的配置，例如通过状态机304对测试参数进行配置，因此在每个如图1所示的子测试电路30还包括状态机304，此处的状态机304为有限状态机(finite state machine,FSM)，该状态机304可以包括：第一状态控制接口、第二状态控制接口、第三状态控制接口和第四状态控制接口。该状态机304适用于图2、图5、图6、图7和图9所描述的示例。
其中，第一状态控制接口，用于生成输出捕获使能信号so_cap_en，并将该输出捕获使能信号so_cap_en传递至每个如图1所示的子测试电路30中的每个数据分发电路301的第一控制端，通过配置第四选择器3011，来控制在当前时间数据分发电路301接收测试总线的测试扫描数据还是接收被测电路01的扫描输出数据。
第二状态控制接口，用于生成第一门控使能信号ch_in_gate_en，并用该第一门控使能信号ch_in_gate_en对第一门控电路306进行配置，从而控制如图1所示的子测试电路30中的每个数据分发电路301的测试扫描数据，是否传输至与如图1所示的子测试电路30中对应的被测电路01的扫描输入通道channel_in。
第三状态控制接口，用于生成第二门控使能信号ch_out_gate_en，并用该第二门控使能信号ch_out_gate_en对第二门控电路进行配置，从而控制与如图1所示的子测试电路30中对应的被测电路01的扫描输出通道channel_out的扫描输出数据，是否传输至被测电路01对应的数据分发电路301中。(在图2、图5、图6、图7和图9中的在状态机FSM侧的信号标识为gate_en，可对应于第一门控电路306中的ch_in_gate_en和第二门控电路307中的ch_out_gate_en)。
第四状态控制接口，用于生成扫描使能信号scan_enable，并用该扫描使能信号对被测电路01的扫描结构进行配置，从而控制与如图1所示的子测试电路30对应的被测电路01的扫描结构是否进行测试扫描。
通过有限状态机304生成如上四种信号，来对测试电路的测试过程进行配置，配置简单易行。
可选地，对应于图2、图5、图6、图7和图9中的示例中，每个如图1所示的子测试电路30还可以包括分频电路305，分频电路305可采用分频器(dividers,DIV)。分频电路305分别连接总线时钟接口和被测电路01的扫描时钟接口，用于将测试总线的时钟scanbus_clk分频为被测电路01的扫描时钟scan_clock。在上述可选方案中，将测试总线的高速扫描时钟分频为被测电路01中的低速扫描时钟，便于对被测电路01进行扫描测试。
示例性地，图11为本申请实施例提供的一种电路测试方法的流程图。该电路测试方法可用于EDA软件中对被测电路进行测试，并且适用于使用图2、图5、图6、图7和图9中所示出的任一种测试电路，测试被测电路。
请参考图11，该电路测试方法包括：
S1101，生成配置信息和测试向量。应理解，配置信息和测试向量可以由EDA软 件生成，在测试过程中，EDA软件可以根据测试人员给定的一些测试参数，生成配置信息和测试激励数据。配置信息可用于配置测试电路；测试向量为被测电路的测试激励数据，并由被测电路的电路结构确定。
S1102，根据配置信息，配置测试电路。
在配置测试电路之前，需要明确同时测试的被测电路。因此在测试时可以对被测电路进行分组测试，分组的原则一般可以按照总测试时间最短的原则。
在配置测试电路时，根据不同的测试电路结构，具体的配置方法和配置内容并不相同。
例如，在如上图2和图5所示的测试电路中，可通过控制器303的第一信号接口配置移位选择控制信号bus_shift，来控制第一选择器302选择的输入与输出的连接关系，当被测电路不参与测试时，将该被测电路所对应的子测试电路中的第一选择器置于直连模式，即第一选择器302被配置为第一输入端与输出端连通。可通过控制器303的第二信号接口配置旁路使能信号dru_bp，使不参与测试的被测电路所对应的子测试电路中的数据分发电路置于旁路状态，即对应的数据分发电路301中的第一输入端和第二输出端之间不经过寄存器。
在如上图6所示的测试电路中，可通过控制器303配置扫描输出选择信号so_select和扫描输入选择信号si_select。其中扫描输出选择信号so_select由第三信号接口输出，用于配置第二选择器308，使与如图1所示的子测试电路30对应的被测电路01的扫描输出通道channel_out，与该子测试电路30中的一个数据分发电路301连通。扫描输入选择信号由第四信号接口输出，用于配置第三选择器309，使子测试电路30选择其中一个数据分发电路301，与子测试电路30对应的被测电路01的扫描输入通道channel_in连通。
在如上图7所示的测试电路中，可通过控制器303的第二信号接口配置旁路使能信号dru_bp，旁路使能信号dru_bp可以作为数据分发电路的复位信号，当数据分发电路301被复位时，则表示数据分发电路301未被选中，因此被选中的数据分发电路301的第一输出端输出的值即为被选中的测试总线02的输入的值，从而实现测试总线02、数据分发电路301以及被测电路01的扫描通道之间的一一对应关系。
在如上图9所示的测试电路中，可通过控制器303的第一信号接口配置移位选择控制信号bus_shift，来控制第一选择器302选择的输入与输出的连接关系，当被测电路不参与测试时，将该被测电路01所对应的如图1所示的子测试电路30中的第一选择器302置于直连模式，即第一选择器302被配置为第一输入端与输出端连通。
此外，在如上图2、图5、图6、图7和图9中所示出的任一种测试电路中，还通过状态机304的第一状态控制接口配置输出捕获使能信号so_cap_en，通过状态机304的第二状态控制接口配置第一门控使能信号ch_in_gate_en，通过状态机304的第三状态控制接口配置第二门控使能信号ch_out_gate_en，通过状态机304的第四状态控制接口配置扫描使能信号scan_enable。输出捕获使能信号so_cap_en、第一门控使能信号ch_in_gate_en、第二门控使能信号ch_out_gate_en以及扫描使能信号scan_enable的作用请参考图2所对应的示例中关于状态机的描述，此处不再赘述。
另外，配置过程中还需要配置分频电路305的分频比，其中分频电路305的分频 比是由被测电路01的扫描输入通道channel_in的数量、扫描输出通道channel_out的数量以及测试总线02的位宽来确定的，分频电路305的分频比R div的计算式为：
Figure PCTCN2020112660-appb-000001
其中，CI i为第i个待测的被测电路的扫描输入通道的数量，CO i为第i个待测得被测电路的扫描输出通道的数量，B为总线位宽。
S1103，将测试向量传输至测试总线，并通过测试电路传输至被测电路的扫描输入通道中。其中，测试向量为被测电路的测试激励数据，并由被测电路的电路结构确定。
将测试向量通过测试电路传输至被测电路的扫描输入通道中，包括：根据被测电路的扫描输入通道与测试总线的输入的对应关系，通过与被测电路的扫描输入通道对应的测试总线的输入，将测试向量传输至被测电路的扫描输入通道中。
其中，被测电路的扫描输入通道channel_in与测试总线02的输入通道scanbus_in的对应关系，由被测电路01对应的如图1所示的子测试电路30中的数据分发电路301确定。
例如，在如上图2和图5所示的测试电路中，被测电路的扫描输入通道channel_in与对应的如图1所示的子测试电路30中的数据分发电路301属于一一对应关系。因此被测电路的扫描输入通道channel_in与测试总线02的输入通道scanbus_in的对应关系，实际为该被测电路01对应的如图1所示的子测试电路30中的数据分发电路301与测试总线02的实际连接关系。
在如上图6所示的测试电路中，被测电路01的扫描输入通道channel_in与该被测电路01对应的如图1所示的子测试电路30中的数据分发电路301属于一对多的关系。因此被测电路的扫描输入通道channel_in与测试总线的输入通道scanbus_in的对应关系，可以由控制器303配置的扫描输入选择信号si_select来配置，配置后被测电路01的扫描输入通道channel_in选中的数据分发电路301所连接的测试总线02，即对应于该被测电路01的扫描输入通道channel_in。
在如上图7所示的测试电路中，被测电路01的扫描输入通道channel_in与该被测电路01对应的如图1所示的子测试电路30中的数据分发电路301属于一对多的关系。因此被测电路01的扫描输入通道channel_in与测试总线02的输入通道scanbus_in的对应关系，可以由旁路使能信号dru_bp来控制，旁路使能信号dru_bp可以控制数据分发电路301进行复位，当数据分发电路301未被复位时，则该数据分发电路301被对应的被测电路01的扫描输入通道channel_in选中。即被测电路01的扫描输入通道channel_in与测试总线02的输入通道scanbus_in的对应关系由未被复位的数据分发电路301来确定。
S1104，将被测电路的测试结果数据，通过被测电路传输至测试总线的输出。具体来说，根据被测电路的扫描输出通道与测试总线的输出的对应关系，将被测电路的扫描输出通道输出的测试结果数据，传输至与被测电路的扫描输出通道对应的测试总线的输出。
其中，被测电路的扫描输出通道与测试总线的输出通道的对应关系，由被测电路对应的子测试电路中的数据分发电路确定。被测电路01的扫描输出通道channel_out与测试总线02的输出通道scanbus_out的对应关系的确定方法，与S1103步骤中的被 测电路的扫描输入通道与测试总线的输入的对应关系的确定方法相类似，此处不再赘述。
应当说明的是，在测试电路对被测电路进行测试时，可能会有多个被测电路同时测试。然而测试总线的位宽有限，因此测试总线会被复用，即测试总线会通过时序拆分的方法对多个被测电路的扫描输入通道传输数据。在一个总线时钟周期内，测试总线只能给一个扫描输入通道传输数据或从一个扫描输出通道输出数据，因此如果测试总线的其中一个输入需要给多个扫描输入通道channel_in传输数据，或其中一个输出需要从多个扫描输出通道channel_out输出数据，则将传输的数据拆分在多个总线时钟周期内依次传输，具体示例可参考图13所示的测试方案。
此外，测试总线每传输一个周期的扫描数据，会增加一个总线时钟周期将数据分发电路中的测试向量数据传输至被测电路01的扫描输入通道channel_in中，并且将被测电路01的扫描输出通道channel_out的测试结果数据传输至数据分发电路中。其中一个周期的扫描数据是指所有待测的被测电路扫描一次的测试扫描数据。
对于上述电路的测试方法，下面以图2所示的测试电路为例进行说明。在图2所示的示例中，假设被测电路A(core_A)和被测电路C(core_C)同时进行扫描测试，而被测电路B(core_B)暂不进行测试。由于被测电路B不进行测试，因此将被测电路B所对应的子测试电路中的第一选择器302通过移位选择控制信号bus_shift配置为直连状态，即在该示例中将移位选择控制信号bus_shift置0，并且将被测电路B所对应的子测试电路中控制数据分发电路301旁路的旁路使能信号dru_bp置0，使数据分发电路301的第一输入端和第二输出端直接连通。
表1
Figure PCTCN2020112660-appb-000002
请参考图12所示的测试方案，图12是本实施例中图2所对应的一种测试方案的结构示意图。根据图12中显示的测试总线资源分配，对被测电路A和被测电路C同时进行扫描测试，而被测电路B暂不进行测试的情况下，测试总线02与被测电路01的扫描通道的对应关系请参考表1。
根据表1中测试总线02与被测电路01的扫描通道的对应关系，将测试向量通过测试总线的输入通道scanbus_in传输至被测电路的扫描输入通道中，并且将测试结果数据从被测电路的扫描输出通道传输至测试总线的输出通道scanbus_out。由于测试总线的每个输入或输出只对应被测电路的一个扫描通道，因此在一个周期就可以将测试向量以及测试结果数据传输完成。
在图2所示的示例中，假设被测电路A(core_A)、被测电路B(core_B)和被测电路C(core_C)同时进行测试，请参考图13所示的测试方案，图13是本实施例中图2所对应的另一种测试方案的结构示意图。
在此示例中，测试总线02的总线位宽为8位，被测电路A具有3个扫描通道，被测电路B具有5个扫描通道，被测电路C具有4个扫描通道，其中扫描通道的数量为被测电路的扫描输入通道数量和扫描输出通道数量之中的最大值。因此，对于测试总线的分配，被测电路A需要分配测试总线的3位输入输出，被测电路B需要分配测试总线的5位输入输出，即被测电路A和被测电路B已经将测试总线的资源全部占用，对于被测电路C则只能对测试总线进行复用，并将测试向量输入数据和测试结果数据分别在两个不同的时钟周期(cycle)进行输入或输出，在此种测试方案中，测试总线02与被测电路01的扫描输入通道的对应关系请参考表2，其中表2中的channel[x]可代表图2中的channel_in[x]或channel_out[x]，x为表示位数的整数，如在测试向量输入数据传输时，表2中的channel[x]代表channel_in[x]；如在测试结果数据传输时，表2中的channel[x]代表channel_out[x]。
表2
input Cycle1 Cycle2 output
scanbus_in[0] core_C.channel[0] core_A.channel[0] scanbus_out[4]
scanbus_in[1] core_C.channel[1] core_A.channel[1] scanbus_out[5]
scanbus_in[2] core_C.channel[2] core_A.channel[2] scanbus_out[6]
scanbus_in[3] core_C.channel[3] core_B.channel[0] scanbus_out[7]
scanbus_in[4] / core_B.channel[1] scanbus_out[0]
scanbus_in[5] / core_B.channel[2] scanbus_out[1]
scanbus_in[6] / core_B.channel[3] scanbus_out[2]
scanbus_in[7] / core_B.channel[4] scanbus_out[3]
在图13所示的测试方案中，按照上述图15显示的测试方法进行测试，最终得到的测试波形图如图14所示。
应当注意的是，上述图13所示的测试方案中仅仅是一种示例，在实际的被测电路在测试时，其中的一个被测电路的扫描通道数量也可能超过测试总线的位宽，在此情况下，测试总线02的一个输入通道scanbus_in对应的被测电路01的扫描输入通道channel_in数量可能超过一个，测试总线02的一个输出通道scanbus_out对应的被测电路01的扫描输入通道channel_out数量也可能超过一个，在此情况下同样也需要通过时序拆分的方式，在多个总线时钟周期进行数据的传输。
示例性地，图15为本申请实施例提供一种测试电路的设计方法的流程图。
请参考图15，该测试电路的设计方法包括：
S1501，获取每个被测电路的扫描输入通道数量、扫描输出通道数量，以及测试总线的总线位宽。
S1502，根据测试总线的总线位宽、以及每个被测电路的扫描输入通道数量、扫描输出通道数量，在测试总线上配置每个被测电路所对应的子测试电路中的数据分发电路，生成如上图2、图5、图6、图7和图9中所示出的任一种测试电路。
其中，每个被测电路所对应的子测试电路中的数据分发电路的数量，由测试总线的总线位宽，或每个被测电路的扫描输入通道和扫描输出通道数量确定。
在图2和图5的示例中，每个被测电路01所对应的如图1所示的子测试电路30中的数据分发电路301的数量，与该被测电路01中的扫描输入通道channel_in和扫描输出通道channel_out的数量关联，即等于相对应的被测电路中的扫描输入通道channel_in数量和扫描输出通道channel_out数量中的最大值。
本申请实施例还提供一种计算机可读存储介质，所述计算机存储介质中存储有计算机可读指令，当计算机读取并执行所述计算机可读指令时，使得计算机执行上述如图11所示的方法实施例中的电路测试方法。
本申请实施例还提供一种计算机程序产品，当计算机读取并执行所述计算机程序产品时，使得计算机执行上述如图11所示的方法实施例中的电路测试方法。
应理解，在本申请实施例中的处理器可以是中央处理单元(central processing unit，CPU)，该处理器还可以是其他通用处理器、数字信号处理器(digital signal processor，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现成可编程门阵列(field programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
还应理解，本申请实施例中的存储器可以是易失性存储器或非易失性存储器，或可包括易失性和非易失性存储器两者。其中，非易失性存储器可以是只读存储器(read-only memory，ROM)、可编程只读存储器(programmable ROM，PROM)、可擦除可编程只读存储器(erasable PROM，EPROM)、电可擦除可编程只读存储器(electrically EPROM，EEPROM)或闪存。易失性存储器可以是随机存取存储器(random access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的随机存取存储器(random access memory，RAM)可用，例如静态随机存取存储器(static RAM，SRAM)、动态随机存取存储器(DRAM)、同步动态随机存取存储器(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储器(double data rate SDRAM，DDR SDRAM)、增强型同步动态随机存取存储器(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储器(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储器(direct rambus RAM，DR RAM)。
上述实施例，可以全部或部分地通过软件、硬件(如电路)、固件或其他任意组合来实现。当使用软件实现时，上述实施例可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令或计算机程序。在计算机上加载或执行所述计算机指令或计算机程序时，全部或部分地产生按照本申请实施例所述的流程或功能。所述计算机可以为通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集合的服务器、 数据中心等数据存储设备。所述可用介质可以是磁性介质(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质。半导体介质可以是固态硬盘。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (19)

  1. 一种测试电路，其特征在于，包括：
    与多个被测电路分别对应的多个子测试电路，所述多个子测试电路用于分别将对应的被测电路连接在测试总线上；
    所述多个子测试电路中第j个子测试电路包括Nj个数据分发电路和M个第一选择器，其中，Nj和M均为正整数，M等于所述测试总线的位宽，并且M大于或等于Nj；
    所述第j个子测试电路为所述多个子测试电路中的任意一个子测试电路；
    在第j个所述子测试电路中，所述Nj个数据分发电路的第一输入端，分别与所述测试总线的Nj个输入连接，所述Nj个数据分发电路的第一输出端，与第j个子测试电路对应的所述被测电路的扫描输入通道连接，所述Nj个数据分发电路的第二输入端，与第j个子测试电路对应的所述被测电路的扫描输出通道连接；
    在第j个所述子测试电路中，所述M个第一选择器的输出端分别连接所述测试总线的M个输出；
    所述M个第一选择器中的Nj个所述第一选择器的第一输入端，分别连接Nj个所述数据分发电路的第二输出端，其余的M-Nj个所述第一选择器的第一输入端，分别连接M-Nj个未设置所述数据分发电路的所述测试总线的输入；
    所述M个第一选择器中的Nj个所述第一选择器的第二输入端，分别连接Nj个所述数据分发电路的第二输出端，其余的M-Nj个所述第一选择器的第二输入端，分别连接M-Nj个未设置所述数据分发电路的所述测试总线的输入；
    每个所述第一选择器的第一输入端和第二输入端连接的所述测试总线不同。
  2. 根据权利要求1所述的测试电路，其特征在于，所述多个子测试电路中第j个子测试电路中，按照预设的测试总线顺序，所述Nj个数据分发电路的第一输入端依次连接前Nj个所述测试总线的输入；
    前Nj个所述第一选择器的第一输入端依次连接所述Nj个数据分发电路的第二输出端；后M-Nj个所述第一选择器的第一输入端依次连接所述测试总线的后M-Nj个输入；
    前M-Nj个所述第一选择器的第二输入端依次连接所述测试总线的后M-Nj个输入；后Nj个所述第一选择器的第二输入端依次连接所述Nj个所述数据分发电路的第二输出端。
  3. 根据权利要求2所述的测试电路，其特征在于，所述预设的测试总线顺序为所述测试总线位序的顺序或倒序。
  4. 根据权利要求1至3任一项所述测试电路，其特征在于，所述Nj个数据分发电路中的CI j个所述数据分发电路的第一输出端，分别与所述第j个子测试电路对应的所述被测电路的CI j个扫描输入通道连接，所述Nj个数据分发电路中的CO j个所述数据分发电路的第二输入端，分别与所述第j个子测试电路对应的所述被测电路的CO j个扫描输出通道连接；其中，Nj＝Max(CI j,CO j)。
  5. 根据权利要求1至4任一项所述的测试电路，其特征在于，每个所述数据分发 电路均包括第四选择器、寄存器和第五选择器；
    所述第四选择器的第一输入端和第二输入端分别连接所述数据分发电路的第一输入端和第二输入端；
    所述寄存器的输入端连接所述第四选择器的输出端，所述寄存器的输出端连接所述第五选择器的第一输入端；
    所述第五选择器的第二输入端连接所述数据分发电路的第一输入端，所述第五选择器的输出端连接所述数据分发电路的第二输出端；
    所述数据分发电路的第一输出端，连接所述数据分发电路的第一输入端或所述寄存器的输出端或所述数据分发电路的第二输出端。
  6. 根据权利要求5所述的测试电路，其特征在于，每个所述子测试电路还包括控制器，所述控制器包括：
    第一信号接口，用于控制所述第一选择器中的第一输入端与输出端连通，或所述第一选择器中的第二输入端与输出端连通；
    第二信号接口，用于控制所述数据分发电路的第一输入端和第二输出端直接连通或通过所述寄存器连通。
  7. 根据权利要求1至6任一项所述的测试电路，其特征在于，所述多个子测试电路的第j个子测试电路中，所述数据分发电路通过第一门控电路与所述第j个子测试电路相对应的所述被测电路的扫描输入通道连接，用于控制所述数据分发电路中的数据是否输出到与所述第j个子测试电路相对应的所述被测电路的扫描输入通道中；
    所述数据分发电路通过第二门控电路与所述第j个子测试电路相对应的被测电路的扫描输出通道之间连接，用于控制与所述第j个子测试电路相对应的所述被测电路的扫描输出通道的数据是否输出到所述数据分发电路中。
  8. 根据权利要求7所述的测试电路，其特征在于，每个所述子测试电路还包括状态机，所述状态机包括：
    第一状态控制接口，用于生成输出捕获使能信号，控制所述子测试电路中的每个所述数据分发电路是否接收被测电路的扫描输出数据；
    第二状态控制接口，用于生成第一门控使能信号，控制所述子测试电路中的每个所述数据分发电路的数据，是否传输至与所述子测试电路中对应的被测电路的扫描输入通道；
    第三状态控制接口，用于生成第二门控使能信号，控制与所述子测试电路中对应的被测电路的扫描输出通道的数据，是否传输至所述被测电路中的所述数据分发电路中；
    第四状态控制接口，用于生成扫描使能信号，用于控制与所述子测试电路对应的所述被测电路的扫描结构是否进行测试扫描。
  9. 根据权利要求1至8任一项所述的测试电路，其特征在于，所述测试电路设置于所述被测电路的内部或外部。
  10. 根据权利要求1至9任一项所述的测试电路，其特征在于，每个所述子测试电路还包括分频电路，所述分频电路分别连接总线时钟接口和被测电路的扫描时钟接口，用于将所述测试总线的时钟分频为所述被测电路的扫描时钟。
  11. 一种集成电路，其特征在于，包括：多个被测电路、测试总线以及如权利要求1至10任一项所述的测试电路；
    所述多个被测电路通过所述测试电路中与所述被测电路对应的多个子测试电路连接在测试总线上。
  12. 一种电子设备，其特征在于：包括印刷电路板以及如权利要求11所述的集成电路；所述集成电路设置于所述印刷电路板上。
  13. 一种电路测试方法，其特征在于，适用于使用测试电路测试被测电路，所述测试电路为如权利要求1至10中任一项所述的测试电路；
    所述方法包括：
    生成配置信息和测试向量；
    其中，所述配置信息用于配置所述测试电路；所述测试向量为所述被测电路的测试激励数据，并由所述被测电路的电路结构确定。
  14. 根据权利要求13所述的电路测试方法，其特征在于，所述方法还包括：
    根据所述配置信息，配置所述测试电路；
    将测试向量传输至测试总线，并通过所述测试电路传输至所述被测电路的扫描输入通道中；
    将所述被测电路的测试结果数据，通过所述被测电路传输至所述测试总线的输出。
  15. 根据权利要求14所述的电路测试方法，其特征在于，所述将测试向量传输至测试总线，并通过所述测试电路传输至所述被测电路的扫描输入通道中，包括：
    根据所述被测电路的扫描输入通道与所述测试总线的输入的对应关系，通过与所述被测电路的扫描输入通道对应的测试总线的输入，将所述测试向量传输至所述被测电路的扫描输入通道中；
    其中，所述被测电路的扫描输入通道与所述测试总线的输入的对应关系，由所述被测电路对应的子测试电路中的数据分发电路确定。
  16. 根据权利要求14所述的电路测试方法，其特征在于，所述将所述被测电路的测试结果数据，通过所述被测电路传输至所述测试总线的输出，包括：
    根据所述被测电路的扫描输出通道与所述测试总线的输出的对应关系，将所述被测电路的扫描输出通道输出的测试结果数据，传输至与所述被测电路的扫描输出通道对应的所述测试总线的输出；
    其中，所述被测电路的扫描输出通道与所述测试总线的输出的对应关系，由所述被测电路对应的子测试电路中的数据分发电路确定。
  17. 根据权利要求15所述的电路测试方法，其特征在于，所述根据所述被测电路的扫描输入通道与所述测试总线的输入的对应关系，将所述测试向量通过与所述被测电路的扫描输入通道对应的测试总线的输入，传输至所述被测电路的扫描输入通道中，包括：
    所述测试总线在多个总线时钟周期，依次将所述测试向量传输至待测的所述被测电路的扫描输入通道中；其中，所述测试总线的其中一个输入对应的所述被测电路的扫描输入通道的数量超过一个。
  18. 根据权利要求16所述的电路测试方法，其特征在于，所述根据所述被测电路 的扫描输出通道与所述测试总线的输出的对应关系，将所述被测电路的扫描输出通道输出的测试结果数据，传输至与所述被测电路的扫描输出通道对应的所述测试总线的输出，包括：
    所述测试总线在多个时钟周期，依次将所述被测电路的扫描输出通道中的测试结果数据，传输至所述测试总线的输出，其中，所述测试总线的其中一个输出对应的所述被测电路的扫描输出通道的数量超过一个。
  19. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质包括程序或指令，当所述程序或指令在计算机上运行时，使得所述计算机执行如权利要求13至18中任一项所述的电路测试方法。
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