WO2022041011A1 - 一种用于ldo的瞬态提升电路、芯片系统及设备 - Google Patents

一种用于ldo的瞬态提升电路、芯片系统及设备 Download PDF

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Publication number
WO2022041011A1
WO2022041011A1 PCT/CN2020/111524 CN2020111524W WO2022041011A1 WO 2022041011 A1 WO2022041011 A1 WO 2022041011A1 CN 2020111524 W CN2020111524 W CN 2020111524W WO 2022041011 A1 WO2022041011 A1 WO 2022041011A1
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Prior art keywords
transistor
ldo
coupled
voltage
circuit
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PCT/CN2020/111524
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English (en)
French (fr)
Inventor
石玉楠
熊付荣
屈熹
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/111524 priority Critical patent/WO2022041011A1/zh
Priority to CN202080101677.8A priority patent/CN115668092A/zh
Priority to EP20950683.1A priority patent/EP4194991A4/en
Publication of WO2022041011A1 publication Critical patent/WO2022041011A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/575—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices characterised by the feedback circuit

Definitions

  • the present application relates to the field of electronic technology, and in particular, to a transient boost circuit, chip system and device for LDO.
  • LDOs with larger on-chip capacitors, or LDOs with off-chip capacitors are usually used to supply power to these subsystems.
  • the on-chip capacitors or off-chip capacitors here Voltage ripple due to load transients can be reduced, thereby guaranteeing the transient response of the LDO.
  • the on-chip capacitor will take up a larger chip area; if an LDO with an off-chip capacitor is used, the off-chip capacitor will take up additional PCB area.
  • the present application provides a transient boosting circuit, chip system and device for an LDO, which are used to reduce the chip area occupied by a capacitor while increasing the transient of the LDO.
  • a transient boost circuit for a low dropout linear regulator LDO comprising: an LDO for outputting a first voltage, where the first voltage may refer to various subsystems or systems The power supply voltage, the first voltage can also be referred to as the output voltage of the LDO; at least one detection circuit coupled with the LDO, each detection circuit in the at least one detection circuit includes a first capacitor, an amplifier and a second capacitor; wherein, the first detection circuit a capacitor for generating a coupling voltage according to the change of the first voltage, and coupling the coupling voltage to the amplifier, the first capacitor couples the first voltage to the amplifier by means of AC coupling; the amplifier is used for amplifying the Coupling the voltage to obtain the second voltage, for example, the amplifier can be a non-inverting amplifier or an inverting amplifier; the second capacitor is used to couple the second voltage to the LDO, that is, the second capacitor couples the second voltage by means of AC coupling into the LDO to form negative feedback, and the second voltage is used
  • the first voltage output by the LDO is coupled to the amplifier through the first capacitor, and the amplifier amplifies it, so that the first voltage can be achieved by using a smaller first capacitor while improving the transient state of the LDO.
  • the coupling of the first capacitor reduces the chip area occupied by the first capacitor; at the same time, the second voltage output by the amplifier is coupled to the LDO through the second capacitor, so that the second voltage does not directly act on the inherent loop of the LDO, thereby not destroying the LDO.
  • the DC characteristic ensures the stability of the LDO loop.
  • the amplifier is coupled with the LDO through the first capacitor and the second capacitor, so that the bias of the amplifier can be separated from the DC component of the first voltage, which effectively reduces the difficulty and complexity of biasing the amplifier, that is, the design of the amplifier does not need to consider offset, Matching and other requirements, thereby further reducing the chip area and achieving low power consumption and high energy efficiency.
  • the amplifier includes: a first transistor, a second transistor, a third transistor and a first resistor; wherein one pole of the first transistor, one pole of the second transistor and the One end of a resistor is coupled as the output end of the amplifier, the control end of the first transistor, the control end of the second transistor and the other end of the first resistor are coupled as the input end of the amplifier, the other end of the second transistor is coupled with the third transistor One pole of the first transistor and the other pole of the third transistor are coupled to the power supply terminal, the other to the ground terminal, and the control terminal of the third transistor is coupled to the bias voltage terminal.
  • the first transistor is an NMOS transistor
  • the second transistor and the third transistor are both PMOS transistors
  • the one electrode is a drain electrode
  • the other electrode is a source electrode
  • the control terminal is a gate electrode.
  • the amplifier is an inverter-based amplifier
  • the transconductance of the amplifier is the sum of the transconductance of the first transistor and the transconductance of the second transistor, under the same power consumption , its transconductance is twice that of ordinary amplifiers, thereby effectively improving energy efficiency
  • the third transistor is used to provide bias current for the amplifier to avoid the power consumption of the amplifier changing with the change of the power supply terminal voltage and process angle.
  • the amplifier is coupled to the LDO through the first capacitor and the second capacitor, so that only the first resistor can be used to bias the DC operating point of the amplifier independently, which effectively reduces the matching requirement of the amplifier.
  • the at least one detection circuit includes a first detection circuit, and the first detection circuit further includes: a compensation circuit coupled between the second capacitor and the LDO; the compensation circuit is configured to The second voltage adjusts the first voltage to keep the first voltage constant.
  • the compensation circuit can quickly and effectively realize the compensation for the first voltage output by the LDO based on the second voltage, thereby improving the transient performance of the LDO.
  • the compensation circuit includes: a fourth transistor, a fifth transistor, a sixth transistor, a second resistor, and a third resistor; wherein one pole of the fourth transistor, the third resistor One end of the sixth transistor and one pole of the sixth transistor are coupled to the first node, the other pole of the fourth transistor, the control end of the fifth transistor and one end of the second resistor are coupled as the input end of the compensation circuit, and one pole of the fifth transistor and the other end of the second resistor is coupled to the second node, the other end of the fifth transistor, the control end of the sixth transistor and the other end of the third resistor are coupled, and the other end of the sixth transistor is used as the output end of the compensation circuit ; One of the first node and the second node is coupled to the power supply terminal, and the other is coupled to the ground terminal.
  • the fifth transistor is an NMOS transistor, and both the fourth transistor and the sixth transistor are PMOS transistors; or, the fifth transistor is a PMOS transistor, and the fourth transistor and the sixth transistor are both NMOS transistors; the one pole is a drain. , the other is the source, and the control terminal is the gate.
  • the provided compensation circuit is simple and effective, so that the transient performance of the LDO can be improved, and the area of the chip can be further reduced.
  • the LDO has an output terminal, and the output terminal of the compensation circuit is coupled to the output terminal of the LDO.
  • the compensation circuit is fed back to the output end of the LDO to realize compensation for the first voltage output by the LDO, thereby improving the transient performance of the LDO.
  • the compensation circuit includes: a fourth transistor, a fifth transistor and a second resistor; wherein one pole of the fourth transistor is coupled to the first node, and the other pole of the fourth transistor is coupled to the first node.
  • the control terminal of the fifth transistor and one terminal of the second resistor are coupled as the input terminal of the compensation circuit, one terminal of the fifth transistor and the other terminal of the second resistor are coupled to the second node, and the other terminal of the fifth transistor is used as the input terminal of the compensation circuit.
  • the output terminal of the compensation circuit one of the first node and the second node is coupled to the power supply terminal, and the other is coupled to the ground terminal.
  • the fourth transistor is a PMOS transistor
  • the fifth transistor is an NMOS transistor
  • the one electrode is the drain electrode
  • the other electrode is the source electrode
  • the control terminal is the gate electrode.
  • the LDO includes an operational amplifier, a voltage regulating transistor and a sampling circuit, an output terminal of the operational amplifier is coupled to a control terminal of the voltage regulating transistor, and one pole of the voltage regulating transistor is coupled to a power supply terminal , the other pole of the voltage regulating transistor is coupled with the input end of the sampling circuit as the output end of the LDO, the output end of the sampling circuit is coupled with the positive phase input end of the operational amplifier, and the negative phase input end of the operational amplifier is used to receive the reference voltage;
  • the output end of the compensation circuit is coupled with the control end of the voltage regulating transistor.
  • the compensation circuit is fed back to the control terminal of the voltage regulating transistor to realize compensation for the first voltage output by the LDO, thereby improving the transient performance of the LDO.
  • the LDO includes: a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor, an eleventh transistor, and a fourth resistor; wherein one pole of the seventh transistor And one pole of the eighth transistor is coupled with the power supply terminal, the other pole of the seventh transistor is coupled with one pole of the ninth transistor as the output terminal of the LDO, the other pole of the eighth transistor, one pole of the tenth transistor and The control terminal of the seventh transistor is coupled to each other, the other pole of the ninth transistor, the other pole of the tenth transistor and one pole of the eleventh transistor are coupled, the other pole of the eleventh transistor is coupled to the ground terminal, and the tenth transistor is coupled to the ground terminal.
  • the control terminal of a transistor is coupled to one terminal of the fourth resistor, and the other terminal of the fourth resistor is connected to the bias voltage terminal.
  • the seventh transistor, the eighth transistor and the ninth transistor are all PMOS transistors
  • the tenth transistor and the eleventh transistor are all NMOS transistors
  • the one pole of the seventh transistor to the ninth transistor is the source
  • the The other electrode is the drain electrode
  • the one electrode of the tenth transistor and the eleventh transistor is the drain electrode
  • the other electrode is the source electrode
  • the control terminal is the gate electrode.
  • a FVF LDO is provided, so that the chip area occupied by the capacitor can be reduced while the transient state of the LDO is improved by at least one detection circuit coupled to the FVF LDO.
  • the at least one detection circuit further includes a second detection circuit, and a second capacitor in the second detection circuit is coupled to the output end of the amplifier and the control end of the eighth transistor.
  • the detection circuit is fed back to the control terminal of the eighth transistor to achieve compensation for the first voltage output by the LDO, thereby improving the transient performance of the LDO.
  • the at least one detection circuit further includes a third detection circuit, and the second capacitor in the third detection circuit is coupled to the output end of the amplifier and the control end of the tenth transistor.
  • the detection circuit is fed back to the control terminal of the tenth transistor to achieve compensation for the first voltage output by the LDO, thereby improving the transient performance of the LDO.
  • the at least one detection circuit further includes a fourth detection circuit, and the second capacitor in the fourth detection circuit is coupled to the output end of the amplifier and the control end of the eleventh transistor.
  • the detection circuit is fed back to the control terminal of the eleventh transistor to achieve compensation for the first voltage output by the LDO, thereby improving the transient performance of the LDO.
  • a chip system in a second aspect, includes a load circuit, and the transient boost for a low dropout linear regulator LDO as provided in the first aspect or any possible implementation manner of the first aspect Circuit; wherein, the transient boost circuit includes an LDO, and at least one detection circuit coupled with the LDO, the LDO is used for supplying power to the load circuit, and the at least one detection circuit is used for boosting the transient of the LDO.
  • the transient boost circuit includes an LDO, and at least one detection circuit coupled with the LDO, the LDO is used for supplying power to the load circuit, and the at least one detection circuit is used for boosting the transient of the LDO.
  • a third aspect provides a device comprising a load circuit and a circuit board, the circuit board comprising the LDO for a low dropout linear regulator as provided in the first aspect or any possible implementation of the first aspect
  • the transient boost circuit includes an LDO, and at least one detection circuit coupled with the LDO, the LDO is used to supply power to the load circuit, and the at least one detection circuit is used to improve the transient state of the LDO .
  • any of the chip systems and devices provided above include the transient boost circuit for LDO provided above. Therefore, for the beneficial effects that can be achieved, reference can be made to the above provided for LDO. The beneficial effects in the transient boost circuit are not repeated here.
  • FIG. 1 is a schematic structural diagram of an LDO according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a transient boost circuit for an LDO provided by an embodiment of the present application
  • FIG. 3 is a schematic structural diagram of an amplifier provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of another transient boost circuit for an LDO provided by an embodiment of the present application.
  • FIG. 5 is a schematic structural diagram of another transient boost circuit for an LDO provided by an embodiment of the present application.
  • FIG. 6 is a schematic structural diagram of an operational amplifier provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of a FVF LDO provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of another transient boost circuit for an LDO provided by an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of another transient boost circuit for an LDO provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of another transient boost circuit for an LDO provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of yet another transient boost circuit for an LDO provided by an embodiment of the present application.
  • circuits or other components may be described or referred to as “for” performing one or more tasks.
  • “for” is used to connote structure by indicating that the circuit/component includes structure (eg, circuitry) that performs one or more tasks during operation.
  • the specified circuit/component may be said to be used to perform the task even when the specified circuit/component is not currently operational (eg, not turned on).
  • Circuits/components used with the phrase “for” include hardware, such as circuits that perform operations, and the like.
  • At least one (a) of a, b or c may represent: a, b, c, a and b, a and c, b and c or a, b and c, where a, b and c can be It can be single or multiple.
  • words such as “first” and “second” do not limit the quantity and order.
  • the transistors involved in the embodiments of the present application may be metal oxide semiconductor (metal oxide semiconductor, MOS) field effect transistors (may be referred to as MOS transistors for short).
  • MOS metal oxide semiconductor
  • the control terminal of the transistor may refer to the gate of the transistor; in one possible embodiment, one pole of the transistor may refer to the source, and the other pole may refer to the drain; in another possible embodiment
  • one electrode of the transistor may be referred to as the drain electrode, and the other electrode may be referred to as the source electrode.
  • the technical solution of the present application can be applied to various subsystems or systems powered by a low dropout regulator (low dropout regulator, LDO).
  • LDO low dropout regulator
  • the technical solution of the present application can be applied to a radio frequency (RF) transceiver, a digital-to-analog converter (DAC), an analog-to-digital converter (analog-to-digital converter) powered by an LDO , ADC), high-speed digital circuits (eg, system-on-a-chip SoC) and phase-locked loops (phase loop lock, PLL), etc.
  • RF radio frequency
  • DAC digital-to-analog converter
  • ADC analog-to-digital converter
  • ADC analog-to-digital converter
  • PLL phase-locked loops
  • the LDO may include an operational amplifier A0, a voltage regulating transistor M0, a sampling circuit and a load capacitor C0.
  • the sampling circuit may include a resistor Ra and a resistor Rb.
  • the output terminal of the operational amplifier A0 is coupled with the control terminal of the voltage regulating transistor M0 (ie the gate of the PMOS), and one pole of the voltage regulating transistor M0 (ie the source of the PMOS) Coupled with the voltage input terminal (VDD), the other pole of the voltage regulating transistor M0 (ie the drain of the PMOS) is coupled with the input terminal of the sampling circuit as the output terminal of the LDO, and the output terminal of the sampling circuit is connected to the positive terminal of the operational amplifier A0.
  • the phase input terminal is coupled, the negative phase input terminal of the operational amplifier A0 is used to receive the reference voltage V REF , one end of the load capacitor C0 is coupled to the output terminal of the LDO, and the other end is coupled to the ground terminal (GND).
  • the sampling circuit samples the output voltage V OUT through the resistor Ra and the resistor Rb, and feeds back the collected voltage to the positive-phase input terminal of the operational amplifier; the collected voltage of the operational amplifier and the negative-phase input terminal of the operational amplifier receive
  • the reference voltage V REF is compared and amplified, and the amplified voltage is fed back to the input terminal through the gate of the voltage regulating transistor M0 , and dynamically regulated output is performed through the conduction voltage drop of the voltage regulating transistor M0 .
  • the output voltage V OUT of the LDO may overshoot or undershoot, resulting in poor transient performance of the LDO.
  • the overshoot may mean that the actual peak or valley value of the output voltage is greater than the set output voltage range, and the overshoot may mean that the actual peak or valley value of the output voltage is smaller than the set output voltage range.
  • an LDO with a larger on-chip capacitance or an LDO with an off-chip capacitance is usually used.
  • an embodiment of the present application provides a transient boost circuit for an LDO, the principle of which is that the transient performance of the LDO is boosted by at least one detection circuit coupled to the LDO, and the at least one detection circuit can be fed back to the LDO.
  • Any node for example, the output node or the internal node of the LDO, etc. only needs to form a negative feedback.
  • This circuit can be used to reduce the area occupied by capacitors in the LDO while improving the transient performance of the LDO, thereby reducing the area of the chip where the LDO is located.
  • FIG. 2 is a schematic structural diagram of a transient boost circuit for an LDO provided by an embodiment of the present application.
  • the circuit includes: an LDO 1, and at least one detection circuit 2 coupled to the LDO 1.
  • At least one detection circuit 2 may include one or more detection circuits.
  • the LDO 1 is used to output a first voltage V1 , which may refer to a voltage used to supply power to various subsystems or systems, and the first voltage V1 may also be referred to as an output voltage of the LDO 1 .
  • the LDO 1 is the LDO shown in FIG. 1
  • the first voltage V1 is the output voltage V OUT shown in FIG. 1 .
  • each of the at least one detection circuit 2 includes: a first capacitor C1, an amplifier 21 and a second capacitor C2.
  • the first capacitor C1 is used for generating a coupling voltage according to the change of the first voltage V1, and coupling the coupling voltage to the inverting amplifier 21, that is, the first capacitor C1 converts the first voltage V1 to the first voltage V1 by means of AC coupling (AC coupling). Coupled to the amplifier 21, the DC component of the first voltage V1 can be filtered out by the first capacitor.
  • the amplifier 21 is used for amplifying the coupling voltage to obtain the second voltage V2, that is, the second voltage V2 is the voltage after the coupling voltage is amplified.
  • the amplifier 21 may be a non-inverting amplifier or an inverting amplifier, which is used for the coupling voltage Amplify to obtain the second voltage V2.
  • the second capacitor C2 is used to couple the second voltage V2 to the LDO 1, that is, the second capacitor C2 couples the second voltage V2 to the LDO 1 by means of AC coupling, and the second voltage V2 is used to adjust the first voltage V1 to maintain The first voltage V1 is constant.
  • the use of the second capacitor C2 for coupling the second voltage V2 to the LDO 1 may include: the second capacitor C2 directly couples the second voltage V2 to the LDO 1, so as to maintain the first voltage V1 through the internal adjustment of the LDO 1
  • the first voltage V1 is constant; alternatively, the second capacitor C2 indirectly couples the second voltage V2 to the LDO 1, for example, the second capacitor C2 couples the second voltage V2 to the LDO 1 through an intermediate circuit, which can be used for The first voltage V1 is adjusted to keep the first voltage V1 constant, for example, the intermediate circuit is the compensation circuit 22 below.
  • maintaining the first voltage V1 constant can be understood as maintaining the first voltage V1 equal to the preset voltage value, or maintaining the first voltage V1 to fluctuate within a small range near the preset voltage value, for example, the preset voltage value is 5V, if the first voltage V1 fluctuates within the range of [4.9V, 5.1V], it can be understood that the first voltage V1 is constant.
  • the amplifier 21 may use an integrated amplifier module, for example, the amplifier 21 may use an operational transimpedance amplifier (OTA) module; or, the amplifier 21 may also be an amplifier constructed with electronic components.
  • OTA operational transimpedance amplifier
  • the amplifier 21 may include: a first transistor M1 , a second transistor M2 , a third transistor M3 and a first resistor R1 .
  • one pole of the first transistor M1, one pole of the second transistor M2 and one end of the first resistor R1 are coupled as the output end of the amplifier 21, the control end of the first transistor M1, the control end of the second transistor M2 and the first The other end of the resistor R1 is coupled as the input end of the amplifier 21, the other end of the second transistor M2 is coupled with one end of the third transistor M3, the other end of the first transistor M1 and the other end of the third transistor M3
  • One of the transistors M3 is coupled to the power supply terminal, the other is coupled to the ground terminal, and the control terminal of the third transistor M3 is coupled to the bias voltage terminal VBP.
  • the bias voltage terminal VBP is used to provide a bias voltage for the third transistor M3 , and the third transistor M3 acts as a current source to provide a bias current of the amplifier 21 .
  • the first transistor M1 and the second transistor M2 form a common source amplifier, and the first resistor R1 provides a static DC bias voltage through direct coupling, so that both the first transistor M1 and the second transistor M2 are in the saturation region or sub-region. threshold area.
  • the first voltage V1 is coupled to the input terminal of the amplifier 21 through the first capacitor C1 , it is reversely amplified by the first transistor M1 and the second transistor M2 , and the output terminal of the amplifier 21 outputs the second voltage V2 .
  • the first transistor M1 is an NMOS transistor
  • the second transistor M2 and the third transistor M3 are both PMOS transistors
  • the one pole is the drain
  • the other pole is the source
  • the control terminal The gate is taken as an example for description; in practical applications, the first transistor M1 , the second transistor M2 and the third transistor M3 can also be replaced with other transistors with similar functions, and FIG. 3 above does not limit the embodiments of the present application.
  • the above-mentioned amplifier 21 is an inverter based amplifier, and the transconductance of the amplifier 21 is the sum of the transconductance of the first transistor M1 and the transconductance of the second transistor M2.
  • the lead is twice that of a normal amplifier.
  • the third transistor M3 is used to provide a bias current for the amplifier 21 to prevent the power consumption of the amplifier 21 from changing with the change of the power supply terminal voltage and the process angle.
  • the amplifier 21 is coupled to the LDO 1 through the first capacitor C1 and the second capacitor C2, so that only the first resistor R1 can be used to bias the DC operating point of the amplifier 21 independently, effectively reducing the matching requirement of the amplifier 21.
  • the first voltage V1 output by the LDO 1 is coupled to the amplifier 21 through the first capacitor C1, and the amplifier 21 amplifies it, so that while improving the transient state of the LDO, a smaller first voltage V1 can be used.
  • a capacitor C1 realizes the coupling of the first voltage V1, reducing the chip area occupied by the first capacitor C1; at the same time, the second voltage V2 output by the amplifier 21 is coupled to the LDO 1 through the second capacitor C2, so that the second voltage V2 is not directly Acting on the inherent loop of LDO 1, it will not destroy the DC characteristics of LDO 1, and ensure the stability of the LDO 1 loop.
  • the amplifier 21 is coupled to the LDO 1 through the first capacitor C1 and the second capacitor C2, so that the bias of the amplifier 21 can be separated from the DC component of the first voltage V1, which effectively reduces the difficulty and complexity of the bias of the amplifier 21
  • the design of the amplifier 21 does not need to consider requirements such as offset and matching, thereby further reducing the chip area and realizing low power consumption and high energy efficiency.
  • the detection circuits can be divided into two types: the first type is a detection circuit including a compensation circuit, that is, the second capacitor C2 indirectly couples the second voltage V2 to the LDO 1.
  • the voltage V2 is coupled into the LDO 1;
  • the second is a detection circuit that does not include a compensation circuit, that is, the second capacitor C2 directly couples the second voltage V2 into the LDO 1.
  • the at least one detection circuit 2 may comprise at least one of the above two detection circuits. The two detection circuits are described below respectively.
  • the first type a detection circuit including a compensation circuit, that is, the second capacitor C2 indirectly couples the second voltage V2 into the LDO 1 .
  • At least one detection circuit 2 includes a first detection circuit 2a
  • the first detection circuit 2a includes: a compensation circuit 22 coupled between the second capacitor C2 and the LDO 1, the compensation circuit 22 is used to adjust the first detection circuit 22 according to the second voltage V2 A voltage V1 to keep the first voltage V1 constant.
  • the first detection circuit 2a herein may refer to a detection circuit including the compensation circuit 22 .
  • the compensation circuit 22 includes: a fourth transistor M4 , a fifth transistor M5 , a sixth transistor M6 , a second resistor R2 and a third resistor R3 .
  • One pole of the fourth transistor M4, one pole of the third resistor R3 and one pole of the sixth transistor M6 are coupled to the first node 1, the other pole of the fourth transistor M4, the control terminal of the fifth transistor M5 and the second One end of the resistor R2 is coupled to serve as the input end of the compensation circuit 22, one end of the fifth transistor M5 and the other end of the second resistor R2 are coupled to the second node 2, the other end of the fifth transistor M5, the other end of the sixth transistor M6
  • the control terminal is coupled with the other terminal of the third resistor R3, and the other pole of the sixth transistor M6 is used as the output terminal of the compensation circuit 22; one of the first node 1 and the second node 2 is coupled to the power supply terminal, and the other is connected to the ground end coupling.
  • At least one detection circuit 2 may include one or more first detection circuits, and the output ends of the one or more first detection circuits may be coupled to different nodes or the same node of the LDO 1, that is, multiple first detection circuits. The circuit is fed back to a different node of LDO 1 or to the same node.
  • at least one detection circuit 2 includes two first detection circuits, and one of the first detection circuits (represented as 2a-1 in FIG. 4 ) is the first node 1 in the compensation circuit 22 It is coupled with the power supply terminal, the second node 2 is coupled with the ground terminal, and the first node 1 in the compensation circuit 22 of the other first detection circuit (represented as 2a-2 in FIG.
  • the output terminals of the two first detection circuits are both coupled with the output terminal of the LDO 1 (that is, the two first detection circuits are fed back to the output terminal of the LDO 1 ), and the LDO is the LDO shown in FIG. 1 .
  • VBP and VBN respectively represent different bias voltage terminals.
  • the fifth transistor M5 is an NMOS transistor
  • the fourth transistor M4 and the sixth transistor M6 are both PMOS transistors
  • the fifth transistor M5 is used in the first detection circuit 2a-2 as an NMOS transistor.
  • PMOS transistors, the fourth transistor M4 and the sixth transistor M6 are both NMOS transistors, the one is the drain, the other is the source, and the control terminal is the gate as an example to illustrate.
  • the fourth transistor M4 , the fifth transistor M5 , and the sixth transistor M6 may also be replaced with other transistors having similar functions, and the foregoing FIG. 4 does not limit the embodiments of the present application.
  • the second resistor R2 and the third resistor R3 in FIG. 4 can also be replaced with other devices with similar functions.
  • the second resistor R2 can be replaced with an NMOS transistor
  • the third resistor R3 can be replaced with a PMOS transistor.
  • the gate of the NMOS transistor and the gate of the PMOS transistor can be connected to the bias voltage terminal.
  • the first detection circuit 2a-1 may be called an undershoot detection circuit, which is used to realize boost compensation of the first voltage V1 when the first voltage V1 output by the LDO 1 undershoots. Specifically, when the first voltage V1 output by the LDO 1 undershoots, the first detection circuit 2a-1 detects the undershoot glitch of the first voltage V1 through the first capacitor C1 (that is, the coupling is generated according to the change of the first voltage V1).
  • the down-shoot glitch is amplified by the amplifier 21 composed of M1, M2, M3 and R1 to obtain a second voltage V2; the second voltage V2 is coupled to the fifth transistor M5 in the compensation circuit 22 through the second capacitor C2 At this time, the fifth transistor M5 is turned on, the gate voltage of the sixth transistor M6 is pulled down, so that the sixth transistor M6 is turned on, and the drain voltage of the sixth transistor M6 is used to compensate the first voltage output by the LDO 1 V1, realizes the boost compensation of the first voltage V1, that is, realizes the transient compensation when the first voltage V1 undershoots.
  • the transient compensation is triggered only when the second voltage V2 output by the amplifier 21 exceeds the threshold voltage of the fifth transistor M5.
  • the drain current of the fourth transistor M4 passes through the second resistor R2 to form a bias voltage, which can reduce the threshold voltage of the fifth transistor M5, so that the signal coupled through the second capacitor C2 can immediately turn on the fifth transistor M5.
  • the fifth transistor M5 in the compensation circuit 22 is turned off, and the third resistor R3 is pulled up to turn off the sixth transistor M6, so that the first detection circuit 2a-1 has no influence on the LDO 1.
  • the first detection circuit 2a-2 may be called an overshoot detection circuit, which is used to realize the step-down adjustment of the first voltage V1 when the first voltage V1 output by the LDO1 is overshooted. Specifically, when an overshoot of the first voltage V1 output by the LDO 1 occurs, the first detection circuit 2a-2 detects the overshoot of the first voltage V1 through the first capacitor C1 (that is, the coupling is generated according to the change of the first voltage V1).
  • the up-shoot burr is amplified by the amplifier 21 composed of M1, M2, M3 and R1 to obtain the second voltage V2; the second voltage V2 is coupled to the compensation circuit 22 through the second capacitor C2
  • the fifth transistor M5 At this time, the fifth transistor M5 is turned on, the gate voltage of the sixth transistor M6 is pulled down, so that the sixth transistor M6 is turned on, and the drain voltage of the sixth transistor M6 is used to pull down the first output of the LDO 1.
  • the voltage V1 realizes the step-down adjustment of the first voltage V1, that is, realizes the transient compensation when the first voltage V1 overshoots.
  • the transient compensation is triggered only when the second voltage V2 output by the amplifier 21 exceeds the threshold voltage of the fifth transistor M5.
  • the drain current of the fourth transistor M4 passes through the second resistor R2 to form a bias voltage, which can reduce the threshold voltage of the fifth transistor M5, so that the signal coupled through the second capacitor C2 can immediately turn on the fifth transistor M5.
  • the fifth transistor M5 in the compensation circuit 22 is turned off, and the third resistor R3 pulls down to turn off the sixth transistor M6 , so that the first detection circuit 2a-2 has no influence on the LDO 1.
  • the compensation circuit 22 includes: a fourth transistor M4 , a fifth transistor M5 and a second resistor R2 .
  • one pole of the fourth transistor M4 is coupled to the first node 1
  • the other pole of the fourth transistor M4 the control terminal of the fifth transistor M5 and one terminal of the second resistor R2 are coupled as the input terminal of the compensation circuit 22
  • One pole of the five transistors M5 and the other end of the second resistor R2 are coupled to the second node 2
  • the other pole of the fifth transistor M5 is used as the output end of the compensation circuit 22; one of the first node 1 and the second node 2 is connected to The power terminal is coupled, and the other is coupled to the ground terminal.
  • At least one detection circuit 2 may include one or more first detection circuits, and the output ends of the one or more first detection circuits may be coupled to different nodes or the same node of the LDO 1, that is, multiple first detection circuits.
  • the circuit is fed back to a plurality of first detection circuits.
  • at least one detection circuit 2 includes a first detection circuit 2a, the first node 1 in the compensation circuit 22 of the first detection circuit 2a is coupled to the power supply terminal, and the second node 2 is connected to the ground terminal. Coupling; this LDO is the LDO shown in FIG.
  • the output end of the first detection circuit 2a is coupled with the gate of the voltage regulating transistor M0 in the LDO 1, that is, the first detection circuit 2a is fed back to the gate of the voltage regulating transistor M0 in the LDO 1 pole).
  • the working principle of the first detection circuit 2a is similar to that of the first detection circuit 2a-1 described above, and details are not described herein again in this embodiment of the present application.
  • the fourth transistor M4 is a PMOS transistor
  • the fifth transistor M5 is an NMOS transistor
  • the one pole is the drain
  • the other pole is the source
  • the control terminal is the gate as an example for illustration.
  • the fourth transistor M4 and the fifth transistor M5 can also be replaced by other transistors with similar functions.
  • description is given by taking as an example that at least one detection circuit 2 includes the first detection circuit 2a. The above-mentioned FIG. 5 does not limit the embodiment of the present application.
  • the first detection circuit shown in FIG. 4 and FIG. 5 can be applied to LDOs of other structures in addition to the LDO1 shown in FIG. 1 .
  • the operational amplifier A0 in the LDO 1 may be an operational amplifier constructed by a plurality of transistors, or the LDO may be a flipped voltage follower (FVF) LDO, that is, an FVF LDO.
  • FVF flipped voltage follower
  • the operational amplifier A0 in the LDO 1 may include a total of 12 transistors from T1 to T12.
  • the connection relationship between the transistors T1 and T12 is as shown in the figure, and VBP and VBN represent bias voltages respectively.
  • at least one detection circuit 2 can be fed back to any node in the operational amplifier A0 to form negative feedback, for example, at least one detection circuit 2 can be fed back to the gate of transistor T2 (also referred to as the gate of transistor T3 ) , or at least one detection circuit 2 is fed back to the gate of the transistor T5 (also referred to as the gate of the transistor T6 ).
  • the gate of transistor T2 also referred to as the gate of transistor T3
  • at least one detection circuit 2 is fed back to the gate of the transistor T5 (also referred to as the gate of the transistor T6 ).
  • the transistors T1, T4, T8, T9, T10, T11 and T12 are all PMOS transistors, and T2, T3, T5, T6 and T7 are all NMOS transistors as examples.
  • the above transistors T1 to T12 can also be replaced with other transistors having similar functions, or the operational amplifier A0 includes more or less transistors, and FIG. 6 above does not limit the embodiments of the present application.
  • the LDO 1 when the LDO 1 is a FVF LDO, the LDO 1 may include: a seventh transistor M7, an eighth transistor M8, a ninth transistor M9, a tenth transistor M10, an eleventh transistor M11, and a Four resistors R4.
  • one pole of the seventh transistor M7 and one pole of the eighth transistor M8 are both coupled to the power supply terminal, the other pole of the seventh transistor M7 is coupled to one pole of the ninth transistor M9 as the output terminal of the LDO 1, the eighth The other pole of the transistor M8, one pole of the tenth transistor M10 and the control terminal of the seventh transistor M7 are coupled (the voltage of the coupling point is represented as V FB2 ), the other pole of the ninth transistor M9 and the other pole of the tenth transistor M10 are coupled.
  • One pole is coupled to one pole of the eleventh transistor M11 (the voltage at the coupling point is represented as V FB1 ), the other pole of the eleventh transistor M11 is coupled to the ground terminal, and the control terminal of the eleventh transistor M11 is connected to the fourth resistor One end of R4 is coupled to each other, and the other end of the fourth resistor R4 is connected to the bias voltage terminal VBN1.
  • the seventh transistor M7 , the eighth transistor M8 and the ninth transistor M9 are all PMOS transistors
  • the tenth transistor M10 and the eleventh transistor M11 are all NMOS transistors
  • the seventh transistors M7 to the ninth transistors are all NMOS transistors.
  • the one electrode of the transistor is the source electrode
  • the other electrode is the drain electrode
  • the one electrode electrode of the tenth transistor M10 and the eleventh transistor M11 is the drain electrode
  • the other electrode electrode is the source electrode
  • the control terminal is the gate electrode
  • An example is used to illustrate; in practical applications, the seventh transistor M7 to the eleventh transistor M11 can also be replaced with other transistors with similar functions, and the above-mentioned FIG. 7 does not limit the embodiments of the present application.
  • the output end of the first detection circuit shown in the above-mentioned FIG. 4 or FIG. 5 can also be coupled with the output end of the FVF LDO or other nodes inside the FVF LDO.
  • the output end of the first detection circuit is connected to the FVF LDO.
  • the control end of the seventh transistor M7 is coupled, or the output end of the first detection circuit is coupled with the control end of the eighth transistor M8 in the FVF LDO, or the output end of the first detection circuit is coupled with the control end of the tenth transistor M10 in the FVF LDO terminal coupling, or the output terminal of the first detection circuit is coupled with the control terminal of the eleventh transistor M11 in the FVF LDO, etc.
  • the second detection circuit does not include a compensation circuit, that is, the second capacitor C2 directly couples the second voltage V2 into the LDO 1.
  • the following takes the structure of the FVF LDO shown in FIG. 7 as an example to illustrate.
  • At least one detection circuit 2 includes a second detection circuit 2b, and the second capacitor C2 in the second detection circuit 2b is coupled to the output end of the amplifier 21 and the eighth transistor M8
  • the control terminal (that is, the gate) of the second detection circuit 2b is fed back to the gate of the eighth transistor M8 in the FVF LDO.
  • the second detection circuit 2b does not work. It is assumed that the current flowing through the eleventh transistor M11 is I11, the current flowing through the eighth transistor M8 is I8, and the current flowing through the eighth transistor M8 is I8.
  • the second detection circuit 2b detects the undershoot glitch of the first voltage V1 through the first capacitor C1 (ie, the coupling voltage is generated according to the change of the first voltage V1), and the undershoot glitch passes through After the amplification process of the amplifier 21, a second voltage V2 is obtained; the second voltage V2 is coupled to the gate of the eighth transistor M8 in the FVF LDO through the second capacitor C2, and the gate-source (ie Vgs) voltage of the eighth transistor M8 decreases.
  • the second detection circuit 2b detects the upshoot burr of the first voltage V1 through the first capacitor C1 (ie, the coupling voltage is generated according to the change of the first voltage V1 ), and the upshoot burr passes through the amplifier 21 After the amplification process, the second voltage V2 is obtained; the second voltage V2 is coupled to the gate of the eighth transistor M8 in the FVF LDO through the second capacitor C2, and the gate-source voltage (ie Vgs) of the eighth transistor M8 increases. is larger to control the current I8 flowing through the eighth transistor M8 to increase.
  • At least one detection circuit 2 includes a third detection circuit 2c, and the second capacitor C2 in the third detection circuit 2c is coupled between the output end of the inverting amplifier 21 and the third detection circuit 2c.
  • the control terminal (ie the gate) of the tenth transistor M10, that is, the third detection circuit 2c is fed back to the gate of the tenth transistor M10 in the FVF LDO.
  • the second detection circuit 2b does not work. It is assumed that the current flowing through the eleventh transistor M11 is I11, the current flowing through the eighth transistor M8 is I8, and the current flowing through the eighth transistor M8 is I8.
  • the third detection circuit 2c detects the undershoot glitch of the first voltage V1 through the first capacitor C1 (ie, the coupling voltage is generated according to the change of the first voltage V1), and the undershoot glitch passes through
  • the second voltage V2 is obtained; the second voltage V2 is coupled to the gate of the tenth transistor M10 in the FVF LDO through the second capacitor C2, and the gate-source voltage of the tenth transistor M10 is ( That is, Vgs) increases to control the current I10 flowing through the tenth transistor M10 to increase, and at the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, I10 is greater than I8 at this time, so the gate voltage of the seventh transistor V BF2 will be pulled down, and the gate-source voltage (ie Vgs) of the seventh transistor M7 will increase rapidly, thereby increasing the output current of the FVF LDO, that is, to achieve trans
  • the third detection circuit 2c detects the upshoot burr of the first voltage V1 through the first capacitor C1 (ie, the coupling voltage is generated according to the change of the first voltage V1), and the upshoot burr is reversed by
  • the amplifier 21 amplifies, the second voltage V2 is obtained; the second voltage V2 is coupled to the gate of the tenth transistor M10 in the FVF LDO through the second capacitor C2, and at this time the gate-source voltage of the tenth transistor M10 (ie Vgs ) decreases to control the current I10 flowing through the tenth transistor M10 to decrease.
  • At least one detection circuit 2 includes a fourth detection circuit 2d, and the second capacitor C2 in the fourth detection circuit 2d is coupled between the output end of the inverting amplifier 21 and the first detection circuit 2d.
  • the control terminal (ie the gate) of the eleventh transistor M11, that is, the fourth detection circuit 2d is fed back to the gate of the eleventh transistor M11 in the FVF LDO.
  • the second detection circuit 2b does not work. It is assumed that the current flowing through the eleventh transistor M11 is I11, the current flowing through the eighth transistor M8 is I8, and the current flowing through the eighth transistor M8 is I8.
  • the fourth detection circuit 2d detects the undershoot burr of the first voltage V1 through the first capacitor C1 (ie, the coupling voltage is generated according to the change of the first voltage V1), and the undershoot burr passes through After amplifying processing by the inverting amplifier 21, a second voltage V2 is obtained; the second voltage V2 is coupled to the gate of the eleventh transistor M11 in the FVF LDO through the second capacitor C2, at this time the gate-source of the eleventh transistor M11
  • the voltage (ie Vgs) increases to control the current I10 flowing through the eleventh transistor M10 to increase, and at the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, the current I9 flowing through the ninth transistor M9 decreases, The current I10 flowing through the tenth transistor M10 increases, and at this time I10 is greater than I8, so that the gate voltage V BF2 of the seventh transistor will be pulled down, and the gate-source voltage (ie Vgs)
  • the fourth detection circuit 2d detects the overshoot burr of the first voltage V1 through the first capacitor C1 (ie, the coupling voltage is generated according to the change of the first voltage V1 ), and the overshoot burr passes through the amplifier 21
  • the second voltage V2 is obtained; the second voltage V2 is coupled to the gate of the eleventh transistor M11 in the FVF LDO through the second capacitor C2, at this time the gate-source voltage of the eleventh transistor M11 (ie Vgs ) decreases to control the current I11 flowing through the eleventh transistor M11 to decrease, and at the same time, since the current I8 flowing through the eighth transistor M8 remains unchanged, the current I9 flowing through the ninth transistor M9 increases, and the current I9 flowing through the tenth transistor M9 increases.
  • the current I10 of the transistor M10 decreases, and at this time I10 is smaller than I8, so that the gate voltage V BF2 of the seventh transistor will be pulled up, and the gate-source voltage (ie Vgs) of the seventh transistor M7 will decrease, thereby reducing the FVF
  • the output current of the LDO is the transient compensation when the first voltage V1 is overshooted.
  • multiple detection circuits can be used to realize the transient compensation of the LDO 1, and the output ends of the multiple detection circuits can be coupled with different nodes in the LDO 1, Just ensure that the coupling of each detection circuit and LDO 1 forms a negative feedback.
  • At least one detection circuit 2 may include four detection circuits and are denoted as 201 to 204 respectively, wherein the output end of the detection circuit 201 is connected to the FVF LDO.
  • the output terminal of the detection circuit 202 is coupled with the gate of the seventh transistor M7 in the FVF LDO
  • the output terminal of the detection circuit 203 is coupled with the gate of the eighth transistor M8 in the FVF LDO
  • the output of the detection circuit 204 The terminal is coupled to the gate of the eleventh transistor M11 in the FVF LDO.
  • the working principle of the detection circuit 201 is similar to that of the first detection circuit 2a-1 shown in FIG. 4, and the working principle of the detection circuit 202 is similar to that of the first detection circuit 2a shown in FIG. 5.
  • the working principle of the detection circuit 203 is similar to that of the second detection circuit 2b shown in FIG. 8, and the working principle of the detection circuit 204 is similar to that of the fourth detection circuit 2d shown in FIG. 10.
  • transient compensation is performed on the overshoot or undershoot of the LDO 1 through multiple detection circuits, so that the transient compensation of the LDO 1 can be realized faster, thereby improving the transient performance of the LDO 1;
  • the multiple detection circuits can be in a closed state, thereby not affecting the DC characteristics of the LDO 1 and ensuring the stability of the LDO 1 loop.
  • an embodiment of the present application further provides a chip system, the chip system includes a load circuit, and any one of the above-mentioned transient boost circuits for LDOs, the transient boost circuit includes an LDO, and the At least one detection circuit coupled to the LDO for powering the load circuit, the at least one detection circuit for increasing the transient of the LDO.
  • the load circuit may include at least one of the following: an RF transceiver, a DAC, an ADC, a high-speed digital circuit (eg, a system-on-a-chip SoC), and a PLL.
  • Embodiments of the present application also provide a device, the device includes a load circuit and a circuit board, the circuit board includes any one of the above-mentioned transient boost circuits for an LDO, the transient boost circuit includes an LDO, and The LDO is coupled to at least one detection circuit for powering the load circuit, the at least one detection circuit for increasing the transient of the LDO.
  • the load circuit may include at least one of the following: an RF transceiver, a DAC, an ADC, a high-speed digital circuit (such as a system-on-a-chip SoC), and a PLL; in addition, the device may be a communication device or a voltage regulator device. This embodiment of the present application does not specifically limit this.
  • transient boost circuit for the LDO can all be cited in the chip system or the device, which will not be repeated in the embodiments of the present application.
  • a non-transitory computer-readable storage medium for use with a computer having software for creating an integrated circuit, the computer-readable storage medium having stored thereon one or more A computer readable data structure, one or more computer readable data structures having photomask data for fabricating the transient boost circuit for the LDO provided by any one of the illustrations provided above.

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Abstract

一种用于LDO的瞬态提升电路、芯片系统及设备，用于在提高LDO的瞬态的同时，降低电容占用的芯片面积。该电路包括：LDO，用于输出第一电压；与所述LDO耦合的至少一个检测电路（2），所述至少一个检测电路（2）中的每个检测电路（2）包括第一电容、放大器（21）和第二电容；其中，所述第一电容，用于根据所述第一电压的变化产生耦合电压，并将所述耦合电压耦合至所述放大器（21）；所述放大器（21），用于放大所述耦合电压，以得到第二电压；所述第二电容，用于将所述第二电压耦合至所述LDO，所述第二电压用于调节所述第一电压以维持所述第一电压的恒定。

Description

一种用于LDO的瞬态提升电路、芯片系统及设备 技术领域
本申请涉及电子技术领域，尤其涉及一种用于LDO瞬态提升电路、芯片系统及设备。
背景技术
随着物联网(internet of things，IOT)系统的快速发展，可穿戴、植入式等IOT芯片的应用场景越来越多。在IOT系统中，诸如射频(radio frequency，RF)收发机、数模-模数转换器、高速数字电路和锁相环(phase loop lock，PLL)等一些高敏感的子系统对电源有较高的瞬态需求。因此，这些子系统通常使用一些具有高瞬态性能的低压差线性稳压器(low dropout regulator，LDO)来供电。
现有技术中，通常使用具有较大片内电容的LDO、或者带片外电容(该片外电容的电容值一般在uF级)的LDO对这些子系统供电，这里的片内电容或者片外电容可以减少由于负载瞬变引起的电压纹波，从而保证该LDO的瞬态响应。但是，如果使用具有片内电容的LDO，则该片内电容会占用较大的芯片面积；如果使用带片外电容的LDO，则该片外电容会占据额外的PCB面积。
发明内容
本申请提供一种用于LDO的瞬态提升电路、芯片系统及设备，用于在提高LDO的瞬态的同时，降低电容占用的芯片面积。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，提供一种用于低压差线性稳压器LDO的瞬态提升电路，该电路包括：LDO，用于输出第一电压，第一电压可以是指用于给各种子系统或者系统供电的电压，第一电压也可以称为LDO的输出电压；与该LDO耦合的至少一个检测电路，至少一个检测电路中的每个检测电路包括第一电容、放大器和第二电容；其中，第一电容，用于根据第一电压的变化产生耦合电压，并将耦合电压耦合至放大器，第一电容通过交流耦合(AC coupling)的方式将第一电压耦合至放大器中；放大器，用于放大该耦合电压，以得到第二电压，比如，该放大器可以是正相放大器或者反相放大器；第二电容，用于将第二电压耦合至LDO，即第二电容通过交流耦合的方式将第二电压耦合至LDO中以形成负反馈，第二电压用于调节第一电压以维持第一电压的恒定。
上述技术方案中，LDO输出的第一电压通过第一电容耦合至放大器，由放大器对其进行放大处理，从而在提高LDO的瞬态的同时，可以使用较小的第一电容来实现第一电压的耦合，减小第一电容占用的芯片面积；同时，放大器输出的第二电压通过第二电容耦合至LDO，使得第二电压不直接作用于LDO的固有环路中，从而不会破坏LDO的直流特性，保证了LDO环路的稳定性。另外，放大器通过第一电容和第二电容与LDO耦合，从而可以将放大器的偏置和第一电压的直流分量分开，有效降低放大器的偏置难度和复杂度，即放大器的设计不必考虑失调、匹配等需求，从而进一步减小了芯片面积，实现低功耗高能效。
在第一方面的一种可能的实现方式中，该放大器包括：第一晶体管、第二晶体管、 第三晶体管和第一电阻；其中，第一晶体管的一极、第二晶体管的一极和第一电阻的一端耦合作为放大器的输出端，第一晶体管的控制端、第二晶体管的控制端和第一电阻的另一端相耦合作为放大器的输入端，第二晶体管的另一极与第三晶体管的一极耦合，第一晶体管的另一极和第三晶体管的另一极中的一个与电源端耦合、另一个与接地端耦合，第三晶体管的控制端与偏置电压端耦合。可选的，第一晶体管为NMOS管，第二晶体管和第三晶体管均为PMOS管，所述一极为漏极，所述另一极为源极，所述控制端为栅极。上述可能的实现方式中，该放大器是基于反相器(invertor based)的放大器，该放大器的跨导为第一晶体管的跨导和第二晶体管的跨导之和，在功耗相同的情况下，其跨导是普通放大器的两倍，从而有效提高能效；第三晶体管用于为放大器提供偏置电流，避免放大器的功耗随电源端电压和工艺角的变化而变化。此外，放大器通过第一电容和第二电容与LDO耦合，使得只使用第一电阻就可以单独偏置放大器的直流工作点，有效的减小了放大器的匹配需求。
在第一方面的一种可能的实现方式中，至少一个检测电路包括第一检测电路，第一检测电路还包括：耦合在第二电容与LDO之间的补偿电路；该补偿电路，用于根据第二电压调节第一电压以维持第一电压的恒定。上述可能的实现方式中，通过补偿电路可以快速、有效地基于第二电压实现对LDO输出的第一电压的补偿，从而提高LDO的瞬态性能。
在第一方面的一种可能的实现方式中，该补偿电路包括：第四晶体管、第五晶体管、第六晶体管、第二电阻和第三电阻；其中，第四晶体管的一极、第三电阻的一端和第六晶体管的一极耦合于第一节点，第四晶体管的另一极、第五晶体管的控制端和第二电阻的一端相耦合作为补偿电路的输入端，第五晶体管的一极和第二电阻的另一端耦合于第二节点，第五晶体管的另一极、第六晶体管的控制端和第三电阻的另一端相耦合，第六晶体管的另一极作为补偿电路的输出端；第一节点和第二节点中的一个与电源端耦合、另一个与接地端耦合。可选的，第五晶体管为NMOS管，第四晶体管和第六晶体管均为PMOS管；或者，第五晶体管为PMOS管，第四晶体管和第六晶体管均为NMOS管；所述一极为漏极，所述另一极为源极，所述控制端为栅极。上述可能的实现方式中，提供的补偿电路简单有效，从而可以在提高LDO的瞬态性能的同时，进一步降低芯片的面积。
在第一方面的一种可能的实现方式中，该LDO具有输出端，补偿电路的输出端与LDO的输出端耦合。上述可能的实现方式中，通过将补偿电路反馈至LDO的输出端，以实现对LDO输出的第一电压的补偿，从而提高LDO的瞬态性能。
在第一方面的一种可能的实现方式中，该补偿电路包括：第四晶体管、第五晶体管和第二电阻；其中，第四晶体管的一极耦合于第一节点，第四晶体管的另一极、第五晶体管的控制端和第二电阻的一端相耦合作为补偿电路的输入端，第五晶体管的一极和第二电阻的另一端耦合于第二节点，第五晶体管的另一极作为补偿电路的输出端；第一节点和第二节点中的一个与电源端耦合、另一个与接地端耦合。可选的，第四晶体管为PMOS管，第五晶体管为NMOS管，所述一极为漏极，所述另一极为源极，所述控制端为栅极。上述可能的实现方式中，提供的补偿电路简单有效，从而可以在提高LDO的瞬态性能的同时，进一步降低芯片的面积。
在第一方面的一种可能的实现方式中，该LDO包括运算放大器、调压晶体管和取样电路，运算放大器的输出端与调压晶体管的控制端耦合，调压晶体管的一极与电源端耦合，调压晶体管的另一极与取样电路的输入端相耦合作为LDO的输出端，取样电路的输出端与运算放大器的正相输入端耦合，运算放大器的负相输入端用于接收参考电压；其中，补偿电路的输出端与调压晶体管的控制端耦合。上述可能的实现方式中，通过将补偿电路反馈至调压晶体管的控制端，以实现对LDO输出的第一电压的补偿，从而提高LDO的瞬态性能。
在第一方面的一种可能的实现方式中，该LDO包括：第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和第四电阻；其中，第七晶体管的一极和第八晶体管的一极均与电源端耦合，第七晶体管的另一极与第九晶体管的一极相耦合作为LDO的输出端，第八晶体管的另一极、第十晶体管的一极和第七晶体管的控制端相耦合，第九晶体管的另一极、第十晶体管的另一极和第十一晶体管的一极相耦合，第十一晶体管的另一极与接地端耦合，第十一晶体管的控制端与第四电阻的一端相耦合，第四电阻的另一端与偏置电压端连接。可选的，第七晶体管、第八晶体管和第九晶体管均为PMOS管，第十晶体管和第十一晶体管均为NMOS管，第七晶体管至第九晶体管的所述一极为源极、所述另一极为漏极，第十晶体管和第十一晶体管的所述一极为漏极、所述另一极为源极，所述控制端为栅极。上述可能的实现方式中，提供了一种FVF LDO，从而通过与该FVF LDO耦合的至少一个检测电路可以在提高LDO的瞬态的同时，降低电容占用的芯片面积。
在第一方面的一种可能的实现方式中，至少一个检测电路还包括第二检测电路，第二检测电路中的第二电容耦合在放大器的输出端与第八晶体管的控制端。上述可能的实现方式中，通过将检测电路反馈至第八晶体管的控制端，以实现对LDO输出的第一电压的补偿，从而提高LDO的瞬态性能。
在第一方面的一种可能的实现方式中，至少一个检测电路还包括第三检测电路，第三检测电路中的第二电容耦合在放大器的输出端与第十晶体管的控制端。上述可能的实现方式中，通过将检测电路反馈至第十晶体管的控制端，以实现对LDO输出的第一电压的补偿，从而提高LDO的瞬态性能。
在第一方面的一种可能的实现方式中，至少一个检测电路还包括第四检测电路，第四检测电路中的第二电容耦合在放大器的输出端与第十一晶体管的控制端。上述可能的实现方式中，通过将检测电路反馈至第十一晶体管的控制端，以实现对LDO输出的第一电压的补偿，从而提高LDO的瞬态性能。
第二方面，提供一种芯片系统，该芯片系统包括负载电路、以及如第一方面或者第一方面的任一种可能的实现方式所提供的用于低压差线性稳压器LDO的瞬态提升电路；其中，该瞬态提升电路包括LDO、以及与该LDO耦合的至少一个检测电路，该LDO用于为该负载电路供电，该至少一个检测电路用于提高该LDO的瞬态。
第三方面，提供一种设备，该设备包括负载电路和电路板、该电路板包括如第一方面或者第一方面的任一种可能的实现方式所提供的用于低压差线性稳压器LDO的瞬态提升电路；其中，该瞬态提升电路包括LDO、以及与该LDO耦合的至少一个检测电路，该LDO用于为该负载电路供电，该至少一个检测电路用于提高该LDO的瞬 态。
可以理解地，上述提供的任一种芯片系统和设备均包含了上文所提供的用于LDO的瞬态提升电路，因此，其所能达到的有益效果可参考上文所提供的用于LDO的瞬态提升电路中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种LDO的结构示意图；
图2为本申请实施例提供的一种用于LDO的瞬态提升电路的结构示意图；
图3为本申请实施例提供的一种放大器的结构示意图；
图4为本申请实施例提供的另一种用于LDO的瞬态提升电路的结构示意图；
图5为本申请实施例提供的又一种用于LDO的瞬态提升电路的结构示意图；
图6为本申请实施例提供的一种运算放大器的结构示意图；
图7为本申请实施例提供的一种FVF LDO的结构示意图；
图8为本申请实施例提供的另一种用于LDO的瞬态提升电路的结构示意图；
图9为本申请实施例提供的又一种用于LDO的瞬态提升电路的结构示意图；
图10为本申请实施例提供的另一种用于LDO的瞬态提升电路的结构示意图；
图11为本申请实施例提供的又一种用于LDO的瞬态提升电路的结构示意图。
具体实施方式
下文将详细论述各实施例的制作和使用。但应了解，本申请提供的许多适用发明概念可实施在多种具体环境中。所论述的具体实施例仅仅说明用以实施和使用本说明和本技术的具体方式，而不限制本申请的范围。
除非另有定义，否则本文所用的所有科技术语都具有与本领域普通技术人员公知的含义相同的含义。
各电路或其它组件可描述为或称为“用于”执行一项或多项任务。在这种情况下，“用于”用来通过指示电路/组件包括在操作期间执行一项或多项任务的结构(例如电路系统)来暗指结构。因此，即使当指定的电路/组件当前不可操作(例如未打开)时，该电路/组件也可以称为用于执行该任务。与“用于”措辞一起使用的电路/组件包括硬件，例如执行操作的电路等。
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述。在本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。字符“/”一般表示前后关联对象是一种“或”的关系。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a和b，a和c，b和c或a、b和c，其中a、b和c可以是单个，也可以是多个。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的” 或者“例如”等词旨在以具体方式呈现相关概念。
另外，本申请实施例中所涉及的晶体管可以是金属氧化物半导体(metal oxide semiconductor，MOS)场效应晶体管(可以简称为MOS管)。本申请实施例中晶体管的控制端可以是指晶体管的栅极；在一种可能的实施例中，晶体管的一极可以是指源极，另一极可以是指漏极；在另一种可能的实施例中，晶体管的一极可以是指漏极，另一极可以是指源极。
本申请的技术方案可以应用于采用低压差线性稳压器(low dropout regulator，LDO)供电的各种子系统或者系统中。比如，本申请的技术方案可以应用于采用LDO供电的射频(radio frequency，RF)收发机、数模转换器(digital-to-analog converter，DAC)、模数转换器(analog-to-digital converter，ADC)、高速数字电路(比如，芯片系统SoC)和锁相环(phase loop lock，PLL)等。
图1为本申请实施例提供的一种通用的LDO的电路示意图，该LDO可以包括：运算放大器A0、调压晶体管M0、取样电路和负载电容C0，取样电路可以包括电阻Ra和电阻Rb。其中，以调压晶体管M0为PMOS管为例，运算放大器A0的输出端与调压晶体管M0的控制端(即PMOS的栅极)耦合，调压晶体管M0的一极(即PMOS的源极)与电压输入端(VDD)耦合，调压晶体管M0的另一极(即PMOS的漏极)与取样电路的输入端相耦合作为该LDO的输出端，取样电路的输出端与运算放大器A0的正相输入端耦合，运算放大器A0的负相输入端用于接收参考电压V REF，负载电容C0的一端与该LDO的输出端耦合、另一端与接地端(GND)耦合。
该LDO在工作时，取样电路通过电阻Ra和电阻Rb对输出电压V OUT进行采样，并将采集的电压反馈至运算放大器的正相输入端；运算放大器该采集的电压和负相输入端接收的参考电压V REF进行比较并放大，放大后的电压经过调压晶体管M0的栅极反馈给输入端，通过调压晶体管M0的导通压降进行动态的稳压输出。
其中，当该LDO在上电或者后级负载发生急剧变化等情况时，该LDO的输出电压V OUT会出现上冲或下冲的现象，从而导致该LDO的瞬态性能较差。该上冲可以是指实际的输出电压的峰值或谷值大于设定的输出电压范围，该上冲可以是指实际的输出电压的峰值或谷值小于设定的输出电压范围。目前，为了保证LDO具有较好的瞬态响应，通常使用具有较大片内电容的LDO，或者带片外电容的LDO。但是，如果使用具有片内电容的LDO，则该片内电容会占用较大的芯片面积；如果使用带片外电容的LDO，则该片外电容会占据额外的PCB面积。基于此，本申请实施例提供一种用于LDO的瞬态提升电路，其原理在于，通过与LDO耦合的至少一个检测电路提升LDO的瞬态性能，该至少一个检测电路可以反馈至LDO中的任一节点(比如，输出节点或者LDO的内部节点等)，只需形成负反馈即可。该电路可用于在提高LDO的瞬态性能的同时，降低LDO中的电容所占用的面积，从而降低LDO所在芯片的面积。
图2为本申请实施例提供的一种用于LDO的瞬态提升电路的结构示意图，参见图2，该电路包括：LDO 1、以及与LDO 1耦合的至少一个检测电路2，至少一个检测电路2可以包括一个或者多个检测电路。
其中，LDO 1用于输出第一电压V1，第一电压V1可以是指用于给各种子系统或者系统供电的电压，第一电压V1也可以称为LDO 1的输出电压。比如，LDO 1为图 1所示的LDO，第一电压V1即为图1所示的输出电压V OUT。
另外，至少一个检测电路2中的每个检测电路包括：第一电容C1、放大器21和第二电容C2。其中，第一电容C1用于根据第一电压V1的变化产生耦合电压，并将该耦合电压耦合至反相放大器21，即第一电容C1通过交流耦合(AC coupling)的方式将第一电压V1耦合至放大器21中，第一电压V1中的直流分量可以被第一电容滤掉。放大器21用于放大该耦合电压，以得到第二电压V2，即第二电压V2是该耦合电压放大后的电压，比如，该放大器21可以是正相放大器或者反相放大器，用于对该耦合电压放大处理以得到第二电压V2。第二电容C2用于将第二电压V2耦合至LDO 1，即第二电容C2通过交流耦合的方式将第二电压V2耦合至LDO 1中，第二电压V2用于调节第一电压V1以维持第一电压V1的恒定。
可以理解的是，第二电容C2用于将第二电压V2耦合至LDO 1可以包括：第二电容C2直接将第二电压V2耦合至LDO 1，以通过LDO 1内部调节第一电压V1来维持第一电压V1的恒定；或者，第二电容C2将第二电压V2间接耦合至LDO 1，比如，第二电容C2将第二电压V2通过一个中间电路耦合至LDO 1，该中间电路可以用于调节第一电压V1以维持第一电压V1的恒定，比如，该中间电路为下文中的补偿电路22。另外，维持第一电压V1的恒定可以理解为：维持第一电压V1等于预设电压值、或者维持第一电压V1在预设电压值附近的一个小范围波动，比如，该预设电压值为5V，若第一电压V1在[4.9V，5.1V]这个范围内波动，可理解为第一电压V1恒定。
可选的，放大器21可以采用集成的放大器模块，比如，放大器21可以采用跨导运算放大器(operational transimpedance amplifier，OTA)模块；或者，放大器21也可以采用电子元器件搭建的放大器。示例性的，如图3所示，放大器21可以包括：第一晶体管M1、第二晶体管M2、第三晶体管M3和第一电阻R1。其中，第一晶体管M1的一极、第二晶体管M2的一极和第一电阻R1的一端耦合作为放大器21的输出端，第一晶体管M1的控制端、第二晶体管M2的控制端和第一电阻R1的另一端相耦合作为放大器21的输入端，第二晶体管M2的另一极与第三晶体管M3的一极耦合，第一晶体管M1的另一极和第三晶体管M3的另一极中的一个与电源端耦合、另一个与接地端耦合，第三晶体管M3的控制端与偏置电压端VBP耦合。
其中，偏置电压端VBP用于为第三晶体管M3提供偏置电压，第三晶体管M3作为电流源提供放大器21的偏置电流。第一晶体管M1和第二晶体管M2组成共源(common source amplifier)放大器，第一电阻R1通过直接耦合提供静态直流偏置电压，使得第一晶体管M1和第二晶体管M2均处在饱和区或者亚阈值区。具体的，当第一电压V1通过第一电容C1耦合到放大器21的输入端之后，会被第一晶体管M1和第二晶体管M2反向放大，并从放大器21的输出端输出第二电压V2。
需要说明的是，图3中以第一晶体管M1为NMOS管，第二晶体管M2和第三晶体管M3均为PMOS管，所述一极为漏极，所述另一极为源极，所述控制端为栅极为例进行说明；在实际应用中，第一晶体管M1、第二晶体管M2和第三晶体管M3还可以替换为具有类似功能的其他晶体管，上述图3并不对本申请实施例构成限制。
上述放大器21是基于反相器(invertor based)的放大器，该放大器21的跨导为第一晶体管M1的跨导和第二晶体管M2的跨导之和，在功耗相同的情况下，其跨导 是普通放大器的两倍。第三晶体管M3用于为放大器21提供偏置电流，避免放大器21的功耗随电源端电压和工艺角的变化而变化。放大器21通过第一电容C1和第二电容C2与LDO 1耦合，使得只使用第一电阻R1就可以单独偏置放大器21的直流工作点，有效的减小了放大器21的匹配需求。
在本申请实施例中，LDO 1输出的第一电压V1通过第一电容C1耦合至放大器21，由放大器21对其进行放大处理，从而在提高LDO的瞬态的同时，可以使用较小的第一电容C1来实现第一电压V1的耦合，减小第一电容C1占用的芯片面积；同时，放大器21输出的第二电压V2通过第二电容C2耦合至LDO 1，使得第二电压V2不直接作用于LDO 1的固有环路中，从而不会破坏LDO 1的直流特性，保证了LDO 1环路的稳定性。另外，放大器21通过第一电容C1和第二电容C2与LDO 1耦合，从而可以将放大器21的偏置和第一电压V1的直流分量分开，有效降低放大器21的偏置(bias)难度和复杂度，即放大器21的设计不必考虑失调(offset)、匹配等需求，从而进一步减小了芯片面积，实现低功耗高能效。
进一步的，根据第二电容C2是否直接将第二电压V2耦合至LDO 1中，可以将检测电路分为两种：第一种为包括补偿电路的检测电路，即第二电容C2间接将第二电压V2耦合至LDO 1中；第二种为不包括补偿电路的检测电路，即第二电容C2直接将第二电压V2耦合至LDO 1中。至少一个检测电路2可以包括上述两种检测电路中的至少一种。下面分别对这两种检测电路进行介绍说明。
第一种、包括补偿电路的检测电路，即第二电容C2间接将第二电压V2耦合至LDO 1中。
具体的，至少一个检测电路2包括第一检测电路2a，第一检测电路2a包括：耦合在第二电容C2与LDO 1之间的补偿电路22，补偿电路22用于根据第二电压V2调节第一电压V1以维持第一电压V1的恒定。本文中第一检测电路2a可以是指包括补偿电路22的检测电路。
在一种可能的实施例中，如图4所示，补偿电路22包括：第四晶体管M4、第五晶体管M5、第六晶体管M6、第二电阻R2和第三电阻R3。其中，第四晶体管M4的一极、第三电阻R3的一端和第六晶体管M6的一极耦合于第一节点①，第四晶体管M4的另一极、第五晶体管M5的控制端和第二电阻R2的一端相耦合作为补偿电路22的输入端，第五晶体管M5的一极和第二电阻R2的另一端耦合于第二节点②，第五晶体管M5的另一极、第六晶体管M6的控制端和第三电阻R3的另一端相耦合，第六晶体管M6的另一极作为补偿电路22的输出端；第一节点①和第二节点②中的一个与电源端耦合、另一个与接地端耦合。
可选的，至少一个检测电路2可以包括一个或者多个第一检测电路，这一个或者多个第一检测电路的输出端可以与LDO 1的不同节点或者同一节点耦合，即多个第一检测电路反馈至LDO 1的不同节点或者同一节点。示例性的，如图4所示，假设至少一个检测电路2包括两个第一检测电路，其中一个第一检测电路(图4中表示为2a-1)的补偿电路22中的第一节点①与电源端耦合、第二节点②与接地端耦合，另一个第一检测电路(图4中表示为2a-2)的补偿电路22中的第一节点①与接地端耦合、第二节点②与电源端耦合。图4中以这两个第一检测电路的输出端均与LDO 1的输出端耦合 (即这两个第一检测电路均反馈至LDO 1的输出端)、该LDO为图1所示的LDO为例进行说明，VBP和VBN分别表示不同的偏置电压端。
需要说明的是，第一检测电路2a-1中以第五晶体管M5为NMOS管，第四晶体管M4和第六晶体管M6均为PMOS管，第一检测电路2a-2中以第五晶体管M5为PMOS管，第四晶体管M4和第六晶体管M6均为NMOS管，所述一极为漏极，所述另一极为源极，所述控制端为栅极为例进行说明。在实际应用中，第四晶体管M4、第五晶体管M5和第六晶体管M6还可以替换为具有类似功能的其他晶体管，上述图4并不对本申请实施例构成限制。
另外，图4中的第二电阻R2和第三电阻R3也可以替换为具有类似功能的其他器件，比如，第二电阻R2可以替换为一个NMOS管，第三电阻R3可以替换为一个PMOS管，该NMOS管的栅极和该PMOS管的栅极可以与偏置电压端连接。
上述图4中，第一检测电路2a-1可以称为下冲(undershoot)检测电路，用于在LDO 1输出的第一电压V1发生下冲时，实现第一电压V1的增压补偿。具体的，当LDO 1输出的第一电压V1发生下冲时，第一检测电路2a-1通过第一电容C1检测到第一电压V1的下冲毛刺(即根据第一电压V1的变化产生耦合电压)，该下冲毛刺通过M1、M2、M3和R1构成的放大器21放大处理后，得到第二电压V2；第二电压V2通过第二电容C2被耦合到补偿电路22中第五晶体管M5的栅极，此时第五晶体管M5被开启、第六晶体管M6的栅极电压被拉低，从而第六晶体管M6被开启，第六晶体管M6的漏极电压用于补偿LDO 1输出的第一电压V1，实现第一电压V1的增压补偿，即实现第一电压V1下冲时的瞬态补偿。
在上述第一检测电路2a-1工作过程中，只有经过放大器21输出的第二电压V2超过第五晶体管M5的阈值电压，才会触发瞬态补偿。第四晶体管M4的漏极电流经过第二电阻R2后形成了一个偏置电压，可以降低第五晶体管M5的阈值电压，使得通过第二电容C2耦合过来的信号能够马上开启第五晶体管M5。此外，当LDO 1输出的第一电压V1未发生下冲、或者下冲小于第五晶体管M5的阈值电压时，补偿电路22中的第五晶体管M5关闭，第三电阻R3上拉关闭第六晶体管M6，从而第一检测电路2a-1对LDO 1无影响。
上述图4中，第一检测电路2a-2可以称为上冲(overshoot)检测电路，用于在LDO1输出的第一电压V1发生上冲时，实现第一电压V1的降压调整。具体的，当LDO 1输出的第一电压V1发生上冲时，第一检测电路2a-2通过第一电容C1检测到第一电压V1的上冲毛刺(即根据第一电压V1的变化产生耦合电压)，该上冲毛刺通过M1、M2、M3和R1构成的放大器21放大处理后，得到第二电压V2；第二电压V2通过第二电容C2被耦合到补偿电路22中第五晶体管M5的栅极，此时第五晶体管M5被开启、第六晶体管M6的栅极电压被拉低，从而第六晶体管M6被开启，第六晶体管M6的漏极电压用于拉低LDO 1输出的第一电压V1，实现第一电压V1的降压调整，即实现第一电压V1上冲时的瞬态补偿。
在上述第一检测电路2a-2工作过程中，只有经过放大器21输出的第二电压V2超过第五晶体管M5的阈值电压，才会触发瞬态补偿。第四晶体管M4的漏极电流经过第二电阻R2后形成了一个偏置电压，可以降低第五晶体管M5的阈值电压，使得通 过第二电容C2耦合过来的信号能够马上开启第五晶体管M5。此外，当LDO 1输出的第一电压V1未发生上冲、或者上冲小于第五晶体管M5的阈值电压时，补偿电路22中的第五晶体管M5关闭，第三电阻R3下拉关闭第六晶体管M6，从而第一检测电路2a-2对LDO 1无影响。
在另一种可能的实施例中，如图5所示，补偿电路22包括：第四晶体管M4、第五晶体管M5和第二电阻R2。其中，第四晶体管M4的一极耦合于第一节点①，第四晶体管M4的另一极、第五晶体管M5的控制端和第二电阻R2的一端相耦合作为补偿电路22的输入端，第五晶体管M5的一极和第二电阻R2的另一端耦合于第二节点②，第五晶体管M5的另一极作为补偿电路22的输出端；第一节点①和第二节点②中的一个与电源端耦合、另一个与接地端耦合。
可选的，至少一个检测电路2可以包括一个或者多个第一检测电路，这一个或者多个第一检测电路的输出端可以与LDO 1的不同节点或者同一节点耦合，即多个第一检测电路反馈至多个第一检测电路。示例性的，如图5所示，假设至少一个检测电路2包括第一检测电路2a，第一检测电路2a的补偿电路22中的第一节点①与电源端耦合、第二节点②与接地端耦合；该LDO为图1所示的LDO，第一检测电路2a的输出端与LDO 1中调压晶体管M0的栅极耦合，即第一检测电路2a反馈至LDO 1中调压晶体管M0的栅极)。其中，第一检测电路2a的工作原理与上述第一检测电路2a-1的工作原理类似，本申请实施例在此不再赘述。
需要说明的是，图5中以第四晶体管M4为PMOS管，第五晶体管M5为NMOS管，所述一极为漏极，所述另一极为源极，所述控制端为栅极为例进行说明；在实际应用中，第四晶体管M4和第五晶体管M5还可以替换为具有类似功能的其他晶体管。另外，图5中以至少一个检测电路2包括第一检测电路2a为例进行说明。上述图5并不对本申请实施例构成限制。
进一步的，上述图4和图5所示的第一检测电路除了应用于上述图1所示的LDO1外，还可以应用在其他结构的LDO中。比如，LDO 1中的运算放大器A0可以是通过多个晶体管搭建的运算放大器，或者该LDO可以为翻转电压跟随器(flipped voltage follower，FVF)LDO，即FVF LDO。
示例性的，如图6所示，LDO 1中的运算放大器A0可以包括T1至T12共12个晶体管，晶体管T1至T12的连接关系具体如图所示，VBP和VBN分别表示偏置电压。其中，至少一个检测电路2可以反馈至运算放大器A0中的任一节点以形成负反馈即可，比如，至少一个检测电路2反馈至晶体管T2的栅极(也可以称为晶体管T3的栅极)，或者至少一个检测电路2反馈至晶体管T5的栅极(也可以称为晶体管T6的栅极)。需要说明的是，图6中以晶体管T1、T4、T8、T9、T10、T11和T12均为PMOS管，T2、T3、T5、T6和T7均为NMOS管为例进行说明，上述晶体管T1至T12还可以替换为具有类似功能的其他晶体管，或者运算放大器A0包括更多或者更少的晶体管，上述图6并不对本申请实施例构成限制。
示例性的，如图7所示，当LDO 1为FVF LDO时，LDO 1可以包括：第七晶体管M7、第八晶体管M8、第九晶体管M9、第十晶体管M10、第十一晶体管M11和第四电阻R4。其中，第七晶体管M7的一极和第八晶体管M8的一极均与电源端耦合， 第七晶体管M7的另一极与第九晶体管M9的一极相耦合作为LDO 1的输出端，第八晶体管M8的另一极、第十晶体管M10的一极和第七晶体管M7的控制端相耦合(耦合点的电压表示为V FB2)，第九晶体管M9的另一极、第十晶体管M10的另一极和第十一晶体管M11的一极相耦合(耦合点的电压表示为V FB1)，第十一晶体管M11的另一极与接地端耦合，第十一晶体管M11的控制端与第四电阻R4的一端相耦合，第四电阻R4的另一端与偏置电压端VBN1连接。
需要说明的是，图7中以第七晶体管M7、第八晶体管M8和第九晶体管M9均为PMOS管，第十晶体管M10和第十一晶体管M11均为NMOS管，第七晶体管M7至第九晶体管的所述一极为源极、所述另一极为漏极，第十晶体管M10和第十一晶体管M11的所述一极为漏极、所述另一极为源极，所述控制端为栅极为例进行说明；在实际应用中，第七晶体管M7至第十一晶体管M11还可以替换为具有类似功能的其他晶体管，上述图7并不对本申请实施例构成限制。
上述图4或图5所示的第一检测电路的输出端也可以与该FVF LDO的输出端、或者该FVF LDO内部的其他节点耦合，比如，第一检测电路的输出端与该FVF LDO中第七晶体管M7的控制端耦合，或者第一检测电路的输出端与该FVF LDO中第八晶体管M8的控制端耦合，或者第一检测电路的输出端与该FVF LDO中第十晶体管M10的控制端耦合，或者第一检测电路的输出端与该FVF LDO中第十一晶体管M11的控制端耦合等。
第二种、不包括补偿电路的检测电路，即第二电容C2直接将第二电压V2耦合至LDO 1中。下面以图7所示的FVF LDO的结构为例进行举例说明。
在一种可能的实施例中，如图8所示，至少一个检测电路2包括第二检测电路2b，第二检测电路2b中的第二电容C2耦合在放大器21的输出端与第八晶体管M8的控制端(即栅极)，即第二检测电路2b反馈至FVF LDO中第八晶体管M8的栅极。
具体的，在该FVF LDO输出的第一电压V1正常时，第二检测电路2b不工作，假设流过第十一晶体管M11的电流为I11、流过第八晶体管M8的电流为I8、流过第十晶体管M10的电流为I10、流过第九晶体管M9的电流为I9，I11＝I9+I8，I8＝I10。
其中，当该FVF LDO发生下冲时，第二检测电路2b通过第一电容C1检测到第一电压V1的下冲毛刺(即根据第一电压V1的变化产生耦合电压)，该下冲毛刺通过放大器21放大处理后，得到第二电压V2；第二电压V2通过第二电容C2被耦合到该FVF LDO中第八晶体管M8的栅极，第八晶体管M8的栅源极(即Vgs)电压减小，以控制流过第八晶体管M8的电流I8减小，同时由于流过第十晶体管M10的电流I10保持不变，此时I10大于I8，从而第七晶体管的栅极电压V BF2会被拉低，第七晶体管M7的栅源极电压(即Vgs)迅速增大，进而增大该FVF LDO的输出电流，即实现第一电压V1下冲时的瞬态补偿。
当该FVF LDO发生上冲时，第二检测电路2b通过第一电容C1检测到第一电压V1的上冲毛刺(即根据第一电压V1的变化产生耦合电压)，该上冲毛刺通过放大器21放大处理后，得到第二电压V2；第二电压V2通过第二电容C2被耦合到该FVF LDO中第八晶体管M8的栅极，此时第八晶体管M8的栅源极电压(即Vgs)增大，以控制流过第八晶体管M8的电流I8增大，同时由于流过第十晶体管M10的电流I10保持不 变，此时I10小于I8，从而第七晶体管的栅极电压V BF2会被拉高，第七晶体管M7的栅源极电压(即Vgs)减小，进而减小该FVF LDO的输出电流，即实现第一电压V1上冲时的瞬态补偿。
在另一种可能的实施例中，如图9所示，至少一个检测电路2包括第三检测电路2c，第三检测电路2c中的第二电容C2耦合在反相放大器21的输出端与第十晶体管M10的控制端(即栅极)，即第三检测电路2c反馈至FVF LDO中第十晶体管M10的栅极。
具体的，在该FVF LDO输出的第一电压V1正常时，第二检测电路2b不工作，假设流过第十一晶体管M11的电流为I11、流过第八晶体管M8的电流为I8、流过第十晶体管M10的电流为I10、流过第九晶体管M9的电流为I9，I11＝I9+I8，I8＝I10。
其中，当该FVF LDO发生下冲时，第三检测电路2c通过第一电容C1检测到第一电压V1的下冲毛刺(即根据第一电压V1的变化产生耦合电压)，该下冲毛刺通过反相放大器21放大处理后，得到第二电压V2；第二电压V2通过第二电容C2被耦合到该FVF LDO中第十晶体管M10的栅极，此时第十晶体管M10的栅源极电压(即Vgs)增大，以控制流过第十晶体管M10的电流I10增大，同时由于流过第八晶体管M8的电流I8保持不变，此时I10大于I8，从而第七晶体管的栅极电压V BF2会被拉低，第七晶体管M7的栅源极电压(即Vgs)迅速增大，进而增大该FVF LDO的输出电流，即实现第一电压V1下冲时的瞬态补偿。
当该FVF LDO发生上冲时，第三检测电路2c通过第一电容C1检测到第一电压V1的上冲毛刺(即根据第一电压V1的变化产生耦合电压)，该上冲毛刺通过反相放大器21放大处理后，得到第二电压V2；第二电压V2通过第二电容C2被耦合到该FVF LDO中第十晶体管M10的栅极，此时第十晶体管M10的栅源极电压(即Vgs)减小，以控制流过第十晶体管M10的电流I10减小，同时由于流过第八晶体管M8的电流I8保持不变，此时I10小于I8，从而第七晶体管的栅极电压V BF2会被拉高，第七晶体管M7的栅源极电压(即Vgs)减小，进而减小该FVF LDO的输出电流，即实现第一电压V1上冲时的瞬态补偿。
在又一种可能的实施例中，如图10所示，至少一个检测电路2包括第四检测电路2d，第四检测电路2d中的第二电容C2耦合在反相放大器21的输出端与第十一晶体管M11的控制端(即栅极)，即第四检测电路2d反馈至FVF LDO中第十一晶体管M11的栅极。
具体的，在该FVF LDO输出的第一电压V1正常时，第二检测电路2b不工作，假设流过第十一晶体管M11的电流为I11、流过第八晶体管M8的电流为I8、流过第十晶体管M10的电流为I10、流过第九晶体管M9的电流为I9，I11＝I9+I8，I8＝I10。
其中，当该FVF LDO发生下冲时，第四检测电路2d通过第一电容C1检测到第一电压V1的下冲毛刺(即根据第一电压V1的变化产生耦合电压)，该下冲毛刺通过反相放大器21放大处理后，得到第二电压V2；第二电压V2通过第二电容C2被耦合到该FVF LDO中第十一晶体管M11的栅极，此时第十一晶体管M11的栅源极电压(即Vgs)增大，以控制流过第十一晶体管M10的电流I10增大，同时由于流过第八晶体管M8的电流I8保持不变，流过第九晶体管M9的电流I9减小，流过第十晶体管M10 的电流I10增大，此时I10大于I8，从而第七晶体管的栅极电压V BF2会被拉低，第七晶体管M7的栅源极电压(即Vgs)迅速增大，进而增大该FVF LDO的输出电流，即实现第一电压V1下冲时的瞬态补偿。
当该FVF LDO发生上冲时，第四检测电路2d通过第一电容C1检测到第一电压V1的上冲毛刺(即根据第一电压V1的变化产生耦合电压)，该上冲毛刺通过放大器21放大处理后，得到第二电压V2；第二电压V2通过第二电容C2被耦合到该FVF LDO中第十一晶体管M11的栅极，此时第十一晶体管M11的栅源极电压(即Vgs)减小，以控制流过第十一晶体管M11的电流I11减小，同时由于流过第八晶体管M8的电流I8保持不变，流过第九晶体管M9的电流I9增大，流过第十晶体管M10的电流I10减小，此时I10小于I8，从而第七晶体管的栅极电压V BF2会被拉高，第七晶体管M7的栅源极电压(即Vgs)减小，进而减小该FVF LDO的输出电流，即实现第一电压V1上冲时的瞬态补偿。
进一步的，对于LDO 1的上冲补偿、或者下冲补偿，均可以使用多个检测电路来实现LDO 1的瞬态补偿，该多个检测电路的输出端可以与LDO 1中的不同节点耦合，只需保证每个检测电路与LDO 1的耦合形成负反馈即可。
示例性的，如图11所示，以FVF LDO的下冲补偿为例，至少一个检测电路2可以包括四个检测电路且分别表示为201至204，其中检测电路201的输出端与该FVF LDO的输出端耦合，检测电路202的输出端与该FVF LDO中第七晶体管M7的栅极耦合，检测电路203的输出端与该FVF LDO中第八晶体管M8的栅极耦合，检测电路204的输出端与该FVF LDO中第十一晶体管M11的栅极耦合。
其中，检测电路201的工作原理与上述图4所示的第一检测电路2a-1的工作原理类似，检测电路202的工作原理与上述图5所示的第一检测电路2a的工作原理类似，检测电路203的工作原理与上述图8所示的第二检测电路2b的工作原理类似，检测电路204的工作原理与上述图10所示的第四检测电路2d的工作原理类似，具体参见上文中的相关描述，本申请实施例在此不再赘述。
在本申请实施例中，通过多个检测电路对LDO 1的上冲或下冲进行瞬态补偿，可以更快地实现LDO 1的瞬态补偿，从而提高LDO 1的瞬态性能；此外，在LDO 1输出的第一电压V1正常或者变化较小时，这多个检测电路中可以处于关闭状态，从而不影响LDO 1的直流特性，保证了LDO 1环路的稳定性。
基于此，本申请实施例还提供一种芯片系统，该芯片系统包括负载电路、以及上文所提供的任一种用于LDO的瞬态提升电路，该瞬态提升电路包括LDO、以及与该LDO耦合的至少一个检测电路，该LDO用于为该负载电路供电，该至少一个检测电路用于提高该LDO的瞬态。可选的，该负载电路可以包括以下至少一项：RF收发机、DAC、ADC、高速数字电路(比如，芯片系统SoC)、PLL。
本申请实施例还提供一种设备，该设备包括负载电路和电路板、该电路板包括上文所提供的任一种用于LDO的瞬态提升电路，该瞬态提升电路包括LDO、以及与该LDO耦合的至少一个检测电路，该LDO用于为该负载电路供电，该至少一个检测电路用于提高该LDO的瞬态。可选的，该负载电路可以包括以下至少一项：RF收发机、DAC、ADC、高速数字电路(比如，芯片系统SoC)、PLL；另外，该设备可以是通信设备 或者稳压设备等。本申请实施例对此不作具体限制。
需要说明的是，上文中提供的用于LDO的瞬态提升电路的相关描述均可引援至该芯片系统或该设备中，本申请实施例在此不再赘述。
在本申请的另一方面，还提供一种与计算机一起使用的非瞬时性计算机可读存储介质，该计算机具有用于创建集成电路的软件，该计算机可读存储介质上存储有一个或多个计算机可读数据结构，一个或多个计算机可读数据结构具有用于制造上文所提供的任意一个图示所提供的用于LDO的瞬态提升电路的光掩膜数据。
最后应说明的是：以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何在本申请揭露的技术范围内的变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种用于低压差线性稳压器LDO的瞬态提升电路，其特征在于，包括：
    LDO，用于输出第一电压；
    与所述LDO耦合的至少一个检测电路，所述至少一个检测电路中的每个检测电路包括第一电容、放大器和第二电容；
    其中，所述第一电容，用于根据所述第一电压的变化产生耦合电压，并将所述耦合电压耦合至所述放大器；
    所述放大器，用于放大所述耦合电压，以得到第二电压；
    所述第二电容，用于将所述第二电压耦合至所述LDO，所述第二电压用于调节所述第一电压以维持所述第一电压的恒定。
  2. 根据权利要求1所述的电路，其特征在于，所述放大器包括：第一晶体管、第二晶体管、第三晶体管和第一电阻；
    其中，所述第一晶体管的一极、所述第二晶体管的一极和所述第一电阻的一端耦合作为所述放大器的输出端，所述第一晶体管的控制端、所述第二晶体管的控制端和所述第一电阻的另一端相耦合作为所述放大器的输入端，所述第二晶体管的另一极与所述第三晶体管的一极耦合，所述第一晶体管的另一极和所述第三晶体管的另一极中的一个与电源端耦合、另一个与接地端耦合，所述第三晶体管的控制端与偏置电压端耦合。
  3. 根据权利要求1或2所述的电路，其特征在于，所述至少一个检测电路包括第一检测电路，所述第一检测电路还包括：耦合在所述第二电容与所述LDO之间的补偿电路；
    所述补偿电路，用于根据所述第二电压调节所述第一电压以维持所述第一电压的恒定。
  4. 根据权利要求3所述的电路，其特征在于，所述补偿电路包括：第四晶体管、第五晶体管、第六晶体管、第二电阻和第三电阻；
    其中，所述第四晶体管的一极、所述第三电阻的一端和所述第六晶体管的一极耦合于第一节点，所述第四晶体管的另一极、所述第五晶体管的控制端和所述第二电阻的一端相耦合作为所述补偿电路的输入端，所述第五晶体管的一极和所述第二电阻的另一端耦合于第二节点，所述第五晶体管的另一极、所述第六晶体管的控制端和所述第三电阻的另一端相耦合，所述第六晶体管的另一极作为所述补偿电路的输出端；
    所述第一节点和所述第二节点中的一个与电源端耦合、另一个与接地端耦合。
  5. 根据权利要求4所述的电路，其特征在于，所述LDO具有输出端，所述补偿电路的输出端与所述LDO的输出端耦合。
  6. 根据权利要求3所述的电路，其特征在于，所述补偿电路包括：第四晶体管、第五晶体管和第二电阻；
    其中，所述第四晶体管的一极耦合于第一节点，所述第四晶体管的另一极、所述第五晶体管的控制端和所述第二电阻的一端相耦合作为所述补偿电路的输入端，所述第五晶体管的一极和所述第二电阻的另一端耦合于第二节点，所述第五晶体管的另一 极作为所述补偿电路的输出端；所述第一节点和所述第二节点中的一个与电源端耦合、另一个与接地端耦合。
  7. 根据权利要求6所述的电路，其特征在于，所述LDO包括运算放大器、调压晶体管和取样电路，所述运算放大器的输出端与所述调压晶体管的控制端耦合，所述调压晶体管的一极与电源端耦合，所述调压晶体管的另一极与所述取样电路的输入端相耦合作为所述LDO的输出端，所述取样电路的输出端与所述运算放大器的正相输入端耦合，所述运算放大器的负相输入端用于接收参考电压；
    其中，所述补偿电路的输出端与所述调压晶体管的控制端耦合。
  8. 根据权利要求1-5任一项所述的电路，其特征在于，所述LDO包括：第七晶体管、第八晶体管、第九晶体管、第十晶体管、第十一晶体管和第四电阻；
    其中，所述第七晶体管的一极和所述第八晶体管的一极均与电源端耦合，所述第七晶体管的另一极与所述第九晶体管的一极相耦合作为所述LDO的输出端，所述第八晶体管的另一极、所述第十晶体管的一极和所述第七晶体管的控制端相耦合，所述第九晶体管的另一极、所述第十晶体管的另一极和所述第十一晶体管的一极相耦合，所述第十一晶体管的另一极与接地端耦合，所述第十一晶体管的控制端与所述第四电阻的一端相耦合，所述第四电阻的另一端与偏置电压端连接。
  9. 根据权利要求8所述的电路，其特征在于，所述至少一个检测电路还包括第二检测电路，所述第二检测电路中的所述第二电容耦合在所述放大器的输出端与第八晶体管的控制端。
  10. 根据权利要求8或9所述的电路，其特征在于，所述至少一个检测电路还包括第三检测电路，所述第三检测电路中的所述第二电容耦合在所述放大器的输出端与第十晶体管的控制端。
  11. 根据权利要求8-10任一项所述的电路，其特征在于，所述至少一个检测电路还包括第四检测电路，所述第四检测电路中的所述第二电容耦合在所述放大器的输出端与第十一晶体管的控制端。
  12. 一种芯片系统，其特征在于，所述芯片系统包括负载电路、以及权利要求1-11任一项所述的用于低压差线性稳压器LDO的瞬态提升电路；其中，所述瞬态提升电路包括LDO、以及与所述LDO耦合的至少一个检测电路，所述LDO用于为所述负载电路供电，所述至少一个检测电路用于提高所述LDO的瞬态。
  13. 一种设备，其特征在于，所述设备包括负载电路和电路板，所述电路板包括权利要求1-11任一项所述的用于低压差线性稳压器LDO的瞬态提升电路；其中，所述瞬态提升电路包括LDO、以及与所述LDO耦合的至少一个检测电路，所述LDO用于为所述负载电路供电，所述至少一个检测电路用于提高所述LDO的瞬态。
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CN115525087A (zh) * 2022-03-29 2022-12-27 南京市智凌芯科技股份有限公司 一种快速响应低压差线性稳压器
CN115525087B (zh) * 2022-03-29 2023-06-27 南京市智凌芯科技股份有限公司 一种快速响应低压差线性稳压器

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