WO2022033591A1 - 外延结构及应用其的半导体芯片 - Google Patents

外延结构及应用其的半导体芯片 Download PDF

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WO2022033591A1
WO2022033591A1 PCT/CN2021/112614 CN2021112614W WO2022033591A1 WO 2022033591 A1 WO2022033591 A1 WO 2022033591A1 CN 2021112614 W CN2021112614 W CN 2021112614W WO 2022033591 A1 WO2022033591 A1 WO 2022033591A1
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epitaxial structure
type contact
quantum well
step portion
contact layer
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PCT/CN2021/112614
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English (en)
French (fr)
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郑兆祯
丁新琪
涂庆明
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深圳市中光工业技术研究院
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Publication of WO2022033591A1 publication Critical patent/WO2022033591A1/zh
Priority to US18/166,452 priority Critical patent/US20230187901A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/16—Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface
    • H01S5/166—Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface with window regions comprising non-semiconducting materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0421—Electrical excitation ; Circuits therefor characterised by the semiconducting contacting layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04256—Electrodes, e.g. characterised by the structure characterised by the configuration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/16—Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface
    • H01S5/162—Window-type lasers, i.e. with a region of non-absorbing material between the active region and the reflecting surface with window regions made by diffusion or disordening of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/30—Structure or shape of the active region; Materials used for the active region
    • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers

Definitions

  • the utility model relates to the field of semiconductor lasers, in particular to an epitaxial structure and a semiconductor chip using the same.
  • Semiconductor laser-pumped all-solid-state lasers are a new type of laser that emerged in the late 1980s. Its overall efficiency is at least 10 times higher than that of lamp pumping. Since the heat load per unit output is reduced, higher power can be obtained, and the system life and reliability are about 100 times that of the lamp pumping system. Therefore, semiconductor laser pumping technology It injects new vitality and vitality into solid-state lasers, making all-solid-state lasers have the dual characteristics of solid-state lasers and semiconductor lasers at the same time. Its appearance and gradual maturity are a revolution of solid-state lasers and the development direction of solid-state lasers.
  • the utility model provides an epitaxial structure and a semiconductor chip using the same, so as to solve the problem of catastrophic optical mirror surface damage in the prior art.
  • a technical solution adopted by the present invention is to provide an epitaxial structure, the epitaxial structure includes a quantum well structure, a P-type contact layer and an electrode layer that are stacked in sequence; wherein, the P-type contact layer
  • the layer includes a first step part and a second step part arranged in a step shape, and the second step part is closer to the quantum well structure than the first step part; wherein, the first step part and the second step part are The portion is filled with the first insulating portion.
  • the length of the first stepped portion along the resonant cavity direction of the epitaxial structure is greater than the length of the second stepped portion along the resonant cavity direction of the epitaxial structure.
  • the length of the second step portion along the resonant cavity direction of the epitaxial structure is greater than or equal to 1 um and less than or equal to 30 um.
  • the height of the first step portion along the stacking direction of the P-type contact layer and the electrode layer is greater than the height of the second step portion along the P-type contact layer and the electrode layer. The height in the stacking direction.
  • the height of the second step portion along the stacking direction of the P-type contact layer and the electrode layer is greater than or equal to 1 nm and less than or equal to 100 nm.
  • the electrode layer includes a third stepped portion arranged in a stepped shape with the first stepped portion, and the third stepped portion is filled with a second insulating portion.
  • the length of the third step portion along the resonant cavity direction of the epitaxial structure is greater than the length of the first step portion along the resonant cavity direction of the epitaxial structure.
  • the epitaxial structure further includes a P-type cladding layer and a first waveguide layer disposed between the P-type contact layer and the quantum well structure.
  • the epitaxial structure further includes a second waveguide layer, an N-type cladding layer, and an N-type substrate sequentially disposed on a side of the quantum well structure away from the P-type contact layer.
  • another technical solution adopted by the present invention is to provide a semiconductor chip, the semiconductor chip includes a substrate and the epitaxial structure described in any one of the above, and the epitaxial structure is disposed on the substrate superior.
  • FIG. 1 is a schematic structural diagram of a first embodiment of an epitaxial structure provided by the present invention.
  • FIG. 2 is a schematic structural diagram of a second embodiment of an epitaxial structure provided by the present invention.
  • FIG. 3 is a schematic structural diagram of a third embodiment of an epitaxial structure provided by the present invention.
  • FIG. 4 is a schematic structural diagram of a third embodiment of an epitaxial structure provided by the present invention.
  • FIG. 5 is a schematic structural diagram of a third embodiment of an epitaxial structure provided by the present invention.
  • FIG. 6 is a schematic structural diagram of an embodiment of a semiconductor chip provided by the present invention.
  • the present invention provides an epitaxial structure 10 .
  • the epitaxial structure 10 includes a quantum well structure 100 , a P-type contact layer 200 and an electrode layer 300 that are stacked in sequence.
  • the P-type contact layer 200 includes a first stepped portion 410 and a second stepped portion 420 .
  • the first stepped portion 410 and the second stepped portion 420 may be arranged in a stepped shape, and the second stepped portion 420 is opposite to each other.
  • the first step portion 410 is closer to the quantum well structure 100.
  • both the first step portion 410 and the second step portion 420 are filled with the first insulating portion 400.
  • the first insulating portion 400 may be composed of It is composed of materials with non-conductive and good thermal conductivity, such as silicon dioxide, silicon carbide, and aluminum nitride.
  • the P-type contact layer 200 may be etched to generate a stepped structure, and then the first insulating portion 400 may be epitaxially generated on the stepped structure by an insulating material such as silicon dioxide, silicon carbide, or aluminum nitride. , which can effectively limit the radiation current in the resonant cavity, thereby effectively suppressing the non-radiative recombination in the end face area, that is, reducing the absorption of light in the end face area, thereby improving the anti-catastrophic optical mirror damage value.
  • an insulating material such as silicon dioxide, silicon carbide, or aluminum nitride.
  • the second step portion 420 is closer to the quantum well structure 100, when the quantum well hybrid process is performed in the region below the second step portion 420, the diffusion efficiency is higher than that in other regions. And the heat treatment time required for the whole process is also shorter, that is, the diffusion efficiency of the dopant material is faster and the mixing is easier, preventing the doping of the mixed material to other layers or lateral doping during the quantum well mixing process, that is It can reduce the damage to the entire epitaxial structure 10 during the manufacturing process or reduce unnecessary diffusion during the manufacturing process, reduce the damage to the cavity surface structure of the epitaxial structure 10, and further reduce the absorption of light on the cavity surface, so as to improve the damage value of the anti-catastrophic optical mirror surface. , improve the life and quality of the entire semiconductor chip.
  • the second step portion 420 is closer to the quantum well structure 100 , it is more convenient to track the blue shift (PL blue shift) measurement during the quantum well hybrid process.
  • the quantum well hybrid process can be directly performed under the first insulating portion 400, compared to the process realized by ion injection or the like.
  • the quantum well hybrid process can be directly used as the laser resonator region, which can effectively simplify the process and reduce the manufacturing cost.
  • the length L1 of the first stepped portion 410 along the resonant cavity direction of the epitaxial structure 10 is greater than the length L2 of the second stepped portion 420 along the resonant cavity direction of the epitaxial structure 10 .
  • the length L2 of the second step portion 420 along the resonant cavity direction of the epitaxial structure 10 is greater than or equal to 1 um and less than or equal to 30 um, and may specifically be 1 um, 10 um or 30 um.
  • the height H1 of the first step portion 410 along the stacking direction of the P-type contact layer 200 and the electrode layer 300 is greater than the height H1 of the second step portion 420 along the stacking direction of the P-type contact layer 200 and the electrode layer 300 .
  • Height H2 is greater than the height H1 of the second step portion 420 along the stacking direction of the P-type contact layer 200 and the electrode layer 300 .
  • the height H2 of the second step portion 420 along the stacking direction of the P-type contact layer 200 and the electrode layer 300 is greater than or equal to 1 nm and less than or equal to 100 nm. Specifically, it can be 1 nm, 50 nm or 100 nm, which are not specifically limited here.
  • the first step portion 410 and the second step portion 420 run through the entire P-type contact layer 200 as a whole, that is, the second step portion 420 is directly connected to the quantum well structure 100 , and the first step portion 410 is directly connected to the electrode layer. 300 connections.
  • the P-type contact layer 200 may further include a fourth step portion 430 arranged in a step shape with the first step portion 410 , and the fourth step portion 430 is further filled with the first insulating portion 400 .
  • the electrode layer 300 further includes a third stepped portion 510 , and the third stepped portion 510 may be disposed in a stepped shape with the first stepped portion 410 .
  • the third step portion 510 and the first step portion 410 are arranged in a step shape.
  • the third step portion 510 is filled with a second insulating portion 500 , and the second insulating portion 500 may be integrally formed with the first insulating portion 410 . That is, in an alternative embodiment, the first insulating portion 400 and the second insulating portion 500 may be formed simultaneously using silicon dioxide.
  • the third step portion 510 and the fourth step portion 430 may also be arranged in a step shape.
  • the length L3 of the third stepped portion 510 along the resonant cavity direction of the epitaxial structure 10 is greater than the length L1 of the first stepped portion 410 along the resonant cavity direction of the epitaxial structure 10 .
  • the epitaxial structure 10 further includes a P-type cladding layer 610 and a first waveguide layer 620 disposed between the P-type contact layer 200 and the quantum well structure 100 .
  • the epitaxial structure 10 further includes a second waveguide layer 630 , an N-type cladding layer 640 and an N-type substrate 650 , which are sequentially disposed on the side of the quantum well structure 100 away from the P-type contact layer 200 .
  • the thickness of the N-type cladding layer 640 along the stacking direction is generally greater than or equal to 500 nm and less than or equal to 5000 nm, and may specifically be 500 nm, 3000 nm or 5000 nm, and the thickness of the second waveguide layer 630 along the stacking direction is generally greater than or equal to 50 nm. It is less than or equal to 250 nm, specifically 50 nm, 200 nm or 250 nm.
  • the thickness of the first waveguide layer 620 along the stacking direction is generally greater than or equal to 50 nm and less than or equal to 250 nm, and may specifically be 50 nm, 100 nm or 250 nm.
  • the thickness of the P-type cladding layer 610 along the stacking direction is generally greater than or equal to 500 nm and less than or equal to 5000 nm, and may specifically be 500 nm, 2000 nm or 5000 nm.
  • the present application further provides a semiconductor chip 1 .
  • the semiconductor chip 1 includes a substrate 20 and the epitaxial structure 10 described in any of the above embodiments, and the epitaxial structure 10 is disposed on the substrate 20 .
  • the epitaxial structure provided by the present invention and the semiconductor chip using the same are formed by etching the P-type contact layer 200 to form a stepped structure, and then the first insulating portion 400 is epitaxially generated by silicon dioxide on the stepped structure. , which can effectively confine the radiation current in the resonant cavity, thereby effectively suppressing the non-radiative recombination in the end face region, that is, reducing the absorption of light in the end face region, thereby increasing the catastrophic optical mirror damage value.
  • the first insulating portion 400 of the present application further includes a first step portion 410 and a second step portion 420.
  • the second step portion 420 is closer to the quantum well structure 100, the second step portion 420 is performed in the region below the second step portion 420.
  • the diffusion efficiency is higher, and the heat treatment time required for the entire process is also shorter, which prevents the hybrid material from being doped into other layers during the quantum well hybrid process, which can reduce the process.
  • the destruction of 10 or the excess diffusion during the process can be reduced, and the damage to the cavity surface structure of the epitaxial structure 10 can be reduced, and the absorption of light by the cavity surface can be reduced, so as to improve the catastrophic optical mirror damage value, and improve the life of the entire semiconductor chip. quality.
  • the second step portion 420 is closer to the quantum well structure 100 , it is more convenient to track the blue shift (PL blue shift) measurement during the quantum well hybrid process. Furthermore, by arranging the first insulating portion 400, the quantum well hybrid process can be performed directly under the first insulating portion 400. For the method of realizing the process by means of ion injection, etc., there is no need to relocate the area of the quantum well hybrid process. , and the quantum well hybrid process can be directly used as the laser resonator region, which can effectively simplify the process and reduce the manufacturing cost.

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Semiconductor Lasers (AREA)

Abstract

本实用新型公开一种外延结构及应用其的半导体芯片，该外延结构包括依次层叠设置的量子阱结构、P型接触层以及电极层；P型接触层包括呈台阶状设置的第一台阶部与第二台阶部，第二台阶部相对第一台阶部更靠近量子阱结构；第一台阶部与第二台阶部填充有第一绝缘部。通过上述方式，可以有效提高半导体芯片的抗灾变性光学镜面损伤值。

Description

外延结构及应用其的半导体芯片 技术领域
本实用新型涉及半导体激光领域，特别涉及一种外延结构及应用其的半导体芯片。
背景技术
半导体激光泵浦的全固态激光器是20世纪80年代末期出现的新型激光器。其总体效率至少要比灯泵浦高10倍，由于单位输出的热负荷降低，可获取更高的功率，系统寿命和可靠性大约是闪光灯泵浦系统的100倍，因此，半导体激光器泵浦技术为固体激光器注入了新的生机和活力，使全固态激光器同时具有固体激光器和半导体激光器的双重特点，它的出现和逐渐成熟是固体激光器的一场革命，也是固体激光器的发展方向。并且，它已渗透到各个学科领域，例如：激光信息存储与处理、激光材料加工、激光医学及生物学、激光通讯、激光印刷、激光光谱学、激光化学、激光分离同位素、激光核聚变、激光投影显示、激光检测与计量及军用激光技术等，极大地促进了这些领域的技术进步和前所未有的发展。
增大光输出功率、提高可靠性和工作寿命一直是半导体激光器领域的研究重点，而灾变性光学镜面损伤是影响半导体激光器最大输出功率和可靠性不可忽视的重要因素，灾变性光学镜面损伤是激光器腔面区域吸收谐振腔内部较高的光辐射后，导致该处温度超过其熔点，从而发生腔面融化的一种灾变性破坏。
如何防止灾变性光学镜面损伤成为一个重要的趋势。
实用新型内容
本实用新型提供一种外延结构及应用其的半导体芯片，以解决现有技术中灾变性光学镜面损伤的问题。
为解决上述技术问题，本实用新型采用的一个技术方案是：提供一种外延结构，所述外延结构包括依次层叠设置的量子阱结构、P型接触层以及电极层；其中，所述P型接触层包括呈台阶状设置的第一台阶部与第二台阶部，所述第二台阶部相对所述第一台阶部更靠近所述量子阱结构；其中，所述第一台阶部与第二台阶部填充有第一绝缘部。
根据本实用新型提供的一实施方式，所述第一台阶部沿所述外延结构的谐振腔方向的长度大于所述第二台阶部沿所述外延结构的谐振腔方向的长度。
根据本实用新型提供的一实施方式，所述第二台阶部沿所述外延结构的谐振腔方向的长度大于或等于1um，小于或等于30um。
根据本实用新型提供的一实施方式，所述第一台阶部沿所述P型接触层与电极层的层叠方向上的高度大于所述第二台阶部沿所述P型接触层与电极层的层叠方向上的高度。
根据本实用新型提供的一实施方式，所述第二台阶部沿所述P型接触层与电极层的层叠方向上的高度大于或等于1nm，小于或等于100nm。
根据本实用新型提供的一实施方式，所述电极层包括与所述第一台阶部呈台阶状设置的第三台阶部，所述第三台阶部填充有第二绝缘部。
根据本实用新型提供的一实施方式，所述第三台阶部沿所述外延结构的谐振腔方向的长度大于所述第一台阶部沿所述外延结构的谐振腔方向的长度。
根据本实用新型提供的一实施方式，所述外延结构还包括设置于所述P型接触层与所述量子阱结构之间的P型覆盖层以及第一波导层。
根据本实用新型提供的一实施方式，所述外延结构还包括依次设置于所述量子阱结构远离所述P型接触层的一侧的第二波导层、N型覆盖层以及N型衬底。
为解决上述技术问题，本实用新型采用的另一个技术方案是：提供一种半导体芯片，所述半导体芯片包括基板以及上述中任一项所述的外延结构，所述外延结构设置于所述基板上。
有益效果：区别于现有技术，通过在P型接触层上设置台阶部，且 在台阶部填充第一绝缘部，可以有效的将辐射电流限制在谐振腔内，从而可以有效的抑制端面区域的非辐射复合，即减少端面区域对光的吸收，进而提高灾变性光学镜面损伤值。
附图说明
图1是本实用新型提供的外延结构第一实施例的结构示意图；
图2是本实用新型提供的外延结构第二实施例的结构示意图；
图3是本实用新型提供的外延结构第三实施例的结构示意图；
图4是本实用新型提供的外延结构第三实施例的结构示意图；
图5是本实用新型提供的外延结构第三实施例的结构示意图；
图6是本实用新型提供的半导体芯片一实施例的结构示意图。
具体实施方式
下面将结合本实用新型实施例中的附图，对本实用新型实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本实用新型的一部分实施例，而不是全部的实施例。基于本实用新型中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本实用新型保护的范围。
另外，若本实用新型实施例中有涉及“第一”、“第二”等的描述，则该“第一”、“第二”等的描述仅用于描述目的，而不能理解为指示或暗示其相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括至少一个该特征。另外，各个实施例之间的技术方案可以相互结合，但是必须是以本领域普通技术人员能够实现为基础，当技术方案的结合出现相互矛盾或无法实现时应当认为这种技术方案的结合不存在，也不在本实用新型要求的保护范围之内。
请一并参阅图1-图5，本实用新型提供一种外延结构10，该外延结构10包括依次层叠设置的量子阱结构100、P型接触层200以及电极层300。
如图1所示，P型接触层200上包括第一台阶部410与第二台阶部 420，第一台阶部410与第二台阶部420具体可以呈台阶状设置，且第二台阶部420相对第一台阶部410而言，更为靠近量子阱结构100，可选的，第一台阶部410与第二台阶部420均填充有第一绝缘部400，该第一绝缘部400具体可以由到不导电且导热性较好的材料所组成，如可以是二氧化硅、碳化硅以及氮化铝等等。
在可选实施例中，可以通过在P型接触层200进行蚀刻，从而生成台阶结构，随后在台阶结构通过二氧化硅、碳化硅或者氮化铝等绝缘材料进行外延生成出第一绝缘部400，可以有效的将辐射电流限制在谐振腔内，从而可以有效的抑制端面区域的非辐射复合，即减少端面区域对光的吸收，进而以提高抗灾变性光学镜面损伤值。
且进一步的，由于第二台阶部420更为靠近量子阱结构100，因此在第二台阶部420下方区域进行量子阱混杂制程时，相比在其他区域进行量子阱混杂制程，扩散效率更高，且整个制程所需的热处理时间也较短，即掺杂材料的扩散效率更快，混杂更容易，防止在量子阱混杂制程过程中混杂材料掺杂到其他层或者侧向掺杂的情况，即可以减少制程过程对整个外延结构10的破坏或者降低制程过程中多馀的扩散，减少对外延结构10腔面结构的损害，进而可以减少腔面对光的吸收，以提高抗灾变性光学镜面损伤值，提高整个半导体芯片的寿命与质量。
且进一步的，由于第二台阶部420离量子阱结构100更近，因此在量子阱混杂制程过程中，可以在追踪蓝移(PL blue shift)量测时，可以更为便捷。
且进一步的，通过设置第一台阶部410和第二台阶部420，并在第一绝缘部400，可以直接在第一绝缘部400下面进行量子阱混杂制程，相比通过离子注射等方式实现制程的方法而言，无需重新去定位量子阱混杂制程的区域，并可以直接将量子阱混杂制程作为激光谐振腔区域，可以有效的简化工艺，减少制作成本。
如图1所示，第一台阶部410沿该外延结构10的谐振腔方向的长度L1大于第二台阶部420沿外延结构10的谐振腔方向的长度L2。
可选的，该第二台阶部420沿外延结构10的谐振腔方向的长度L2 大于或等于1um，小于或等于30um，具体可以是1um，10um或者30um。
如图1所示，第一台阶部410沿着P型接触层200与电极层300的层叠方向上的高度H1大于第二台阶部420沿P型接触层200与电极层300的层叠方向上的高度H2。
可选的，第二台阶部420沿P型接触层200与电极层300的层叠方向上的高度H2大于或等于1nm，小于或等于100nm。具体可以是1nm、50nm或者100nm，这里均不作具体限定。
如图3所示，第一台阶部410和第二台阶部420整体贯穿整个P型接触层200，即第二台阶部420直接与量子阱结构100连接，第一台阶部410则直接与电极层300连接。
如图4所示，P型接触层200上还可以进一步包括与第一台阶部410呈台阶状设置的第四台阶部430，第四台阶部430上也进一步填充有第一绝缘部400。
如图2所示，电极层300还包括有第三台阶部510，该第三台阶部510可以与第一台阶部410呈台阶状设置。且第三台阶部510与第一台阶部410呈台阶状设置。可选的，该第三台阶部510上填充有第二绝缘部500，且该第二绝缘部500可以与第一绝缘部410一体成型。即在可选实施例中，第一绝缘部400与第二绝缘部500可以使用二氧化硅而同时生成。
在其他实施例中，第三台阶部510也可以与第四台阶部430呈台阶状设置。
其中，第三台阶部510沿外延结构10的谐振腔方向的长度L3大于第一台阶部410沿外延结构10的谐振腔方向的长度L1。
如图5所示，外延结构10还包括设置于P型接触层200与量子阱结构100之间的P型覆盖层610以及第一波导层620。
如图5所示，外延结构10还包括依次设置于量子阱结构100远离P型接触层200的一侧的第二波导层630、N型覆盖层640以及N型衬底650。
其中，N型包覆层640沿层叠方向上的厚度一般大于或等于500nm小于或等于5000nm，具体可以为500nm、3000nm或者5000nm，第二波导层630沿层叠方向上的厚度一般大于或等于50nm，小于或等于250nm，具体 可以为50nm、200nm或者250nm。第一波导层620沿层叠方向上的厚度一般大于或等于50nm，小于或等于250nm，具体可以为50nm、100nm或者250nm。P型包覆层610沿层叠方向上的厚度一般大于或等于500nm小于或等于5000nm，具体可以为500nm、2000nm或者5000nm。
如图6所示，本申请还提供一种半导体芯片1，该半导体芯片1包括基板20以及上述任一实施例所述的外延结构10，且该外延结构10设置于基板20上。
综上所述，本实用新型提供的外延结构及应用其的半导体芯片通过在P型接触层200进行蚀刻，从而生成台阶结构，随后在台阶结构通过二氧化硅进行外延生成出第一绝缘部400，可以有效的将辐射电流限制在谐振腔内，从而可以有效的抑制端面区域的非辐射复合，即减少端面区域对光的吸收，进而提高灾变性光学镜面损伤值。且进一步的，本申请的第一绝缘部400进一步包括第一台阶部410和第二台阶部420，由于第二台阶部420更为靠近量子阱结构100，因此在第二台阶部420下方区域进行量子阱混杂制程时，扩散效率更高，且整个制程所需的热处理时间也较短，防止在量子阱混杂制程过程中混杂材料掺杂到其他层的情况，即可以减少制程过程对整个外延结构10的破坏或者降低制程过程中多馀的扩散，减少对外延结构10腔面结构的损害，进而可以减少腔面对光的吸收，以提高灾变性光学镜面损伤值，提高整个半导体芯片的寿命与质量。且进一步的，由于第二台阶部420离量子阱结构100更近，因此在量子阱混杂制程过程中，可以在追踪蓝移(PL blue shift)量测时，可以更为便捷。且进一步的，通过设置第一绝缘部400，可以直接在第一绝缘部400下面进行量子阱混杂制程，想通过离子注射等方式实现制程的方法而言，无需重新去定位量子阱混杂制程的区域，并可以直接将量子阱混杂制程作为激光谐振腔区域，可以有效的简化工艺，减少制作成本。
以上仅为本实用新型的实施方式，并非因此限制本实用新型的专利范围，凡是利用本实用新型说明书及附图内容所作的等效结果或等效流程变换，或直接或间接运用在其他相关的技术领域，均同理包括在本实用新型的专利保护范围内。

Claims (10)

  1. 一种外延结构，其特征在于，所述外延结构包括依次层叠设置的量子阱结构、P型接触层以及电极层；
    其中，所述P型接触层包括呈台阶状设置的第一台阶部与第二台阶部，所述第二台阶部相对所述第一台阶部更靠近所述量子阱结构；
    其中，所述第一台阶部与第二台阶部填充有第一绝缘部。
  2. 根据权利要求1所述的外延结构，其特征在于，所述第一台阶部沿所述外延结构的谐振腔方向的长度大于所述第二台阶部沿所述外延结构的谐振腔方向的长度。
  3. 根据权利要求2所述的外延结构，其特征在于，所述第二台阶部沿所述外延结构的谐振腔方向的长度大于或等于1um，小于或等于30um。
  4. 根据权利要求1-3任一项所述的外延结构，其特征在于，所述第一台阶部沿所述P型接触层与电极层的层叠方向上的高度大于所述第二台阶部沿所述P型接触层与电极层的层叠方向上的高度。
  5. 根据权利要求4所述的外延结构，其特征在于，所述第二台阶部沿所述P型接触层与电极层的层叠方向上的高度大于或等于1nm，小于或等于100nm。
  6. 根据权利要求1所述的外延结构，其特征在于，所述电极层包括与所述第一台阶部呈台阶状设置的第三台阶部，所述第三台阶部填充有第二绝缘部。
  7. 根据权利要求6所述的外延结构，其特征在于，所述第三台阶部沿所述外延结构的谐振腔方向的长度大于所述第一台阶部沿所述外延结构的谐振腔方向的长度。
  8. 根据权利要求1所述的外延结构，其特征在于，所述外延结构还包括设置于所述P型接触层与所述量子阱结构之间的P型覆盖层以及第一波导层。
  9. 根据权利要求8所述的外延结构，其特征在于，所述外延结构还包括依次设置于所述量子阱结构远离所述P型接触层的一侧的第二波导层、 N型覆盖层以及N型衬底。
  10. 一种半导体芯片，其特征在于，所述半导体芯片包括基板以及权利要求1-9中任一项所述的外延结构，所述外延结构设置于所述基板上。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002064247A (ja) * 2000-08-17 2002-02-28 Sony Corp 半導体レーザおよびその製造方法
CN104600565A (zh) * 2015-01-22 2015-05-06 中国科学院半导体研究所 一种具有低电子泄漏的砷化镓激光器及其制作方法
CN108141010A (zh) * 2015-09-28 2018-06-08 欧司朗光电半导体有限公司 半导体激光器
CN108352678A (zh) * 2015-09-28 2018-07-31 欧司朗光电半导体有限公司 具有在棱面上受抑制的电流注入的半导体激光器
CN213212654U (zh) * 2020-08-13 2021-05-14 深圳市中光工业技术研究院 外延结构及应用其的半导体芯片

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002064247A (ja) * 2000-08-17 2002-02-28 Sony Corp 半導体レーザおよびその製造方法
CN104600565A (zh) * 2015-01-22 2015-05-06 中国科学院半导体研究所 一种具有低电子泄漏的砷化镓激光器及其制作方法
CN108141010A (zh) * 2015-09-28 2018-06-08 欧司朗光电半导体有限公司 半导体激光器
CN108352678A (zh) * 2015-09-28 2018-07-31 欧司朗光电半导体有限公司 具有在棱面上受抑制的电流注入的半导体激光器
CN213212654U (zh) * 2020-08-13 2021-05-14 深圳市中光工业技术研究院 外延结构及应用其的半导体芯片

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