WO2022033547A1 - Double side cooling power package - Google Patents

Double side cooling power package Download PDF

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Publication number
WO2022033547A1
WO2022033547A1 PCT/CN2021/112235 CN2021112235W WO2022033547A1 WO 2022033547 A1 WO2022033547 A1 WO 2022033547A1 CN 2021112235 W CN2021112235 W CN 2021112235W WO 2022033547 A1 WO2022033547 A1 WO 2022033547A1
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WO
WIPO (PCT)
Prior art keywords
conduction
double side
cooling substrate
power package
semiconductor chip
Prior art date
Application number
PCT/CN2021/112235
Other languages
French (fr)
Inventor
Chung Hsing Tzu
Original Assignee
Lite-On Semiconductor Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lite-On Semiconductor Corporation filed Critical Lite-On Semiconductor Corporation
Priority to CN202180004154.6A priority Critical patent/CN114556550A/en
Publication of WO2022033547A1 publication Critical patent/WO2022033547A1/en

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Definitions

  • the disclosure relates to a power package, and particularly relates to a double side cooling power package.
  • the power device generates high amount of heat during operation, the heat dissipation is thus one of the main issues to be improved.
  • the double side cooling power package undergoes compressive stress and/or thermal stress caused by the difference in thermal expansion coefficient, it may be cracked or damaged.
  • the disclosure provides a double side cooling power package which can solve the problem caused by compressive stress and/or thermal stress.
  • the double side cooling power package of the disclosure includes a first cooling substrate, a second cooling substrate, at least one semiconductor chip, and a plurality of first conduction ribbons.
  • the second cooling substrate is disposed opposite to the first cooling substrate.
  • the semiconductor chip is bonded on one of the first cooling substrate and the second cooling substrate.
  • the first conduction ribbons are disposed between the first cooling substrate and the second cooling substrate, wherein each of the first conduction ribbons includes a first portion, a second portion and a bendable portion connecting the first portion and the second portion.
  • the bendable portion forms a closed loop with the edge of the first portion.
  • One of the first portion and the second portion is in direct contact with the semiconductor chip, and another of the first portion and the second portion extends away from the semiconductor chip.
  • the first conduction ribbons are discontinuous structures.
  • the first conduction ribbons are continuous structures.
  • the first portion is in direct contact with the semiconductor chip.
  • the first portion is coupled to the semiconductor chip through a first solder.
  • the semiconductor chip is bonded on the first cooling substrate, and the second portion of each of the first conduction ribbons is in direct contact with the second cooling substrate.
  • the semiconductor chip is bonded on the first cooling substrate, and the second portion of each of the first conduction ribbons is coupled to the second cooling substrate through a second solder.
  • the second portion is in direct contact with the semiconductor chip.
  • the second portion is coupled to the semiconductor chip through a first solder.
  • the semiconductor chip is bonded on the first cooling substrate, and the first portion of each of the first conduction ribbons is in direct contact with the second cooling substrate.
  • the semiconductor chip is bonded on the first cooling substrate, and the first portion of each of the first conduction ribbons is in direct contact with the second cooling substrate.
  • the package further includes a plurality of metal preforms disposed between the second cooling substrate and the semiconductor chip, wherein the metal preforms are in direct contact with the second cooling substrate, and the one of the first portion and the second portion is disposed between the metal preform and the semiconductor chip.
  • the package further includes at least one second conduction ribbon disposed between the first cooling substrate and the second cooling substrate, wherein the second conduction ribbon has the same shape as each of the first conduction ribbons, and the second conduction ribbon and the semiconductor chip are non-contact.
  • the second conduction ribbon and the first conduction ribbons are discontinuous structures.
  • the second conduction ribbon and the first conduction ribbons are continuous structures.
  • the first cooling substrate and the second cooling substrate are direct bond copper (DBC) substrates.
  • DBC direct bond copper
  • the disclosure provides a specific conduction ribbons in the double side cooling power package.
  • the bendable portion of the conduction ribbon is elastically deformed during the thermal compression process, and thus it can absorb the stress incurred by the thermal compression and the thermal stress amongst different materials.
  • the robustness of the package and the semiconductor chips is therefore improved.
  • the disclosure is also advantageous in terms of the processing cost (only one or two solder reflow steps are needed) and ideal heat dissipation performance.
  • FIG. 1A is a schematic side view of a double side cooling power package according to a first embodiment of the disclosure.
  • FIG. 1B is a three-dimensional view of the first conduction ribbons in the double side cooling power package of FIG. 1A.
  • FIG. 2 is a schematic side view of a double side cooling power package according to a second embodiment of the disclosure.
  • FIG. 3 is a schematic side view of a double side cooling power package according to a third embodiment of the disclosure.
  • FIG. 4 is a schematic side view of a double side cooling power package according to a fourth embodiment of the disclosure.
  • FIG. 5 is a schematic side view of a double side cooling power package according to a fifth embodiment of the disclosure.
  • FIG. 6 is a schematic side view of a double side cooling power package according to a sixth embodiment of the disclosure.
  • FIG. 7 is a schematic side view of a double side cooling power package according to a seventh embodiment of the disclosure.
  • FIG. 8 is a schematic side view of a double side cooling power package according to a eighth embodiment of the disclosure.
  • FIG. 9 is a schematic side view of a double side cooling power package according to a ninth embodiment of the disclosure.
  • FIG. 1A is a schematic side view of a double side cooling power package according to a first embodiment of the disclosure.
  • FIG. 1B is a three-dimensional view of the first conduction ribbons in the double side cooling power package of FIG. 1A.
  • the double side cooling power package 10 of the first embodiment includes a first cooling substrate 100, a second cooling substrate 102, at least one semiconductor chip 104, and a plurality of first conduction ribbons 106.
  • the second cooling substrate 102 is disposed opposite to the first cooling substrate 100.
  • the first cooling substrate 100 and the second cooling substrate 102 are direct bond copper (DBC) substrates, for example.
  • the first cooling substrate 100 includes at least a upper metal layer 100a, a lower metal layer 100b, and a dielectric plate 100c between the upper metal layer 100a and the lower metal layer 100b.
  • the second cooling substrate 102 includes at least a upper metal layer 102a, a lower metal layer 102b, and a dielectric plate 102c between the upper metal layer 102a and the lower metal layer 102b.
  • the semiconductor chip 104 is bonded on the first cooling substrate 100 through a solder 108, but the disclosure is not limited thereto; in another embodiment, the semiconductor chip 104 is bonded on the first cooling substrate 100 by ultrasonic compression (UC) bonding.
  • the semiconductor chip 104 is, for example, an IGBT, a MOSFET, a FRD (fast recovery diode) , or a wide band gap-based chip.
  • the first conduction ribbons 106 are disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein each of the first conduction ribbons 106 includes a first portion 106a, a second portion 106b and a bendable portion 106c connecting the first portion 106a and the second portion 106b.
  • the conduction ribbons 106 extend along Y-direction with the same geometry as illustrated in FIGs 1A-1B.
  • a material of the conductive ribbons 104 is, for example, copper.
  • there are two first conduction ribbons 106 in the first embodiment and they are continuous structures, wherein the connection parts are those second portions 106, and it is expected that the current capacity and thermal capacity of the double side cooling power package 10 can be further improved due to the continuous structure.
  • the bendable portion 106c forms a closed loop with the edge E of the first portion 106a, and the bendable portion 106c is an elastically deformable structure that can absorb stress or pressure when the double side cooling power package 10 is affected by thermal expansion or compressive stress.
  • the first portion 106a is in direct contact with the semiconductor chip 104 by bonding through UC bonding, but the disclosure is not limited thereto; in another embodiment, the first portion 106a can be bonded to the semiconductor chip 104 through a solder (not shown) .
  • the second portion 106b extends away from the semiconductor chip 104, and the second portion 106b of each of the first conduction ribbons 106 is in direct contact with the second cooling substrate 102.
  • the method for bonding the second portion 106b to the second cooling substrate 102 includes UC bonding or Laser welding, etc.
  • the disclosure is not limited thereto; in another embodiment, the second portion 106b can be bonded to the second cooling substrate 102 through another solder (not shown) .
  • the size of each of the conductive ribbons 106 can be changed based on desired needs; for example, the thickness t1 of the first conduction ribbon 106, the thickness t2 of the semiconductor chip 104, and the height difference h between the second portion 106b and the first portion 106a can be changed based on desired needs.
  • FIG. 2 is a schematic side view of a double side cooling power package according to a second embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
  • the difference between the first and the second embodiments is an additional solder 200 disposed between the semiconductor chip 104 and the first portion 106a of each of the conductive ribbons 106.
  • the composition of the solder 200 is the same as that of the solder 108
  • single reflow process may be performed during the manufacture for the double side cooling power package 20 of the second embodiment. For instance, the solders 108 are applied on the first cooling substrate 100 first, the semiconductor chips 104 are attached on the solders 108b, the additional solders 200 are then applied on the first portion 106a, the first cooling substrate 100 and the second cooling substrate 102 are laminated for bonding the semiconductor chips 104 to the solders 200, and the single reflow process is performed.
  • the solder 108 can have a higher melting point than the solder 200, and two-step reflow processes may be performed during the manufacture for the double side cooling power package 20 of the second embodiment. For instance, the solders 108 are applied on the first cooling substrate 100 first, the semiconductor chips 104 are attached on the solders 108b, a first reflow process is then performed, the additional solders 200 are applied on the first portion 106a after the first reflow process, the first cooling substrate 100 and the second cooling substrate 102 are laminated for bonding the semiconductor chips 104 to the solders 200, and a second reflow process is performed. Since the melting point of the solder 108 is higher than that of the solder 200, the solder 108 will not melt and deform during the second reflow process.
  • FIG. 3 is a schematic side view of a double side cooling power package according to a third embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
  • the first conduction ribbons 106 in the double side cooling power package 30 of the third embodiment are discontinuous structures, wherein the second portions 106b of different first conduction ribbons 106 are separated. Therefore, according to the capacity of circuit, the locations of the semiconductor chips 104 as well as the first conduction ribbons 106 can be modified.
  • the first conduction ribbons 106 in the double side cooling power package 30 may be a combination of continuous structures and discontinuous structures.
  • FIG. 4 is a schematic side view of a double side cooling power package according to a fourth embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
  • the difference between the first and the fourth embodiments is a second conduction ribbon 400 added in the double side cooling power package 40 of the fourth embodiment.
  • the second conduction ribbon 400 is disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein the second conduction ribbon 400 has the same shape as each of the first conduction ribbons 106, but the size therebetween may be a little different.
  • the second conduction ribbon 400 includes a first portion 400a, a second portion 400b and a bendable portion 400c connecting the first portion 400a and the second portion 400b, wherein the first portion 400a is in direct contact with the first cooling substrate 100, and the second portion 400b is in direct contact with the second cooling substrate 102.
  • the second conduction ribbon 400 and the semiconductor chip 104 are non-contact, and thus it can provide additional path for electric current and heat depending on the design of the circuit or topology.
  • the second conduction ribbon 400 and the first conduction ribbons 106 are continuous structures, wherein the second portion 400b connects to one of the second portion 106b.
  • FIG. 5 is a schematic side view of a double side cooling power package according to a fifth embodiment of the disclosure, wherein the reference symbols used in the fourth embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the fourth embodiment, and will not be repeated here.
  • the difference between the fifth and the fourth embodiments is the second conduction ribbon 400 and the first conduction ribbons 106 are discontinuous structures in the double side cooling power package 50 of the fifth embodiment, wherein the second portions 106b and 400b are separated. Therefore, according to the capacity of circuit, the locations of the semiconductor chips 104 as well as the first conduction ribbons 106 and the second conduction ribbon 400 can be modified.
  • FIG. 6 is a schematic side view of a double side cooling power package according to a sixth embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
  • the difference between the first and the sixth embodiments is a plurality of metal preforms 600 added in the double side cooling power package 60 of the fourth embodiment.
  • the metal preforms 600 are disposed between the second cooling substrate 102 and the semiconductor chips 104, and the metal preforms 600 are preferably formed corresponding to the center of each of the semiconductor chips 104.
  • the metal preforms 600 are in direct contact with the lower metal layer 102b of the second cooling substrate 102 by Laser welding or UC bonding (also known as ultrasonic welding) such as thermal ultrasonic compression, for example.
  • the first portion 106a of the first conduction ribbons 106 is disposed between the metal preform 600 and the semiconductor chip 104, and the first portion 106a can be bonded to the metal preform 600 through a solder 602.
  • the thickness of the metal preforms 600 is less than or equal to the height difference between the second portion 106b and the first portion 106a. Since the metal preforms 600 is, for example, made of copper with excellent thermal conductivity, the heat generated by the semiconductor chips 104 can be effectively transferred to the second cooling substrate 102 through the metal preforms 600.
  • FIG. 7 is a schematic side view of a double side cooling power package according to a seventh embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
  • the double side cooling power package 70 of the seventh embodiment also includes a first cooling substrate 100, a second cooling substrate 102, semiconductor chips 104, and a first conduction ribbons 106.
  • the second portion 106b of the first conduction ribbons 106 is coupled to the semiconductor chip 104 through a solder 700, but the disclosure is not limited thereto; in another embodiment, the semiconductor chip 104 is bonded on the second portion 106b by ultrasonic compression (UC) bonding.
  • UC ultrasonic compression
  • the method for bonding the first portion 106a to the second cooling substrate 102 includes UC bonding or Laser welding, etc.
  • the disclosure is not limited thereto; in another embodiment, the first portion 106a can be bonded to the second cooling substrate 102 through another solder (not shown) .
  • FIG. 8 is a schematic side view of a double side cooling power package according to a eighth embodiment of the disclosure, wherein the reference symbols used in the seventh embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the seventh embodiment, and will not be repeated here.
  • the difference between the seventh and the eighth embodiments is a second conduction ribbon 800 added in the double side cooling power package 80 of the fourth embodiment.
  • the second conduction ribbon 800 is disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein the second conduction ribbon 800 has the same shape as the first conduction ribbon 106, but the size therebetween may be a little different.
  • the second conduction ribbon 800 includes a first portion 800a, a second portion 800b and a bendable portion 800c connecting the first portion 800a and the second portion 800b.
  • the first portions 106a and 800a can be bonded to the second cooling substrate 102 through a solder 802.
  • the second conduction ribbon 800 and the semiconductor chip 104 are non-contact, and thus it can provide additional path for electric current and heat depending on the design of the circuit or topology.
  • the second conduction ribbon 800 and the first conduction ribbon 106 are discontinuous structures, wherein the second portion 800b and 106b are separated.
  • the second conduction ribbon 800 and the first conduction ribbon 106 may be continuous structures, or a combination of continuous structures and discontinuous structures.
  • FIG. 9 is a schematic side view of a double side cooling power package according to a ninth embodiment of the disclosure, wherein the reference symbols used in the seventh embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the seventh embodiment, and will not be repeated here.
  • the difference between the seventh and the ninth embodiments is a plurality of metal preforms 900 added in the double side cooling power package 90 of the fourth embodiment.
  • the metal preforms 900 are disposed between the second cooling substrate 102 and the semiconductor chips 104, wherein the metal preforms 900 are in direct contact with the lower metal layer 102b of the second cooling substrate 102.
  • the metal preforms 900 can be formed by UC bonding or Laser welding, etc.
  • the second portion 106b of the first conduction ribbons 106 is disposed between the metal preform 900 and the semiconductor chip 104, and the second portion 106b can be bonded to the metal preform 900 through a solder 902.
  • the metal preforms 900 is, for example, made of copper with excellent thermal conductivity, the metal preforms 900 can efficiently conduct heat from the semiconductor chips 104 towards the second cooling substrate 102, thereby good for heat dissipation of the double side cooling power package 90.
  • the double side cooling power package according to the disclosure can absorb the stress incurred by the thermal compression and the thermal stress amongst different materials by a specific conduction ribbons.
  • the bendable portion of the conduction ribbon is elastically deformed during the thermal compression process, and thus the robustness of the package and the semiconductor chips is therefore improved.
  • the disclosure is also advantageous in terms of the processing cost (only one or two solder reflow steps are needed) and ideal heat dissipation performance through the conduction ribbons.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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Abstract

A double side cooling power package includes a first cooling substrate, a second cooling substrate, at least one semiconductor chip, and a plurality of first conduction ribbons. The second cooling substrate is disposed opposite to the first cooling substrate. The semiconductor chip is bonded on one of the first cooling substrate and the second cooling substrate. The first conduction ribbons are disposed between the first cooling substrate and the second cooling substrate, wherein each of the first conduction ribbons includes a first portion, a second portion and a bendable portion connecting the first portion and the second portion. The bendable portion forms a closed loop with the edge of the first portion. One of the first portion and the second portion is in direct contact with the semiconductor chip, and another of the first portion and the second portion extends away from the semiconductor chip.

Description

DOUBLE SIDE COOLING POWER PACKAGE BACKGROUND Technical Field
The disclosure relates to a power package, and particularly relates to a double side cooling power package.
Description of Related Art
The power device generates high amount of heat during operation, the heat dissipation is thus one of the main issues to be improved.
Recently, a double side cooling power package has been widely used to utilize the heat sink efficiently. For example, there are two heat sinks disposed on two surfaces of the power device, and thus the heat dissipation efficiency can be improved.
However, if the double side cooling power package undergoes compressive stress and/or thermal stress caused by the difference in thermal expansion coefficient, it may be cracked or damaged.
SUMMARY
The disclosure provides a double side cooling power package which can solve the problem caused by compressive stress and/or thermal stress.
The double side cooling power package of the disclosure includes a first cooling substrate, a second cooling substrate, at least one semiconductor chip, and a plurality of first conduction ribbons. The second cooling substrate is disposed opposite to the first cooling substrate. The semiconductor chip is bonded on one of the first cooling substrate and the  second cooling substrate. The first conduction ribbons are disposed between the first cooling substrate and the second cooling substrate, wherein each of the first conduction ribbons includes a first portion, a second portion and a bendable portion connecting the first portion and the second portion. The bendable portion forms a closed loop with the edge of the first portion. One of the first portion and the second portion is in direct contact with the semiconductor chip, and another of the first portion and the second portion extends away from the semiconductor chip.
In an embodiment of the disclosure, the first conduction ribbons are discontinuous structures.
In an embodiment of the disclosure, the first conduction ribbons are continuous structures.
In an embodiment of the disclosure, the first portion is in direct contact with the semiconductor chip.
In an embodiment of the disclosure, the first portion is coupled to the semiconductor chip through a first solder.
In an embodiment of the disclosure, the semiconductor chip is bonded on the first cooling substrate, and the second portion of each of the first conduction ribbons is in direct contact with the second cooling substrate.
In an embodiment of the disclosure, the semiconductor chip is bonded on the first cooling substrate, and the second portion of each of the first conduction ribbons is coupled to the second cooling substrate through a second solder.
In an embodiment of the disclosure, the second portion is in direct contact with the semiconductor chip.
In an embodiment of the disclosure, the second portion is coupled to the semiconductor chip through a first solder.
In an embodiment of the disclosure, the semiconductor chip is bonded on the first cooling substrate, and the first portion of each of the first conduction ribbons is in direct contact with the second cooling substrate.
In an embodiment of the disclosure, the semiconductor chip is bonded on the first cooling substrate, and the first portion of each of the first conduction ribbons is in direct contact with the second cooling substrate.
In an embodiment of the disclosure, the package further includes a plurality of metal preforms disposed between the second cooling substrate and the semiconductor chip, wherein the metal preforms are in direct contact with the second cooling substrate, and the one of the first portion and the second portion is disposed between the metal preform and the semiconductor chip.
In an embodiment of the disclosure, the package further includes at least one second conduction ribbon disposed between the first cooling substrate and the second cooling substrate, wherein the second conduction ribbon has the same shape as each of the first conduction ribbons, and the second conduction ribbon and the semiconductor chip are non-contact.
In an embodiment of the disclosure, the second conduction ribbon and the first conduction ribbons are discontinuous structures.
In an embodiment of the disclosure, the second conduction ribbon and the first conduction ribbons are continuous structures.
In an embodiment of the disclosure, the first cooling substrate and the second cooling substrate are direct bond copper (DBC) substrates.
Based on the above, the disclosure provides a specific conduction ribbons in the double side cooling power package. In detail, the bendable portion of the conduction ribbon is elastically deformed during the thermal compression process, and thus it can absorb the stress incurred by the thermal compression and the thermal stress amongst different materials. The  robustness of the package and the semiconductor chips is therefore improved. In addition, the disclosure is also advantageous in terms of the processing cost (only one or two solder reflow steps are needed) and ideal heat dissipation performance.
To make the aforementioned more comprehensible, several embodiments accompanied with drawings are described in detail as follows.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1A is a schematic side view of a double side cooling power package according to a first embodiment of the disclosure.
FIG. 1B is a three-dimensional view of the first conduction ribbons in the double side cooling power package of FIG. 1A.
FIG. 2 is a schematic side view of a double side cooling power package according to a second embodiment of the disclosure.
FIG. 3 is a schematic side view of a double side cooling power package according to a third embodiment of the disclosure.
FIG. 4 is a schematic side view of a double side cooling power package according to a fourth embodiment of the disclosure.
FIG. 5 is a schematic side view of a double side cooling power package according to a fifth embodiment of the disclosure.
FIG. 6 is a schematic side view of a double side cooling power package according to a sixth embodiment of the disclosure.
FIG. 7 is a schematic side view of a double side cooling power package according to a seventh embodiment of the disclosure.
FIG. 8 is a schematic side view of a double side cooling power package according to a eighth embodiment of the disclosure.
FIG. 9 is a schematic side view of a double side cooling power package according to a ninth embodiment of the disclosure.
DESCRIPTION OF THE EMBODIMENTS
Referring to the embodiments below and the accompanied drawings for a sufficient understanding of the disclosure. However, the disclosure may be implemented in many other different forms and should not be construed as limited to the embodiments described hereinafter. In the drawings, for clarity, the elements and relative dimensions thereof may not be scaled. For easy understanding, the same elements in the following embodiments will be denoted by the same reference numerals.
FIG. 1A is a schematic side view of a double side cooling power package according to a first embodiment of the disclosure. FIG. 1B is a three-dimensional view of the first conduction ribbons in the double side cooling power package of FIG. 1A.
Referring to FIGs. 1A and 1B, the double side cooling power package 10 of the first embodiment includes a first cooling substrate 100, a second cooling substrate 102, at least one semiconductor chip 104, and a plurality of first conduction ribbons 106. The second cooling substrate 102 is disposed opposite to the first cooling substrate 100. In the embodiment, the first cooling substrate 100 and the second cooling substrate 102 are direct bond copper (DBC) substrates, for example. The first cooling substrate 100 includes at least a upper metal layer 100a, a lower metal layer 100b, and a dielectric plate 100c between the upper metal layer 100a and the lower metal layer 100b. The second cooling substrate 102 includes at least a upper  metal layer 102a, a lower metal layer 102b, and a dielectric plate 102c between the upper metal layer 102a and the lower metal layer 102b. The semiconductor chip 104 is bonded on the first cooling substrate 100 through a solder 108, but the disclosure is not limited thereto; in another embodiment, the semiconductor chip 104 is bonded on the first cooling substrate 100 by ultrasonic compression (UC) bonding. The semiconductor chip 104 is, for example, an IGBT, a MOSFET, a FRD (fast recovery diode) , or a wide band gap-based chip. The first conduction ribbons 106 are disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein each of the first conduction ribbons 106 includes a first portion 106a, a second portion 106b and a bendable portion 106c connecting the first portion 106a and the second portion 106b. The conduction ribbons 106 extend along Y-direction with the same geometry as illustrated in FIGs 1A-1B. A material of the conductive ribbons 104 is, for example, copper. In particular, there are two first conduction ribbons 106 in the first embodiment, and they are continuous structures, wherein the connection parts are those second portions 106, and it is expected that the current capacity and thermal capacity of the double side cooling power package 10 can be further improved due to the continuous structure. The bendable portion 106c forms a closed loop with the edge E of the first portion 106a, and the bendable portion 106c is an elastically deformable structure that can absorb stress or pressure when the double side cooling power package 10 is affected by thermal expansion or compressive stress. In the embodiment, the first portion 106a is in direct contact with the semiconductor chip 104 by bonding through UC bonding, but the disclosure is not limited thereto; in another embodiment, the first portion 106a can be bonded to the semiconductor chip 104 through a solder (not shown) . The second portion 106b extends away from the semiconductor chip 104, and the second portion 106b of each of the first conduction ribbons 106 is in direct contact with the second cooling substrate 102. Since the materials of the first conduction ribbons 106 and the lower metal layer 102b may be the same, the method for bonding the second portion 106b to  the second cooling substrate 102 includes UC bonding or Laser welding, etc. However, the disclosure is not limited thereto; in another embodiment, the second portion 106b can be bonded to the second cooling substrate 102 through another solder (not shown) . In addition, the size of each of the conductive ribbons 106 can be changed based on desired needs; for example, the thickness t1 of the first conduction ribbon 106, the thickness t2 of the semiconductor chip 104, and the height difference h between the second portion 106b and the first portion 106a can be changed based on desired needs.
FIG. 2 is a schematic side view of a double side cooling power package according to a second embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
Referring to FIG. 2, the difference between the first and the second embodiments is an additional solder 200 disposed between the semiconductor chip 104 and the first portion 106a of each of the conductive ribbons 106. If the composition of the solder 200 is the same as that of the solder 108, single reflow process may be performed during the manufacture for the double side cooling power package 20 of the second embodiment. For instance, the solders 108 are applied on the first cooling substrate 100 first, the semiconductor chips 104 are attached on the solders 108b, the additional solders 200 are then applied on the first portion 106a, the first cooling substrate 100 and the second cooling substrate 102 are laminated for bonding the semiconductor chips 104 to the solders 200, and the single reflow process is performed. In another embodiment, if the composition of the solder 200 is different from that of the solder 108, the solder 108 can have a higher melting point than the solder 200, and two-step reflow processes may be performed during the manufacture for the double side cooling power package 20 of the second embodiment. For instance, the solders 108 are applied on the first cooling substrate 100 first, the semiconductor chips 104 are attached on the solders 108b, a first reflow  process is then performed, the additional solders 200 are applied on the first portion 106a after the first reflow process, the first cooling substrate 100 and the second cooling substrate 102 are laminated for bonding the semiconductor chips 104 to the solders 200, and a second reflow process is performed. Since the melting point of the solder 108 is higher than that of the solder 200, the solder 108 will not melt and deform during the second reflow process.
FIG. 3 is a schematic side view of a double side cooling power package according to a third embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
Referring to FIG. 3, the first conduction ribbons 106 in the double side cooling power package 30 of the third embodiment are discontinuous structures, wherein the second portions 106b of different first conduction ribbons 106 are separated. Therefore, according to the capacity of circuit, the locations of the semiconductor chips 104 as well as the first conduction ribbons 106 can be modified. In another embodiment, the first conduction ribbons 106 in the double side cooling power package 30 may be a combination of continuous structures and discontinuous structures.
FIG. 4 is a schematic side view of a double side cooling power package according to a fourth embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
Referring to FIG. 4, the difference between the first and the fourth embodiments is a second conduction ribbon 400 added in the double side cooling power package 40 of the fourth embodiment. The second conduction ribbon 400 is disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein the second conduction ribbon 400 has the same shape as each of the first conduction ribbons 106, but the size therebetween may be a little  different. For example, the second conduction ribbon 400 includes a first portion 400a, a second portion 400b and a bendable portion 400c connecting the first portion 400a and the second portion 400b, wherein the first portion 400a is in direct contact with the first cooling substrate 100, and the second portion 400b is in direct contact with the second cooling substrate 102. The second conduction ribbon 400 and the semiconductor chip 104 are non-contact, and thus it can provide additional path for electric current and heat depending on the design of the circuit or topology. In the embodiment, the second conduction ribbon 400 and the first conduction ribbons 106 are continuous structures, wherein the second portion 400b connects to one of the second portion 106b.
FIG. 5 is a schematic side view of a double side cooling power package according to a fifth embodiment of the disclosure, wherein the reference symbols used in the fourth embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the fourth embodiment, and will not be repeated here.
Referring to FIG. 5, the difference between the fifth and the fourth embodiments is the second conduction ribbon 400 and the first conduction ribbons 106 are discontinuous structures in the double side cooling power package 50 of the fifth embodiment, wherein the  second portions  106b and 400b are separated. Therefore, according to the capacity of circuit, the locations of the semiconductor chips 104 as well as the first conduction ribbons 106 and the second conduction ribbon 400 can be modified.
FIG. 6 is a schematic side view of a double side cooling power package according to a sixth embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
Referring to FIG. 6, the difference between the first and the sixth embodiments is a plurality of metal preforms 600 added in the double side cooling power package 60 of the fourth  embodiment. The metal preforms 600 are disposed between the second cooling substrate 102 and the semiconductor chips 104, and the metal preforms 600 are preferably formed corresponding to the center of each of the semiconductor chips 104. The metal preforms 600 are in direct contact with the lower metal layer 102b of the second cooling substrate 102 by Laser welding or UC bonding (also known as ultrasonic welding) such as thermal ultrasonic compression, for example. In addition, the first portion 106a of the first conduction ribbons 106 is disposed between the metal preform 600 and the semiconductor chip 104, and the first portion 106a can be bonded to the metal preform 600 through a solder 602. In one embodiment, the thickness of the metal preforms 600 is less than or equal to the height difference between the second portion 106b and the first portion 106a. Since the metal preforms 600 is, for example, made of copper with excellent thermal conductivity, the heat generated by the semiconductor chips 104 can be effectively transferred to the second cooling substrate 102 through the metal preforms 600.
FIG. 7 is a schematic side view of a double side cooling power package according to a seventh embodiment of the disclosure, wherein the reference symbols used in the first embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the first embodiment, and will not be repeated here.
Referring to FIG. 7, the double side cooling power package 70 of the seventh embodiment also includes a first cooling substrate 100, a second cooling substrate 102, semiconductor chips 104, and a first conduction ribbons 106. However, the second portion 106b of the first conduction ribbons 106 is coupled to the semiconductor chip 104 through a solder 700, but the disclosure is not limited thereto; in another embodiment, the semiconductor chip 104 is bonded on the second portion 106b by ultrasonic compression (UC) bonding. The first portion 106a of the first conduction ribbon 106 is in direct contact with the second cooling substrate 102. Since the materials of the first conduction ribbon 106 and the lower metal layer  102b may be the same, the method for bonding the first portion 106a to the second cooling substrate 102 includes UC bonding or Laser welding, etc. However, the disclosure is not limited thereto; in another embodiment, the first portion 106a can be bonded to the second cooling substrate 102 through another solder (not shown) .
FIG. 8 is a schematic side view of a double side cooling power package according to a eighth embodiment of the disclosure, wherein the reference symbols used in the seventh embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the seventh embodiment, and will not be repeated here.
Referring to FIG. 8, the difference between the seventh and the eighth embodiments is a second conduction ribbon 800 added in the double side cooling power package 80 of the fourth embodiment. The second conduction ribbon 800 is disposed between the first cooling substrate 100 and the second cooling substrate 102, wherein the second conduction ribbon 800 has the same shape as the first conduction ribbon 106, but the size therebetween may be a little different. For example, the second conduction ribbon 800 includes a first portion 800a, a second portion 800b and a bendable portion 800c connecting the first portion 800a and the second portion 800b. The  first portions  106a and 800a can be bonded to the second cooling substrate 102 through a solder 802. The second conduction ribbon 800 and the semiconductor chip 104 are non-contact, and thus it can provide additional path for electric current and heat depending on the design of the circuit or topology. In the embodiment, the second conduction ribbon 800 and the first conduction ribbon 106 are discontinuous structures, wherein the  second portion  800b and 106b are separated. Alternatively, the second conduction ribbon 800 and the first conduction ribbon 106 may be continuous structures, or a combination of continuous structures and discontinuous structures.
FIG. 9 is a schematic side view of a double side cooling power package according to a ninth embodiment of the disclosure, wherein the reference symbols used in the seventh  embodiment are used to equally represent the same or similar devices. The description of the same components can be derived from the seventh embodiment, and will not be repeated here.
Referring to FIG. 9, the difference between the seventh and the ninth embodiments is a plurality of metal preforms 900 added in the double side cooling power package 90 of the fourth embodiment. The metal preforms 900 are disposed between the second cooling substrate 102 and the semiconductor chips 104, wherein the metal preforms 900 are in direct contact with the lower metal layer 102b of the second cooling substrate 102. The metal preforms 900 can be formed by UC bonding or Laser welding, etc. In addition, the second portion 106b of the first conduction ribbons 106 is disposed between the metal preform 900 and the semiconductor chip 104, and the second portion 106b can be bonded to the metal preform 900 through a solder 902. Since the metal preforms 900 is, for example, made of copper with excellent thermal conductivity, the metal preforms 900 can efficiently conduce heat from the semiconductor chips 104 towards the second cooling substrate 102, thereby good for heat dissipation of the double side cooling power package 90.
In summary, the double side cooling power package according to the disclosure can absorb the stress incurred by the thermal compression and the thermal stress amongst different materials by a specific conduction ribbons. In particular, the bendable portion of the conduction ribbon is elastically deformed during the thermal compression process, and thus the robustness of the package and the semiconductor chips is therefore improved. In addition, the disclosure is also advantageous in terms of the processing cost (only one or two solder reflow steps are needed) and ideal heat dissipation performance through the conduction ribbons.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.
REFERENCE SIGNS LIST
10, 20, 30, 40, 50, 60, 70, 80, 90: double side cooling power package
100: first cooling substrate
100a, 102a: upper metal layer
100b, 102b: lower metal layer
100c, 102c: dielectric plate
102: second cooling substrate
104: semiconductor chip
106: first conduction ribbons
106a, 400a, 800a: first portion
106b, 400b, 800b: second portion
106c, 400c, 800c: bendable portion
108, 200, 602, 700, 802, 902: solder
400, 800: second conduction ribbon
600, 900: metal preform
E: edge
h: height difference
t1, t2: thickness

Claims (16)

  1. A double side cooling power package, comprising:
    a first cooling substrate;
    a second cooling substrate, disposed opposite to the first cooling substrate;
    at least one semiconductor chip, bonded on one of the first cooling substrate and the second cooling substrate; and
    a plurality of first conduction ribbons disposed between the first cooling substrate and the second cooling substrate, wherein each of the first conduction ribbons comprises a first portion, a second portion and a bendable portion connecting the first portion and the second portion, the bendable portion forms a closed loop with the edge of the first portion, one of the first portion and the second portion is coupled to the semiconductor chip, and another of the first portion and the second portion extends away from the semiconductor chip.
  2. The double side cooling power package according to claim 1, wherein the first conduction ribbons are discontinuous structures.
  3. The double side cooling power package according to claim 1, wherein the first conduction ribbons are continuous structures.
  4. The double side cooling power package according to claim 1, wherein the first portion is in direct contact with the semiconductor chip.
  5. The double side cooling power package according to claim 1, wherein the first portion is coupled to the semiconductor chip through a first solder.
  6. The double side cooling power package according to claim 1, wherein the semiconductor chip is bonded on the first cooling substrate, and the second portion of each of the first conduction ribbons is in direct contact with the second cooling substrate.
  7. The double side cooling power package according to claim 1, wherein the semiconductor chip is bonded on the first cooling substrate, and the second portion of each of the first  conduction ribbons is coupled to the second cooling substrate through a second solder.
  8. The double side cooling power package according to claim 1, wherein the second portion is in direct contact with the semiconductor chip.
  9. The double side cooling power package according to claim 1, wherein the second portion is coupled to the semiconductor chip through a first solder.
  10. The double side cooling power package according to claim 1, wherein the semiconductor chip is bonded on the first cooling substrate, and the first portion of each of the first conduction ribbons is in direct contact with the second cooling substrate.
  11. The double side cooling power package according to claim 1, wherein the semiconductor chip is bonded on the first cooling substrate, and the second portion of each of the first conduction ribbons is coupled to the second cooling substrate through a second solder.
  12. The double side cooling power package according to claim 1, further comprises a plurality of metal preforms disposed between the second cooling substrate and the semiconductor chip, wherein the metal preforms are in direct contact with the second cooling substrate, and the one of the first portion and the second portion is disposed between the metal preform and the semiconductor chip.
  13. The double side cooling power package according to claim 1, further comprises at least one second conduction ribbon disposed between the first cooling substrate and the second cooling substrate, wherein the second conduction ribbon has the same shape as each of the first conduction ribbons, and the second conduction ribbon and the semiconductor chip are non-contact.
  14. The double side cooling power package according to claim 13, wherein the second conduction ribbon and the first conduction ribbons are discontinuous structures.
  15. The double side cooling power package according to claim 13, wherein the second conduction ribbon and the first conduction ribbons are continuous structures.
  16. The double side cooling power package according to claim 1, wherein the first cooling substrate and the second cooling substrate comprise direct bond copper substrates.
PCT/CN2021/112235 2020-08-12 2021-08-12 Double side cooling power package WO2022033547A1 (en)

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