CN114556550A - Double-sided cooling power packaging structure - Google Patents

Double-sided cooling power packaging structure Download PDF

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Publication number
CN114556550A
CN114556550A CN202180004154.6A CN202180004154A CN114556550A CN 114556550 A CN114556550 A CN 114556550A CN 202180004154 A CN202180004154 A CN 202180004154A CN 114556550 A CN114556550 A CN 114556550A
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China
Prior art keywords
cooling
package structure
power package
cooling substrate
substrate
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Pending
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CN202180004154.6A
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Chinese (zh)
Inventor
资重兴
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Luxemburg Dahl International Ltd By Share Ltd
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Lite On Semiconductor Corp
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Publication of CN114556550A publication Critical patent/CN114556550A/en
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

The invention provides a double-sided cooling power packaging structure which comprises a first cooling substrate, a second cooling substrate, at least one semiconductor chip and a plurality of first conductive strips. The second cooling substrate is arranged opposite to the first cooling substrate. The semiconductor wafer is bonded to one of the first cooling substrate and the second cooling substrate. The first conductive strips are disposed between the first and second cooled substrates, wherein each first conductive strip includes a first portion, a second portion, and a bendable portion connecting the first and second portions. The bendable portion forms a closed loop at an edge of the first portion. One of the first and second portions is in direct contact with the semiconductor wafer, while the other of the first and second portions extends away from the semiconductor wafer.

Description

Double-sided cooling power packaging structure
Technical Field
The present invention relates to a power package structure, and more particularly, to a double-sided cooling power package structure.
Background
Power devices typically generate a large amount of heat during operation, and thus heat dissipation is one of the major issues to be improved.
Recently, a double-sided cooling power package has been widely used as an effective heat sink (heat sink). For example, two heat sinks are provided on both sides of the power device, and therefore, the heat dissipation efficiency can be improved.
However, if the dual-sided cooling power package structure is subjected to compressive stress and/or thermal stress due to the difference in thermal expansion coefficients, it may be broken or damaged
Disclosure of Invention
The invention aims at a double-sided cooling power packaging structure which can solve the problems caused by pressure stress and/or thermal stress.
The double-sided cooling power package structure comprises a first cooling substrate, a second cooling substrate, at least one semiconductor chip and a plurality of first conductive strips (conductive strips). The second cooling substrate is arranged opposite to the first cooling substrate. The semiconductor wafer is bonded to one of the first cooling substrate and the second cooling substrate. The first conductive strips are disposed between a first cooling substrate and a second cooling substrate, wherein each first conductive strip includes a first portion, a second portion, and a bendable portion (bendable port) connecting the first portion and the second portion. The bendable portion forms a closed loop (closed loop) at an edge of the first portion. One of the first and second portions is in direct contact with the semiconductor wafer, while the other of the first and second portions extends away from the semiconductor wafer.
In an embodiment of the invention, the first conductive strip is a discontinuous structure.
In one embodiment of the present invention, the first conductive strip is a continuous structure.
In an embodiment of the invention, the first portion is in direct contact with the semiconductor wafer.
In one embodiment of the present invention, the first portion is bonded to the semiconductor wafer via a first solder.
In an embodiment of the invention, the semiconductor die is bonded on the first cooling substrate, and the second portion of each first conductive strip is in direct contact with the second cooling substrate.
In one embodiment of the present invention, the semiconductor die is bonded on the first cooling substrate, and the second portion of each first conductive strap is bonded to the second cooling substrate via a second solder.
In an embodiment of the invention, the second portion is in direct contact with the semiconductor wafer.
In one embodiment of the present invention, the second portion is bonded to the semiconductor wafer via a first solder.
In one embodiment of the present invention, the semiconductor die is bonded to the first cooling substrate with the first portion of each first conductive strap in direct contact with the second cooling substrate.
In one embodiment of the present invention, the semiconductor die is bonded on the first cooling substrate, and the second portion of each first conductive strip is bonded to the second cooling substrate via a second solder.
In an embodiment of the invention, the package structure further comprises a plurality of metal pre-forms disposed between the second cooling substrate and the semiconductor die, wherein the metal pre-forms are in direct contact with the second cooling substrate and one of the first portion and the second portion is disposed between the metal pre-forms and the semiconductor die.
In an embodiment of the invention, the package structure further includes at least one second conductive strip disposed between the first cooling substrate and the second cooling substrate, wherein the second conductive strip has the same shape as each of the first conductive strips, and the second conductive strip does not contact the semiconductor wafer.
In an embodiment of the invention, the second conductive strip and the first conductive strip are discontinuous structures.
In an embodiment of the present invention, the second conductive strip and the first conductive strip are a continuous structure.
In an embodiment of the invention, the first cooling substrate and the second cooling substrate are Direct Bonded Copper (DBC) substrates.
Based on the above, the present invention provides a specific conductive tape in a dual-sided cooling power package structure. Specifically, the bendable portion of the conductive tape is elastically deformed during thermal compression, thereby absorbing stress generated by thermal compression and thermal stress between different materials. Therefore, the robustness of the package structure and the semiconductor chip can be improved. In addition, the present invention also has advantages in terms of process cost (only one or two reflow soldering steps are needed) and desirable heat dissipation performance.
In order that the foregoing may be more readily understood, several embodiments are described in detail below with reference to the accompanying drawings.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The accompanying drawings illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention.
Fig. 1A is a schematic side view of a double-sided cooling power package structure according to a first embodiment of the invention.
Fig. 1B is a perspective view of a first conductive strip in the dual-sided cooling power package structure of fig. 1A.
Fig. 2 is a schematic side view of a double-sided cooling power package structure according to a second embodiment of the invention.
Fig. 3 is a schematic side view of a double-sided cooling power package structure according to a third embodiment of the invention.
Fig. 4 is a schematic side view of a double-sided cooling power package structure according to a fourth embodiment of the invention.
Fig. 5 is a schematic side view of a double-sided cooling power package structure according to a fifth embodiment of the invention.
Fig. 6 is a schematic side view of a dual-sided cooling power package structure according to a sixth embodiment of the invention.
Fig. 7 is a schematic side view of a dual-side cooling power package according to a seventh embodiment of the invention.
Fig. 8 is a schematic side view of a double-sided cooling power package structure according to an eighth embodiment of the invention.
Fig. 9 is a schematic side view of a dual-side cooling power package structure according to a ninth embodiment of the invention.
Description of the reference numerals
10. 20, 30, 40, 50, 60, 70, 80, 90: double-sided cooling power packaging structure
100: first cooling substrate
100a, 102 a: upper metal layer
100b, 102 b: lower metal layer
100c, 102 c: dielectric plate
102: second cooling substrate
104: semiconductor wafer
106: a first conductive band
106a, 400a, 800 a: first part
106b, 400b, 800 b: the second part
106c, 400c, 800 c: bendable portion
108. 200, 602, 700, 802, 902: solder
400. 800: second conductive tape
600. 900: metal preform
E: edge of a container
h: height difference
t1, t 2: thickness of
Detailed Description
The present invention will be fully understood with reference to the following examples and the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, the devices and their relative dimensions may not be to scale for clarity. For ease of understanding, like components in the following embodiments may be denoted by like reference numerals.
Fig. 1A is a schematic side view of a double-sided cooling power package structure according to a first embodiment of the invention. Fig. 1B is a perspective view of a first conductive strip in the dual-sided cooling power package structure of fig. 1A.
Referring to fig. 1A and 1B, a dual-side cooling power package 10 of the first embodiment includes a first cooling substrate 100, a second cooling substrate 102, at least one semiconductor chip 104, and a plurality of first conductive strips 106. The second cooling substrate 102 is disposed opposite to the first cooling substrate 100. In this embodiment, the first cooling substrate 100 and the second cooling substrate 102 are, for example, direct copper clad ceramic (DBC) substrates. The first cooling substrate 100 includes at least an upper metal layer 100a, a lower metal layer 100b, and a dielectric plate 100c between the upper metal layer 100a and the lower metal layer 100 b. The second cooling substrate 102 includes at least an upper metal layer 102a, a lower metal layer 102b, and a dielectric plate 102c between the upper metal layer 102a and the lower metal layer 102 b. The semiconductor chip 104 is bonded to the first cooling substrate 100 via a solder 108, but the invention is not limited thereto; in another embodiment, the semiconductor wafer 104 is bonded to the first cooled substrate 100 by Ultrasonic Compression (UC). The semiconductor die 104 is, for example, an IGBT, a MOSFET, a Fast Recovery Diode (FRD), or a wide bandgap die. The first conductive strips 106 are disposed between the first and second cooling substrates 100, 102, wherein each first conductive strip 106 includes a first portion 106a, a second portion 106b, and a bendable portion (bendable port) 106c connecting the first portion 106a and the second portion 106 b. The first conductive strip 106 extends in the Y-direction in the same geometry as shown in fig. 1A-1B. The conductive strip 106 is made of a material such as copper. Specifically, the first embodiment has two first conductive strips 106, and is a continuous structure, wherein the connection portion is the second portion 106b thereof, and due to the continuous structure, it is expected to further increase the current capacity (current capacity) and the thermal capacity (thermal capacity) of the double-sided cooling power package 10. The bendable portion 106c forms a closed loop (closed loop) at the edge E of the first portion 106a, and the bendable portion 106c is an elastically deformable structure, so that when the dual-sided cooling power package structure 10 is affected by thermal expansion or compression stress, stress or pressure can be absorbed. In the present embodiment, the first portion 106a is in direct contact with the semiconductor wafer 104 by UC bonding, but the invention is not limited thereto; in another embodiment, the first portion 106a may be bonded to the semiconductor die 104 by solder (not shown). The second portion 106b extends away from the semiconductor wafer 104 and the second portion 106b of each first conductive strip 106 directly contacts the second cooling substrate 102. Since the materials of the first conductive band 106 and the lower metal layer 102b can be the same, the joining method of the second portion 106b and the second cooling substrate 102 includes UC joining or laser welding. However, the present invention is not limited thereto; in another embodiment, the second portion 106b may be bonded to the second cooling substrate 102 by solder (not shown). In addition, the size of each first conductive strip 106 may vary as desired; for example, the thickness t1 of the first conductive strip 106, the thickness t2 of the semiconductor wafer 104, and the height difference h between the second portion 106b and the first portion 106a may be varied as desired.
Fig. 2 is a side view of a double-sided cooling power package structure according to a second embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to designate the same or similar components. The contents of the same or similar components can also refer to the related description of the first embodiment, and are not repeated.
Referring to fig. 2, the difference between the first and second embodiments is that an additional solder 200 is disposed between the semiconductor wafer 104 and the first portion 106a of each first conductive strip 106. If the composition of the solder 200 is the same as the composition of the solder 108, a single reflow process may be performed during the fabrication of the double-sided cooling power package 20 of the second embodiment. For example, solder 108 is applied to the first cooled substrate 100, the semiconductor die 104 is attached to the solder 108, additional solder 200 is applied to the first portion 106a, the first cooled substrate 100 and the second cooled substrate 102 are laminated to bond the semiconductor die 104 to the solder 200, and the single reflow soldering process described above is performed. In another embodiment, if the composition of the solder 200 is different from the composition of the solder 108, the solder 108 may have a higher melting point than the solder 200 and a secondary reflow process may be performed during the fabrication of the double-sided cooling power package structure 20 of the second embodiment. For example, the solder 108 is applied to the first cooling substrate 100, the semiconductor wafer 104 is attached to the solder 108, a first reflow process is performed, additional solder 200 is applied to the first portion 106a after the first reflow process, the first cooling substrate 100 and the second cooling substrate 102 are laminated to bond the semiconductor wafer 104 to the solder 200, and a second reflow process is performed. Since the melting point of solder 108 is higher than the melting point of solder 200, solder 108 does not melt and deform during the second reflow process.
Fig. 3 is a schematic side view of a double-sided cooling power package structure according to a third embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to designate the same or similar components. The contents of the same or similar components can also refer to the related description of the first embodiment, and are not repeated.
Referring to fig. 3, the first conductive strip 106 of the double-sided cooling power package structure 30 of the third embodiment is a discontinuous structure, wherein the second portions 106b of different first conductive strips 106 are separated. Thus, the position of the semiconductor wafer 104 and the first conductive strap 106 may vary depending on the capacity of the circuit. In another embodiment, the first conductive strip 106 in the dual sided cooling power package structure 30 may be a combination of a continuous structure and a discontinuous structure.
Fig. 4 is a schematic side view of a double-sided cooling power package structure according to a fourth embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to designate the same or similar components. The contents of the same or similar components can also refer to the related description of the first embodiment, and are not repeated.
Referring to fig. 4, the difference between the first and fourth embodiments is that the double-sided cooling power package structure 40 of the fourth embodiment further includes a second conductive strap 400. A second conductive strip 400 is disposed between the first and second cooled substrates 100, 102, wherein the second conductive strip 400 has the same shape as each of the first conductive strips 106, but may differ in size. For example, the second conductive strip 400 includes a first portion 400a, a second portion 400b, and a bendable portion 400c connecting the first portion 400a and the second portion 400b, wherein the first portion 400a is in direct contact with the first cooling substrate 100 and the second portion 400b is in direct contact with the second cooling substrate 102. The second conductive strip 400 does not contact the semiconductor wafer 104 and therefore provides an additional path for current and heat depending on the design of the circuit or topology. In this embodiment, the second conductive strip 400 is a continuous structure with the first conductive strip 106, wherein the second portion 400b is connected to a second portion 106 b.
Fig. 5 is a schematic side view of a double-sided cooling power package structure according to a fifth embodiment of the present invention, wherein the same reference numerals as in the fourth embodiment are used to designate the same or similar components. The contents of the same or similar components can also refer to the related description of the fourth embodiment, and are not repeated.
Referring to fig. 5, the difference between the fifth embodiment and the fourth embodiment is that the second conductive strip 400 and the first conductive strip 106 in the double-sided cooling power package structure 50 of the fifth embodiment are discontinuous structures, wherein the second portions 106b and 400b are separated. Thus, the position of the semiconductor wafer 104 and the positions of the first and second conductive strips 106, 400 may be varied depending on the capacity of the circuit.
Fig. 6 is a schematic side view of a double-sided cooling power package structure according to a sixth embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to designate the same or similar components. The contents of the same or similar components can also refer to the related description of the first embodiment, and are not repeated.
Referring to fig. 6, the difference between the first and sixth embodiments is that there are a plurality of metal pre-forms 600 in the double-sided cooling power package structure 60 of the sixth embodiment. The metal pre-form 600 is disposed between the second cooling substrate 102 and the semiconductor wafers 104, and the metal pre-form 600 is preferably formed corresponding to the center of each semiconductor wafer 104. The metal preform 600 is in direct contact with the lower metal layer 102b of the second cooling substrate 102, for example, by laser welding or UC bonding (also referred to as ultrasonic welding) such as ultrasonic thermocompression bonding (thermal ultrasonic compression). Further, the first portion 106a of the first conductive strip 106 is disposed between the metal pre-form 600 and the semiconductor wafer 104, and the first portion 106a may be bonded to the metal pre-form 600 by solder 602. In an embodiment, the thickness of the metal pre-form 600 is less than or equal to the difference in height between the second portion 106b and the first portion 106 a. Since the metal preform 600 is made of, for example, copper having excellent thermal conductivity, heat generated by the semiconductor wafer 104 can be efficiently transferred to the second cooling substrate 102 through the metal preform 600.
Fig. 7 is a schematic side view of a double-sided cooling power package structure according to a seventh embodiment of the present invention, wherein the same reference numerals as in the first embodiment are used to designate the same or similar components. The contents of the same or similar components can also refer to the related description of the first embodiment, and are not repeated.
Referring to fig. 7, the dual-side cooling power package structure 70 of the seventh embodiment also includes a first cooling substrate 100, a second cooling substrate 102, at least one semiconductor chip 104, and a plurality of first conductive strips 106. However, the second portion 106b of the first conductive strap 106 is bonded to the semiconductor wafer 104 by solder 700, although the invention is not limited thereto. In another embodiment, the semiconductor wafer 104 may be bonded to the second portion 106b by Ultrasonic Compression (UC) bonding. The first portion 106a of the first conductive strip 106 is in direct contact with the second cooled substrate 102. Since the materials of the first conductive tape 106 and the lower metal layer 102b may be the same, the joining method of the first portion 106a and the second cooling substrate 102 includes UC joining, laser welding, or the like. However, the present invention is not limited thereto; in another embodiment, the first portion 106a may be bonded to the second cooling substrate 102 by other solders (not shown).
Fig. 8 is a side view schematic diagram of a double-sided cooling power package structure according to an eighth embodiment of the present invention, wherein the same reference numerals as in the seventh embodiment are used to designate the same or similar components. The contents of the same or similar components can also refer to the related description of the seventh embodiment, and are not repeated.
Referring to fig. 8, the difference between the eighth embodiment and the seventh embodiment is that the double-sided cooling power package structure 80 of the eighth embodiment further includes a second conductive strap 800. A second conductive strip 800 is disposed between the first cooled substrate 100 and the second cooled substrate 102, wherein the second conductive strip 800 has the same shape as the first conductive strip 106, but may differ slightly in size. For example, the second conductive strip 800 includes a first portion 800a, a second portion 800b, and a bendable portion 800c connecting the first portion 800a and the second portion 800 b. The first portions 106a and 800a may be bonded to the second cooling substrate 102 by solder 802. The second conductive strip 800 does not contact the semiconductor wafer 104 and therefore may provide an additional path for current and heat depending on the design of the circuit or topology. In this embodiment, the second conductive strip 800 is discontinuous from the first conductive strip 106, wherein the second portions 800b and 106b are separated. Alternatively, the second conductive strip 800 is a continuous structure with the first conductive strip 106, or a combination of a continuous structure and a discontinuous structure.
Fig. 9 is a side view schematic diagram of a double-sided cooling power package structure according to a ninth embodiment of the present invention, wherein the same reference numerals as in the seventh embodiment are used to designate the same or similar components. The contents of the same or similar components can also refer to the related description of the seventh embodiment, and are not repeated.
Referring to fig. 9, the ninth and seventh embodiments are different in that a plurality of metal pre-forms 900 are further provided in the double-sided cooling power package structure 90 of the ninth embodiment. The metal pre-form 900 is arranged between the second cooling substrate 102 and the semiconductor wafer 104, wherein the metal pre-form 900 is in direct contact with the lower metal layer 102b of the second cooling substrate 102. The metal preform 9 may be formed by UC joining or laser welding or the like. Further, the second portion 106b of the first conductive strip 106 is disposed between the metal pre-form 900 and the semiconductor wafer 104, and the second portion 106b may be bonded to the metal pre-form 900 by solder 902. Since the metal preform 900 is made of, for example, copper having excellent thermal conductivity, heat generated by the semiconductor chip 104 can be efficiently transferred to the second cooling substrate 102 through the metal preform 900, thereby facilitating heat dissipation of the double-sided cooling power package structure 90.
In summary, the double-sided cooling power package structure according to the present invention can absorb the thermal compression and stress generated by thermal stress between different materials through the specific conductive tape. Specifically, the bendable portions of the conductive tape are elastically deformed during the thermal compression process, thereby improving the robustness of the package and the semiconductor wafer. In addition, the present invention also has advantages in terms of process cost (only one or two reflow soldering steps are needed) and desirable heat dissipation through conductive tape.
It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (16)

1. A dual-sided cooling power package structure comprising:
a first cooling substrate;
a second cooling substrate disposed opposite to the first cooling substrate;
at least one semiconductor wafer bonded to one of the first cooling substrate and the second cooling substrate; and
a plurality of first conductive strips disposed between the first cooling substrate and the second cooling substrate, wherein each of the first conductive strips includes a first portion, a second portion, and a bendable portion connecting the first portion and the second portion, the bendable portion forming a closed loop at an edge of the first portion, one of the first portion and the second portion being in direct contact with the semiconductor wafer, and the other of the first portion and the second portion extending away from the semiconductor wafer.
2. The dual sided cooling power package structure of claim 1, wherein the first conductive strip is a discontinuous structure.
3. The dual sided cooling power package structure of claim 1, wherein the first conductive strap is a continuous structure.
4. The dual sided cooled power package structure of claim 1, wherein the first portion is in direct contact with the semiconductor die.
5. The dual sided cooling power package structure of claim 1, wherein the first portion is bonded to the semiconductor die via a first solder.
6. The dual sided cooling power package structure of claim 1, wherein the semiconductor die is bonded on the first cooling substrate and the second portion of each of the first conductive strips is in direct contact with the second cooling substrate.
7. The dual sided cooling power package structure of claim 1, wherein the semiconductor die is bonded on the first cooling substrate and the second portion of each of the first conductive strips is bonded to the second cooling substrate via a second solder.
8. The dual sided cooled power package structure of claim 1, wherein the second portion is in direct contact with the semiconductor die.
9. The dual sided cooling power package structure of claim 1, wherein the second portion is bonded to the semiconductor die via a first solder.
10. The dual sided cooled power package structure of claim 1, wherein the semiconductor die is bonded on the first cooling substrate and the first portion of each of the first conductive strips is in direct contact with the second cooling substrate.
11. The dual sided cooling power package structure of claim 1, wherein the semiconductor die is bonded on the first cooling substrate and the second portion of each of the first conductive strips is bonded to the second cooling substrate via a second solder.
12. The dual sided cooling power package structure of claim 1, further comprising a plurality of metal pre-forms disposed between the second cooling substrate and the semiconductor die, wherein the metal pre-forms are in direct contact with the second cooling substrate and the one of the first portion and the second portion is disposed between the metal pre-forms and the semiconductor die.
13. The dual sided cooling power package structure of claim 1, further comprising at least a second conductive strip disposed between the first cooling substrate and the second cooling substrate, wherein the second conductive strip has the same shape as each of the first conductive strips and does not contact the semiconductor die.
14. The dual sided cooling power package structure of claim 13, wherein the second conductive strip is a discontinuous structure with the first conductive strip.
15. The dual sided cooling power package structure of claim 13, wherein the second conductive strip is a continuous structure with the first conductive strip.
16. The dual sided cooled power package structure of claim 13, wherein the first and second cooling substrates comprise direct copper clad ceramic substrates.
CN202180004154.6A 2020-08-12 2021-08-12 Double-sided cooling power packaging structure Pending CN114556550A (en)

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US8358000B2 (en) * 2009-03-13 2013-01-22 General Electric Company Double side cooled power module with power overlay
US20110260314A1 (en) * 2010-04-27 2011-10-27 Stmicroelectronics S.R.L. Die package and corresponding method for realizing a double side cooling of a die package
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DE102017213170A1 (en) * 2017-07-31 2019-01-31 Infineon Technologies Ag SOLDERING A LADDER TO ALUMINUM METALLIZATION
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US10770369B2 (en) * 2018-08-24 2020-09-08 Advanced Semiconductor Engineering, Inc. Semiconductor device package
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