WO2022012203A1 - 反熔丝存储单元状态检测电路及存储器 - Google Patents

反熔丝存储单元状态检测电路及存储器 Download PDF

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Publication number
WO2022012203A1
WO2022012203A1 PCT/CN2021/097918 CN2021097918W WO2022012203A1 WO 2022012203 A1 WO2022012203 A1 WO 2022012203A1 CN 2021097918 W CN2021097918 W CN 2021097918W WO 2022012203 A1 WO2022012203 A1 WO 2022012203A1
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WIPO (PCT)
Prior art keywords
memory cell
node
fuse memory
time point
current
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PCT/CN2021/097918
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English (en)
French (fr)
Inventor
季汝敏
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to US17/400,517 priority Critical patent/US11817163B2/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G11C17/165—Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5004—Voltage

Definitions

  • the present disclosure relates to the technical field of integrated circuits, exemplarily, to an anti-fuse memory cell state detection circuit and a memory using the circuit.
  • One-time programmable memory is widely used in various types of memory to realize redundant replacement of damaged memory cells and fine-tuning of circuit modules.
  • the commonly used one-time programmable memory utilizes the breakdown or non-breakdown state of antifuse memory cells for information storage.
  • the breakdown state of the anti-fuse memory cell is usually detected only by a simple logic gate circuit (such as an inverter, etc.).
  • a simple logic gate circuit such as an inverter, etc.
  • an inverter is used to detect the breakdown state of the anti-fuse memory cell, as shown in FIG. 1 .
  • the path resistance will be relatively small, then during the detection, the voltage generated on the Node1 node is low, so that the output D_out of the inverter is high; otherwise, If the anti-fuse memory cell 11 to be tested is in a state that has not been programmed to break down, the path resistance will be large, and the voltage generated on the Node1 node will be high, exceeding the inversion point of the inverter, so that the output D_out of the inverter is low. .
  • the resistance of the anti-fuse memory cell after being broken down will fluctuate in a wide range, and the influence of process, voltage, temperature and other factors on the inversion point of logic gate circuits such as inverters, it is easy to cause the anti-fuse memory cell to fail.
  • the storage state detection is wrong, resulting in a decrease in chip yield, so an anti-fuse memory cell state detection circuit with better performance is urgently needed.
  • the purpose of the present disclosure is to provide an anti-fuse memory cell state detection circuit and a memory using the same, which are used to at least to a certain extent overcome the storage state detection of anti-fuse memory cells due to the limitations and defects of the related art Inaccurate results.
  • an anti-fuse memory cell state detection circuit comprising: a first current module, a first end connected to an anti-fuse memory cell array through a first node, a second end connected to a second node,
  • the anti-fuse memory cell array includes at least one bit line, each of which is connected to the first node and a plurality of anti-fuse memory cells, and the first current module is used for outputting through the second node detection current, the detection current is related to the resistance value of the anti-fuse memory cell to be tested in the anti-fuse memory cell array;
  • the second current module the first end is connected to the first end of the reference resistor through the third node, and the second current module
  • the two ends are connected to the fourth node, the second end of the reference resistor is grounded, the second current module is configured to output a reference current through the fourth node, and the reference current is related to the resistance value of the reference resistor; compare The first input terminal is connected to the second node, and the second
  • the first current module includes: a first amplifier, a first input terminal is connected to a reference voltage, a second input terminal is connected to the first node, and an output terminal is connected to a fifth node;
  • the first switch element the first end is connected to the power supply voltage, the second end is connected to the first node, and the control end is connected to the fifth node;
  • the second switch element the first end is connected to the power supply voltage, and the second end is connected to the the second node, the control end is connected to the fifth node;
  • the third switch element the first end is connected to the second node, the second end is grounded, and the control end is connected to the controller.
  • the second current module includes: a second amplifier, a first input terminal is connected to the reference voltage, a second input terminal is connected to the third node, and an output terminal is connected to the sixth node; a fourth switching element, the first terminal is connected to the power supply voltage, the second terminal is connected to the third node, and the control terminal is connected to the sixth node; the fifth switching element, the first terminal is connected to the power supply voltage, and the first terminal is connected to the power supply voltage.
  • Two terminals are connected to the fourth node, and the control terminal is connected to the sixth node; the sixth switching element, the first terminal is connected to the fourth node, the second terminal is grounded, and the control terminal is connected to the controller.
  • it further includes: a first energy storage module, a first end connected to the second node, and a second end connected to ground; a second energy storage module, a first end connected to the fourth energy storage module node, the second terminal is grounded.
  • it further includes a flip-flop, the input terminal of which is connected to the output terminal of the comparator.
  • a controller which connects the word lines of the plurality of anti-fuse memory cells and the comparator, and is configured to: pass the anti-fuse to be tested at a first time point
  • the word line of the filament memory cell outputs a first control signal to electrically connect the anti-fuse memory cell to be tested to the bit line, and outputs a second control signal to control the first current module to input all the signals to the first input terminal of the comparator.
  • the detection current and the second current module input the reference current to the second input end of the comparator; obtain the output signal of the comparator at a second time point to determine the anti-fuse storage unit to be tested The storage state of ; wherein, the second time point is after the first time point.
  • the second time point is determined according to the following manner: acquiring the first voltage change line and all the first voltage change lines of the second node when the anti-fuse memory cell is in a breakdown state the second voltage change line of the fourth node; the time point when the difference between the first voltage change line and the second voltage change line reaches a preset threshold is taken as the second time point.
  • the second time point is determined according to the following manner: acquiring a third voltage change line of the second node when the anti-fuse memory cell is in a non-breakdown state and The second voltage change line of the fourth node; the time point when the difference between the third voltage change line and the second voltage change line reaches a preset threshold is taken as the second time point.
  • the reference resistor is a ZQ calibration resistor.
  • the anti-fuse memory cell array includes: a plurality of anti-fuse memory cell sub-arrays, each of the anti-fuse memory cell sub-arrays corresponds to a bit line, each The anti-fuse memory cell sub-array includes a plurality of anti-fuse memory cells; a plurality of seventh switch elements corresponding to the anti-fuse memory cell sub-array, and the first end of each of the seventh switch elements is connected to In the corresponding bit line of the anti-fuse memory cell sub-array, the second end of each of the seventh switching elements is connected to the first node, and the default state of the seventh switching element is an off state.
  • a control terminal of each of the seventh switching elements is connected to a controller, and the controller is configured to: at a third time point, the anti-fuse storage unit to be tested is located in the anti-fuse storage unit.
  • the seventh switch element corresponding to the fuse memory cell sub-array outputs a third control signal to control the seventh switch element to be turned on; at a first time point, a first control signal is output to the word line of the anti-fuse memory cell to be tested signal to electrically connect the anti-fuse memory cell to be tested to the bit line, output a second control signal to control the first current module to input the detection current and the second current module to the first input terminal of the comparator inputting the reference current to the second input terminal of the comparator; acquiring the output signal of the comparator at a second time point to determine the storage state of the anti-fuse storage unit to be tested; wherein the third The time point is before the second time point.
  • a method for detecting the state of an anti-fuse memory cell which is applied to the anti-fuse memory cell state detection circuit described in any of the above, including: an anti-fuse to be tested at a first time point
  • the word line of the memory cell outputs a first control signal to electrically connect the anti-fuse memory cell to be tested to the bit line, and outputs a second control signal to control the first current module to input the first input terminal of the comparator with the Detecting current, the second current module inputs the reference current to the second input end of the comparator; acquires the output signal of the comparator at a second time point to determine the A breakdown state; wherein the second time point is after the first time point.
  • the anti-fuse memory cell array includes: a plurality of anti-fuse memory cell sub-arrays, each of the anti-fuse memory cell sub-arrays corresponds to a bit line, each The anti-fuse memory cell sub-array includes a plurality of anti-fuse memory cells; a plurality of seventh switch elements corresponding to the anti-fuse memory cell sub-array, and the first end of each of the seventh switch elements is connected to The bit line of the corresponding anti-fuse memory cell sub-array, the second end of each seventh switch element is connected to the first node, the control end of each seventh switch element is connected to the controller, so The default state of the seventh switch element is an off state; the method further includes: at a third time point, the seventh switch element corresponding to the anti-fuse memory cell sub-array where the anti-fuse memory cell to be tested is located outputs a third control signal to control the seventh switching element to be turned on, and the third time point is before the second time point
  • a memory including the anti-fuse memory cell state detection circuit according to any one of the above.
  • the embodiment of the present disclosure reflects the resistance of the anti-fuse memory cell to be tested and the reference resistance on the voltage of the second node and the voltage of the fourth node by using two current modules, and uses a comparator to compare the voltage of the second node and the fourth node.
  • the voltage of the node is used to judge the resistance of the anti-fuse memory cell to be tested, and then to judge the storage state of the anti-fuse memory cell to be tested, so that the flip point can be accurately controlled, and a more accurate detection result can be obtained.
  • the resistance fluctuation of the breakdown state and the shift of the switching point of the logic gate lead to misjudgment of the storage state of the anti-fuse memory cell.
  • FIG. 1 is a schematic diagram of an anti-fuse memory cell state detection circuit in the related art.
  • FIG. 2 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in an exemplary embodiment of the present disclosure.
  • FIG. 3 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in an embodiment of the present disclosure.
  • FIG. 4 is a schematic diagram of an equivalent circuit of the circuit shown in FIG. 3 .
  • FIG. 5 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in another embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a detection method applied to the controller of the circuit shown in FIG. 5 .
  • FIG. 7 is a schematic diagram of a manner in which the second time point is determined according to an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a manner in which the second time point is determined according to another embodiment of the present disclosure.
  • FIG. 9 is a schematic diagram of the voltage change line of the second node and the voltage change line of the fourth node in the non-breakdown state of the anti-fuse memory cell.
  • FIG. 10 is a schematic diagram of the voltage change line of the second node and the voltage change line of the fourth node in the breakdown state of the anti-fuse memory cell.
  • FIG. 11 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in yet another embodiment of the present disclosure.
  • FIG. 12 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • FIG. 13 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • FIG. 14 is a flowchart of a detection method of the controller of the circuit shown in FIG. 13 .
  • Example embodiments will now be described more fully below with reference to the accompanying drawings.
  • Example embodiments can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art.
  • the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.
  • numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure.
  • those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed.
  • well-known solutions have not been shown or described in detail to avoid obscuring aspects of the present disclosure.
  • FIG. 2 is a schematic structural diagram of an anti-fuse memory cell state detection circuit in an exemplary embodiment of the present disclosure.
  • the anti-fuse memory cell state detection circuit 200 may include:
  • the first end is connected to the first end of the reference resistor Rref through the third node N3, the second end is connected to the fourth node N4, the second end of the reference resistor Rref is grounded, and the second current module 23 is used for passing through the first end of the reference resistor Rref.
  • the four-node N4 outputs a reference current, and the reference current is related to the resistance value of the reference resistor Rref;
  • the comparator 24 has a first input terminal connected to the second node N2, and a second input terminal connected to the fourth node N4, for detecting the storage state of the anti-fuse memory cell to be tested.
  • FIG. 1 Please refer to FIG. 1 for the structure of the anti-fuse memory cell array 22 and the anti-fuse memory cells shown in FIG. 2 .
  • FIG. 3 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in an embodiment of the present disclosure.
  • the first current module 21 may include:
  • the first amplifier OP1 the first input terminal is connected to the reference voltage Vref, the second input terminal is connected to the first node N1, and the output terminal is connected to the fifth node N5;
  • the first switching element M1 the first terminal is connected to the power supply voltage VDD, the second terminal is connected to the first node N1, and the control terminal is connected to the fifth node N5;
  • the second switching element M2 the first terminal is connected to the power supply voltage VDD, the second terminal is connected to the second node N2, and the control terminal is connected to the fifth node N5;
  • the third switching element M3 has a first end connected to the second node N2, a second end connected to ground, and a control end connected to a controller (not shown).
  • the second current module 23 may include:
  • the second amplifier OP2 the first input terminal is connected to the reference voltage Vref, the second input terminal is connected to the third node N3, and the output terminal is connected to the sixth node N6;
  • the fourth switching element M4 the first end is connected to the power supply voltage VDD, the second end is connected to the third node N3, and the control end is connected to the sixth node N6;
  • the fifth switching element M5 the first end is connected to the power supply voltage VDD, the second end is connected to the fourth node N4, and the control end is connected to the sixth node N6;
  • the sixth switching element M6 has a first end connected to the fourth node N4, a second end connected to ground, and a control end connected to a controller (not shown).
  • the first switching element M1 and the second switching element M2 are both N-type transistors, the first input terminal of the first amplifier OP1 is a non-inverting input terminal, and the second input terminal is an inverting input terminal. . If both the first switching element M1 and the second switching element M2 are P-type transistors, the first input terminal of the first amplifier OP2 is an inverting input terminal, and the second input terminal is a non-inverting input terminal. Similarly, if the fourth switching element M4 and the fifth switching element M5 are both N-type transistors, the first input terminal of the second amplifier OP2 is a non-inverting input terminal, and the second input terminal is an inverting input terminal.
  • the first input terminal of the second amplifier OP2 is an inverting input terminal
  • the second input terminal is a non-inverting input terminal.
  • the connection is as shown in FIG. 3 .
  • Those skilled in the art can determine the connection mode of the amplifier by themselves according to the type of the switching element, and the present disclosure is not limited thereto.
  • FIG. 4 is a schematic diagram of an equivalent circuit of the embodiment shown in FIG. 3 .
  • the first amplifier OP1 , the first switching element M1 and the second switching element M2 are used in the first current module 21 to convert the resistance of the anti-fuse memory cell to be tested into a current source
  • To charge the second node N2 set the third switching element M3 at the second node N2 to control the start time of the current source to charge the second node N2 or to clear the voltage of the second node N2; in the second current module 23, use
  • the second amplifier OP2, the fourth switching element M4 and the fifth switching element M5 convert the reference resistance into a current source to charge the fourth node N4, and the sixth switching element M6 is set at the fourth node N4 to control the current source to charge the fourth node N4 Start time or clear the voltage of the fourth node N4 to realize the judgment of the resistance of the anti-fuse memory cell to be tested (ie the storage state) by detecting and comparing the potentials of the second node N2 and the fourth node N4.
  • the parasitic capacitance C1 existing at the second node N2 may be used to detect the voltage of the second node N2
  • the parasitic capacitance C2 existing at the fourth node N4 may be used to detect the voltage of the fourth node N4.
  • the parasitic capacitances C1 and C2 are comprehensive parasitic capacitances, including the parasitic capacitances at the input terminals of the comparator 24 .
  • FIG. 5 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in another embodiment of the present disclosure.
  • the anti-fuse memory cell array 22 , the comparator 24 , the third switching element M3 , and the sixth switching element M6 are all connected to the controller CON.
  • the controller CON is connected to the word line of each anti-fuse memory cell in the anti-fuse memory cell array 22, connected to the output end of the comparator 24, and connected to the control of the third switching element M3 and the sixth switching element M6. end.
  • FIG. 6 is a flowchart of a detection method implemented by the controller CON in the embodiment shown in FIG. 5 .
  • the controller CON may be configured to perform a detection method 600, which may include:
  • Step S1 at a first time point, output a first control signal through the word line of the anti-fuse memory cell to be tested to electrically connect the anti-fuse memory cell to be tested to the bit line, and output a second control signal to control the first current module pair
  • the first input terminal of the comparator inputs the detection current, and the second current module inputs the reference current to the second input terminal of the comparator;
  • step S2 the output signal of the comparator is acquired at a second time point to determine the storage state of the anti-fuse memory cell to be tested; wherein, the second time point is after the first time point.
  • the resistance of the path where the first node N1 is located will change according to the breakdown state of the anti-fuse memory cell.
  • the voltage of the first node N1 will maintain the same voltage value as the reference voltage Vref connected to the amplifier OP1, so that a first current is generated in the path where the first node N1 is located, and the first current is opposite to the voltage to be measured.
  • the resistance of a fuse memory cell is negatively correlated.
  • a second current is generated in the path where the second node N2 is located.
  • the second current is in a constant proportional relationship with the first current, and the ratio is determined by the first switching element M1. It is determined by the size and performance of the second switching element M2. That is, the second current is also negatively correlated with the resistance of the anti-fuse memory unit to be tested. The larger the resistance of the anti-fuse memory unit to be tested is, the smaller the second current is; Second, the larger the current.
  • the second current charges the second node N2, the larger the second current, the faster the charging speed of the second node N2, the faster the voltage change speed of the second node N2; the smaller the second current, the faster the charging speed of the second node N2 The slower it is, the slower the voltage of the second node N2 changes. It can be seen from the above analysis that the larger the resistance of the anti-fuse memory cell to be tested is, the smaller the second current is, and the slower the voltage change speed of the second node N2; the smaller the resistance of the anti-fuse memory cell to be tested, the lower the second current. larger, the faster the voltage of the second node N2 changes.
  • the larger the reference resistance the slower the voltage change speed of the fourth node N4; the smaller the reference resistance, the faster the voltage change speed of the fourth node N4.
  • the comparator 24 is used to compare the voltage of the second node N2 with the fourth node at the second time point By comparing the node N4, the comparison result between the resistance of the anti-fuse memory cell to be tested and the reference resistance can be judged, and then the storage state of the anti-fuse memory cell to be tested can be judged.
  • comparator 24 may be a differential amplifier.
  • the method of acquiring the output signal of the comparator 24 can be either reading the output signal of the comparator 24 at the second time point, or controlling the comparator 24 to change to enable at the second time point through the enable pin of the comparator 24 .
  • the comparison result between the voltage of the second node N2 and the voltage of the fourth node N4 is output.
  • the selection of the second time point is an important means to achieve accurate detection.
  • FIG. 7 is a schematic diagram of a manner in which the second time point is determined according to an embodiment of the present disclosure.
  • the second time point may be determined according to the following manner:
  • Step S71 acquiring the first voltage change line of the second node in the breakdown state of the anti-fuse memory cell and the second voltage change line of the fourth node;
  • Step S72 taking the time point when the difference between the first voltage change line and the second voltage change line reaches the preset threshold as the second time point.
  • FIG. 8 is a schematic diagram of a manner of determining a second time point according to another embodiment of the present disclosure.
  • the second time point may be determined according to the following manner:
  • Step S81 acquiring the third voltage change line of the second node in the non-breakdown state of the anti-fuse memory cell and the second voltage change line of the fourth node;
  • Step S82 taking the time point when the difference between the third voltage change line and the second voltage change line reaches the preset threshold as the second time point.
  • the above-mentioned preset threshold is greater than the differential input voltage threshold of the comparator.
  • FIGS. 7 and 8 will be described below with reference to FIGS. 9 and 10 .
  • 9 and 10 are schematic diagrams of a first voltage change line, a second voltage change line, and a third voltage change line.
  • R1 and R2 are derived from statistical data, which are obtained by statistical analysis of R1 and R2 in the process of R&D and production of anti-fuse memory cells.
  • the voltage V1(t) of the second node N2 increases from 0 to the first voltage of VDD as a function of time t from the first time point T1
  • the line of change is:
  • V1(t) I 1 (t)*t/C1 (1)
  • I 1 (t) is the current of the second node N2 when the path resistance includes R1.
  • the voltage V3(t) of the second node N2 increases from 0 to VDD with the change of time t from the first time point T1.
  • the third voltage change line is:
  • V3(t) I 3 (t)*t/C1 (2)
  • I 3 (t) is the current of the second node N2 when the path resistance includes R2.
  • the voltage V2(t) of the fourth node N4 rises from 0 to VDD from the first time point T1 as the time t changes.
  • the second voltage change line is:
  • V2(t) I 2 (t)*t/C2 (3)
  • I 2 (t) is the constant current at the fourth node N4.
  • the time when ⁇ V 1 (t) is equal to the preset threshold can be set as the second time point T2 (as shown in FIG. 9 ), or the time when ⁇ V 2 (t) is equal to the preset threshold can be set as the second time point T2 ( Figure 10).
  • the preset threshold may be determined according to the parameters of the comparator 24 , eg, greater than the differential input voltage threshold of the comparator 24 . The larger the preset threshold, the higher the detection accuracy; the smaller the preset threshold, the shorter the detection time.
  • the differential input voltage threshold referred to in the embodiments of the present invention refers to the minimum voltage difference between the non-inverting input terminal and the inverting input terminal that can be detected by the comparator, and the minimum voltage difference is related to the design parameters, process deviation, temperature, input of the comparator. Therefore, those skilled in the art can adjust the setting value of the preset threshold by themselves according to the actual situation, so as to realize the common optimal solution of detection accuracy and detection time.
  • the default states of the third switching element M3 and the sixth switching element M6 are both on states.
  • Both the third switching element M3 and the sixth switching element M6 may be, for example, N-type transistors.
  • the third switching element M3 and the sixth switching element M6 are controlled to be turned off by the controller, and the voltages of the second node N2 and the fourth node N4 start to rise.
  • the ZQ calibration resistor may be used as the reference resistor Rref.
  • FIG. 11 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in yet another embodiment of the present disclosure.
  • the detection circuit 200 may further include:
  • the first energy storage module 25 the first end is connected to the second node N2, and the second end is grounded;
  • the first end of the second energy storage module 26 is connected to the fourth node N4, and the second end is grounded.
  • the first energy storage module 25 and the second energy storage module 26 may be configured as a first detection capacitor C3 and a second detection capacitor C4 (as shown in FIG. 12 ).
  • the function of the first detection capacitor C3 is the same as that of the parasitic capacitor C1, both for detecting the voltage of the second node N2;
  • the function of the second detection capacitor C4 is the same as that of the parasitic capacitor C2, both for detecting the voltage of the fourth node N4.
  • C1 involved in formulas (1) to (5) can be replaced by C3, and C2 involved in formulas (1) to (5) can be replaced by C4.
  • the capacitance values of the first detection capacitor C3 and the second detection capacitor C4 may be set to be equal.
  • other energy storage solutions may also be used for the second node N2 and the fourth node N4, which are not particularly limited in the present disclosure.
  • FIG. 12 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • the detection circuit 200 may further include:
  • the flip-flop 27 has an input terminal connected to the output terminal of the comparator 24, and both the first output terminal and the second output terminal are connected to the controller CON.
  • the flip-flop 27 can be, for example, a D flip-flop, which is used to latch the output signal of the comparator 27 so as to facilitate reading by the controller CON.
  • Those skilled in the art can set the model of the trigger 24 by themselves, and the present disclosure is not limited thereto.
  • the settings of the first energy storage module 25 , the second energy storage module 26 or the trigger 27 do not affect the implementation of the control method shown in FIG. 6 and the selection logic of the second time point.
  • FIG. 13 is a schematic circuit diagram of an anti-fuse memory cell state detection circuit in still another embodiment of the present disclosure.
  • the first node N1 is connected to a plurality of bit lines, and the anti-fuse memory cell array 22 may include:
  • a plurality of anti-fuse memory cell sub-arrays 22m (m is a bit line serial number), each anti-fuse memory cell sub-array 22m corresponds to a bit line BLm, and each anti-fuse memory cell sub-array 22m includes a plurality of anti-fuses storage unit;
  • a plurality of seventh switching elements M7m corresponding to the anti-fuse memory cell sub-array 22m the first end of each seventh switching element M7m is connected to the corresponding bit line BLm of the anti-fuse memory cell sub-array 22m, and each seventh switching element M7m is connected to the bit line BLm of the corresponding anti-fuse memory cell sub-array 22m
  • the second end of the switching element M7m is connected to the third node N3, the control end of each seventh switching element M7m is connected to the controller CON, and the default state of the seventh switching element M7m is an off state.
  • the memory states of the anti-fuse memory cells in the plurality of anti-fuse memory cell sub-arrays 22m are detected.
  • the circuit area can be greatly saved.
  • the first node N1 can be connected to 16 bit lines at the same time, and the specific manner is shown in FIG. 13 .
  • FIG. 14 is a flowchart of a detection method corresponding to the circuit shown in FIG. 13 .
  • controller CON can be configured to perform the following methods:
  • Step S141 at a third time point, the seventh switch element corresponding to the anti-fuse memory cell sub-array where the anti-fuse memory cell to be tested is located outputs a third control signal to control the seventh switch element to be turned on;
  • Step S1 at a first time point, the word line of the anti-fuse memory cell to be tested outputs a first control signal to electrically connect the anti-fuse memory cell to be tested to the bit line, and outputs a second control signal to control the first current module to compare The first input terminal of the comparator inputs the detection current, and the second current module inputs the reference current to the second input terminal of the comparator;
  • Step S2 obtain the output signal of the comparator at the second time point to determine the storage state of the anti-fuse storage unit to be tested;
  • the first time point and the third time point are both before the second time point.
  • the method shown in FIG. 6 may further include step S141, and the order of step S141 and step S1 may be exchanged.
  • the third time point may be before the first time point, or after the first time point, and may also be equal to the first time point, as long as the third time point and the first time point are both Before the second time point, the charging path may be turned on before starting to detect the voltage of the second node N2 at the second time point.
  • the third control signal is at a low level; when the seventh switch element is an N-type transistor, the third control signal is at a high level.
  • the third control signal may also be other types of signals, which is not particularly limited in the present disclosure.
  • the anti-fuse memory cell state detection circuit and the anti-fuse memory cell state detection method provided by the embodiments of the present disclosure generate a current pair related to the resistance of the anti-fuse memory cell to be tested by using a first current module at a first time point
  • the second node N2 is charged, the second current module is used to generate a current related to the reference resistor to charge the fourth node N4, and the voltages of the second node N2 and the fourth node N4 are compared by a comparator at the second time point, which can accurately Controls the output toggle point of the comparator.
  • the probability of voltage misjudgment can be reduced as much as possible, the output of the comparator is more accurate, and the In the related art, the storage state of the anti-fuse memory cell is misjudged due to the resistance fluctuation of the anti-fuse memory cell and the switching voltage shift of the logic gate.
  • a memory including the anti-fuse memory cell state detection circuit shown in any one of the above embodiments.
  • the memory may be, for example, a DRAM memory.
  • modules or units of the apparatus for action performance are mentioned in the above detailed description, this division is not mandatory. Indeed, according to embodiments of the present disclosure, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided into multiple modules or units to be embodied.
  • the embodiment of the present disclosure reflects the resistance of the anti-fuse memory cell to be tested and the reference resistance on the voltage of the second node and the voltage of the fourth node by using two current modules, and uses a comparator to compare the voltage of the second node and the fourth node.
  • the voltage of the node is used to judge the resistance of the anti-fuse memory cell to be tested, and then to judge the storage state of the anti-fuse memory cell to be tested, so that the flip point can be accurately controlled and more accurate detection results can be obtained.
  • the resistance fluctuation of the breakdown state and the shift of the switching point of the logic gate lead to misjudgment of the storage state of the anti-fuse memory cell.

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)

Abstract

一种反熔丝存储单元状态检测电路及存储器，电路包括：第一电流模块（21），第一端通过第一节点（N1）连接反熔丝存储单元阵列（22），第二端连接第二节点（N2），第一电流模块（21）用于通过第二节点（N2）输出检测电流，检测电流与反熔丝存储单元阵列（22）中待测反熔丝存储单元的阻值相关；第二电流模块（23），第一端通过第三节点（N3）连接参考电阻（Rref）的第一端，第二端连接第四节点（N4），参考电阻（Rref）的第二端接地，第二电流模块（23）用于通过第四节点（N4）输出参考电流，参考电流与参考电阻（Rref）的阻值相关；比较器（24），第一输入端连接第二节点（N2），第二输入端连接第四节点（N4），用于检测待测反熔丝存储单元的存储状态，可以提高反熔丝存储单元存储状态检测的准确度。

Description

反熔丝存储单元状态检测电路及存储器
交叉引用
本公开要求于2020年07月16日提交的申请号为202010688530.5、名称为“反熔丝存储单元状态检测电路及存储器”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及集成电路技术领域，示例性而言，涉及一种反熔丝存储单元状态检测电路及应用该电路的存储器。
背景技术
一次性可编程存储(One time programmable，OTP)广泛应用于各类存储器中，用于实现损坏存储单元的冗余替换、电路模块的微调整等。常用的一次性可编程存储利用反熔丝存储单元的击穿或未击穿状态来进行信息存储。
通常仅通过简单的逻辑门电路(如反相器等)对反熔丝存储单元的击穿状态进行检测。在相关技术中，利用反相器来对反熔丝存储单元的击穿状态进行检测，如图1所示。如果待测反熔丝存储单元11属于被编程击穿的状态，通路电阻会比较小，那么在进行检测时，Node1节点上产生的电压较低，使得反相器的输出D_out为高；反之，如果待测反熔丝存储单元11属于未被编程击穿的状态，通路电阻会较大，Node1节点上产生的电压较高，超过反相器的翻转点，使得反相器的输出D_out为低。由于反熔丝存储单元被击穿后的电阻会在较宽范围内波动，以及工艺、电压、温度等因素对反相器等逻辑门电路的翻转点的影响，容易导致反熔丝存储单元的存储状态检测错误，造成芯片良率下降，因此亟需要一种性能更优的反熔丝存储单元状态检测电路。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于提供一种反熔丝存储单元状态检测电路及应用该电路的存储器，用于至少在一定程度上克服由于相关技术的限制和缺陷而导致的反熔丝存储单元的存储状态检测结果不准确的问题。
根据本公开的第一方面，提供一种反熔丝存储单元状态检测电路，包括：第一电流模块，第一端通过第一节点连接反熔丝存储单元阵列，第二端连接第二节点，所述反熔丝存储单元阵列包括至少一条位线，每条所述位线连接所述第一节点和多个反熔丝存储单元，所述第一电流模块用于通过所述第二节点输出检测电流，所述检测电流与所述反熔丝存储单元阵列中待测反熔丝存储单元的阻值相关；第二电流模块，第一端通过第三节点连接参 考电阻的第一端，第二端连接第四节点，所述参考电阻的第二端接地，所述第二电流模块用于通过所述第四节点输出参考电流，所述参考电流与所述参考电阻的阻值相关；比较器，第一输入端连接所述第二节点，第二输入端连接所述第四节点，用于检测待测反熔丝存储单元的存储状态。
在本公开的一种示例性实施例中，所述第一电流模块包括：第一放大器，第一输入端连接参考电压，第二输入端连接所述第一节点，输出端连接第五节点；第一开关元件，第一端连接电源电压，第二端连接所述第一节点，控制端连接所述第五节点；第二开关元件，第一端连接所述电源电压，第二端连接所述第二节点，控制端连接所述第五节点；第三开关元件，第一端连接所述第二节点，第二端接地，控制端连接控制器。
在本公开的一种示例性实施例中，所述第二电流模块包括：第二放大器，第一输入端连接所述参考电压，第二输入端连接所述第三节点，输出端连接第六节点；第四开关元件，第一端连接所述电源电压，第二端连接所述第三节点，控制端连接所述第六节点；第五开关元件，第一端连接所述电源电压，第二端连接所述第四节点，控制端连接所述第六节点；第六开关元件，第一端连接所述第四节点，第二端接地，控制端连接控制器。
在本公开的一种示例性实施例中，还包括：第一储能模块，第一端连接所述第二节点，第二端接地；第二储能模块，第一端连接所述第四节点，第二端接地。
在本公开的一种示例性实施例中，还包括：触发器，输入端连接所述比较器的输出端。
在本公开的一种示例性实施例中，还包括：控制器，连接所述多个反熔丝存储单元的字线和所述比较器，设置为：在第一时间点通过待测反熔丝存储单元的字线输出第一控制信号以使待测反熔丝存储单元电连接至位线，输出第二控制信号控制所述第一电流模块对所述比较器的第一输入端输入所述检测电流、所述第二电流模块对所述比较器的第二输入端输入所述参考电流；在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；其中，所述第二时间点在所述第一时间点之后。
在本公开的一种示例性实施例中，所述第二时间点根据以下方式确定：获取所述第二节点在所述反熔丝存储单元为击穿状态下的第一电压变化线和所述第四节点的第二电压变化线；将所述第一电压变化线与所述第二电压变化线的差值达到预设阈值的时间点作为所述第二时间点。
在本公开的一种示例性实施例中，所述第二时间点根据以下方式确定：获取所述第二节点在所述反熔丝存储单元为未击穿状态下的第三电压变化线和所述第四节点的第二电压变化线；将所述第三电压变化线与所述第二电压变化线的差值达到预设阈值的时间点作为所述第二时间点。
在本公开的一种示例性实施例中，所述参考电阻为ZQ校准电阻。
在本公开的一种示例性实施例中，所述反熔丝存储单元阵列包括：多个反熔丝存储单元子阵列，每个所述反熔丝存储单元子阵列对应一条位线，每个所述反熔丝存储单元子阵列包括多个反熔丝存储单元；与所述反熔丝存储单元子阵列对应的多个第七开关元件，每 个所述第七开关元件的第一端连接对应的反熔丝存储单元子阵列的位线，每个所述第七开关元件的第二端连接所述第一节点，所述第七开关元件的默认状态为关断状态。
在本公开的一种示例性实施例中，每个所述第七开关元件的控制端均连接控制器，所述控制器设置为：在第三时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第七开关元件输出第三控制信号以控制所述第七开关元件导通；在第一时间点对所述待测反熔丝存储单元的字线输出第一控制信号以使待测反熔丝存储单元电连接至位线，输出第二控制信号控制所述第一电流模块对所述比较器的第一输入端输入所述检测电流、所述第二电流模块对所述比较器的第二输入端输入所述参考电流；在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；其中，所述第三时间点在所述第二时间点之前。
根据本公开的一个方面，提供一种反熔丝存储单元状态检测方法，应用于如上述任意一项所述的反熔丝存储单元状态检测电路，包括：在第一时间点对待测反熔丝存储单元的字线输出第一控制信号以使待测反熔丝存储单元电连接至位线，输出第二控制信号控制所述第一电流模块对所述比较器的第一输入端输入所述检测电流、所述第二电流模块对所述比较器的第二输入端输入所述参考电流；在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的击穿状态；其中，所述第二时间点在所述第一时间点之后。
在本公开的一种示例性实施例中，所述反熔丝存储单元阵列包括：多个反熔丝存储单元子阵列，每个所述反熔丝存储单元子阵列对应一条位线，每个所述反熔丝存储单元子阵列包括多个反熔丝存储单元；与所述反熔丝存储单元子阵列对应的多个第七开关元件，每个所述第七开关元件的第一端连接对应的反熔丝存储单元子阵列的位线，每个所述第七开关元件的第二端连接所述第一节点，每个所述第七开关元件的控制端连接所述控制器，所述第七开关元件的默认状态为关断状态；所述方法还包括：在第三时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第七开关元件输出第三控制信号以控制所述第七开关元件导通，所述第三时间点在所述第二时间点之前。
根据本公开的一个方面，提供一种存储器，包括如上述任意一项所述的反熔丝存储单元状态检测电路。
本公开实施例通过使用两个电流模块将待测反熔丝存储单元的电阻与参考电阻反映在第二节点的电压和第四节点的电压上，使用比较器比较第二节点的电压和第四节点的电压以判断待测反熔丝存储单元的电阻，进而判断待测反熔丝存储单元的存储状态，可以使得翻转点得到精确控制、获得更准确的检测结果，避免由于反熔丝存储单元的击穿状态电阻波动和逻辑门的翻转点偏移导致对反熔丝存储单元的存储状态误判。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是相关技术中反熔丝存储单元状态检测电路的示意图。
图2是本公开示例性实施例中反熔丝存储单元状态检测电路的结构示意图。
图3是本公开一个实施例中反熔丝存储单元状态检测电路的一种电路示意图。
图4是图3所示电路的等效电路示意图。
图5是本公开另一个实施例中反熔丝存储单元状态检测电路的一种电路示意图。
图6是应用于图5所示电路的控制器的检测方法的流程图。
图7是本公开实施例确定第二时间点的方式的示意图。
图8是本公开另一个实施例确定第二时间点的方式的示意图。
图9是反熔丝存储单元未击穿状态下的第二节点的电压变化线和第四节点的电压变化线的示意图。
图10是反熔丝存储单元击穿状态下的第二节点的电压变化线和第四节点的电压变化线的示意图。
图11是本公开又一个实施例中反熔丝存储单元状态检测电路的电路示意图。
图12是本公开再一个实施例中反熔丝存储单元状态检测电路的电路示意图。
图13是本公开再一个实施例中反熔丝存储单元状态检测电路的结构示意图。
图14是图13所示电路的控制器的检测方法的流程图。
具体实施方式
以下现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施方式使得本公开将更加全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中，提供许多具体细节从而给出对本公开的实施方式的充分理解。然而，本领域技术人员将意识到，可以实践本公开的技术方案而省略所述特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知技术方案以避免喧宾夺主而使得本公开的各方面变得模糊。
此外，附图仅为本公开的示意性图解，图中相同的附图标记表示相同或类似的部分，因而将省略对它们的重复描述。附图中所示的一些方框图是功能实体，不一定必须与物理或逻辑上独立的实体相对应。可以采用软件形式来实现这些功能实体，或在一个或多个硬件模块或集成电路中实现这些功能实体，或在不同网络和/或处理器装置和/或微控制器装置中实现这些功能实体。
下面结合附图对本公开示例实施方式进行详细说明。
图2是本公开示例性实施例中反熔丝存储单元状态检测电路的结构示意图。
参考图2，反熔丝存储单元状态检测电路200可以包括：
第一电流模块21，第一端通过第一节点N1连接反熔丝存储单元阵列22，第二端连接第二节点N2，反熔丝存储单元阵列22包括至少一条位线，每条位线连接第一节点N1和多个反熔丝存储单元，第一电流模块21用于通过第二节点N2输出检测电流，检测电流与反熔丝存储单元阵列22中待测反熔丝存储单元的阻值相关；
第二电流模块23，第一端通过第三节点N3连接参考电阻Rref的第一端，第二端连接第四节点N4，参考电阻Rref的第二端接地，第二电流模块23用于通过第四节点N4输出参考电流，参考电流与参考电阻Rref的阻值相关；
比较器24，第一输入端连接第二节点N2，第二输入端连接第四节点N4，用于检测待测反熔丝存储单元的存储状态。
图2所示的反熔丝存储单元阵列22和反熔丝存储单元的结构请参见图1。
图3是本公开一个实施例中反熔丝存储单元状态检测电路的一种电路示意图。
参考图3，在一个实施例中，第一电流模块21可以包括：
第一放大器OP1，第一输入端连接参考电压Vref，第二输入端连接第一节点N1，输出端连接第五节点N5；
第一开关元件M1，第一端连接电源电压VDD，第二端连接第一节点N1，控制端连接第五节点N5；
第二开关元件M2，第一端连接电源电压VDD，第二端连接第二节点N2，控制端连接第五节点N5；
第三开关元件M3，第一端连接第二节点N2，第二端接地，控制端连接控制器(未示出)。
第二电流模块23可以包括：
第二放大器OP2，第一输入端连接参考电压Vref，第二输入端连接第三节点N3，输出端连接第六节点N6；
第四开关元件M4，第一端连接电源电压VDD，第二端连接第三节点N3，控制端连接第六节点N6；
第五开关元件M5，第一端连接电源电压VDD，第二端连接第四节点N4，控制端连接第六节点N6；
第六开关元件M6，第一端连接第四节点N4，第二端接地，控制端连接控制器(未示出)。
在图3所示实施例中，如果第一开关元件M1、第二开关元件M2均为N型晶体管，第一放大器OP1的第一输入端为同相输入端，第二输入端为反相输入端。如果第一开关元件M1、第二开关元件M2均为P型晶体管，第一放大器OP2的第一输入端为反相输入 端，第二输入端为同相输入端。同理，如果第四开关元件M4、第五开关元件M5均为N型晶体管，第二放大器OP2的第一输入端为同相输入端，第二输入端为反相输入端。如果第四开关元件M4、第五开关元件M5均为P型晶体管，第二放大器OP2的第一输入端为反相输入端，第二输入端为同相输入端。例如，第一开关元件M1、第二开关元件M2、第四开关元件M4、第五开关元件M5均为P型晶体管时，连接方式如图3所示。本领域技术人员可以根据开关元件的种类自行确定放大器的连接方式，本公开不以此为限。
图4是图3所示实施例的等效电路示意图。
参考图4，在本公开实施例中，在第一电流模块21中使用第一放大器OP1、第一开关元件M1和第二开关元件M2，将待测反熔丝存储单元的电阻转换成电流源对第二节点N2充电，在第二节点N2设置第三开关元件M3控制电流源对第二节点N2充电的开始时间或对第二节点N2电压进行清零；在第二电流模块23中，使用第二放大器OP2、第四开关元件M4和第五开关元件M5将参考电阻转换成电流源对第四节点N4充电，在第四节点N4设置第六开关元件M6控制电流源对第四节点N4充电的开始时间或对第四节点N4电压进行清零，以通过对第二节点N2和第四节点N4的电位的检测和比较实现对待测反熔丝存储单元的电阻(即存储状态)的判断。
在一个实施例中，可以利用第二节点N2存在的寄生电容C1来检测第二节点N2的电压、利用第四节点N4存在的寄生电容C2来检测第四节点N4的电压。其中，寄生电容C1、C2为综合寄生电容，包括比较器24输入端的寄生电容。
图5是本公开另一个实施例中反熔丝存储单元状态检测电路的一种电路示意图。
参考图5，在一个实施例中，反熔丝存储单元阵列22、比较器24、第三开关元件M3、第六开关元件M6均连接控制器CON。示例性可以为，控制器CON连接反熔丝存储单元阵列22中的各反熔丝存储单元的字线，连接比较器24的输出端，连接第三开关元件M3和第六开关元件M6的控制端。
图6是图5所示实施例中控制器CON实现的检测方法的流程图。
参考图6，控制器CON可以设置为执行检测方法600，检测方法600可以包括：
步骤S1，在第一时间点通过待测反熔丝存储单元的字线输出第一控制信号以使待测反熔丝存储单元电连接至位线，输出第二控制信号控制第一电流模块对比较器的第一输入端输入检测电流、第二电流模块对比较器的第二输入端输入参考电流；
步骤S2，在第二时间点获取比较器的输出信号以确定待测反熔丝存储单元的存储状态；其中，第二时间点在第一时间点之后。
下面结合图2～图5对图6的控制方法进行说明。
在第一时间点对待测反熔丝存储单元的字线输出第一控制信号后，第一节点N1所在通路的电阻会根据反熔丝存储单元的击穿状态变化。通过放大器OP1的设置，第一节点N1的电压会维持与放大器OP1所连接的参考电压Vref相同的电压值，从而在第一节点N1所在的通路产生第一电流，该第一电流与待测反熔丝存储单元的电阻负相关。同时由 于第一开关元件M1和第二开关元件M2的设置，使得第二节点N2所在的通路产生第二电流，该第二电流与第一电流成恒定比例关系，该比例由第一开关元件M1和第二开关元件M2的尺寸、性能决定。即，第二电流与待测反熔丝存储单元的电阻同样负相关，待测反熔丝存储单元的电阻越大，第二电流越小；待测反熔丝存储单元的电阻越小，第二电流越大。
第二电流对第二节点N2充电，第二电流越大，第二节点N2的充电速度越快，第二节点N2的电压变化速度越快；第二电流越小，第二节点N2的充电速度越慢，第二节点N2的电压变化速度越慢。通过以上分析可知，待测反熔丝存储单元的电阻越大，第二电流越小，第二节点N2的电压变化速度越慢；待测反熔丝存储单元的电阻越小，第二电流越大，第二节点N2的电压变化速度越快。
同理，在第二电流模块23，参考电阻越大，第四节点N4的电压变化速度越慢；参考电阻越小，第四节点N4的电压变化速度越快。
通过在第一时间点控制第一电流模块21和第二电流模块23同时对第二节点N2和第四节点N4充电，在第二时间点使用比较器24将第二节点N2的电压与第四节点N4相比较，可以判断待测反熔丝存储单元的电阻与参考电阻的比较结果，进而判断待测反熔丝存储单元的存储状态。在一个实施例中，比较器24可以是差分放大器。
获取比较器24的输出信号的方法既可以为在第二时间点读取比较器24的输出信号，也可以为通过比较器24的使能引脚控制比较器24在第二时间点转变为使能状态，输出第二节点N2的电压与第四节点N4的电压的比较结果。
在合适的时间点使用比较器24进行检测，可以使比较器的翻转点得到精确控制，防止反熔丝存储单元的电阻波动或者逻辑门自身翻转点偏移导致的存储状态检测错误。因此，本公开实施例中，对第二时间点的选择是实现精确检测的重要手段。
图7是本公开实施例确定第二时间点的方式的示意图。
参考图7，在本公开的一种示例性实施例中，第二时间点可以根据以下方式确定：
步骤S71，获取第二节点在反熔丝存储单元的击穿状态下的第一电压变化线和第四节点的第二电压变化线；
步骤S72，将第一电压变化线与第二电压变化线的差值达到预设阈值的时间点作为第二时间点。
图8是本公开另一实施例确定第二时间点的方式的示意图。
参考图8，在本公开的一种示例性实施例中，第二时间点可以根据以下方式确定：
步骤S81，获取第二节点在反熔丝存储单元的未击穿状态下的第三电压变化线和第四节点的第二电压变化线；
步骤S82，将第三电压变化线与第二电压变化线的差值达到预设阈值的时间点作为第二时间点。
在本公开实施例中，上述预设阈值大于比较器的差分输入电压阈值。
下面结合图9和图10对图7和图8所示实施例进行说明。
图9和图10是第一电压变化线、第二电压变化线、第三电压变化线的示意图。
设反熔丝存储单元在未击穿状态下的最小电阻为R1，在击穿状态下的最大电阻为R2。其中，R1和R2均来自于统计数据，通过在反熔丝存储单元的研发和生产过程中对R1和R2进行统计分析得出。
参考图9，在第一电流模块21中，当通路电阻包括R1时，随时间t的变化第二节点N2的电压V1(t)从第一时间点T1开始由0上升至VDD的第一电压变化线为：
V1(t)＝I 1(t)*t/C1   (1)
其中，I 1(t)是在通路电阻包括R1时第二节点N2的电流。
参考图10，在通路电阻包括R2时，随时间t的变化第二节点N2的电压V3(t)从第一时间点T1开始由0上升至VDD的第三电压变化线为：
V3(t)＝I 3(t)*t/C1   (2)
其中，I 3(t)是在通路电阻包括R2时第二节点N2的电流。
参考图9和图10，在第二电流模块23中，由于参考电阻Rref不变，随时间t的变化第四节点N4的电压V2(t)从第一时间点T1开始由0上升至VDD的第二电压变化线为：
V2(t)＝I 2(t)*t/C2   (3)
其中，I 2(t)是第四节点N4处的恒定电流。
由公式(1)～(3)和图9、图10可知，当设置R2＜Rref＜R1，假设C1＝C2时，V1(t)＜V2(t)＜V3(t)，有：
ΔV 1(t)＝V2(t)-V1(t)＝(I 2(t)-I 1(t))*t/C1   (4)
ΔV 2(t)＝V3(t)-V2(t)＝(I 3(t)-I 2(t))*t/C1   (5)
接下来，既可以将ΔV 1(t)等于预设阈值的时间设置为第二时间点T2(如图9)，也可以将ΔV 2(t)等于预设阈值的时间设置为第二时间点T2(如图10)。预设阈值可以根据比较器24的参数确定，例如，大于比较器24的差分输入电压阈值。预设阈值越大，检测准确度越高；预设阈值越小，检测时间越短。本发明实施例中所称的差分输入电压阈值指的是比较器能够检测出的同相输入端和反向输入端的最小电压差，该最小电压差与比较器的设计参数、工艺偏差、温度、输入电压值等有关，因此，本领域技术人员可以根据实际情况自行调整预设阈值的设置数值，以实现检测准确度和检测时间的共同最优方案。
可以理解的是，在开始检测前，为控制第二节点N2和第四节点N4的电压均为零，第三开关元件M3和第六开关元件M6的默认状态均为导通状态。第三开关元件M3和第六开关元件M6例如均可以为N型晶体管。在检测开始时，第三开关元件M3和第六开关元件M6受控制器控制关断，第二节点N2和第四节点N4的电压开始上升。通过使用第三开关元件M3和第六开关元件M6控制第二节点N2和第四节点N4的充电开始时间，可以获得更加准确的检测结果，有效提高检测精度。
在一些实施例中，可以使用ZQ校准电阻作为参考电阻Rref。
图11是本公开又一个实施例中反熔丝存储单元状态检测电路的电路示意图。
参考图11，为了减小第二节点N2和第四节点N4的寄生电容容值偏差造成的电压变化线随机偏差，可以对第二节点N2和第四节点N4分别添加额外的储能模块。即，检测电路200还可以包括：
第一储能模块25，第一端连接第二节点N2，第二端接地；
第二储能模块26，第一端连接第四节点N4，第二端接地。
第一储能模块25和第二储能模块26例如可以设置为第一检测电容C3和第二检测电容C4(如图12所示)。第一检测电容C3的作用与寄生电容C1相同，均是为了检测第二节点N2的电压；第二检测电容C4的作用与寄生电容C2相同，均是为了检测第四节点N4的电压。此时公式(1)～(5)涉及的C1可以替换为C3，公式(1)～(5)涉及的C2可以替换为C4。
为了方便计算，可以将第一检测电容C3与第二检测电容C4的容值设置为相等。在本公开的其他实施例中，也可以对第二节点N2和第四节点N4使用其他储能方案，本公开对此不作特殊限制。
图12是本公开再一个实施例中反熔丝存储单元状态检测电路的电路示意图。
参考图12，在本公开的其他实施例中，检测电路200还可以包括：
触发器27，输入端连接比较器24的输出端，第一输出端和第二输出端均连接控制器CON。
触发器27例如可以为D触发器，用于对比较器27的输出信号进行锁存，以方便控制器CON读取。本领域技术人员可以自行设置触发器24的型号，本公开不以此为限。
可以理解的是，第一储能模块25、第二储能模块26或触发器27的设置不影响图6所示控制方法的实施，不影响第二时间点的选取逻辑。
图13是本公开再一个实施例中反熔丝存储单元状态检测电路的电路示意图。
参考图13，在一个实施例中，第一节点N1连接多个位线，反熔丝存储单元阵列22可以包括：
多个反熔丝存储单元子阵列22m(m为位线序号)，每个反熔丝存储单元子阵列22m对应一条位线BLm，每个反熔丝存储单元子阵列22m包括多个反熔丝存储单元；
与反熔丝存储单元子阵列22m对应的多个第七开关元件M7m，每个第七开关元件M7m的第一端连接对应的反熔丝存储单元子阵列22m的位线BLm，每个第七开关元件M7m的第二端连接第三节点N3，每个第七开关元件M7m的控制端连接控制器CON，第七开关元件M7m的默认状态为关断状态。
通过在第一节点连接多个反熔丝存储单元子阵列22m，共享反熔丝存储状态检测电路，来对多个反熔丝存储单元子阵列22m中的反熔丝存储单元的存储状态进行检测，可以极大的节省电路面积，在一个实施例中，第一节点N1可以同时连接16个位线，具体方式如图13所示。
图14是图13所示电路对应的检测方法的流程图。
参考图14，在图13所示电路中，控制器CON可以设置为执行以下方法：
步骤S141，在第三时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第七开关元件输出第三控制信号以控制第七开关元件导通；
步骤S1，在第一时间点对待测反熔丝存储单元的字线输出第一控制信号以使待测反熔丝存储单元电连接至位线，输出第二控制信号控制第一电流模块对比较器的第一输入端输入检测电流、第二电流模块对比较器的第二输入端输入参考电流；
步骤S2，在第二时间点获取比较器的输出信号以确定待测反熔丝存储单元的存储状态；
其中，第一时间点和第三时间点均在第二时间点之前。
即图6所示的方法还可以包括步骤S141，步骤S141与步骤S1的顺序可以调换。
在图14所示实施例中，第三时间点可以在第一时间点之前，也可以在第一时间点之后，还可以与第一时间点相等，只要第三时间点和第一时间点均在第二时间点之前即可，以在第二时间点开始检测第二节点N2的电压前开启充电通路。
当第七开关元件为P型晶体管时，第三控制信号为低电平；当第七开关元件为N型晶体管时，第三控制信号为高电平。当第七开关元件为其他类型的元件时，第三控制信号也可以为其他类型的信号，本公开对此不作特殊限制。
本公开实施例提供的反熔丝存储单元状态检测电路和反熔丝存储单元状态检测方法，通过在第一时间点使用第一电流模块产生与待测反熔丝存储单元的电阻相关的电流对第二节点N2充电，使用第二电流模块产生与参考电阻相关的电流对第四节点N4充电，在第二时间点使用比较器将第二节点N2和第四节点N4的电压进行比较，可以精确控制比较器的输出翻转点。通过使用第二节点N2的电压变化线和第四节点N4的电压变化线的差值判断用于检测的第二时间点，可以尽量降低电压误判概率，使比较器的输出更为准确，避免相关技术中由于反熔丝存储单元的电阻波动和逻辑门的翻转电压偏移导致的反熔丝存储单元的存储状态误判。
根据本公开的一个方面，提供一种存储器，包括如上述任意一实施例所示的反熔丝存储单元状态检测电路。该存储器例如可以是DRAM存储器。
应当注意，尽管在上文详细描述中提及了用于动作执行的设备的若干模块或者单元，但是这种划分并非强制性的。实际上，根据本公开的实施方式，上文描述的两个或更多模块或者单元的特征和功能可以在一个模块或者单元中具体化。反之，上文描述的一个模块或者单元的特征和功能可以进一步划分为由多个模块或者单元来具体化。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和构思由权利要求 指出。
工业实用性
本公开实施例通过使用两个电流模块将待测反熔丝存储单元的电阻与参考电阻反映在第二节点的电压和第四节点的电压上，使用比较器比较第二节点的电压和第四节点的电压以判断待测反熔丝存储单元的电阻，进而判断待测反熔丝存储单元的存储状态，可以使得翻转点得到精确控制、获得更准确的检测结果，避免由于反熔丝存储单元的击穿状态电阻波动和逻辑门的翻转点偏移导致对反熔丝存储单元的存储状态误判。

Claims (14)

  1. 一种反熔丝存储单元状态检测电路，其中，包括：
    第一电流模块，第一端通过第一节点连接反熔丝存储单元阵列，第二端连接第二节点，所述反熔丝存储单元阵列包括至少一条位线，每条所述位线连接所述第一节点和多个反熔丝存储单元，所述第一电流模块用于通过所述第二节点输出检测电流，所述检测电流与所述反熔丝存储单元阵列中待测反熔丝存储单元的阻值相关；
    第二电流模块，第一端通过第三节点连接参考电阻的第一端，第二端连接第四节点，所述参考电阻的第二端接地，所述第二电流模块用于通过所述第四节点输出参考电流，所述参考电流与所述参考电阻的阻值相关；
    比较器，第一输入端连接所述第二节点，第二输入端连接所述第四节点，用于检测待测反熔丝存储单元的存储状态。
  2. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述第一电流模块包括：
    第一放大器，第一输入端连接参考电压，第二输入端连接所述第一节点，输出端连接第五节点；
    第一开关元件，第一端连接电源电压，第二端连接所述第一节点，控制端连接所述第五节点；
    第二开关元件，第一端连接所述电源电压，第二端连接所述第二节点，控制端连接所述第五节点；
    第三开关元件，第一端连接所述第二节点，第二端接地，控制端连接控制器。
  3. 如权利要求1或2所述的反熔丝存储单元状态检测电路，其中，所述第二电流模块包括：
    第二放大器，第一输入端连接参考电压，第二输入端连接所述第三节点，输出端连接第六节点；
    第四开关元件，第一端连接电源电压，第二端连接所述第三节点，控制端连接所述第六节点；
    第五开关元件，第一端连接所述电源电压，第二端连接所述第四节点，控制端连接所述第六节点；
    第六开关元件，第一端连接所述第四节点，第二端接地，控制端连接控制器。
  4. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，还包括：
    第一储能模块，第一端连接所述第二节点，第二端接地；
    第二储能模块，第一端连接所述第四节点，第二端接地。
  5. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，还包括：
    触发器，输入端连接所述比较器的输出端。
  6. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，还包括：
    控制器，连接所述多个反熔丝存储单元的字线和所述比较器，设置为：
    在第一时间点通过待测反熔丝存储单元的字线输出第一控制信号以使所述待测反熔丝存储单元电连接至位线，输出第二控制信号控制所述第一电流模块对所述比较器的第一输入端输入所述检测电流、所述第二电流模块对所述比较器的第二输入端输入所述参考电流；
    在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；
    其中，所述第二时间点在所述第一时间点之后。
  7. 如权利要求6所述的反熔丝存储单元状态检测电路，其中，所述第二时间点根据以下方式确定：
    获取所述第二节点在所述反熔丝存储单元为击穿状态下的第一电压变化线和所述第四节点的第二电压变化线；
    将所述第一电压变化线与所述第二电压变化线的差值达到预设阈值的时间点作为所述第二时间点。
  8. 如权利要求6所述的反熔丝存储单元状态检测电路，其中，所述第二时间点根据以下方式确定：
    获取所述第二节点在所述反熔丝存储单元为未击穿状态下的第三电压变化线和所述第四节点的第二电压变化线；
    将所述第三电压变化线与所述第二电压变化线的差值达到预设阈值的时间点作为所述第二时间点。
  9. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述参考电阻为ZQ校准电阻。
  10. 如权利要求1所述的反熔丝存储单元状态检测电路，其中，所述反熔丝存储单元阵列包括：
    多个反熔丝存储单元子阵列，每个所述反熔丝存储单元子阵列对应一条位线，每个所述反熔丝存储单元子阵列包括多个反熔丝存储单元；
    与所述反熔丝存储单元子阵列对应的多个第七开关元件，每个所述第七开关元件的第一端连接对应的反熔丝存储单元子阵列的位线，每个所述第七开关元件的第二端连接所述第一节点，所述第七开关元件的默认状态为关断状态。
  11. 如权利要求10所述的反熔丝存储单元状态检测电路，其中，每个所述第七开关元件的控制端均连接控制器，所述控制器设置为：
    在第三时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第七开关元件输出第三控制信号以控制所述第七开关元件导通；
    在第一时间点对所述待测反熔丝存储单元的字线输出第一控制信号以使待测反熔丝存储单元电连接至位线，输出第二控制信号控制所述第一电流模块对所述比较器的第一输入端输入所述检测电流、所述第二电流模块对所述比较器的第二输入端输入所述参考电 流；
    在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；
    其中，所述第三时间点在所述第二时间点之前。
  12. 一种反熔丝存储单元状态检测方法，其中，应用于如权利要求1～9任一项所述的反熔丝存储单元状态检测电路，包括：
    在第一时间点对待测反熔丝存储单元的字线输出第一控制信号以使待测反熔丝存储单元电连接至位线，输出第二控制信号控制所述第一电流模块对所述比较器的第一输入端输入所述检测电流、所述第二电流模块对所述比较器的第二输入端输入所述参考电流；
    在第二时间点获取所述比较器的输出信号以确定所述待测反熔丝存储单元的存储状态；
    其中，所述第二时间点在所述第一时间点之后。
  13. 如权利要求12所述的反熔丝存储单元状态检测方法，其中，所述反熔丝存储单元阵列包括：多个反熔丝存储单元子阵列，每个所述反熔丝存储单元子阵列对应一条位线，每个所述反熔丝存储单元子阵列包括多个反熔丝存储单元；与所述反熔丝存储单元子阵列对应的多个第七开关元件，每个所述第七开关元件的第一端连接对应的反熔丝存储单元子阵列的位线，每个所述第七开关元件的第二端连接所述第一节点，每个所述第七开关元件的控制端连接控制器，所述第七开关元件的默认状态为关断状态；
    所述方法还包括：
    在第三时间点对待测反熔丝存储单元所在的反熔丝存储单元子阵列对应的第七开关元件输出第三控制信号以控制所述第七开关元件导通，所述第三时间点在所述第二时间点之前。
  14. 一种存储器，其中，包括如权利要求1～11任一项所述的反熔丝存储单元状态检测电路。
PCT/CN2021/097918 2020-07-16 2021-06-02 反熔丝存储单元状态检测电路及存储器 Ceased WO2022012203A1 (zh)

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