WO2022011635A1 - 半导体结构及其制作方法 - Google Patents

半导体结构及其制作方法 Download PDF

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WO2022011635A1
WO2022011635A1 PCT/CN2020/102318 CN2020102318W WO2022011635A1 WO 2022011635 A1 WO2022011635 A1 WO 2022011635A1 CN 2020102318 W CN2020102318 W CN 2020102318W WO 2022011635 A1 WO2022011635 A1 WO 2022011635A1
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semiconductor layer
layer
light
conductivity type
emitting
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PCT/CN2020/102318
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English (en)
French (fr)
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程凯
刘撰
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苏州晶湛半导体有限公司
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Priority to US17/916,413 priority Critical patent/US20230154902A1/en
Priority to CN202080102500.XA priority patent/CN115917767A/zh
Priority to PCT/CN2020/102318 priority patent/WO2022011635A1/zh
Priority to TW110125227A priority patent/TWI811729B/zh
Publication of WO2022011635A1 publication Critical patent/WO2022011635A1/zh

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    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
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    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
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    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
    • H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
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    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/14—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a carrier transport control structure, e.g. highly-doped semiconductor layer or current-blocking structure
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    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
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    • H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/405—Reflective materials
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    • H01L33/44—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
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    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a manufacturing method thereof.
  • Group III nitride semiconductor materials have the advantages of large band gap (0.7eV ⁇ 6.2eV), high carrier saturation mobility, high breakdown electric field, good thermal conductivity, etc., and are very suitable for the preparation of blue, green, ultraviolet LED devices and Integrated electronic devices with high frequency, high power and resistance to electromagnetic radiation.
  • LEDs based on III-nitride semiconductor materials can be classified into horizontal structures and vertical structures.
  • the P electrode and the N electrode are arranged on the same side of the light emitting structure, and the conduction current flows along the horizontal direction (vertical to the thickness direction of the LED).
  • the P electrode and the N electrode are arranged on both sides of the light emitting structure, and the on-current flows along the vertical direction (the thickness direction of the LED).
  • LEDs with a horizontal structure can be divided into a front-mounted structure and a flip-chip structure.
  • the P electrode is located on the light path of the light-emitting structure.
  • the flip-chip structure neither the P electrode nor the N electrode is located on the light path of the light emitting structure.
  • the LED manufacturing methods in the prior art are suitable for large-size chip categories and application markets, but are not suitable for small-size chips, resulting in low manufacturing efficiency of mini-level (50 ⁇ m-100 ⁇ m) and micro-level ( ⁇ 50 ⁇ m) LED chips.
  • one aspect of the present invention provides a semiconductor structure, comprising:
  • adjacent light-emitting units are connected together by connecting columns, and in the row direction, the width of the connecting columns is smaller than the width of the light-emitting units; in the column direction, the connecting columns are The width is smaller than the width of the light emitting unit.
  • the connecting column includes a trunk and a branch
  • the trunk includes a first trunk extending in a row direction and/or a second trunk extending in a column direction
  • the branch connects the first trunk and the light emitting unit, or connect the second trunk with the light-emitting unit.
  • the light-emitting unit includes an N-type semiconductor layer, a P-type semiconductor layer, and a light-emitting layer located between the N-type semiconductor layer and the P-type semiconductor layer, and the connection post is connected to the N-type semiconductor layer. are located in the same layer or the connecting column is located in the same layer as the P-type semiconductor layer.
  • the light-emitting unit further includes a P electrode and an N electrode, the P electrode is electrically connected to the P-type semiconductor layer, and the N electrode is electrically connected to the N-type semiconductor layer.
  • the P electrode is located on a side of the P-type semiconductor layer away from the light-emitting layer, and the N-electrode is located at a side of the N-type semiconductor layer away from the light-emitting layer.
  • both the P electrode and the N electrode are located on a side of the P-type semiconductor layer away from the light-emitting layer.
  • both the P electrode and the N electrode are located on a side of the N-type semiconductor layer away from the light-emitting layer.
  • the light-emitting unit further includes a current spreading layer, and the current spreading layer is located on a side of the P-type semiconductor layer away from the light-emitting layer.
  • the light emitting unit further includes a light reflection layer, the light reflection layer is located on the side of the N-type semiconductor layer away from the light-emitting layer or on the side of the P-type semiconductor layer away from the light-emitting layer .
  • the material of the light-emitting layer includes a single quantum well material or a multiple quantum well material.
  • the light-emitting unit includes one light-emitting subunit or multiple light-emitting subunits.
  • the material of the light-emitting unit includes a group III nitride material.
  • Another aspect of the present invention provides a method for fabricating a semiconductor structure, comprising:
  • a substrate is provided, on which a semiconductor layer of a first conductivity type, a light-emitting layer and a semiconductor layer of a second conductivity type are sequentially formed, wherein the first conductivity type is one of N-type and P-type, and the The second conductivity type is another one of N-type and P-type;
  • the second conductive type semiconductor layer in the third predetermined area, the light emitting layer and the first conductive type semiconductor layer form a light-emitting unit connected to adjacent light-emitting units. connecting columns; in the row direction, the width of the third predetermined area is smaller than the width of the second predetermined area; in the column direction, the width of the third predetermined area is smaller than the width of the second predetermined area;
  • the substrate is removed from the groove by wet etching, and the removal rate of the etching solution used in the wet etching to the substrate in the horizontal plane direction is greater than the removal rate in the thickness direction.
  • the third predetermined area includes a main area and a branch area
  • the main area includes a first main area extending in the row direction and/or a second main area extending in the column direction
  • the branch area is connected to the the first trunk area and the second predetermined area, or connect the second trunk area and the second predetermined area.
  • the second conductivity type in the third predetermined area is also removed type semiconductor layer and the light emitting layer, and the first conductive type semiconductor layer is reserved to form the connection column.
  • the semiconductor layer of the second conductivity type, the light emitting layer and the first conductivity type are removed in the first predetermined region.
  • the method further includes: removing the second conductive type semiconductor layer and the light emitting layer in a part of the first predetermined region, exposing the first conductive type semiconductor layer. a partial area; a first electrode is formed on the exposed semiconductor layer of the first conductivity type, and a second electrode is formed on the semiconductor layer of the second conductivity type.
  • the method includes: removing the second conductivity type semiconductor layer and the light emitting layer in a partial area of the first predetermined area, exposing a partial area of the first conductivity type semiconductor layer; A first electrode is formed on the semiconductor layer of the conductivity type, and a second electrode is formed on the semiconductor layer of the second conductivity type.
  • the semiconductor layer of the first conductivity type is a P-type semiconductor layer
  • a current diffusion layer is formed on the exposed semiconductor layer of the first conductivity type
  • the two-conductivity-type semiconductor layer is a P-type semiconductor layer.
  • a current diffusion layer is formed on the second-conductivity-type semiconductor layer.
  • a light reflection layer is formed first; or after the semiconductor layer of the second conductivity type is formed, the light reflection layer is also formed.
  • the material of the light-emitting layer includes a single quantum well material or a multiple quantum well material.
  • the light-emitting unit includes one light-emitting subunit or multiple light-emitting subunits.
  • the material of the semiconductor layer of the first conductivity type, and/or the light emitting layer, and/or the semiconductor layer of the second conductivity type includes a group III nitride material.
  • the material of the substrate is single crystal silicon
  • the etching solution is a mixed solution of hydrofluoric acid, nitric acid and acetic acid.
  • the semiconductor layer of the conductivity type, the light-emitting layer and the semiconductor layer of the first conductivity type form a groove, and the semiconductor layer of the second conductivity type, the light-emitting layer and the semiconductor layer of the first conductivity type in the second predetermined area and the third predetermined area are reserved,
  • the semiconductor layer of the second conductivity type, the light emitting layer and the semiconductor layer of the first conductivity type in the second predetermined area form a light emitting unit arranged in an array, and the semiconductor layer of the second conductivity type, the light emitting layer and the first conductivity type semiconductor layer in the third predetermined area
  • the conductive type semiconductor layer forms a connection column connecting adjacent light-emitting units; in the row direction, the width of the third predetermined area is smaller than the width of the second predetermined area; in the column direction, the width of the third predetermined area is smaller than the width of the second predetermined area width. In this way, the substrate can be removed from the groove by wet etching, and a plurality of small-sized LED structures can
  • the semiconductor layer of the second conductivity type and the semiconductor layer of the first conductivity type in the first predetermined region are also removed.
  • the semiconductor layer of the second conductivity type and the light-emitting layer in the third predetermined region are also removed.
  • the semiconductor layer of the first conductivity type is retained to form a connection column.
  • the thickness of the connecting column is relatively thin, which can facilitate subsequent cutting to form individual LED structures.
  • the third predetermined area includes a main area and a branch area
  • the main area includes a first main area extending in the row direction and/or a second main area extending in the column direction
  • the branch area is connected to the first main area.
  • the second predetermined area or connecting the second trunk area and the second predetermined area.
  • the trunk area can easily identify the arrangement of the light-emitting units, and can improve the uniformity of force between the light-emitting units.
  • the method further includes: removing the second conductivity type semiconductor layer and the light emitting layer in a partial area of the first predetermined area, exposing a partial area of the first conductivity type semiconductor layer; A first electrode is formed on the semiconductor layer of the second conductivity type, and a second electrode is formed on the semiconductor layer of the second conductivity type.
  • the method further includes: removing the first conductive type semiconductor layer.
  • the second conductive type semiconductor layer and the light emitting layer in a part of the predetermined area expose a part of the first conductive type semiconductor layer; a first electrode is formed on the exposed first conductive type semiconductor layer, and a second conductive type is formed on the exposed semiconductor layer.
  • a second electrode is formed on the semiconductor layer of the type.
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention
  • FIG. 2 to 4 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1;
  • FIG. 5 is a top view of the semiconductor structure according to the first embodiment of the present invention.
  • Figure 6 is a cross-sectional view taken along line CC in Figure 5;
  • Fig. 7 is a sectional view along line DD in Fig. 5;
  • FIG. 8 is a top view of a semiconductor structure according to a second embodiment of the present invention.
  • FIG. 9 is a cross-sectional view along line EE in FIG. 8;
  • FIG. 10 is a top view of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 11 is a schematic diagram of an intermediate structure corresponding to the process of manufacturing the semiconductor structure in FIG. 10;
  • FIG. 12 is a top view of a semiconductor structure according to a fourth embodiment of the present invention.
  • FIG. 13 is a schematic cross-sectional structure diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • FIG. 14 is a schematic cross-sectional structure diagram of a semiconductor structure according to a sixth embodiment of the present invention.
  • FIG. 15 is a schematic cross-sectional structure diagram of a semiconductor structure according to a seventh embodiment of the present invention.
  • 16 to 19 are schematic diagrams of intermediate structures corresponding to the process of fabricating the semiconductor structure in FIG. 15;
  • FIG. 20 is a schematic cross-sectional structure diagram of a semiconductor structure according to an eighth embodiment of the present invention.
  • FIG. 21 is a schematic diagram of an intermediate structure corresponding to the process of fabricating the semiconductor structure in FIG. 20 .
  • the first predetermined area 1a The second predetermined area 1b
  • Branch area 1e The first trunk area 1f
  • FIG. 1 is a flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention
  • FIGS. 2 to 4 are schematic diagrams of intermediate structures corresponding to the process in FIG. 1
  • FIG. 5 is a top view of the semiconductor structure according to the first embodiment of the present invention
  • FIG. 6 is a cross-sectional view along line CC in FIG. 5
  • FIG. 7 is a cross-sectional view along line DD in FIG. 5 .
  • a substrate 10 is provided, and a semiconductor layer of the first conductivity type, a light-emitting layer 11c and a semiconductor layer of the second conductivity type are sequentially formed on the substrate 10,
  • the first conductivity type is one of N-type and P-type
  • the second conductivity type is the other of N-type and P-type.
  • 3 is a cross-sectional view taken along line AA in FIG. 2 .
  • the material of the substrate 10 may be sapphire, silicon carbide, silicon, diamond, GaN or one of sapphire, silicon carbide, silicon, diamond and GaN on it.
  • the semiconductor layer of the first conductivity type may be the N-type semiconductor layer 11a, and its material may be, for example, an N-type Group III nitride material.
  • the N-type doping element may include at least one of Si, Ge, Sn, Se, or Te.
  • the Group III nitride material may include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.
  • the formation process of the N-type semiconductor layer 11a may include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE, Molecular Beam Epitaxy), Or Plasma Enhanced Chemical Vapor Deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or Low Pressure Chemical Vapor Deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or Metal-Organic Chemical Vapor Deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), or a combination thereof.
  • ALD Atomic layer deposition
  • CVD Chemical Vapor Deposition
  • MBE molecular beam epitaxy
  • PECVD Plasma Enhanced Chemical Vapor Deposition
  • LPCVD Low Pressure Chemical Vapor Deposition
  • MOCVD Metal-Organic Chemical Vapor Deposition
  • the N-type semiconductor layer 11a may include one or more layers.
  • the light emitting layer 11c may include at least one of a single quantum well structure, a multiple quantum well (MQW) structure, a quantum wire structure, and a quantum dot structure.
  • the light emitting layer 11c may include a well layer and a barrier layer formed of a group III nitride material.
  • the Group III nitride material may include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.
  • the well layer may include an Al x Ga 1-x N layer, where x is the percentage of the mass of Al element to the sum of the mass of Al element and Ga element, 1 ⁇ x ⁇ 0; and/or the barrier layer may include Al y Ga 1-y N layer, where y is the percentage of the mass of the Al element to the sum of the mass of the Al element and the Ga element, 1 ⁇ y ⁇ 0.
  • the forbidden band width of the well layer is smaller than that of the barrier layer.
  • the well layer and/or the barrier layer may or may not be doped with Al.
  • Undoping Al can improve its own crystal quality, but doping Al can reduce its own resistance.
  • Alternating multiple layers of well layers and barrier layers can form a multi-quantum well structure, which further improves the luminous efficiency.
  • the semiconductor layer of the second conductivity type may be a P-type semiconductor layer 11b, such as a P-type group III nitride material.
  • the P-type doping element may include at least one of Mg, Zn, Ca, Sr, or Ba.
  • the Group III nitride material may include any one or a combination of GaN, AlGaN, InGaN, and AlInGaN.
  • the formation process of the P-type semiconductor layer 11b may refer to the formation process of the N-type semiconductor layer 11a.
  • the P-type semiconductor layer 11b may include one or more layers.
  • the P-type semiconductor layer 11 b may also be close to the substrate 10 , and the N-type semiconductor layer 11 a may be far away from the substrate 10 .
  • the semiconductor layer of the second conductivity type, the light emitting layer 11c and the semiconductor layer of the first conductivity type in the first predetermined region 1a are removed to form a groove 1v, and the remaining The semiconductor layers of the second conductivity type, the light-emitting layer 11c and the semiconductor layer of the first conductivity type in the second predetermined area 1b and the third predetermined area 1c, the semiconductor layer of the second conductivity type, the light-emitting layer 11c and the semiconductor layer of the second conductivity type in the second predetermined area 1b
  • the semiconductor layer of the first conductivity type forms the light-emitting units 11 arranged in an array, and the semiconductor layer of the second conductivity type, the light-emitting layer 11c and the semiconductor layer of the first conductivity type in the third predetermined area 1c form a connection between the adjacent light-emitting units 11 .
  • FIG. 4 is a cross-sectional view taken along line BB in FIG. 2 .
  • the removal of the semiconductor layer of the second conductivity type, the light emitting layer 11c and the semiconductor layer of the first conductivity type in the first predetermined region 1a is achieved by dry etching.
  • the etching gas for dry etching may include a mixed gas of BCl 3 and Cl 2 .
  • the removal of the semiconductor layer of the second conductivity type, the light emitting layer 11c and the semiconductor layer of the first conductivity type in the first predetermined region 1a is achieved by wet etching.
  • the wet etching solution is, for example, a KOH solution, which is corrosive on the N side but non-corrosive on the Ga side.
  • the N-side of the semiconductor layer of the second conductivity type, the light emitting layer 11c, and the semiconductor layer of the first conductivity type can be controlled to face upward through the growth process.
  • the N-side up of the second conductivity type semiconductor layer, the light-emitting layer 11c and the first conductivity type semiconductor layer means: with the Ga-N bond parallel to the C axis ([0001] crystal direction) as a reference, each Ga The N atoms in the -N bond are further away from the semiconductor substrate 10 . It can be understood that, at this time, the lower surfaces of the semiconductor layer of the second conductivity type, the light emitting layer 11c and the semiconductor layer of the first conductivity type are Ga surfaces.
  • step S3 in FIG. 1 and as shown in FIGS. 2 to 7 the substrate 10 is removed by wet etching from the groove 1v, and the removal rate of the etching solution used in the wet etching to the substrate 10 in the horizontal plane direction is greater than direction removal rate.
  • 5 is a top view of the semiconductor structure after the substrate is removed;
  • FIG. 6 is a cross-sectional view along line CC in FIG. 5 ;
  • FIG. 7 is a cross-sectional view along line DD in FIG. 5 .
  • one crystal direction of the horizontal plane may be [110]
  • the crystal direction of the thickness direction may be [111]
  • the etching solution may be a mixed solution of hydrofluoric acid, nitric acid and acetic acid. Since the removal rate of the etching solution in the [110] crystallographic orientation is greater than that in the [110] crystallographic orientation, the silicon substrate 10 can be separated from the semiconductor structure 1 without being completely etched, which speeds up the rate of stripping the substrate 10 .
  • substrate 10 materials such as sapphire, silicon carbide, diamond or GaN
  • targeted solutions can also be used for stripping.
  • the semiconductor structure 1 according to the first embodiment of the present invention includes:
  • the width w1 of the connecting columns 12 is smaller than the width W1 of the light-emitting units 11; in the column direction, the connecting columns 12
  • the width w2 of the light emitting unit 11 is smaller than the width W2 of the light emitting unit 11 .
  • a plurality of small-sized light-emitting units 11 are connected together by connecting columns 12, which can be easily transferred.
  • the connecting pillars 12 can be cut to form individual light-emitting units 11 .
  • FIG. 8 is a top view of a semiconductor structure according to a second embodiment of the present invention
  • FIG. 9 is a cross-sectional view taken along line EE in FIG. 8 .
  • the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, the only difference being that the connection pillars 12 and the semiconductor layer of the first conductivity type are located on the same layer.
  • connection pillars 12 and the N-type semiconductor layer 11 a are located in the same layer; when the P-type semiconductor layer 11 b is close to the substrate 10 , the connection pillars 12 and the P-type semiconductor layer 11 b are located in the same layer.
  • Floor when the N-type semiconductor layer 11 a is close to the substrate 10 , the connection pillars 12 and the N-type semiconductor layer 11 a are located in the same layer; when the P-type semiconductor layer 11 b is close to the substrate 10 , the connection pillars 12 and the P-type semiconductor layer 11 b are located in the same layer.
  • the thickness of the connecting column 12 is relatively thin, which can facilitate subsequent cutting to form each discrete light-emitting unit 11 .
  • the fabrication method of the semiconductor structure 2 of the second embodiment is substantially the same as the fabrication method of the semiconductor structure 1 of the first embodiment, and the only difference is that in step S2, the semiconductor layer of the second conductivity type in the first predetermined region 1a is removed When the light-emitting layer 11c and the first-conductivity-type semiconductor layer are removed, the second-conductivity-type semiconductor layer and the light-emitting layer 11c in the third predetermined region 1c are also removed, and the first-conductivity-type semiconductor layer is retained to form the connection post 12 .
  • the removal of the semiconductor layer of the second conductivity type, the light-emitting layer 11c and the semiconductor layer of the first conductivity type in the first predetermined region 1a and the removal of the semiconductor layer of the second conductivity type and the light-emitting layer 11c in the third predetermined region 1c may be performed in different steps in progress. In other words, dry etching or wet etching can be performed respectively using mask layers of different patterns.
  • FIG. 10 is a top view of a semiconductor structure according to a third embodiment of the present invention.
  • FIG. 11 is a schematic diagram of an intermediate structure corresponding to the process of fabricating the semiconductor structure in FIG. 10 .
  • the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, the only difference being that the connection pillar 12 includes a trunk 12a and a branch 12b, and the trunk 12a includes a first trunk extending in the row direction 12c and the second trunk 12d extending in the column direction, the branch 12b connects the first trunk 12c and the light emitting unit 11, or connects the second trunk 12d and the light emitting unit 11.
  • the trunk 12a may include a first trunk 12c extending in the row direction, connecting a row of light-emitting units 11 together; or the trunk 12a may include a second trunk 12d extending in the column direction, connecting a column of light-emitting units 11 to each other. Together.
  • the trunk 12 a can facilitate the identification of the arrangement of the light-emitting units 11 , and can improve the uniformity of force between the light-emitting units 11 in the semiconductor structure 3 .
  • the fabrication method of the semiconductor structure 3 of the third embodiment is substantially the same as the fabrication method of the semiconductor structures 1 and 2 of the first and second embodiments, and the difference is only that: in step S2, the third predetermined area is 1c includes a trunk area 1d and a branch area 1e, the trunk area 1d includes a first trunk area 1f extending in the row direction and/or a second trunk area 1g extending in the column direction, and the branch area 1e connects the first trunk area 1f and the second trunk area 1f The predetermined area 1b, or connecting the second trunk area 1g and the second predetermined area 1b.
  • FIG. 12 is a top view of a semiconductor structure according to a fourth embodiment of the present invention.
  • the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structure 2 of the second embodiment, the only difference being that the connection pillar 12 includes a trunk 12a and a branch 12b, and the trunk 12a includes a first trunk extending in the row direction 12c and the second trunk 12d extending in the column direction, the branch 12b connects the first trunk 12c and the light emitting unit 11, or connects the second trunk 12d and the light emitting unit 11.
  • the trunk 12a may include a first trunk 12c extending in the row direction, connecting a row of light-emitting units 11 together; or the trunk 12a may include a second trunk 12d extending in the column direction, connecting a column of light-emitting units 11 to each other. Together.
  • FIG. 13 is a schematic cross-sectional structure diagram of a semiconductor structure according to a fifth embodiment of the present invention.
  • the semiconductor structure 5 of the fifth embodiment is substantially the same as the semiconductor structures 1, 2, 3, and 4 of the first, second, third, and fourth embodiments, except that the light emitting unit 11 further includes the P electrode 14 and the The N electrode 13 and the P electrode 14 are electrically connected to the P type semiconductor layer 11b, and the N electrode 13 is electrically connected to the N type semiconductor layer 11a.
  • the material of the P electrode 14 and the N electrode 13 may be metal, such as existing conductive materials such as Ti/Al/Ni/Au and Ni/Au.
  • An ohmic contact is formed between the P electrode 14 and the P-type semiconductor layer 11b, and an ohmic contact is also formed between the N electrode 13 and the N-type semiconductor layer 11a.
  • the fabrication method of the semiconductor structure 5 of the fifth embodiment is substantially the same as the fabrication method of the semiconductor structures 1, 2, 3, and 4 of the first, second, third, and fourth embodiments, and the only difference is that the difference between step S1 and step S2 is: Occasionally, between step S2 and step S3: removing the semiconductor layer of the second conductivity type and the light emitting layer 11c in part of the first predetermined region 1a, exposing a part of the semiconductor layer of the first conductivity type, in the exposed first
  • the first electrode is formed on the semiconductor layer of the conductivity type
  • the second electrode is formed on the semiconductor layer of the second conductivity type.
  • the first electrode is the N electrode 13; when the second conductivity type semiconductor layer is the P type semiconductor layer 11b, the second electrode is the P electrode 14.
  • the first electrode is the P electrode 14; when the semiconductor layer of the second conductivity type is the N-type semiconductor layer 11a, the second electrode is the N electrode 13.
  • the method for forming the first electrode and the second electrode may include: firstly using a physical vapor deposition method or a chemical vapor deposition method to form an entire metal layer, and then patterning the metal layer.
  • FIG. 14 is a schematic cross-sectional structural diagram of a semiconductor structure according to a sixth embodiment of the present invention.
  • the semiconductor structure 6 of the sixth embodiment is substantially the same as the semiconductor structures 1, 2, 3, 4, and 5 of the first, second, third, fourth, and fifth embodiments, except that the light-emitting unit 11 further includes
  • the current diffusion layer 15 is located on the side of the P-type semiconductor layer 11b away from the light-emitting layer 11c.
  • the current diffusion layer 15 can improve the conductivity of the P-type semiconductor layer 11b.
  • the material of the current spreading layer 15 may be ITO.
  • the fabrication method of the semiconductor structure 6 of the sixth embodiment is substantially the same as the fabrication method of the semiconductor structure 5 of the fifth embodiment.
  • the difference between the manufacturing methods of the semiconductor structure 6 and the semiconductor structure 5 is only that before the second electrode is formed,
  • the current diffusion layer 15 is first formed on the semiconductor layer of the second conductivity type.
  • the difference between the manufacturing methods of the semiconductor structure 6 and the semiconductor structure 5 is only that before the first electrode is formed,
  • the current diffusion layer 15 is first formed on the exposed semiconductor layer of the first conductivity type.
  • FIG. 15 is a schematic cross-sectional structure diagram of a semiconductor structure according to a seventh embodiment of the present invention. 16 to 19 are schematic diagrams of intermediate structures corresponding to the process of fabricating the semiconductor structure in FIG. 15 .
  • the semiconductor structure 7 of the seventh embodiment is substantially the same as the semiconductor structure 6 of the sixth embodiment, except that the current diffusion layer 15 has a light reflection layer 16 on the side away from the light emitting layer 11c, and the current diffusion layer 15
  • the protective layer 17 and the light reflection layer 16 are covered in the protective layer 17; the protective layer 17, the upper surface of the P-type semiconductor layer 11b not covered by the protective layer 17, the sidewalls of the P-type semiconductor layer 11b and the light-emitting layer 11c, and the N-type semiconductor layer
  • the upper surface of 11a is covered with an insulating layer 18; the insulating layer 18 has openings exposing parts of the protective layer 17 on the P-type semiconductor layer 11b and the N-type semiconductor layer 11a to form the P electrode 14 and the N electrode 13 correspondingly.
  • the material of the light reflection layer 16 may be silver, which is used to reflect the light emitted by the light emitting layer 11c into the light emitting layer 11c, so as to emit light from the side of the N-type semiconductor layer 11a.
  • the material of the protective layer 17 can be titanium or copper, on the one hand to prevent silver oxidation of the light reflection layer 16, and on the other hand to prevent light from the current diffusion layer 15 side.
  • the fabrication method of the semiconductor structure 7 of the seventh embodiment is substantially the same as the fabrication method of the semiconductor structure 6 of the sixth embodiment.
  • the difference between the fabrication methods of the semiconductor structure 7 and the semiconductor structure 6 is only that the difference between step S1 and step S2 is: Occasionally between steps S2 and S3: forming a light reflective layer 16 on the side of the current spreading layer 15 away from the light emitting layer 11c; forming a protective layer 17 covering the current spreading layer 15 and the light reflective layer 16; forming the protective layer 17, An insulating layer 18 is formed on the upper surface of the P-type semiconductor layer 11b not covering the protective layer 17, the sidewalls of the P-type semiconductor layer 11b and the light-emitting layer 11c, and the exposed upper surface of the N-type semiconductor layer 11a; within the insulating layer 18 Openings are formed to expose parts of the protective layer 17 and the N-type semiconductor layer 11a on the P-type semiconductor layer 11b, respectively, and P-electrodes 14 and N-electrodes 13 are
  • the formation of the P electrode 14 and the N electrode 13 is performed between step S1 and step S2 .
  • the P-type semiconductor layer 11b and the light-emitting layer 11c in part of the first predetermined region 1a are first removed to expose part of the N-type semiconductor layer 11a; then, by physical vapor deposition or chemical vapor deposition A current diffusion material layer is formed on the P-type semiconductor layer 11b, the sidewalls of the P-type semiconductor layer 11b and the light-emitting layer 11c, and the exposed N-type semiconductor layer 11a, the current diffusion material layer is patterned, and the P-type semiconductor layer is retained.
  • the current diffusion material layer in the upper part of the area of 11b forms the current diffusion layer 15 ; then a first leveling layer is formed on the N-type semiconductor layer 11a , and the upper surface of the first leveling layer is flush with the upper surface of the current diffusion layer 15 .
  • the first leveling layer may be an organic material with better fluidity, such as photoresist.
  • a light reflection layer 16 is formed on the upper surface of the first leveling layer and the upper surface of the current spreading layer 15 by sputtering or electroless plating; The light reflective layer 16 is taken away together.
  • a second leveling layer is formed on the N-type semiconductor layer 11a, and the upper surface of the second leveling layer is flush with the upper surface of the light reflection layer 16;
  • a gap is formed between the diffusion layer 15 and the sidewall of the light reflection layer 16; as shown in FIG. 18, a sputtering method or an electroless plating method is used to form a protection layer on the upper surface of the second leveling layer, the upper surface of the light reflection layer 16 and the gap. layer 17; tear off the second leveling layer, and the protective layer 17 on the second leveling layer is taken away together.
  • an insulating layer 18 is formed on the surface; an opening is formed in the insulating layer 18 to respectively expose the protective layer 17 on the P-type semiconductor layer 11b and a partial region of the N-type semiconductor layer 11a, and P is formed in the opening and on the insulating layer 18 outside the opening. Electrode 14 and N electrode 13 .
  • the P-type semiconductor layer 11b, the light-emitting layer 11c, and the N-type semiconductor layer 11a in the first predetermined region 1a can be removed to form the groove 1v; or the first predetermined region can be removed.
  • the P-type semiconductor layer 11b, the light-emitting layer 11c, and the N-type semiconductor layer 11a of 1a are formed with the groove 1v, and then the insulating layer 18, the P electrode 14, and the N electrode 13 are formed.
  • the difference between the fabrication methods of the semiconductor structure 7 and the semiconductor structure 6 is only that the difference between step S1 and step S2 is: Occasionally or between step S2 and step S3: forming a light reflective layer 16 on the N-type semiconductor layer 11a; forming a protective layer 17 covering the light reflective layer 16; 11a, the sidewalls of the N-type semiconductor layer 11a and the light-emitting layer 11c, the current diffusion layer 15, and the upper surface of the P-type semiconductor layer 11b without the current diffusion layer 15 to form an insulating layer 18;
  • the protective layer 17 on the type semiconductor layer 11a and the partial region of the current diffusion layer 15 on the P type semiconductor layer 11b are openings, and N electrodes 13 and P electrodes 14 are formed in the openings and on the insulating layer 18 outside the openings.
  • FIG. 20 is a schematic cross-sectional structure diagram of a semiconductor structure according to an eighth embodiment of the present invention.
  • FIG. 21 is a schematic diagram of an intermediate structure corresponding to the process of fabricating the semiconductor structure in FIG. 20 .
  • the semiconductor structure 8 and the fabrication method thereof of the eighth embodiment are substantially the same as the semiconductor structure 7 of the seventh embodiment and the fabrication method thereof, except that the light-emitting unit 11 includes two light-emitting subunits, The first electrodes on the semiconductor layers of the first type of adjacent light-emitting subunits are connected together.
  • each light-emitting subunit when the semiconductor structure 8 is cut, it can be cut along the middle of the first electrode, so that each light-emitting subunit has one first electrode.
  • the first electrode is the N electrode 13 .
  • the first electrode is the P electrode 14 .
  • the first electrodes are exposed to the first type of semiconductor layer by removing the second type of semiconductor layer and the light-emitting layer 11c in part of the region. formed in some areas.
  • a plurality of electrical connection structures may also be formed in the first type semiconductor layer to form a first electrode on the side of the second type semiconductor layer away from the light emitting layer 11c.
  • a first electrode may also be formed on the side of the first type semiconductor layer away from the light emitting layer 11c.

Abstract

本申请提供了一种半导体结构及其制作方法，半导体结构的制作方法中：对于自下而上依次分布的衬底、第一导电类型的半导体层、发光层与第二导电类型的半导体层，去除第一预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层形成凹槽，保留第二、第三预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层，第二预定区域保留的各层形成阵列式排布的发光单元，第三预定区域保留的各层形成连接相邻发光单元的连接柱；在行与列方向上，第三预定区域的宽度都小于第二预定区域的宽度。如此，对于镂空的第一导电类型的半导体层、发光层与第二导电类型的半导体层，可自凹槽湿法腐蚀去除衬底，大批量形成多个小尺寸LED结构。

Description

半导体结构及其制作方法 技术领域
本申请涉及半导体技术领域，尤其涉及一种半导体结构及其制作方法。
背景技术
III族氮化物半导体材料具有禁带宽度大(0.7eV～6.2eV)、载流子饱和迁移速率高、击穿电场高、导热性能好等优点，非常适于制备蓝、绿、紫外LED器件以及高频、大功率、抗电磁辐射的集成电子器件。
基于III族氮化物半导体材料的LED可分为水平结构和垂直结构。水平结构中，P电极与N电极设置在发光结构的同侧，导通电流沿水平方向(垂直LED的厚度方向)流动。垂直结构中，P电极与N电极设置在发光结构的两侧，导通电流沿垂直方向(LED的厚度方向)流动。水平结构的LED可分为正装结构与倒装结构。正装结构中，P电极位于发光结构出光的光路上。倒装结构中，P电极与N电极都不位于发光结构出光的光路上。
现有技术中的LED制作方法适用于大尺寸芯片类别和应用市场，不适用于小尺寸芯片，导致mini级别(50μm～100μm)和micro级别(＜50μm)的LED芯片制作效率较低。
有鉴于此，实有必要提供一种半导体结构及其制作方法，提高小尺寸LED芯片的制作效率。
发明内容
为实现上述目的，本发明一方面提供一种半导体结构，包括：
阵列式排布的发光单元，相邻所述发光单元之间通过连接柱连接在一起，在行方向上，所述连接柱的宽度小于所述发光单元的宽度；在列方向上，所述连接柱的宽度小于所述发光单元的宽度。
可选地，所述连接柱包括主干与分支，所述主干包括沿行方向延伸的第一主干和/或沿列方向延伸的第二主干，所述分支连接所述第一主干与所述发光单元，或连接所述第二主干与所述发光单元。
可选地，所述发光单元包括N型半导体层、P型半导体层以及位于所述N型半导体层与所述P型半导体层之间的发光层，所述连接柱与所述N型半导体层位于同层或所述连接柱与所述P型半导体层位于同层。
可选地，所述发光单元还包括P电极与N电极，所述P电极与所述P型半导体层电连接，所述N电极与所述N型半导体层电连接。
可选地，所述P电极位于所述P型半导体层远离所述发光层的一侧，所述N电极位于所述N型半导体层远离所述发光层的一侧。
可选地，所述P电极与所述N电极都位于所述P型半导体层远离所述发光层的一侧。
可选地，所述P电极与所述N电极都位于所述N型半导体层远离所述发光层的一侧。
可选地，所述发光单元还包括电流扩散层，所述电流扩散层位于所述P型半导体层远离所述发光层的一侧。
可选地，所述发光单元还包括光反射层，所述光反射层位于所述N型半导体层远离所述发光层的一侧或位于所述P型半导体层远离所述发光层的一侧。
可选地，所述发光层的材料包括单量子阱材料或多量子阱材料。
可选地，所述发光单元包括一个发光子单元或多个发光子单元。
可选地，所述发光单元的材料包括Ⅲ族氮化物材料。
本发明另一方面提供一种半导体结构的制作方法，包括：
提供衬底，在所述衬底上依次形成第一导电类型的半导体层、发光层与第二导电类型的半导体层，所述第一导电类型为N型与P型中的一种，所述第二导电类型为N型与P型中的另一种；
去除第一预定区域的所述第二导电类型的半导体层、所述发光层与所述第一导电类型的半导体层形成凹槽，保留第二预定区域与第三预定区域的所述第二导电类型的半导体层、所述发光层与所述第一导电类型的半导体层，所述第二预定区域的所述第二导电类型的半导体层、所述发光层与所述第一导电类型的半导体层形成阵列式排布的发光单元，所述第三预定区域的所述第二导电类型的半导体层、所述发光层与所述第一导电类型的半导体层形成连接相邻所述发光单元的连接柱；在行方向上，所述第三预定区域的宽度小于所述第二预定区域的宽度；在列方向上，所述第三预定区域的宽度小于所述第二预定区域的宽度；
自所述凹槽湿法腐蚀去除所述衬底，所述湿法腐蚀使用的腐蚀液对所述衬底在水平面方向的去除速率大于在厚度方向的去除速率。
可选地，所述第三预定区域包括主干区域与分支区域，所述主干区域包括沿行方向延伸的第一主干区域和/或沿列方向延伸的第二主干区域，所述分支区域连接所述第一主干区域与所述第二预定区域，或连接所述第二主干区域与所述第二预定区域。
可选地，去除第一预定区域的所述第二导电类型的半导体层、所述发光层与所述第一导电类型的半导体层时，还去除所述第三预定区域的所述第二导电类型的半导体层与所述发光层，保留所述第一导电类型的半导体层形 成所述连接柱。
可选地，形成第一导电类型的半导体层、发光层与第二导电类型的半导体层后，去除第一预定区域的所述第二导电类型的半导体层、所述发光层与所述第一导电类型的半导体层形成凹槽前，还包括：去除所述第一预定区域中部分区域的所述第二导电类型的半导体层与所述发光层，暴露所述第一导电类型的半导体层的部分区域；在所暴露的所述第一导电类型的半导体层上形成第一电极，在所述第二导电类型的半导体层上形成第二电极。
可选地，去除第一预定区域的所述第二导电类型的半导体层、所述发光层与所述第一导电类型的半导体层形成凹槽后，湿法腐蚀去除所述衬底前，还包括：去除所述第一预定区域中部分区域的所述第二导电类型的半导体层与所述发光层，暴露所述第一导电类型的半导体层的部分区域；在所暴露的所述第一导电类型的半导体层上形成第一电极，在所述第二导电类型的半导体层上形成第二电极。
可选地，若所述第一导电类型的半导体层为P型半导体层，形成第一电极前，先在所暴露的所述第一导电类型的半导体层上形成电流扩散层；若所述第二导电类型的半导体层为P型半导体层，形成第二电极前，先在所述第二导电类型的半导体层上形成电流扩散层。
可选地，在所述衬底上形成第一导电类型的半导体层前，先形成光反射层；或形成第二导电类型的半导体层后，还形成光反射层。
可选地，所述发光层的材料包括单量子阱材料或多量子阱材料。
可选地，所述发光单元包括一个发光子单元或多个发光子单元。
可选地，所述第一导电类型的半导体层、和/或所述发光层、和/或所述第二导电类型的半导体层的材料包括Ⅲ族氮化物材料。
可选地，所述衬底的材料为单晶硅，所述腐蚀液为氢氟酸、硝酸、乙酸的混和液。
与现有技术相比，本发明的有益效果在于：
1)本发明的半导体结构的制作方法中：对于自下而上依次分布的衬底、第一导电类型的半导体层、发光层与第二导电类型的半导体层，去除第一预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层形成凹槽，保留第二预定区域与第三预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层，第二预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层形成阵列式排布的发光单元，第三预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层形成连接相邻发光单元的连接柱；在行方向上，第三预定区域的宽度小于第二预定区域的宽度；在列方向上，第三预定区域的宽度小于第二预定区域的宽度。如此，可自凹槽湿法腐蚀去除衬底，大批量形成多个小尺寸的LED结构。
2)可选方案中，去除第一预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层时，还去除第三预定区域的第二导电类型的半导体层与发光层，保留第一导电类型的半导体层形成连接柱。连接柱的厚度较薄，可方便后续切割形成各个分立的LED结构。
3)可选方案中，第三预定区域包括主干区域与分支区域，主干区域包括沿行方向延伸的第一主干区域和/或沿列方向延伸的第二主干区域，分支区域连接第一主干区域与第二预定区域，或连接第二主干区域与第二预定区域。主干区域可方便辨识各发光单元的排布方式，且能提高各发光单元之间的受力均匀性。
4)可选方案中，形成第一导电类型的半导体层、发光层与第二导电类型的半导体层后，去除第一预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层形成凹槽前，还包括：去除第一预定区域中部分区域的第二导电类型的半导体层与发光层，暴露第一导电类型的半导体层的部分区域；在所暴露的第一导电类型的半导体层上形成第一电极，在第二导电类型的半导体层上形成第二电极。本方案可一次大批量形成若干正装或倒装 的LED结构。
5)可选方案中，去除第一预定区域的第二导电类型的半导体层、发光层与第一导电类型的半导体层形成凹槽后，湿法腐蚀去除衬底前，还包括：去除第一预定区域中部分区域的第二导电类型的半导体层与发光层，暴露第一导电类型的半导体层的部分区域；在所暴露的第一导电类型的半导体层上形成第一电极，在第二导电类型的半导体层上形成第二电极。本方案也可一次大批量形成若干正装或倒装的LED结构。
附图说明
图1是本发明第一实施例的半导体结构的制作方法的流程图；
图2至图4是图1中的流程对应的中间结构示意图；
图5是本发明第一实施例的半导体结构的俯视图；
图6是沿着图5中的CC线的剖视图；
图7是沿着图5中的DD线的剖视图；
图8是本发明第二实施例的半导体结构的俯视图；
图9是沿着图8中的EE线的剖视图；
图10是本发明第三实施例的半导体结构的俯视图；
图11是制作图10中的半导体结构流程对应的中间结构示意图；
图12是本发明第四实施例的半导体结构的俯视图；
图13是本发明第五实施例的半导体结构的截面结构示意图；
图14是本发明第六实施例的半导体结构的截面结构示意图；
图15是本发明第七实施例的半导体结构的截面结构示意图；
图16至图19是制作图15中的半导体结构流程对应的中间结构示意图；
图20是本发明第八实施例的半导体结构的截面结构示意图；
图21是制作图20中的半导体结构流程对应的中间结构示意图。
为方便理解本发明，以下列出本发明中出现的所有附图标记：
半导体结构1、2、3、4、5、6、7、8        衬底10
发光单元11                              N型半导体层11a
P型半导体层11b                          发光层11c
第一预定区域1a                          第二预定区域1b
第三预定区域1c                          凹槽1v
连接柱12                                主干12a
分支12b                                 第一主干12c
第二主干12d                             主干区域1d
分支区域1e                              第一主干区域1f
第二主干区域1g                          N电极13
P电极14                                 电流扩散层15
光反射层16                              保护层17
绝缘层18
具体实施方式
为使本发明的上述目的、特征和优点能够更为明显易懂，下面结合附图对本发明的具体实施例做详细的说明。
图1是本发明第一实施例的半导体结构的制作方法的流程图；图2至4 是图1中的流程对应的中间结构示意图。图5是本发明第一实施例的半导体结构的俯视图；图6是沿着图5中的CC线的剖视图；图7是沿着图5中的DD线的剖视图。
首先，参照图1中的步骤S1、图2与图3所示，提供衬底10，在衬底10上依次形成第一导电类型的半导体层、发光层11c与第二导电类型的半导体层，第一导电类型为N型与P型中的一种，第二导电类型为N型与P型中的另一种。其中，图3是沿着图2中的AA线的剖视图。
衬底10的材料可以为蓝宝石、碳化硅、硅、金刚石、GaN或蓝宝石、碳化硅、硅、金刚石中的一种及其上的GaN。
第一导电类型的半导体层可以为N型半导体层11a，其材料例如可以为N型Ⅲ族氮化物材料。N型掺杂元素可以包括Si、Ge、Sn、Se或Te中的至少一种。Ⅲ族氮化物材料可以包括GaN、AlGaN、InGaN、AlInGaN中的任一种或组合。
N型半导体层11a的形成工艺可以包括：原子层沉积法(ALD，Atomic layer deposition)、或化学气相沉积法(CVD，Chemical Vapor Deposition)、或分子束外延生长法(MBE，Molecular Beam Epitaxy)、或等离子体增强化学气相沉积法(PECVD，Plasma Enhanced Chemical Vapor Deposition)、或低压化学蒸发沉积法(LPCVD，Low Pressure Chemical Vapor Deposition)，或金属有机化合物化学气相沉积法(MOCVD，Metal-Organic Chemical Vapor Deposition)、或其组合方式。
N型半导体层11a可以包括一层或多层。
发光层11c可以包括单量子阱结构、多量子阱(MQW)结构、量子线结构和量子点结构中的至少一种。发光层11c可以包括Ⅲ族氮化物材料形成的阱层和势垒层。Ⅲ族氮化物材料可以包括GaN、AlGaN、InGaN、AlInGaN中的任一种或组合。
例如，阱层可以包括Al xGa 1-xN层，其中x为Al元素的质量占Al元素与Ga元素质量之和的百分比，1≥x≥0；和/或势垒层可以包括Al yGa 1-yN层，其中y为Al元素的质量占Al元素与Ga元素质量之和的百分比，1≥y≥0。阱层的禁带宽度小于势垒层的禁带宽度。
阱层和/或势垒层的形成工艺可以参照N型半导体层11a的形成工艺。
阱层和/或势垒层可以掺杂Al，也可以不掺杂Al。不掺杂Al可以提高自身结晶质量，但是掺杂Al可以降低自身电阻。
阱层和势垒层多层交替可以形成多量子阱结构，进一步提高发光效率。
第二导电类型的半导体层可以为P型半导体层11b，例如P型Ⅲ族氮化物材料。P型掺杂元素可以包括Mg、Zn、Ca、Sr或Ba中的至少一种。Ⅲ族氮化物材料可以包括GaN、AlGaN、InGaN、AlInGaN中的任一种或组合。
P型半导体层11b的形成工艺可以参照N型半导体层11a的形成工艺。
P型半导体层11b可以包括一层或多层。
一些实施例中，也可以P型半导体层11b靠近衬底10，N型半导体层11a远离衬底10。
接着，参照图1中的步骤S2、图2至图4所示，去除第一预定区域1a的第二导电类型的半导体层、发光层11c与第一导电类型的半导体层形成凹槽1v，保留第二预定区域1b与第三预定区域1c的第二导电类型的半导体层、发光层11c与第一导电类型的半导体层，第二预定区域1b的第二导电类型的半导体层、发光层11c与第一导电类型的半导体层形成阵列式排布的发光单元11，第三预定区域1c的第二导电类型的半导体层、发光层11c与第一导电类型的半导体层形成连接相邻发光单元11的连接柱12；在行方向上，第三预定区域1c的宽度小于第二预定区域1b的宽度；在列方向上，第三预定区域1c的宽度小于第二预定区域1b的宽度。其中，图4是沿着图2中的BB线的剖视图。
一些实施例中，去除第一预定区域1a的第二导电类型的半导体层、发光层11c与第一导电类型的半导体层采用干法刻蚀实现。干法刻蚀的刻蚀气体可以包括：BCl 3与Cl 2的混合气体。
一些实施例中，去除第一预定区域1a的第二导电类型的半导体层、发光层11c与第一导电类型的半导体层采用湿法刻蚀实现。湿法刻蚀溶液例如为KOH溶液，它在N面上是腐蚀性的，但在Ga面上是非腐蚀性的。因而，可以通过生长工艺控制第二导电类型的半导体层、发光层11c与第一导电类型的半导体层的N面朝上。第二导电类型的半导体层、发光层11c与第一导电类型的半导体层的N面朝上是指：以平行于C轴([0001]晶向)的Ga-N键作为参照，每一个Ga-N键中的N原子更远离半导体衬底10。可以理解的是，此时，第二导电类型的半导体层、发光层11c与第一导电类型的半导体层的下表面为Ga面。
之后，参照图1中的步骤S3、图2至图7所示，自凹槽1v湿法腐蚀去除衬底10，湿法腐蚀使用的腐蚀液对衬底10在水平面方向的去除速率大于在厚度方向的去除速率。其中，图5是去除衬底后的半导体结构的俯视图；图6是沿着图5中的CC线的剖视图；图7是沿着图5中的DD线的剖视图。
当衬底10的材料为单晶硅时，水平面的一个晶向可以为[110]，厚度方向的晶向可以为[111]，腐蚀液可以为氢氟酸、硝酸、乙酸的混和液。由于腐蚀液在[110]晶向的去除速率大于在[110]晶向的去除速率，因而，硅衬底10无需全部腐蚀即可脱离半导体结构1，加快了剥离衬底10的速率。
对于其它的衬底10材料，例如蓝宝石、碳化硅、金刚石或GaN，也可采用针对性的溶液进行剥离。
参照图5所示，本发明第一实施例的半导体结构1包括：
阵列式排布的发光单元11，相邻发光单元11之间通过连接柱12连接在一起，在行方向上，连接柱12的宽度w1小于发光单元11的宽度W1；在 列方向上，连接柱12的宽度w2小于发光单元11的宽度W2。
半导体结构1中，多个小尺寸的发光单元11通过连接柱12连接在一起，可方便转移。半导体结构1在使用时，可在连接柱12处进行切割，即可形成各个分立的发光单元11。
图8是本发明第二实施例的半导体结构的俯视图；图9是沿着图8中的EE线的剖视图。
参照图8与图9所示，本实施例二的半导体结构2与实施例一的半导体结构1大致相同，区别仅在于：连接柱12与第一导电类型的半导体层位于同层。
换言之，当N型半导体层11a靠近衬底10时，连接柱12与N型半导体层11a位于同层；当P型半导体层11b靠近衬底10时，连接柱12与P型半导体层11b位于同层。
连接柱12的厚度较薄，可方便后续切割形成各个分立的发光单元11。
对应地，本实施例二的半导体结构2的制作方法与实施例一的半导体结构1的制作方法大致相同，区别仅在于：步骤S2中，去除第一预定区域1a的第二导电类型的半导体层、发光层11c与第一导电类型的半导体层时，还去除第三预定区域1c的第二导电类型的半导体层与发光层11c，保留第一导电类型的半导体层形成连接柱12。
去除第一预定区域1a的第二导电类型的半导体层、发光层11c与第一导电类型的半导体层，与去除第三预定区域1c的第二导电类型的半导体层与发光层11c可以在不同工序中进行。换言之，可以采用不同图案的掩膜层分别进行干法刻蚀或湿法刻蚀。
图10是本发明第三实施例的半导体结构的俯视图。图11是制作图10中的半导体结构流程对应的中间结构示意图。
参照图10所示，本实施例三的半导体结构3与实施例一的半导体结构 1大致相同，区别仅在于：连接柱12包括主干12a与分支12b，主干12a包括沿行方向延伸的第一主干12c和沿列方向延伸的第二主干12d，分支12b连接第一主干12c与发光单元11，或连接第二主干12d与发光单元11。
一些实施例中，主干12a可以包括沿行方向延伸的第一主干12c，将一行发光单元11连接在一起；或主干12a可以包括沿列方向延伸的第二主干12d，将一列发光单元11连接在一起。
主干12a可方便辨识各发光单元11的排布方式，且能提高半导体结构3中各发光单元11之间的受力均匀性。
对应地，参照图11所示，本实施例三的半导体结构3的制作方法与实施例一、二的半导体结构1、2的制作方法大致相同，区别仅在于：步骤S2中，第三预定区域1c包括主干区域1d与分支区域1e，主干区域1d包括沿行方向延伸的第一主干区域1f和/或沿列方向延伸的第二主干区域1g，分支区域1e连接第一主干区域1f与第二预定区域1b，或连接第二主干区域1g与第二预定区域1b。
图12是本发明第四实施例的半导体结构的俯视图。
参照图12所示，本实施例四的半导体结构4与实施例二的半导体结构2大致相同，区别仅在于：连接柱12包括主干12a与分支12b，主干12a包括沿行方向延伸的第一主干12c和沿列方向延伸的第二主干12d，分支12b连接第一主干12c与发光单元11，或连接第二主干12d与发光单元11。
一些实施例中，主干12a可以包括沿行方向延伸的第一主干12c，将一行发光单元11连接在一起；或主干12a可以包括沿列方向延伸的第二主干12d，将一列发光单元11连接在一起。
图13是本发明第五实施例的半导体结构的截面结构示意图。
参照图13所示，本实施例五的半导体结构5与实施例一、二、三、四的半导体结构1、2、3、4大致相同，区别仅在于：发光单元11还包括P电 极14与N电极13，P电极14与P型半导体层11b电连接，N电极13与N型半导体层11a电连接。
P电极14与N电极13的材质可以为金属，例如Ti/Al/Ni/Au、Ni/Au等现有的导电材质。
P电极14与P型半导体层11b之间形成欧姆接触，N电极13与N型半导体层11a之间也形成欧姆接触。
半导体结构5切割后，形成各个分立的LED结构。
对应地，本实施例五的半导体结构5的制作方法与实施例一、二、三、四的半导体结构1、2、3、4的制作方法大致相同，区别仅在于：步骤S1与步骤S2之间或步骤S2与步骤S3之间进行：去除第一预定区域1a中部分区域的第二导电类型的半导体层与发光层11c，暴露第一导电类型的半导体层的部分区域，在所暴露的第一导电类型的半导体层上形成第一电极，在第二导电类型的半导体层上形成第二电极。
当第一导电类型的半导体层为N型半导体层11a时，第一电极为N电极13；第二导电类型的半导体层为P型半导体层11b时，第二电极为P电极14。
当第一导电类型的半导体层为P型半导体层11b时，第一电极为P电极14；第二导电类型的半导体层为N型半导体层11a时，第二电极为N电极13。
第一电极与第二电极的形成方法可以包括：先采用物理气相沉积法或化学气相沉积法形成一整面金属层，后对金属层进行图形化。
图14是本发明第六实施例的半导体结构的截面结构示意图。
参照图14所示，本实施例六的半导体结构6与实施例一、二、三、四、五的半导体结构1、2、3、4、5大致相同，区别仅在于：发光单元11还包括电流扩散层15，电流扩散层15位于P型半导体层11b远离发光层11c的一侧。 电流扩散层15可提高P型半导体层11b的导电性能。
电流扩散层15的材料可以为ITO。
对应地，本实施例六的半导体结构6的制作方法与实施例五的半导体结构5的制作方法大致相同。
针对第一类型的半导体层为N型半导体层11a，第二类型的半导体层为P型半导体层11b的情况，半导体结构6与半导体结构5的制作方法的区别仅在于：形成第二电极前，先在第二导电类型的半导体层上形成电流扩散层15。
针对第一类型的半导体层为P型半导体层11b，第二类型的半导体层为N型半导体层11a的情况，半导体结构6与半导体结构5的制作方法的区别仅在于：形成第一电极前，先在所暴露的第一导电类型的半导体层上形成电流扩散层15。
图15是本发明第七实施例的半导体结构的截面结构示意图。图16至图19是制作图15中的半导体结构流程对应的中间结构示意图。
参照图15所示，本实施例七的半导体结构7与实施例六的半导体结构6大致相同，区别仅在于：电流扩散层15远离发光层11c的一侧具有光反射层16，电流扩散层15与光反射层16包覆在保护层17内；保护层17、未覆盖保护层17的P型半导体层11b的上表面、P型半导体层11b与发光层11c的侧壁、以及N型半导体层11a的上表面覆盖有绝缘层18；绝缘层18内具有暴露P型半导体层11b上的保护层17与N型半导体层11a的部分区域的开口，以对应形成P电极14与N电极13。
光反射层16的材料可以为银，用于将发光层11c发出的光反射入发光层11c，从而从N型半导体层11a侧出光。
保护层17的材料可以为钛或铜，一方面防止光反射层16的银氧化，另一方面防止电流扩散层15侧出光。
对应地，本实施例七的半导体结构7的制作方法与实施例六的半导体结构6的制作方法大致相同。
针对第一类型的半导体层为N型半导体层11a，第二类型的半导体层为P型半导体层11b的情况，半导体结构7与半导体结构6的制作方法的区别仅在于：步骤S1与步骤S2之间或步骤S2与步骤S3之间进行：在电流扩散层15远离发光层11c的一侧形成光反射层16；形成包覆电流扩散层15与光反射层16的保护层17；在保护层17、未覆盖保护层17的P型半导体层11b的上表面、P型半导体层11b与发光层11c的侧壁、以及所暴露的N型半导体层11a的上表面形成绝缘层18；在绝缘层18内形成分别暴露P型半导体层11b上的保护层17与N型半导体层11a的部分区域的开口，在开口内以及开口外的绝缘层18上对应形成P电极14与N电极13。
一个实施例中，参照图16至图18所示，P电极14与N电极13的形成在步骤S1与步骤S2之间进行。
具体地，参照图16所示，先去除第一预定区域1a中部分区域的P型半导体层11b与发光层11c，暴露N型半导体层11a的部分区域；接着通过物理气相沉积法或化学气相沉积法在P型半导体层11b、P型半导体层11b与发光层11c的侧壁、以及所暴露的N型半导体层11a上形成一电流扩散材料层，图形化电流扩散材料层，保留P型半导体层11b上部分区域的电流扩散材料层形成电流扩散层15；之后在N型半导体层11a上形成第一流平层，第一流平层的上表面与电流扩散层15的上表面齐平。
第一流平层可以采用流体性较佳的有机材料，例如光刻胶。
参照图17所示，采用溅射法或无极电镀法在第一流平层的上表面与电流扩散层15的上表面形成以一光反射层16；撕除第一流平层，第一流平层上的光反射层16被一并带离。
继续参照图17所示，在N型半导体层11a上形成第二流平层，第二流 平层的上表面与光反射层16的上表面齐平；图形化第二流平层，在电流扩散层15与光反射层16的侧壁形成间隙；结合图18所示，采用溅射法或无极电镀法在第二流平层的上表面、光反射层16的上表面以及间隙形成一保护层17；撕除第二流平层，第二流平层上的保护层17被一并带离。
参照图19所示，在保护层17、未覆盖保护层17的P型半导体层11b的上表面、P型半导体层11b与发光层11c的侧壁、以及所暴露的N型半导体层11a的上表面形成绝缘层18；在绝缘层18内形成分别暴露P型半导体层11b上的保护层17与N型半导体层11a的部分区域的开口，在开口内以及开口外的绝缘层18上对应形成P电极14与N电极13。可以在形成P电极14与N电极13后，再去除第一预定区域1a的P型半导体层11b、发光层11c、以及N型半导体层11a，形成凹槽1v；也可以在去除第一预定区域1a的P型半导体层11b、发光层11c、以及N型半导体层11a，形成凹槽1v后，再形成绝缘层18、P电极14以及N电极13。
针对第一类型的半导体层为P型半导体层11b，第二类型的半导体层为N型半导体层11a的情况，半导体结构7与半导体结构6的制作方法的区别仅在于：步骤S1与步骤S2之间或步骤S2与步骤S3之间进行：在N型半导体层11a上形成光反射层16；形成包覆光反射层16的保护层17；在保护层17、未覆盖保护层17的N型半导体层11a、N型半导体层11a与发光层11c的侧壁、电流扩散层15、以及未设置电流扩散层15的P型半导体层11b的上表面形成绝缘层18；在绝缘层18内形成分别暴露N型半导体层11a上的保护层17与P型半导体层11b上的电流扩散层15的部分区域的开口，在开口内以及开口外的绝缘层18上对应形成N电极13与P电极14。
图20是本发明第八实施例的半导体结构的截面结构示意图。图21是制作图20中的半导体结构流程对应的中间结构示意图。
参照图20与图21所示，本实施例八的半导体结构8及其制作方法与实施例七的半导体结构7及其制作方法大致相同，区别仅在于：发光单元11 包括两个发光子单元，相邻发光子单元的第一类型的半导体层上第一电极连接在一起。
一些实施例中，半导体结构8切割时，可沿第一电极的中部切割，使得每个发光子单元具有一个第一电极。
第一类型的半导体层为N型半导体层11a时，第一电极为N电极13。第一类型的半导体层为P型半导体层11b时，第一电极为P电极14。
上述实施例五、六、七、八的半导体结构5、6、7、8中，第一电极都通过去除部分区域的第二类型的半导体层与发光层11c，暴露第一类型的半导体层的部分区域形成。一些实施例中，还可在第一类型的半导体层内形成多个电连接结构，以在第二类型的半导体层远离发光层11c的一侧形成第一电极。
一些实施例中，去除衬底10后，还可在第一类型的半导体层远离发光层11c的一侧形成第一电极。
虽然本发明披露如上，但本发明并非限定于此。任何本领域技术人员，在不脱离本发明的精神和范围内，均可作各种更动与修改，因此本发明的保护范围应当以权利要求所限定的范围为准。

Claims (20)

  1. 一种半导体结构，其特征在于，包括：
    阵列式排布的发光单元(11)，相邻所述发光单元(11)之间通过连接柱(12)连接在一起，在行方向上，所述连接柱(12)的宽度小于所述发光单元(11)的宽度；在列方向上，所述连接柱(12)的宽度小于所述发光单元(11)的宽度。
  2. 根据权利要求1所述的半导体结构，其特征在于，所述连接柱(12)包括主干(12a)与分支(12b)，所述主干(12a)包括沿行方向延伸的第一主干(12c)和/或沿列方向延伸的第二主干(12d)，所述分支(12b)连接所述第一主干(12c)与所述发光单元(11)，或连接所述第二主干(12d)与所述发光单元(11)。
  3. 根据权利要求1或2所述的半导体结构，其特征在于，所述发光单元(11)包括N型半导体层(11a)、P型半导体层(11b)以及位于所述N型半导体层(11a)与所述P型半导体层(11b)之间的发光层(11c)，所述连接柱(12)与所述N型半导体层(11a)位于同层或所述连接柱(12)与所述P型半导体层(11b)位于同层。
  4. 根据权利要求3所述的半导体结构，其特征在于，所述发光单元(11)还包括P电极(14)与N电极(13)，所述P电极(14)与所述P型半导体层(11b)电连接，所述N电极(13)与所述N型半导体层(11a)电连接。
  5. 根据权利要求3所述的半导体结构，其特征在于，所述P电极(14)位于所述P型半导体层(11b)远离所述发光层(11c)的一侧，所述N电极(13)位于所述N型半导体层(11a)远离所述发光层(11c)的一侧；或所述P电极(14)与所述N电极(13)都位于所述P型半导体层(11b)远离所述发光层(11c)的一侧；或所述P电极(14)与所述N电极(13)都位于所述N型半导体层(11a)远离所述发光层(11c)的一侧。
  6. 根据权利要求3所述的半导体结构，其特征在于，所述发光单元(11) 还包括电流扩散层(15)，所述电流扩散层(15)位于所述P型半导体层(11b)远离所述发光层(11c)的一侧。
  7. 根据权利要求3所述的半导体结构，其特征在于，所述发光单元(11)还包括光反射层(16)，所述光反射层(16)位于所述N型半导体层(11a)远离所述发光层(11c)的一侧或位于所述P型半导体层(11b)远离所述发光层(11c)的一侧。
  8. 根据权利要求3所述的半导体结构，其特征在于，所述发光层(11c)的材料包括单量子阱材料或多量子阱材料。
  9. 根据权利要求1所述的半导体结构，其特征在于，所述发光单元(11)包括一个发光子单元或多个发光子单元。
  10. 根据权利要求1所述的半导体结构，其特征在于，所述发光单元(11)的材料包括Ⅲ族氮化物材料。
  11. 一种半导体结构的制作方法，其特征在于，包括：
    提供衬底(10)，在所述衬底(10)上依次形成第一导电类型的半导体层、发光层(11c)与第二导电类型的半导体层，所述第一导电类型为N型与P型中的一种，所述第二导电类型为N型与P型中的另一种；
    去除第一预定区域(1a)的所述第二导电类型的半导体层、所述发光层(11c)与所述第一导电类型的半导体层形成凹槽(1v)，保留第二预定区域(1b)与第三预定区域(1c)的所述第二导电类型的半导体层、所述发光层(11c)与所述第一导电类型的半导体层，所述第二预定区域(1b)的所述第二导电类型的半导体层、所述发光层(11c)与所述第一导电类型的半导体层形成阵列式排布的发光单元(11)，所述第三预定区域(1c)的所述第二导电类型的半导体层、所述发光层(11c)与所述第一导电类型的半导体层形成连接相邻所述发光单元(11)的连接柱(12)；在行方向上，所述第三预定区域(1c)的宽度小于所述第二预定区域(1b)的宽度；在列方向上，所述第三预定区域(1c)的宽度小于所述第二预定区域(1b)的宽度；
    自所述凹槽(1v)湿法腐蚀去除所述衬底(10)，所述湿法腐蚀使用的腐 蚀液对所述衬底(10)在水平面方向的去除速率大于在厚度方向的去除速率。
  12. 根据权利要求11所述的半导体结构的制作方法，其特征在于，所述第三预定区域(1c)包括主干区域(1d)与分支区域(1e)，所述主干区域(1d)包括沿行方向延伸的第一主干区域(1f)和/或沿列方向延伸的第二主干区域(1g)，所述分支区域(1e)连接所述第一主干区域(1f)与所述第二预定区域(1b)，或连接所述第二主干区域(1g)与所述第二预定区域(1b)。
  13. 根据权利要求11所述的半导体结构的制作方法，其特征在于，去除第一预定区域(1a)的所述第二导电类型的半导体层、所述发光层(11c)与所述第一导电类型的半导体层时，还去除所述第三预定区域(1c)的所述第二导电类型的半导体层与所述发光层(11c)，保留所述第一导电类型的半导体层形成所述连接柱(12)。
  14. 根据权利要求11或12或13所述的半导体结构的制作方法，其特征在于，形成第一导电类型的半导体层、发光层(11c)与第二导电类型的半导体层后，去除第一预定区域(1a)的所述第二导电类型的半导体层、所述发光层(11c)与所述第一导电类型的半导体层形成凹槽(1v)前，或去除第一预定区域(1a)的所述第二导电类型的半导体层、所述发光层(11c)与所述第一导电类型的半导体层形成凹槽(1v)后，湿法腐蚀去除所述衬底(10)前，还包括：去除所述第一预定区域(1a)中部分区域的所述第二导电类型的半导体层与所述发光层(11c)，暴露所述第一导电类型的半导体层的部分区域；在所暴露的所述第一导电类型的半导体层上形成第一电极，在所述第二导电类型的半导体层上形成第二电极。
  15. 根据权利要求14所述的半导体结构的制作方法，其特征在于，若所述第一导电类型的半导体层为P型半导体层(11b)，形成第一电极前，先在所暴露的所述第一导电类型的半导体层上形成电流扩散层(15)；若所述第二导电类型的半导体层为P型半导体层(11b)，形成第二电极前，先在所述第二导电类型的半导体层上形成电流扩散层(15)。
  16. 根据权利要求11或12或13所述的半导体结构的制作方法，其特征 在于，在所述衬底(10)上形成第一导电类型的半导体层前，先形成光反射层(16)；或形成第二导电类型的半导体层后，还形成光反射层(16)。
  17. 根据权利要求11或12或13所述的半导体结构的制作方法，其特征在于，所述发光层(11c)的材料包括单量子阱材料或多量子阱材料。
  18. 根据权利要求11或12或13所述的半导体结构的制作方法，其特征在于，所述发光单元(11)包括一个发光子单元或多个发光子单元。
  19. 根据权利要求11或12或13所述的半导体结构的制作方法，其特征在于，所述第一导电类型的半导体层、和/或所述发光层(11c)、和/或所述第二导电类型的半导体层的材料包括Ⅲ族氮化物材料。
  20. 根据权利要求11所述的半导体结构的制作方法，其特征在于，所述衬底(10)的材料为单晶硅，所述腐蚀液为氢氟酸、硝酸、乙酸的混和液。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130238A (zh) * 2010-12-29 2011-07-20 映瑞光电科技(上海)有限公司 蓝宝石衬底led芯片的切割方法
JP2014090011A (ja) * 2012-10-29 2014-05-15 Mitsuboshi Diamond Industrial Co Ltd Ｌｅｄパターン付き基板の加工方法
US20160240732A1 (en) * 2015-02-17 2016-08-18 Genesis Photonics Inc. Light emitting component
CN109671822A (zh) * 2019-01-10 2019-04-23 佛山市国星半导体技术有限公司 一种防激光切割损伤的led晶圆及其制作方法、切割方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102019262B1 (ko) * 2016-11-29 2019-11-04 고려대학교 산학협력단 발광 소자 디스플레이 장치 및 이의 제조 방법
TWI721340B (zh) * 2018-12-04 2021-03-11 榮創能源科技股份有限公司 發光二極體及其製作方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102130238A (zh) * 2010-12-29 2011-07-20 映瑞光电科技(上海)有限公司 蓝宝石衬底led芯片的切割方法
JP2014090011A (ja) * 2012-10-29 2014-05-15 Mitsuboshi Diamond Industrial Co Ltd Ｌｅｄパターン付き基板の加工方法
US20160240732A1 (en) * 2015-02-17 2016-08-18 Genesis Photonics Inc. Light emitting component
CN109671822A (zh) * 2019-01-10 2019-04-23 佛山市国星半导体技术有限公司 一种防激光切割损伤的led晶圆及其制作方法、切割方法

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