WO2022007093A1 - 液晶显示器及其漏电补偿方法 - Google Patents

液晶显示器及其漏电补偿方法 Download PDF

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Publication number
WO2022007093A1
WO2022007093A1 PCT/CN2020/107744 CN2020107744W WO2022007093A1 WO 2022007093 A1 WO2022007093 A1 WO 2022007093A1 CN 2020107744 W CN2020107744 W CN 2020107744W WO 2022007093 A1 WO2022007093 A1 WO 2022007093A1
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Prior art keywords
thin film
gate driver
refresh rate
liquid crystal
crystal display
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PCT/CN2020/107744
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English (en)
French (fr)
Inventor
廖文武
陈明暐
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深圳市华星光电半导体显示技术有限公司
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Priority to US17/042,966 priority Critical patent/US11961449B2/en
Publication of WO2022007093A1 publication Critical patent/WO2022007093A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G09G3/2096—Details of the interface to the display terminal specific for a flat panel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3622—Control of matrices with row and column drivers using a passive matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0209—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display
    • G09G2320/0214—Crosstalk reduction, i.e. to reduce direct or indirect influences of signals directed to a certain pixel of the displayed image on other pixels of said image, inclusive of influences affecting pixels in different frames or fields or sub-images which constitute a same image, e.g. left and right images of a stereoscopic display with crosstalk due to leakage current of pixel switch in active matrix panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the present invention relates to a liquid crystal display and a leakage compensation method thereof. Specifically, the liquid crystal display of the present invention compensates for the leakage problem caused by the long vertical blank interval at low frequencies by increasing the charging time of each row of thin film transistors in the thin film transistor array.
  • the refresh frequency can be dynamically adjusted to improve the smoothness of the picture.
  • the charging time of each row of thin film transistors at a low refresh rate is the same as the charging time of each row of thin film transistors at a high refresh rate, so the vertical blanking interval T2 at a low refresh rate is higher than that at a higher refresh rate.
  • the vertical blanking interval T1 is long, as shown in Figure 1.
  • the display panel dynamically adjusts the refresh rate, after switching from high refresh rate to low refresh rate, the vertical blanking interval is long, so that the voltage of the thin film transistor must be maintained for a long time, causing serious leakage problems, resulting in low refresh rate and high refresh rate. Excessive panel brightness difference between refresh rates and panel flickering issues.
  • the purpose of the present invention is to provide a leakage compensation mechanism, which adjusts the current refresh rate of the liquid crystal display according to the current frame rate obtained from the graphics processor by the timing controller in the liquid crystal display, and when the current refresh rate of the liquid crystal display is less than the critical frequency , the gate driver is controlled to increase the charging time of the thin film transistor.
  • the present invention can solve the problem of serious leakage of thin film transistor caused by long vertical blanking interval, and the large difference in brightness between low refresh rate and high refresh rate of liquid crystal display, without modifying the circuit design of the liquid crystal display. flickering problem.
  • the present invention discloses a liquid crystal display including a thin film transistor array, a gate driver, a source driver and a timing controller.
  • the thin film transistor array is composed of a plurality of thin film transistors.
  • the gate driver is used for providing scan signals.
  • the source driver is used for providing data signals.
  • the timing controller is electrically connected to the gate driver and the source driver, and is used for adjusting the current refresh rate according to the current frame rate; and when the current refresh rate is less than the critical frequency, transmitting a control signal to the and the gate driver increases the charging time of the plurality of thin film transistors according to the control signal.
  • the present invention further discloses a leakage compensation method for a liquid crystal display.
  • the liquid crystal display includes a thin film transistor array, a gate driver, a source driver and a timing controller.
  • the thin film transistor array is composed of a plurality of thin film transistors.
  • the gate driver is used for providing scan signals.
  • the source driver is used for providing data signals.
  • the leakage compensation method is executed by the timing controller, and includes: adjusting the current refresh rate according to the current frame rate; and when the current refresh rate is less than a critical frequency, transmitting a control signal to the gate driver to make the gate
  • the pole driver increases the charging time of the plurality of thin film transistors according to the control signal.
  • the present invention increases the conduction time of the thin film transistor when the liquid crystal display switches from a high refresh rate to a low refresh rate, and can solve the problem of serious leakage of the thin film transistor caused by a long vertical blanking interval without modifying the circuit design of the liquid crystal display. , and the problem of flickering caused by the large difference in brightness between the low refresh rate and the high refresh rate of the liquid crystal display.
  • FIG. 1 is a schematic diagram illustrating the variation of the length of the vertical blanking interval of the liquid crystal display in the prior art at different refresh rates.
  • Figure 2 depicts a schematic diagram of a liquid crystal display of the present invention.
  • FIG. 3 depicts an implementation scenario between a liquid crystal display and a graphics processor of the present invention.
  • FIG. 4 is a flow chart of the leakage compensation method of the present invention.
  • FIG. 5 is a flow chart of the leakage compensation method of the present invention.
  • FIGS. 2-3 depicts a schematic diagram of a liquid crystal display of the present invention.
  • FIG. 3 depicts an implementation scenario between a liquid crystal display and a graphics processor of the present invention.
  • the liquid crystal display 1 includes a thin film transistor array 2 , a gate driver 3 , a source driver 4 and a timing controller 5 .
  • the thin film transistor array 2 is composed of a plurality of thin film transistors T1-1 to Tm-n.
  • the gates of the thin film transistors T1-1 to Tm-n are electrically connected to the gate driver 3, so that the gate driver 3 provides scan signals for the thin film transistors in each row row by row to turn on the thin film transistors in each row.
  • the sources of the respective thin film transistors T1-1 to Tm-n are electrically connected to the source driver 4, so that the source driver 4 provides data signals after the gate driver 3 turns on the thin film transistors of each row, so as to simultaneously control the conduction.
  • the liquid crystal capacitor and the storage capacitor coupled to the drain of the pass-through thin film transistor are charged.
  • the gate driver 3 starts scanning from the thin film transistors T1-1, T1-2, T1-3 to T1-n in the first row of the thin film transistor array 2, and the source driver 4 is turned on when the gate driver 3 is turned on.
  • the thin film transistors T1-1, T1-2, T1-3 ⁇ T1-n in one row the thin film transistors T1-1, T1-2, T1-3 ⁇ T1-n in the first row are charged at the same time.
  • the gate driver 3 scans the thin film transistors T2-1 to T2-n in the second row.
  • the source driver 4 simultaneously scans the thin film transistors T2-1 to T2-n in the second row.
  • the gate driver 3 scans the thin film transistors Tm-1, Tm-2, Tm-3 to Tm-n in the m-th row in sequence, so that the source driver 4 sequentially charges the thin-film transistors in each row until the m-th row is charged. After the thin film transistors Tm-1, Tm-2, Tm-3 to Tm-n are charged, a screen refresh of the liquid crystal display 1 is completed.
  • the timing controller 5 is electrically connected to the gate driver 3 and the source driver 4, and is used to transmit the gate start pulse and the gate clock pulse to the gate driver 3, so that the gate driver 3 generates the gate driver 3 according to the gate clock pulse for conduction.
  • the scan signal of each row of thin film transistors is passed.
  • the timing controller 5 is also used to transmit the gate-source start pulse and the source clock pulse to the source driver 4, so that the source driver 4 generates a data signal according to the source clock pulse, and the gate driver 3 turns on a plurality of thin film transistors During the period from T1-1 to Tm-n, the plurality of thin film transistors T1-1 to Tm-n are charged.
  • the timing controller 5 adjusts the current refresh rate according to the current frame rate.
  • the timing controller 5 determines that the current refresh rate is lower than the critical frequency, it transmits a control signal to the gate driver 3 so that the gate driver 3 increases the charging time of the plurality of thin film transistors T1-1 ⁇ Tm-n according to the control signal.
  • the frame rate is the rate at which the graphics processor 6 in the display card generates a frame
  • the refresh rate is the gate driver 3 per second from the thin film transistors T1-1, The number of times that T1-2, T1-3 ⁇ T1-n start to scan the thin film transistors Tm-1, Tm-2, Tm-3 ⁇ Tm-n in the mth row, that is, the frequency of the screen update of the LCD 1.
  • the gate driver 3 scans the thin film transistors Tm-1, Tm-2, Tm-3 to Tm-n in the mth row
  • the interval at which ⁇ T1-n starts scanning is called the vertical blank interval.
  • the liquid crystal display 1 of the present invention supports the freesync technology and can dynamically adjust the refresh rate. Therefore, after the timing controller 5 obtains the current frame rate from the graphics processor 6, the current refresh rate of the liquid crystal display 1 can be adjusted to be the same as the current refresh rate. The frame rate is the same. In order to avoid serious leakage problems caused by the increase of the vertical blanking interval of the liquid crystal display 1 when the refresh rate of the liquid crystal display 1 is low, the timing controller 5 of the present invention determines that the current refresh rate of the liquid crystal display 1 is less than the critical frequency, and can The gate driver 3 is controlled to increase the charging time of the thin film transistors T1-1 to Tm-n.
  • the charging time of each row of thin film transistors starts from the rising edge of the scan signal and ends at the falling edge of the gate clock pulse corresponding to the scan signal. Since the gate driver 3 generates a scan signal for turning on the thin film transistors of each row according to the gate clock pulse provided by the timing controller 5, the timing controller 5 can pass the control signal when judging that the current refresh rate is less than the critical frequency, The gate driver 3 is made to advance the clock of the scan signal to increase the charging time of the thin film transistor.
  • the timing controller 5 adjusts the current refresh rate of the liquid crystal display 1 from 120 Hz to 60 Hz.
  • the timing controller 5 further determines that when the current refresh rate of the liquid crystal display 1 is less than the critical frequency of 70 Hz, the timing controller 5 transmits a control signal to the gate driver 3, so that the gate driver 3 changes the time of each line of the scanning signal according to the control signal.
  • the pulse advance is made to increase the charging time of the thin film transistors T1-1 ⁇ Tm-n from 2 ⁇ s to 4 ⁇ s. Accordingly, the present invention can solve the problem of uneven brightness and flickering of the liquid crystal display 1 caused by serious leakage of the thin film transistors T1-1 to Tm-n during the vertical blanking interval.
  • the timing controller 5 also calculates the vertical blanking interval, and transmits the control signal to the gate driver 3 when the vertical blanking interval is greater than the critical time. Specifically, the timing controller 5 not only uses the current refresh rate of the liquid crystal display 1 as the basis for controlling the gate driver 3 to increase the charging time of the thin film transistor, but also determines whether to transmit the control signal to the gate according to the vertical blanking interval. Pole drive 3. When the current refresh rate of the liquid crystal display 1 is less than the critical frequency and the vertical blanking interval is greater than the critical time, the timing controller 5 transmits the control signal to the gate driver 3 . It should be noted that those skilled in the art can understand the calculation method of the above-mentioned vertical blanking interval, so it is not repeated here.
  • the timing controller 5 calculates the leakage voltages of the plurality of thin film transistors at the current refresh rate, and determines the charging time of the thin film transistors according to the leakage voltages.
  • the timing controller 5 calculates the gray-scale voltage maintenance time of the plurality of thin film transistors at the current refresh rate, and determines the charging time of the thin film transistors according to the gray-scale voltage maintenance time.
  • the second embodiment of the present invention describes a leakage compensation method, the flowchart of which is shown in FIG. 4 .
  • the leakage compensation method is suitable for a liquid crystal display, such as the liquid crystal display 1 of the foregoing embodiment.
  • the liquid crystal display includes a liquid crystal display 1 including a thin film transistor array, a gate driver, a source driver and a timing controller.
  • the thin film transistor array is composed of a plurality of thin film transistors.
  • the gate of each of the plurality of thin film transistors is electrically connected to a gate driver.
  • the source of each of the plurality of thin film transistors is electrically connected to a source driver.
  • the gate driver is used for providing scan signals to turn on the thin film transistors of each row.
  • the source driver is used to provide data signals to charge the thin film transistors that are turned on in each row.
  • the leakage compensation method is executed by the timing controller, and the steps included are described as follows.
  • step S402 the current refresh rate is adjusted according to the current frame rate.
  • step S404 it is determined whether the current refresh rate is less than the critical frequency.
  • step S406 is executed to transmit a control signal to the gate driver.
  • the gate driver is made to increase the charging time of the plurality of thin film transistors according to the control signal.
  • step S402 is performed again.
  • the current refresh rate is the same as the current frame rate.
  • step S502 the timing controller further executes step S502 to calculate the vertical blanking interval.
  • step S504 is executed to determine whether the vertical blanking interval is greater than the critical time.
  • step S406 is executed to transmit the control signal to the gate driver.
  • step S502 is performed again.
  • the timing controller calculates the leakage voltage of the current refresh rate, and determines the charging time according to the leakage voltage.
  • the timing controller calculates the gray-scale voltage maintenance time of the current refresh rate, and determines the charging time according to the gray-scale voltage maintenance time.
  • the leakage compensation method of the present invention can also perform all operations described in all the foregoing embodiments and have all corresponding functions, and those skilled in the art can directly understand how this embodiment implements these based on all the foregoing embodiments. The operation and having these functions will not be described in detail.
  • the leakage compensation mechanism of the present invention can increase the charging time of the thin film transistor when the refresh rate of the liquid crystal display is low without modifying the circuit design of the liquid crystal display panel to compensate for the long vertical blanking interval.
  • the liquid crystal display of the present invention since the liquid crystal display of the present invention only needs to adjust the charging time of the thin film transistor, it can not only improve the dynamic refresh rate and provide a time guarantee for Freesync certification, but also avoid the problem of in-plane design problems that cannot be imported by customers, and can also reduce R&D and production.
  • the cost input of line supporting facilities will further improve the efficiency of product development in the early stage and test verification in the later stage.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)
  • Liquid Crystal Display Device Control (AREA)

Abstract

一种液晶显示器及其漏电补偿方法。液晶显示器包括薄膜晶体管阵列、栅极驱动器、源极驱动器以及时序控制器。薄膜晶体管阵列由多个薄膜晶体管所构成。栅极驱动器电性连接至所述多个薄膜晶体管每一者的栅极。源极驱动器电性连接至多个薄膜晶体管每一者的源极。时序控制器控制栅极驱动器导通多个薄膜晶体管，根据当前帧率调整当前刷新率，以及判断当前刷新率小于临界频率时，控制栅极驱动器增加多个薄膜晶体管的导通时间。

Description

液晶显示器及其漏电补偿方法 技术领域
本发明是关于一种液晶显示器及其漏电补偿方法。具體而言，本發明的液晶显示器通过增加薄膜晶体管阵列中每一行薄膜晶体管的充电时间，来补偿低频时垂直消隐间隔（vertical blank interval）长产生的漏电问题。
 背景技术
随着显示面板技术的发展，目前已有不同的显示刷新技术，可动态调整刷新频率，以提升画面的流畅度。然而，在动态调整刷新频率时，低刷新率每一行薄膜晶体管的充电时间与高刷新率每一行薄膜晶体管的充电时间相同，因此在低刷新率时的垂直消隐间隔T2较高刷新率时的垂直消隐间隔T1长，如图1所示。
在垂直消隐间隔较长的情况下，为了维持面板的亮度，薄膜晶体管的电压必须维持较长的时间，而维持时间越长，漏电的问题也越严重，从而导致低刷新率与高刷新率面板亮度差值过大的问题。
有鉴于此，本领域亟需一种漏电补偿机制，在低刷新率时，可补偿薄膜晶体管的充电时间，以避免垂直消隐间隔增加造成面板亮度差值过大，从而衍生面板闪烁的问题。
 技术问题
显示面板在动态调整刷新频率时，从高刷新率切换至低刷新率后，垂直消隐间隔较长，使薄膜晶体管的电压必须维持较长的时间，造成漏电问题严重，导致低刷新率与高刷新率之间面板亮度差值过大以及面板闪烁的问题。
 技术解决方案
本发明的目的在于提供一种漏电补偿机制，其藉由液晶显示器内的时序控制器根据从图形处理器获取的当前帧率，调整液晶显示器当前刷新率，并且在液晶显示器当前刷新率小于临界频率时，控制栅极驱动器增加薄膜晶体管的充电时间。
据此，本发明可在无需修改液晶显示器电路设计的情况下，解决垂直消隐间隔较长导致薄膜晶体管漏电严重的问题，以及液晶显示器在低刷新率与高刷新率之间亮度差值大造成闪烁的问题。
为达上述目的，本发明揭露一种液晶显示器，其包括薄膜晶体管阵列、栅极驱动器、源极驱动器以及时序控制器。所述薄膜晶体管阵列由多个薄膜晶体管所构成。所述栅极驱动器用于提供扫描信号。所述源极驱动器用于提供数据信号。所述时序控制器电性连接至所述栅极驱动器及所述源极驱动器，用于根据当前帧率，调整当前刷新率；以及当所述当前刷新率小于临界频率时，传送控制信号至所述栅极驱动器，使所述栅极驱动器根据所述控制信号，增加对所述多个薄膜晶体管的充电时间。
此外，本发明更揭露一种用于液晶显示器的漏电补偿方法。所述液晶显示器包括薄膜晶体管阵列、栅极驱动器、源极驱动器及时序控制器。所述薄膜晶体管阵列由多个薄膜晶体管所构成。所述栅极驱动器用于提供扫描信号。所述源极驱动器用于提供数据信号。所述漏电补偿方法由所述时序控制器执行，且包括：根据当前帧率，调整当前刷新率；以及当所述当前刷新率小于临界频率时，传送控制信号至所述栅极驱动器，使栅极驱动器根据所述控制信号，增加对所述多个薄膜晶体管的充电时间。
在参阅附图及随后描述的实施方式后，本领域技术人员便可了解本发明的其他目的，以及本发明的技术手段及实施态样。
 有益效果
本发明在液晶显示器从高刷新率切换到低刷新率时，增加薄膜晶体管的导通时间，可在无需修改液晶显示器电路设计的情况下，解决垂直消隐间隔较长导致薄膜晶体管漏电严重的问题，以及液晶显示器在低刷新率与高刷新率之间亮度差值大造成闪烁的问题。
 附图说明
图1描绘现有技术中液晶显示器在不同刷新率时，垂直消隐间隔长短变化的示意图。
图2描绘本发明液晶显示器的示意图。
图3描绘本发明液晶显示器与图形处理器之间的实施情境。
图4是本发明漏电补偿方法的流程图。
图5是本发明漏电补偿方法的流程图。
 本发明的实施方式
以下将透过实施例来解释本发明内容，本发明的实施例并非用以限制本发明须在如实施例所述的任何特定的环境、应用或特殊方式方能实施。因此，关于实施例的说明仅为阐释本发明的目的，而非用以限制本发明。需说明者，以下实施例及附图中，与本发明非直接相关的元件已省略而未绘示，且附图中各元件间的尺寸关系仅为求容易了解，并非用以限制实际比例。
本发明第一实施例请参考图2-3。图2描绘本发明液晶显示器的示意图。图3描绘本发明液晶显示器与图形处理器之间的实施情境。液晶显示器1包括薄膜晶体管阵列2、栅极驱动器3、源极驱动器4以及时序控制器5。薄膜晶体管阵列2由多个薄膜晶体管T1-1~Tm-n所构成。各个薄膜晶体管T1-1~Tm-n的栅极接电性连接至栅极驱动器3，使栅极驱动器3针对每一行的薄膜晶体管逐行提供扫描信号，以导通每一行的薄膜晶体管。各个薄膜晶体管T1-1~Tm-n的源极接电性连接至源极驱动器4，使源极驱动器4在栅极驱动器3导通每一行的薄膜晶体管后，提供数据信号，以同时对导通的薄膜晶体管的漏极耦接的液晶电容及存储电容充电。
具体而言，栅极驱动器3从薄膜晶体管阵列2中第一行的薄膜晶体管T1-1、T1-2、T1-3~T1-n开始扫描，源极驱动器4在栅极驱动器3导通第一行的薄膜晶体管T1-1、T1-2、T1-3~T1-n后，同时对第一行的薄膜晶体管T1-1、T1-2、T1-3~T1-n充电。接着，栅极驱动器3扫描第二行的薄膜晶体管T2-1~T2-n，源极驱动器4在栅极驱动器3导通第二行的薄膜晶体管T2-1~T2-n后，同时对第二行的薄膜晶体管T2-1~T2-n充电。栅极驱动器3依序扫描到第m行的薄膜晶体管Tm-1、Tm-2、Tm-3~Tm-n，使源极驱动器4依序对每一行的薄膜晶体管充电，直到对第m行的薄膜晶体管Tm-1、Tm-2、Tm-3~Tm-n充电后，即完成一次液晶显示器1的画面刷新。
需说明者，为简化说明，图2及图3中仅绘示数个薄膜晶体管，薄膜晶体管的数量并非用以限制本发明。
时序控制器5电性连接至栅极驱动器3及源极驱动器4，用于传送栅极启动脉冲及栅极时钟脉冲至栅极驱动器3，使栅极驱动器3根据栅极时钟脉冲生成用于导通每一行薄膜晶体管的扫描信号。时序控制器5亦用于传送栅源极启动脉冲及源极时钟脉冲至源极驱动器4，使源极驱动器4根据源极时钟脉冲生成数据信号，并于栅极驱动器3导通多个薄膜晶体管T1-1~Tm-n的期间，对多个薄膜晶体管T1-1~Tm-n充电。
接着，时序控制器5根据当前帧率，调整当前刷新率。当时序控制器5判断当前刷新率小于临界频率时，传送控制信号至栅极驱动器3，使栅极驱动器3根据控制信号，增加多个薄膜晶体管T1-1~Tm-n的充电时间。
详言之，请参考图3，帧率为显示卡中的图形处理器6产生帧的速率，刷新率为栅极驱动器3每秒从薄膜晶体管阵列2中第一行的薄膜晶体管T1-1、T1-2、T1-3~T1-n开始扫描到第m行的薄膜晶体管Tm-1、Tm-2、Tm-3~Tm-n的次数，亦即液晶显示器1画面更新的频率。栅极驱动器3在扫描完第m行的薄膜晶体管Tm-1、Tm-2、Tm-3~Tm-n后到下一次从第一行的薄膜晶体管T1-1、T1-2、T1-3~T1-n开始扫描的间隔时间称为垂直消隐间隔（vertical blank interval）。
本发明的液晶显示器1支援自动同步（freesync）技术，能够动态的调整刷新率，因此时序控制器5从图形处理器6获取当前帧率后，可将液晶显示器1的当前刷新率调整为与当前帧率相同。为了避免在液晶显示器1的刷新率较低时，液晶显示器1的垂直消隐间隔增加而导致漏电问题严重，本发明的时序控制器5在判断液晶显示器1的当前刷新率小于临界频率时，可控制栅极驱动器3，使其增加薄膜晶体管T1-1~Tm-n的充电时间。
需说明者，每一行薄膜晶体管的充电时间是由扫描信号的上升沿开始到扫描信号对应的栅极时钟脉冲的下降沿结束。由于栅极驱动器3是根据时序控制器5提供的栅极时钟脉冲生成用于导通每一行薄膜晶体管的扫描信号，因此时序控制器5在判断当前刷新率小于临界频率时，可通过控制信号，使栅极驱动器3将扫描信号的时脉提前，以增加薄膜晶体管的充电时间。
举例而言，假设液晶显示器1的画面每秒刷新120次（即刷新率为120赫兹（Hz）），源极驱动器4对薄膜晶体管的充电时间为2微秒（μs），图形处理器6当前生成帧的速率为每秒60帧（即当前帧率为60 frame per second；FPS），以及临界频率为70 Hz。时序控制器5自图形处理器6接收到当前帧率为60 FPS后，将液晶显示器1的当前刷新率从120 Hz调整为60 Hz。
接着，时序控制器5更进一步判断液晶显示器1的当前刷新率60 Hz小于临界频率70 Hz时，传送控制信号至栅极驱动器3，使栅极驱动器3根据控制信号，将每一行扫描信号的时脉提前，使薄膜晶体管T1-1~Tm-n的充电时间从2 μs增加到4 μs。据此，本发明可解决薄膜晶体管T1-1~Tm-n在垂直消隐间隔严重漏电而造成液晶显示器1亮度不均及画面闪烁的问题。
于一实施例中，时序控制器5还计算垂直消隐间隔，当垂直消隐间隔大于临界时间时，传送控制信号至栅极驱动器3。具体而言，时序控制器5除了以液晶显示器1的当前刷新率作为控制栅极驱动器3增加对薄膜晶体管的充电时间的依据外，更同时根据垂直消隐间隔，来决定是否传送控制信号至栅极驱动器3。当液晶显示器1的当前刷新率小于临界频率，以及垂直消隐间隔大于临界时间时，时序控制器5才会传送控制信号至栅极驱动器3。需说明者，本领域技术人员可了解前述垂直消隐间隔的计算方式，故于此不再赘述。
于一实施例中，时序控制器5计算多个薄膜晶体管于当前刷新率的漏电电压，并根据漏电电压决定薄膜晶体管的充电时间。
此外，于一实施例中，时序控制器5计算多个薄膜晶体管于当前刷新率的灰阶电压维持时间，并根据灰阶电压维持时间决定薄膜晶体管的充电时间。
需说明者，垂直消隐间隔越长代表液晶显示器1当前显示的画面必须维持越久，灰阶电压也需维持更长的时间，薄膜晶体管漏电的情况也越严重。因此，除了前述通过计算漏电电压极灰阶电压维持时间决定充电时间外，本领域技术人员亦可通过计算漏电流值、灰阶电压变化量、像素电容值以及刷新率差值等方法，调整薄膜晶体管的充电时间。
本发明第二实施例描述漏电补偿方法，其流程图如图4所示。漏电补偿方法适用于液晶显示器，例如：前述实施例的液晶显示器1。液晶显示器包括液晶显示器1包括薄膜晶体管阵列、栅极驱动器、源极驱动器及时序控制器。薄膜晶体管阵列由多个薄膜晶体管所构成。所述多个薄膜晶体管每一者的栅极电性连接至栅极驱动器。所述多个薄膜晶体管每一者的源极电性连接至源极驱动器。栅极驱动器用于提供扫描信号，以导通每一行的薄膜晶体管。源极驱动器用于提供数据信号，以对每一行以导通的薄膜晶体管充电。漏电补偿方法由时序控制器执行，其包括的步骤说明如下。
首先，于步骤S402中，根据所述当前帧率，调整当前刷新率。于步骤S404中，判断当前刷新率是否小于临界频率。当所述当前刷新率小于临界频率时，执行步骤S406，传送控制信号至栅极驱动器。使栅极驱动器根据控制信号，增加多个薄膜晶体管的充电时间。当所述当前刷新率大于临界频率时，再次执行步骤S402。
于一实施例中，当前刷新率与所述当前帧率相同。
请参考图5，于一实施例中，时序控制器于执行完步骤S406后，还执行步骤S502，计算垂直消隐间隔。接着，执行步骤S504，判断垂直消隐间隔是否大于临界时间。当垂直消隐间隔大于临界时间时，执行步骤S406，传送控制信号至栅极驱动器。当垂直消隐间隔小于临界时间时，再次执行步骤S502。
此外，于一实施例中，时序控制器计算当前刷新率的漏电电压，并根据漏电电压决定所述充电时间。
于一实施例中，时序控制器计算当前刷新率的灰阶电压维持时间，并根据灰阶电压维持时间决定所述充电时间。
除了上述步骤，本发明的漏电补偿方法亦能执行在所有前述实施例中所阐述的所有操作并具有所有对应的功能，本领域技术人员可直接了解此实施例如何基于所有前述实施例执行此等操作及具有该等功能，故不赘述。
综上所述，本发明的漏电补偿机制可在无需修改液晶显示器面板内电路设计的情况下，当液晶显示器刷新率低时，增加薄膜晶体管充电时间，以补偿垂直消隐间隔时间长而导致的漏电问题，优化支援Freesync功能的液晶显示器。
由于本发明的液晶显示器只需调整薄膜晶体管的充电时间，不仅可提高动态刷新率Freesync认证提供时间保证外，也避免了由于面内设计问题而导致的客户无法导入问题，亦能够减少研发及产线配套设施的成本投入，进一步提高前期产品开发以及后期测试验证效率。
上述的实施例仅用来例举本发明的实施态样，以及阐释本发明的技术特征，并非用来限制本发明的保护范畴。任何熟悉此技术者可轻易完成的改变或均等性的安排均属于本发明所主张的范围，本发明的权利保护范围应以权利要求为准。

Claims (10)

  1. 一种液晶显示器，包括：
    薄膜晶体管阵列，由多个薄膜晶体管所构成；
    栅极驱动器，用于提供扫描信号；
    源极驱动器，用于提供数据信号；以及
    时序控制器，电性连接至所述栅极驱动器及所述源极驱动器，用于：
    根据当前帧率，调整当前刷新率；以及
    当所述当前刷新率小于临界频率时，传送控制信号至所述栅极驱动器，使所述栅极驱动器根据所述控制信号，增加所述多个薄膜晶体管的充电时间。
  2. 如权利要求1所述的液晶显示器，其中所述时序控制器还计算垂直消隐间隔，当所述垂直消隐间隔大于临界时间时，传送所述控制信号至所述栅极驱动器。
  3. 如权利要求1所述的液晶显示器，其中所述当前刷新率与所述当前帧率相同。
  4. 如权利要求1所述的液晶显示器，其中所述时序控制器计算所述多个薄膜晶体管于当前刷新率的漏电电压，并根据所述漏电电压决定所述充电时间。
  5. 如权利要求1所述的液晶显示器，其中所述时序控制器计算所述多个薄膜晶体管于当前刷新率的灰阶电压维持时间，并根据所述灰阶电压维持时间决定所述充电时间。
  6. 一种用于液晶显示器的漏电补偿方法，所述液晶显示器包括薄膜晶体管阵列、栅极驱动器、源极驱动器及时序控制器，所述薄膜晶体管阵列由多个薄膜晶体管所构成，所述栅极驱动器用于提供扫描信号，所述源极驱动器用于提供数据信号，所述漏电补偿方法由所述时序控制器执行，所述方法包括：
    根据当前帧率，调整当前刷新率；以及
    当所述当前刷新率小于临界频率时，传送控制信号至所述栅极驱动器，使所述栅极驱动器根据所述控制信号，增加所述多个薄膜晶体管的充电时间。
  7. 如权利要求6所述的漏电补偿方法，其另包括：
    计算垂直消隐间隔；以及
    当所述垂直消隐间隔大于临界时间时，传送所述控制信号至所述栅极驱动器。
  8. 如权利要求6所述的漏电补偿方法，其中所述当前刷新率与所述当前帧率相同。
  9. 如权利要求6所述的漏电补偿方法，其中所述时序控制器计算当前刷新率的漏电电压，并根据所述漏电电压决定所述充电时间。
  10. 如权利要求6所述的漏电补偿方法，其中所述时序控制器计算当前刷新率的灰阶电压维持时间，并根据所述灰阶电压维持时间决定所述充电时间。
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