WO2022000674A1 - 阵列基板和显示面板 - Google Patents

阵列基板和显示面板 Download PDF

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Publication number
WO2022000674A1
WO2022000674A1 PCT/CN2020/105711 CN2020105711W WO2022000674A1 WO 2022000674 A1 WO2022000674 A1 WO 2022000674A1 CN 2020105711 W CN2020105711 W CN 2020105711W WO 2022000674 A1 WO2022000674 A1 WO 2022000674A1
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WO
WIPO (PCT)
Prior art keywords
area
driving units
array substrate
bending
connection line
Prior art date
Application number
PCT/CN2020/105711
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English (en)
French (fr)
Inventor
李雪
Original Assignee
武汉华星光电半导体显示技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 武汉华星光电半导体显示技术有限公司 filed Critical 武汉华星光电半导体显示技术有限公司
Priority to US17/058,144 priority Critical patent/US11778873B2/en
Priority to EP20908442.5A priority patent/EP4177870A1/en
Publication of WO2022000674A1 publication Critical patent/WO2022000674A1/zh

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/301—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements flexible foldable or roll-able electronic displays, e.g. thin LCD, OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • the present application relates to the field of display technology, in particular to the manufacture of display devices, and in particular to array substrates and display panels.
  • OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • the OLED flexible display panel may damage the circuit in the folding area during the folding process, for example, causing the electrical properties of the circuit in the folding area to change, or even causing the circuit traces in the folding area to break, resulting in the normal transmission of signals, which in turn makes the OLED folding display panel.
  • the display screen is abnormal.
  • the purpose of this application is to provide an array substrate and a display panel, by arranging a plurality of driving units in the non-bending area, and arranging a plurality of first connection lines in the bending area, so as to connect the driving units located on both sides of the bending area , which solves the problem of abnormal display images caused by the breakage of circuit traces in the folding area of the existing OLED foldable display panel.
  • An embodiment of the present application provides an array substrate, which is applied to a display panel.
  • the display panel has a bending area
  • the array substrate has a bending area corresponding to the bending area, and non-returning areas located on both sides of the bending area.
  • the array substrate includes:
  • the plurality of driving units are arranged in the non-bending area
  • each of the first connection lines is connected to the two driving units located on both sides of the first connection line, each of the first connection lines
  • the first connecting line is provided with a plurality of openings
  • each of the second connection lines is used to connect the plurality of driving units located in the bending area, the The width of the first connection line is greater than the width of the second connection line.
  • the distance between two adjacent first connection lines is not less than 3 microns.
  • the display panel has a display area
  • the array substrate has a first area corresponding to the display area
  • the plurality of driving units include a first pixel driving unit, the first pixel driving unit is arranged in the overlapping area of the first area and the non-bending area, and the first pixel driving unit is used to drive the corresponding A first light-emitting unit, the first light-emitting unit is disposed in the bending region.
  • the plurality of driving units further include a second pixel driving unit, the second pixel driving unit is disposed in the overlapping area of the first area and the non-bending area, the second pixel driving unit is The driving unit is used for driving the corresponding second light-emitting unit, and the second light-emitting unit is arranged in the non-bending area;
  • the second connection line includes a scan line and a data line, the scan line is connected to a plurality of the first pixel driving units or a plurality of the second pixel driving units in a corresponding row, and the data line is connected to a plurality of the corresponding column. a plurality of the first pixel driving units and a plurality of the second pixel driving units.
  • the plurality of first connection lines include:
  • a first sub-connection line, the first sub-connection line is arranged in the bending region, and the first sub-connection line connects the two first pixel driving units located on both sides of the first sub-connection line.
  • the array substrate further has a second area, and the second area surrounds the first area
  • the plurality of driving units further include a gate driving unit, the gate driving unit is arranged in the overlapping area of the second area and the non-bending area, and the gate driving unit is connected to a plurality of all the corresponding rows.
  • the first pixel driving unit is used to drive a corresponding plurality of the first light-emitting units, or each of the gate driving units is connected to a plurality of the second pixel driving units in a corresponding row to drive a corresponding plurality of the second pixel driving units. the second light-emitting unit.
  • the plurality of first connection lines include:
  • a second sub-connection line, the second sub-connection line is disposed in the bending region, and the second sub-connection line connects the two gate driving units located on both sides of the second sub-connection line.
  • An embodiment of the present application provides an array substrate, which is applied to a display panel.
  • the display panel has a bending area
  • the array substrate has a bending area corresponding to the bending area, and non-returning areas located on both sides of the bending area.
  • the array substrate includes:
  • the plurality of driving units are arranged in the non-bending area
  • a plurality of first connection lines are arranged in the bending area, and each of the first connection lines is connected to the two driving units located on both sides of the first connection line.
  • the array substrate further includes:
  • each of the second connection lines is used to connect the plurality of driving units located in the bending area, the The width of the first connection line is greater than the width of the second connection line.
  • each of the first connecting lines is provided with a plurality of openings.
  • the distance between two adjacent first connection lines is not less than 3 microns.
  • the display panel has a display area
  • the array substrate has a first area corresponding to the display area
  • the plurality of driving units include a first pixel driving unit, the first pixel driving unit is arranged in the overlapping area of the first area and the non-bending area, and the first pixel driving unit is used to drive the corresponding A first light-emitting unit, the first light-emitting unit is disposed in the bending region.
  • the plurality of driving units further include a second pixel driving unit, the second pixel driving unit is disposed in the overlapping area of the first area and the non-bending area, the second pixel driving unit is The driving unit is used for driving the corresponding second light-emitting unit, and the second light-emitting unit is arranged in the non-bending area;
  • the second connection line includes a scan line and a data line, the scan line is connected to a plurality of the first pixel driving units or a plurality of the second pixel driving units in a corresponding row, and the data line is connected to a plurality of the corresponding column. a plurality of the first pixel driving units and a plurality of the second pixel driving units.
  • the plurality of first connection lines include:
  • a first sub-connection line, the first sub-connection line is arranged in the bending region, and the first sub-connection line connects the two first pixel driving units located on both sides of the first sub-connection line.
  • the array substrate further has a second area, and the second area surrounds the first area
  • the plurality of driving units further include a gate driving unit, the gate driving unit is arranged in the overlapping area of the second area and the non-bending area, and the gate driving unit is connected to a plurality of all the corresponding rows.
  • the first pixel driving unit is used to drive a corresponding plurality of the first light-emitting units, or each of the gate driving units is connected to a plurality of the second pixel driving units in a corresponding row to drive a corresponding plurality of the second pixel driving units. the second light-emitting unit.
  • the plurality of first connection lines include:
  • a second sub-connection line, the second sub-connection line is disposed in the bending region, and the second sub-connection line connects the two gate driving units located on both sides of the second sub-connection line.
  • Embodiments of the present application further provide a display panel, the display panel includes an array substrate, the display panel has a bending area, the array substrate has a bending area corresponding to the bending area, and a bending area located in the bending area Non-bending areas on both sides, the array substrate includes:
  • the plurality of driving units are arranged in the non-bending area
  • a plurality of first connection lines are arranged in the bending area, and each of the first connection lines is connected to the two driving units located on both sides of the first connection line.
  • the array substrate further includes:
  • each of the second connection lines is used to connect the plurality of driving units located in the bending area, the The width of the first connection line is greater than the width of the second connection line.
  • the display panel has a display area
  • the array substrate has a first area corresponding to the display area
  • the plurality of driving units include a first pixel driving unit, the first pixel driving unit is arranged in the overlapping area of the first area and the non-bending area, and the first pixel driving unit is used to drive the corresponding A first light-emitting unit, the first light-emitting unit is disposed in the bending region.
  • the plurality of first connection lines include:
  • a first sub-connection line, the first sub-connection line is arranged in the bending region, and the first sub-connection line connects the two first pixel driving units located on both sides of the first sub-connection line.
  • the present application provides an array substrate and a display panel, the display panel has a bending area, the array substrate has a bending area corresponding to the bending area, and non-bending areas located on both sides of the bending area , by arranging a plurality of driving units in the non-bending area, and arranging a plurality of first connection lines in the bending area, to connect the two driving units located on both sides of the plurality of first connection lines.
  • This solution avoids arranging more complex circuits such as driving units in the bending area, reduces the risk of circuit breakage in the folding area, and improves the bending performance of the OLED folding display panel.
  • FIG. 1 is a schematic top view of a first array substrate according to an embodiment of the present application.
  • FIG. 2 is a schematic top view of a first connection line according to an embodiment of the present application.
  • FIG. 3 is a schematic top view of another first connection line provided by an embodiment of the present application.
  • FIG. 4 is a schematic top view of a second array substrate according to an embodiment of the present application.
  • FIG. 5 is a schematic top view of a third array substrate according to an embodiment of the present application.
  • FIG. 6 is a schematic top view of a fourth array substrate according to an embodiment of the present application.
  • FIG. 7 is a schematic top view of a fifth array substrate according to an embodiment of the present application.
  • FIG. 8 is a schematic top view of a sixth array substrate according to an embodiment of the present application.
  • the present application provides an array substrate, the array substrate includes but not limited to the following embodiments, and the array substrate is applied to a display panel.
  • the display panel has a bending area
  • the array substrate 00 has a bending area 01 corresponding to the bending area, and a bending area 01 located at two sides of the bending area 01 .
  • the non-bending area 02 on the side, the array substrate 00 includes: a plurality of driving units 100, the plurality of driving units 100 are arranged in the non-bending area 02; a plurality of first connection lines 200, the plurality of The first connecting wires 200 are disposed in the bending area 01 , and each of the first connecting wires 200 is connected to the two driving units 100 located on both sides of the plurality of first connecting wires 200 .
  • the array substrate 00 further includes a plurality of second connection lines, the plurality of second connection lines are located in the non-bending area 02, and the plurality of second connection lines are used to connect the In the plurality of driving units 100 in the bending region 01, the width of the first connection line 200 is greater than the width of the second connection line. It can be understood that, when the first connecting wire 200 located in the bending area 01 is bent, the larger the width of the first connecting wire 200 is, the smaller the pressure on the first connecting wire 200 per unit area is. , so the first connection line 200 is less likely to be broken.
  • the outline of the first connection line 200 can be made into a curved shape.
  • the area of the first connecting line 200 can be increased, and the pressure per unit area of the first connecting line 200 is smaller, so the A connecting wire 200 is less likely to be broken;
  • the outline length of the first connecting wire 200 by increasing the outline length of the first connecting wire 200, the degree of dispersion of the first connecting wire 200 can be increased, so as to improve the reliability of the first connecting wire 200. bendability.
  • the distance between two adjacent first connection lines 200 is not less than 3 microns. It can be understood that since the width of the first connecting lines 200 is relatively large, the distance between two adjacent first connecting lines 200 may be small, and the two adjacent first connecting lines 200 are limited here. The distance between them is not less than 3 micrometers, which can effectively avoid a short circuit between two adjacent first connecting lines 200, resulting in an error in signal transmission.
  • each of the first connecting wires 200 is provided with a plurality of openings 202 .
  • the arrangement path of the plurality of openings 202 on each of the first connecting wires 200 may be consistent with the contour shape of the first connecting wires 200 .
  • the outline of the first connection line 200 is in a linear shape, and the plurality of openings 202 are arranged in a straight path along the outline and shape of the first connection line 200 ; for another example, in FIG. 3 , the first connection line 200 is The outline of a connecting line 200 is in a curved shape, and the plurality of openings 202 are arranged in a curved path along the outline of the first connecting line 200 .
  • the shapes or sizes of the plurality of openings 202 on each of the first connecting wires 200 may be the same or different, and the shapes of the openings 202 may be circular, triangular, rectangular or other shapes.
  • the number and arrangement interval of the openings 202 on each of the first connecting wires 200 can be set according to the size and material of the first connecting wires 200 .
  • the opening 202 is provided in the first connecting wire 200, when the first connecting wire 200 is bent under force, if there is a break, the opening 202 can prevent the breakage
  • the cracks extend to two sides or one of the two sides, which can reduce the risk of disconnection of the first connection line 200 .
  • the display panel has a display area
  • the array substrate 00 has a first area 03 corresponding to the display area
  • the plurality of driving units 100 include a plurality of first A pixel driving unit 101, the plurality of first pixel driving units 101 are arranged in the overlapping area of the first area 03 and the non-bending area 02, and each of the first pixel driving units 101 is used for driving a corresponding
  • the first light-emitting unit 301 , a plurality of the first light-emitting units 301 are all disposed in the bending region 01 .
  • the first light-emitting unit 301 is disposed above the array substrate 00 in a region corresponding to the bending region 01 and the first region 03 . It can be understood that since the first light-emitting unit 301 is disposed in the bending area 01, in order to facilitate driving the corresponding first light-emitting unit 301, a plurality of first pixel driving units 101 can be disposed in the first area In the overlapping area of 03 and the non-bending area 02, the area is relatively close to the bending area 01.
  • the plurality of first connection lines 200 include first sub-connection lines 203 , the first sub-connection lines 203 are arranged in the bending area 01 , the first sub-connection lines 203 are The sub-connection line 203 connects the two first pixel driving units 101 located on both sides of the first sub-connection line 203 . It can be understood that, since the first sub-connection line 203 is arranged in the bending area 01, in order to increase the bending resistance of the first sub-connection line 203, the arrangement of the first sub-connection line 203 may be Refer to the above-mentioned related description of the first connection line 200 .
  • the array substrate 00 includes a plurality of connection lines 201 , and each of the connection lines 201 connects the corresponding first pixel driving unit 101 and the corresponding first light emitting unit 301 , the connection line 201 includes a sub-connection line, the sub-connection line is located in the bending region 01 , and the width of the sub-connection line is greater than the width of the second connection line.
  • the sub-connection line is provided with a plurality of openings, and the relevant description of the sub-connection line may refer to the above-mentioned relevant description of the first connection line 200 .
  • the plurality of driving units 100 further include a plurality of second pixel driving units 102 , and the plurality of second pixel driving units 102 are disposed in the first area 03 and the non- In the overlapping area of the bending area 02, each of the second pixel driving units 102 is used to drive the corresponding second light-emitting unit 302, and the plurality of second light-emitting units 302 are arranged in the non-bending area 02 (here Only the distribution of the second light-emitting units 302 in the first area 03 on the lower side is marked); the second connection line includes a scan line 401 and a data line 402, and the scan line 401 connects a plurality of the first light-emitting units in the corresponding row.
  • the second connection line further includes an EM line and a VDD line.
  • the EM lines and the scan lines 401 are arranged in parallel and staggered.
  • the EM lines transmit EM signals, and the EM signals are used to control the corresponding column light-emitting units.
  • each of the EM lines can be connected to A plurality of the first pixel driving units 101 and/or a plurality of the second pixel driving units 102 corresponding to one or two rows; the VDD line and the data line 402 are arranged in parallel and staggered, and the VDD line transmits A voltage signal, the voltage signal is used to provide the operating voltage of the corresponding switching element, further, each of the VDD lines can be connected to a plurality of the first pixel driving units 101 and a plurality of the second pixels corresponding to a column drive unit 102 .
  • the scan lines 401 and the EM lines may be single-layer metal layers made of molybdenum, and the data lines 402 and the VDD lines may be composite metal layers made of "titanium-aluminum-titanium".
  • the second light emitting unit 302 is disposed above the array substrate 00 in a region corresponding to the non-bending region 02 and the first region 03 .
  • the first light-emitting unit 301 disposed opposite to the bending area 01 and the second light-emitting unit 302 disposed opposite to the non-bending area 02 together constitute all light-emitting units for screen display .
  • the first pixel driving unit 101 and the second pixel driving unit 102 are only located in the non-bending area 02, and the first light-emitting unit 301 and the second light-emitting unit 302 are uniform
  • the first pixel driving unit 101 and the second pixel driving unit 102 are distributed in the whole of the first area 03, so the density is higher than that of the prior art.
  • first pixel driving unit 101 and the second pixel driving unit 102 may be uniformly distributed in the non-bending area 02 and the The overlapping area of the non-bending area 02; or the arrangement density of the first pixel driving unit 101 may be greater than that of the second pixel driving unit 102, so as to facilitate the connection between each light-emitting unit and the corresponding pixel driving unit connect.
  • the array substrate 00 further includes a second area 04 , and the second area 04 surrounds the first area 03 ;
  • the plurality of driving units 100 further includes a plurality of a plurality of gate driving units 103, the plurality of gate driving units 103 are disposed in the overlapping area of the second area 04 and the non-bending area 02, and each of the gate driving units 103 is connected to a plurality of corresponding rows of each of the first pixel driving units 101 to drive the corresponding plurality of the first light emitting units 301, or each of the gate driving units 103 is connected to the plurality of the second pixel driving units 102 in the corresponding row to drive The corresponding plurality of the second light-emitting units 302 are driven.
  • the plurality of gate driving units 103 may be arranged on the right side of the display area 03 . Further, the gate driving units 103 are arranged in a one-to-one correspondence with the scan lines 401 to keep the distribution density consistent. ; Further, when the area of each of the gate driving units 103 is large, in order to avoid the mutual interference of the adjacent gate driving units 103, such as FIG. 7, the plurality of gate driving units 103 can be
  • the gate driving units 103 located on the left and right sides of the display area 03 for example, the gate driving units 103 located on the right side of the display area 03 are connected to the scan lines 401 of the corresponding odd columns, located on the left side of the display area 03.
  • the gate driving unit 103 on the side is connected to the scan lines 401 of the corresponding even columns.
  • the plurality of first connection lines 200 include second sub-connection lines 204 , and the second sub-connection lines 204 are arranged in the bending area 01 .
  • the second sub-connection line 204 connects the two gate driving units 103 located on both sides of the second sub-connection line 204 . It can be understood that, since the second sub-connection lines 204 are arranged in the bending region 01, in order to increase the bending resistance of the second sub-connection lines 204, the arrangement of the second sub-connection lines 204 may be Refer to the above-mentioned related description of the first connection line 200 .
  • each of the plurality of second sub-connection lines 204 and the plurality of connection lines located between any two adjacent gate driving units 103 in any of the non-bending regions 02 may include a separate The lines used to transmit the first clock signal, the second clock signal, the positive voltage signal, the negative voltage signal and the upper-level input signal, only the shape of the lines in the second sub-connection line 204 is the same as any one of the non-bending lines. The shapes of the lines between any two adjacent gate driving units 103 in the region 02 are different.
  • the first clock signal and the second clock signal can be used for synchronizing the plurality of gate driving units 103, and the positive voltage signal and the negative voltage signal can be used for driving the plurality of gates
  • the driving unit 103 provides a positive voltage signal or a negative voltage signal, and the upper-level input signal may represent the output signal of the gate driving unit 103 of the previous stage and the input signal of the gate driving unit 103 of the current stage.
  • the gate driving units 103 are disposed on the left and/or right side of the array substrate 00 , and there is no need to consider avoiding the bending area 01 , and the array substrate
  • the number of the plurality of gate driving units 103 on the left and/or right of 00 in the column direction is the same as the number of all pixel driving units in the column direction, so the distribution density of the gate driving units 103
  • the distribution density of the pixel driving units in the column direction may be the same.
  • the present application provides an array substrate and a display panel, the display panel has a bending area, the array substrate has a bending area corresponding to the bending area, and non-bending areas located on both sides of the bending area , by arranging a plurality of driving units in the non-bending area, and arranging a plurality of first connection lines in the bending area, to connect the two driving units located on both sides of the plurality of first connection lines.
  • This solution avoids arranging more complex circuits such as driving units in the bending area, reduces the risk of circuit breakage in the folding area, and improves the bending performance of the OLED folding display panel.

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  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
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Abstract

本申请提供了阵列基板和显示面板，该显示面板具有弯折区域，该阵列基板具有与弯折区域对应的弯折区，和位于弯折区两侧的非弯折区，阵列基板包括：多个驱动单元和多条第一连接线，多个驱动单元设于非弯折区，多条第一连接线设于弯折区，每一第一连接线连接位于该第一连接线两侧的两驱动单元。

Description

阵列基板和显示面板 技术领域
本申请涉及显示技术领域，尤其涉及显示器件的制造，具体涉及阵列基板和显示面板。
 背景技术
OLED (Organic Light Emitting Diode，有机发光二极管)显示面板由于具有可折叠、低能耗、自发光等特点，逐渐向柔性折叠显示方向发展。
然而，OLED柔性显示面板在折叠过程中可能会损坏折叠区的电路，例如造成折叠区的电路电性改变，甚至造成折叠区的电路走线断裂，导致信号无法正常传输，进而使OLED折叠显示面板产生显示画面异常。
因此，有必要提供阵列基板和显示面板，以提高OLED折叠显示面板的弯折性能。
 技术问题
本申请的目的在于提供阵列基板和显示面板，通过将多个驱动单元设于非弯折区，并且在弯折区设置多条第一连接线，以连接位于该弯折区两侧的驱动单元，解决了现有的OLED折叠显示面板因折叠区的电路走线断裂，产生的显示画面异常的问题。
 技术解决方案
本申请实施例提供阵列基板，应用于显示面板，所述显示面板具有弯折区域，所述阵列基板具有与所述弯折区域对应的弯折区，和位于所述弯折区两侧的非弯折区，所述阵列基板包括：
多个驱动单元，所述多个驱动单元设于所述非弯折区；
多条第一连接线，所述多条第一连接线设于所述弯折区，每一所述第一连接线连接位于所述第一连接线两侧的两所述驱动单元，每一所述第一连接线上设置有多个开孔；
多条第二连接线，所述多条第二连接线位于所述非弯折区，每一所述第二连接线用于连接位于所述弯折区的所述多个驱动单元，所述第一连接线的宽度大于所述第二连接线的宽度。
在一实施例中，相邻的两所述第一连接线之间的距离不小于3微米。
在一实施例中，所述显示面板具有显示区，所述阵列基板具有与所述显示区对应的第一区域；
所述多个驱动单元包括第一像素驱动单元，所述第一像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第一像素驱动单元用于驱动对应的第一发光单元，所述第一发光单元设于所述弯折区域。
在一实施例中，所述多个驱动单元还包括第二像素驱动单元，所述第二像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第二像素驱动单元用于驱动对应的第二发光单元，所述第二发光单元设于所述非弯折区；
所述第二连接线包括扫描线和数据线，所述扫描线连接对应行的多个所述第一像素驱动单元或者多个所述第二像素驱动单元，所述数据线连接对应列的多个所述第一像素驱动单元和多个所述第二像素驱动单元。
在一实施例中，所述多条第一连接线包括：
第一子连接线，所述第一子连接线设于所述弯折区，所述第一子连接线连接位于所述第一子连接线两侧的两所述第一像素驱动单元。
在一实施例中，所述阵列基板还具有第二区域，所述第二区域包围所述第一区域；
所述多个驱动单元还包括栅极驱动单元，所述栅极驱动单元设于所述第二区域与所述非弯折区的重叠区域，所述栅极驱动单元连接对应行的多个所述第一像素驱动单元，以驱动对应的多个所述第一发光单元，或者每一所述栅极驱动单元连接对应行的多个所述第二像素驱动单元，以驱动对应的多个所述第二发光单元。
在一实施例中，其中，所述多条第一连接线包括：
第二子连接线，所述第二子连接线设于所述弯折区，所述第二子连接线连接位于所述第二子连接线两侧的两所述栅极驱动单元。
本申请实施例提供阵列基板，应用于显示面板，所述显示面板具有弯折区域，所述阵列基板具有与所述弯折区域对应的弯折区，和位于所述弯折区两侧的非弯折区，所述阵列基板包括：
多个驱动单元，所述多个驱动单元设于所述非弯折区；
多条第一连接线，所述多条第一连接线设于所述弯折区，每一所述第一连接线连接位于所述第一连接线两侧的两所述驱动单元。
在一实施例中，所述阵列基板还包括：
多条第二连接线，所述多条第二连接线位于所述非弯折区，每一所述第二连接线用于连接位于所述弯折区的所述多个驱动单元，所述第一连接线的宽度大于所述第二连接线的宽度。
在一实施例中，每一所述第一连接线上设置有多个开孔。
在一实施例中，相邻的两所述第一连接线之间的距离不小于3微米。
在一实施例中，所述显示面板具有显示区，所述阵列基板具有与所述显示区对应的第一区域；
所述多个驱动单元包括第一像素驱动单元，所述第一像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第一像素驱动单元用于驱动对应的第一发光单元，所述第一发光单元设于所述弯折区域。
在一实施例中，所述多个驱动单元还包括第二像素驱动单元，所述第二像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第二像素驱动单元用于驱动对应的第二发光单元，所述第二发光单元设于所述非弯折区；
所述第二连接线包括扫描线和数据线，所述扫描线连接对应行的多个所述第一像素驱动单元或者多个所述第二像素驱动单元，所述数据线连接对应列的多个所述第一像素驱动单元和多个所述第二像素驱动单元。
在一实施例中，所述多条第一连接线包括：
第一子连接线，所述第一子连接线设于所述弯折区，所述第一子连接线连接位于所述第一子连接线两侧的两所述第一像素驱动单元。
在一实施例中，所述阵列基板还具有第二区域，所述第二区域包围所述第一区域；
所述多个驱动单元还包括栅极驱动单元，所述栅极驱动单元设于所述第二区域与所述非弯折区的重叠区域，所述栅极驱动单元连接对应行的多个所述第一像素驱动单元，以驱动对应的多个所述第一发光单元，或者每一所述栅极驱动单元连接对应行的多个所述第二像素驱动单元，以驱动对应的多个所述第二发光单元。
在一实施例中，所述多条第一连接线包括：
第二子连接线，所述第二子连接线设于所述弯折区，所述第二子连接线连接位于所述第二子连接线两侧的两所述栅极驱动单元。
本申请实施例还提供显示面板，所述显示面板包括阵列基板，所述显示面板具有弯折区域，所述阵列基板具有与所述弯折区域对应的弯折区，和位于所述弯折区两侧的非弯折区，所述阵列基板包括：
多个驱动单元，所述多个驱动单元设于所述非弯折区；
多条第一连接线，所述多条第一连接线设于所述弯折区，每一所述第一连接线连接位于所述第一连接线两侧的两所述驱动单元。
在一实施例中，所述阵列基板还包括：
多条第二连接线，所述多条第二连接线位于所述非弯折区，每一所述第二连接线用于连接位于所述弯折区的所述多个驱动单元，所述第一连接线的宽度大于所述第二连接线的宽度。
在一实施例中，所述显示面板具有显示区，所述阵列基板具有与所述显示区对应的第一区域；
所述多个驱动单元包括第一像素驱动单元，所述第一像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第一像素驱动单元用于驱动对应的第一发光单元，所述第一发光单元设于所述弯折区域。
在一实施例中，所述多条第一连接线包括：
第一子连接线，所述第一子连接线设于所述弯折区，所述第一子连接线连接位于所述第一子连接线两侧的两所述第一像素驱动单元。
 有益效果
本申请提供了阵列基板和显示面板，所述显示面板具有弯折区域，所述阵列基板具有与所述弯折区域对应的弯折区，和位于所述弯折区两侧的非弯折区，通过将多个驱动单元设于所述非弯折区，并在所述弯折区设置多条第一连接线，连接位于所述多条第一连接线两侧的两所述驱动单元。该方案避免了在弯折区设置驱动单元等较为复杂的电路，降低了折叠区的电路走线断裂的风险，提高了OLED折叠显示面板的弯折性能。
 附图说明
下面通过附图来对本发明进行进一步说明。需要说明的是，下面描述中的附图仅仅是用于解释说明本发明的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的第一种阵列基板的俯视示意图。
图2为本申请实施例提供的一种第一连接线的俯视示意图。
图3为本申请实施例提供的另一种第一连接线的俯视示意图。
图4为本申请实施例提供的第二种阵列基板的俯视示意图。
图5为本申请实施例提供的第三种阵列基板的俯视示意图。
图6为本申请实施例提供的第四种阵列基板的俯视示意图。
图7为本申请实施例提供的第五种阵列基板的俯视示意图。
图8为本申请实施例提供的第六种阵列基板的俯视示意图。
 本发明的实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整的描述。显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
在本申请的描述中，需要理解的是，术语“上”、“下”、“周围”、“靠近”等指示的方位或位置关系为基于附图所示的方位或位置关系，例如，“上”只是表面在物体上方，具体指代正上方、斜上方、上表面都可以，只要居于物体水平之上即可；“靠近”是指代图中物体两侧中，与另一物体距离更近的一侧。以上方位或位置关系仅是为了便于描述本申请和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本申请的限制。
另外，还需要说明的是，附图提供的仅仅是和本申请关系比较密切的结构，省略了一些与申请关系不大的细节，目的在于简化附图，使申请点一目了然，而不是表明实际中装置就是和附图一模一样，不作为实际中装置的限制。
本申请提供阵列基板，所述阵列基板包括但不限于以下实施例，所述阵列基板应用于显示面板。
在一实施例中，如图1所示，所述显示面板具有弯折区域，所述阵列基板00具有与所述弯折处区域对应的弯折区01，和位于所述弯折区01两侧的非弯折区02，所述阵列基板00包括：多个驱动单元100，所述多个驱动单元100设于所述非弯折区02；多条第一连接线200，所述多条第一连接线200设于所述弯折区01，每一所述第一连接线200连接位于所述多条第一连接线200两侧的两所述驱动单元100。
在一实施例中，所述阵列基板00还包括多条第二连接线，所述多条第二连接线位于所述非弯折区02，所述多条第二连接线用于连接位于所述弯折区01的所述多个驱动单元100，所述第一连接线200的宽度大于所述第二连接线的宽度。可以理解的，当位于所述弯折区01的所述第一连接线200弯曲时，所述第一连接线200的宽度越大，单位面积的所述第一连接线200受到的压力越小，故所述第一连接线200越不容易断裂。
进一步的，当所述第一连接线200的宽度一定时，可以将所述第一连接线200的轮廓制作为曲线形状。一方面，同理，通过增加所述第一连接线200的长度，可以增加所述第一连接线200的面积，单位面积的所述第一连接线200受到的压力越小，故所述第一连接线200越不容易断裂；另一方面，通过增加所述第一连接线200的轮廓长度，可以增加所述第一连接线200的分散程度，以提高所述第一连接线200的可弯折性。
在一实施例中，相邻的两所述第一连接线200之间的距离不小于3微米。可以理解的，由于所述第一连接线200的宽度较大，相邻的两所述第一连接线200之间的距离可能较小，此处限制相邻的两所述第一连接线200之间的距离不小于3微米，可以有效避免相邻的两所述第一连接线200之间发生短路，导致信号传输有误。
在一实施例中，如图2-3所示，每一所述第一连接线200上设置有多个开孔202。一方面，每一所述第一连接线200上的多个开孔202的排布路径可以和所述第一连接线200的轮廓形状一致。例如图2，所述第一连接线200的轮廓呈直线形状，所述多个开孔202沿着所述第一连接线200的轮廓形状排布为直线路径；又例如图3，所述第一连接线200的轮廓呈曲线形状，所述多个开孔202沿着所述第一连接线200的轮廓形状排布为曲线路径。另一方面，每一所述第一连接线200上的多个开孔202的形状或者大小可以相同或者不同，所述开孔202的形状可以为圆形、三角形、矩形或者其他形状。再一方面，每一所述第一连接线200上的所述开孔202的数量和排布间隔可以根据所述第一连接线200的尺寸和材料进行设置。
可以理解的，由于在所述第一连接线200中设置了所述开孔202，当所述第一连接线200受力弯曲时，若某处断裂，则所述开孔202可以防止断裂处的裂痕向两侧或者其中一侧延伸，可以降低所述第一连接线200断开的风险。
在一实施例中，如图4所示，所述显示面板具有显示区，所述阵列基板00具有与所述显示区对应的第一区域03；所述多个驱动单元100包括多个第一像素驱动单元101，所述多个第一像素驱动单元101设于所述第一区域03与所述非弯折区02的重叠区域，每一所述第一像素驱动单元101用于驱动对应的第一发光单元301，多个所述第一发光单元301均设于所述弯折区域01。
进一步的，所述第一发光单元301设于所述阵列基板00上方与所述弯折区域01且与所述第一区域03对应的区域。可以理解的，由于所述第一发光单元301设于所述弯折区域01中，为了方便驱动对应的第一发光单元301，可以将多个第一像素驱动单元101设于所述第一区域03与所述非弯折区02的重叠区域中，较为靠近所述弯折区域01的区域。
在一实施例中，如图4所示，所述多条第一连接线200包括第一子连接线203，所述第一子连接线203设于所述弯折区01，所述第一子连接线203连接位于所述第一子连接线203两侧的两所述第一像素驱动单元101。可以理解的，由于所述第一子连接线203设于所述弯折区01，为了增加所述第一子连接线203的抗弯折能力，所述第一子连接线203的设置方式可以参考上文中所述第一连接线200的相关描述。
在一实施例中，如图4所示，所述阵列基板00包括多条连接线201，每一所述连接线201连接对应的所述第一像素驱动单元101与对应的第一发光单元301，所述连接线201包括子连接线，所述子连接线位于所述弯折区01，所述子连接线的宽度大于所述第二连接线的宽度。
在一实施例中，所述子连接线上设置有多个开孔，所述子连接线的相关描述可以参考上文对所述第一连接线200的相关描述。
在一实施例中，如图5所示，多个驱动单元100还包括多个第二像素驱动单元102，所述多个第二像素驱动单元102设于所述第一区域03与所述非弯折区02的重叠区域，每一所述第二像素驱动单元102用于驱动对应的第二发光单元302，所述多个第二发光单元302设于所述非弯折区02（此处仅标注出下侧的第一区域03中第二发光单元302的分布情况）；所述第二连接线包括扫描线401和数据线402，所述扫描线401连接对应行的多个所述第一像素驱动单元101或者多个所述第二像素驱动单元102，所述数据线402连接对应列的多个所述第一像素驱动单元101和多个所述第二像素驱动单元102（此处仅标注出上侧的扫描线401和数据线402的分布情况）。
另外的，所述第二连接线还包括EM线、VDD线。具体的，所述EM线与所述扫描线401平行且交错设置，所述EM线传输EM信号，所述EM信号用于控制对应的列发光单元，进一步的，每一所述EM线可以连接一或两行对应的多个所述第一像素驱动单元101和/或多个所述第二像素驱动单元102；所述VDD线与所述数据线402平行且交错设置，所述VDD线传输电压信号，所述电压信号用于提供对应的开关元件的工作电压，进一步的，每一所述VDD线可以连接一列对应的多个所述第一像素驱动单元101和多个所述第二像素驱动单元102。
其中，所述扫描线401和所述EM线可以为采用钼制作的单层金属层，所述数据线402和所述VDD线可以为采用“钛-铝-钛”制作的复合层金属层。
进一步的，所述第二发光单元302设于所述阵列基板00上方与所述非弯折区域02且与所述第一区域03对应的区域。其中，与所述弯折区域01相对设置的所述第一发光单元301、以及与所述非弯折区域02相对设置的所述第二发光单元302共同构成全部的发光单元，以进行画面显示。可以理解的，由于所述第一像素驱动单元101和所述第二像素驱动单元102仅位于所述非弯折区域02中，而所述第一发光单元301和所述第二发光单元302均匀地设于整个所述第一区域03中，故所述第一像素驱动单元101和所述第二像素驱动单元102的分布相对于现有技术而言，密度较大。
其中，所述第一像素驱动单元101和所述第二像素驱动单元102可以以相同的密度和相同的排布方式、不做区分的、均匀地分布于所述非弯折区域02和所述非弯折区02的重叠区域；或者所述第一像素驱动单元101的排布密度可以大于所述第二像素驱动单元102的排布密度，以便于每一发光单元与对应的像素驱动单元的连接。
在一实施例中，如图6-8所示，所述阵列基板00还具有第二区域04，所述第二区域04包围所述第一区域03；所述多个驱动单元100还包括多个栅极驱动单元103，所述多个栅极驱动单元103设于所述第二区域04与所述非弯折区02的重叠区域，每一所述栅极驱动单元103连接对应行的多个所述第一像素驱动单元101，以驱动对应的多个所述第一发光单元301，或者每一所述栅极驱动单元103连接对应行的多个所述第二像素驱动单元102，以驱动对应的多个所述第二发光单元302。
可以理解的，如图6-7所示，当所述弯折区01垂直于所述阵列基板00的左边界或者右边界时，由于所述扫描线401沿着行的方向延伸行、且沿着列的方向排布，且每一所述栅极驱动单元103连接一对应的扫描线401，故所述多个栅极驱动单元103也应该沿着列的方向排布（此处仅标注出下侧的第二区域04中栅极驱动单元103的分布情况），故需要考虑到将所述栅极驱动单元103避开所述弯折区01而设置。例如图6，所述多个栅极驱动单元103可以设置在所述显示区03的右侧，进一步的，所述栅极驱动单元103与所述扫描线401一一对应设置，保持分布密度一致；进一步的，当每一所述栅极驱动单元103的面积较大时，为避免相邻的所述栅极驱动单元103相互干扰，例如图7，可以将所述多个栅极驱动单元103设置在所述显示区03的左侧和右侧，例如位于所述显示区03的右侧的所述栅极驱动单元103连接对应的奇数列的扫描线401，位于所述显示区03的左侧的所述栅极驱动单元103连接对应的偶数列的扫描线401。
在一实施例中，如图6-7所示，所述多条第一连接线200包括第二子连接线204，所述第二子连接线204设于所述弯折区01，所述第二子连接线204连接位于所述第二子连接线204两侧的两所述栅极驱动单元103。可以理解的，由于所述第二子连接线204设于所述弯折区01，为了增加所述第二子连接线204的抗弯折能力，所述第二子连接线204的设置方式可以参考上文中所述第一连接线200的相关描述。
需要注意的，多条所述第二子连接线204、以及位于任一所述非弯折区02中任意相邻两所述栅极驱动单元103之间的多条连接线，各自可以包括分别用于传输第一时钟信号、第二时钟信号、正电压信号、负电压信号和上级输入信号的线路，只是所述第二子连接线204中的线路的形态与位于任一所述非弯折区02中任意相邻两所述栅极驱动单元103之间的线路的形态不同。其中，所述第一时钟信号和所述第二时钟信号可以用于同步所述多个栅极驱动单元103，所述正电压信号和所述负电压信号可以用于向所述多个栅极驱动单元103提供正电压信号或者负电压信号，所述上级输入信号可以表示上一级的栅极驱动单元103的输出信号以及本级栅极驱动单元103的输入信号。
需要注意的是，如图8所示，当所述弯折区01平行于所述阵列基板00的左边界或者右边界时，由于所述扫描线401沿着行的方向延伸行、且沿着列的方向排布，且每一所述栅极驱动单元103连接一对应的扫描线401，故所述多个栅极驱动单元103也应该沿着列的方向排布（此处仅标注出左侧的第二区域04中栅极驱动单元103的分布情况）。观察图7可知，此时所述多个栅极驱动单元103设置在所述阵列基板00的左侧和/或右侧，不需要考虑避免所述弯折区01而设置，且所述阵列基板00的左侧和/或右侧的所述多个栅极驱动单元103在列的方向的数量与所有的像素驱动单元在列的方向的数量相同，故所述栅极驱动单元103的分布密度与像素驱动单元在列的方向的分布密度可以相同。
本申请提供了阵列基板和显示面板，所述显示面板具有弯折区域，所述阵列基板具有与所述弯折区域对应的弯折区，和位于所述弯折区两侧的非弯折区，通过将多个驱动单元设于所述非弯折区，并在所述弯折区设置多条第一连接线，连接位于所述多条第一连接线两侧的两所述驱动单元。该方案避免了在弯折区设置驱动单元等较为复杂的电路，降低了折叠区的电路走线断裂的风险，提高了OLED折叠显示面板的弯折性能。
以上对本申请实施例所提供的阵列基板和显示面板的结构进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种阵列基板，应用于显示面板，其中，所述显示面板具有弯折区域，所述阵列基板具有与所述弯折区域对应的弯折区，和位于所述弯折区两侧的非弯折区，所述阵列基板包括：
    多个驱动单元，所述多个驱动单元设于所述非弯折区；
    多条第一连接线，所述多条第一连接线设于所述弯折区，每一所述第一连接线连接位于所述第一连接线两侧的两所述驱动单元，每一所述第一连接线上设置有多个开孔；
    多条第二连接线，所述多条第二连接线位于所述非弯折区，每一所述第二连接线用于连接位于所述弯折区的所述多个驱动单元，所述第一连接线的宽度大于所述第二连接线的宽度。
  2. 如权利要求1所述的阵列基板，其中，相邻的两所述第一连接线之间的距离不小于3微米。
  3. 如权利要求1所述的阵列基板，其中，所述显示面板具有显示区，所述阵列基板具有与所述显示区对应的第一区域；
    所述多个驱动单元包括第一像素驱动单元，所述第一像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第一像素驱动单元用于驱动对应的第一发光单元，所述第一发光单元设于所述弯折区域。
  4. 如权利要求3所述的阵列基板，其中，所述多个驱动单元还包括第二像素驱动单元，所述第二像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第二像素驱动单元用于驱动对应的第二发光单元，所述第二发光单元设于所述非弯折区；
    所述第二连接线包括扫描线和数据线，所述扫描线连接对应行的多个所述第一像素驱动单元或者多个所述第二像素驱动单元，所述数据线连接对应列的多个所述第一像素驱动单元和多个所述第二像素驱动单元。
  5. 如权利要求3所述的阵列基板，其中，所述多条第一连接线包括：
    第一子连接线，所述第一子连接线设于所述弯折区，所述第一子连接线连接位于所述第一子连接线两侧的两所述第一像素驱动单元。
  6. 如权利要求3所述的阵列基板，其中，所述阵列基板还具有第二区域，所述第二区域包围所述第一区域；
    所述多个驱动单元还包括栅极驱动单元，所述栅极驱动单元设于所述第二区域与所述非弯折区的重叠区域，所述栅极驱动单元连接对应行的多个所述第一像素驱动单元，以驱动对应的多个所述第一发光单元，或者每一所述栅极驱动单元连接对应行的多个所述第二像素驱动单元，以驱动对应的多个所述第二发光单元。
  7. 如权利要求6所述的阵列基板，其中，所述多条第一连接线包括：
    第二子连接线，所述第二子连接线设于所述弯折区，所述第二子连接线连接位于所述第二子连接线两侧的两所述栅极驱动单元。
  8. 一种阵列基板，应用于显示面板，其中，所述显示面板具有弯折区域，所述阵列基板具有与所述弯折区域对应的弯折区，和位于所述弯折区两侧的非弯折区，所述阵列基板包括：
    多个驱动单元，所述多个驱动单元设于所述非弯折区；
    多条第一连接线，所述多条第一连接线设于所述弯折区，每一所述第一连接线连接位于所述第一连接线两侧的两所述驱动单元。
  9. 如权利要求8所述的阵列基板，其中，所述阵列基板还包括：
    多条第二连接线，所述多条第二连接线位于所述非弯折区，每一所述第二连接线用于连接位于所述弯折区的所述多个驱动单元，所述第一连接线的宽度大于所述第二连接线的宽度。
  10. 如权利要求8所述的阵列基板，其中，每一所述第一连接线上设置有多个开孔。
  11. 如权利要求9所述的阵列基板，其中，相邻的两所述第一连接线之间的距离不小于3微米。
  12. 如权利要求9所述的阵列基板，其中，所述显示面板具有显示区，所述阵列基板具有与所述显示区对应的第一区域；
    所述多个驱动单元包括第一像素驱动单元，所述第一像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第一像素驱动单元用于驱动对应的第一发光单元，所述第一发光单元设于所述弯折区域。
  13. 如权利要求12所述的阵列基板，其中，所述多个驱动单元还包括第二像素驱动单元，所述第二像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第二像素驱动单元用于驱动对应的第二发光单元，所述第二发光单元设于所述非弯折区；
    所述第二连接线包括扫描线和数据线，所述扫描线连接对应行的多个所述第一像素驱动单元或者多个所述第二像素驱动单元，所述数据线连接对应列的多个所述第一像素驱动单元和多个所述第二像素驱动单元。
  14. 如权利要求12所述的阵列基板，其中，所述多条第一连接线包括：
    第一子连接线，所述第一子连接线设于所述弯折区，所述第一子连接线连接位于所述第一子连接线两侧的两所述第一像素驱动单元。
  15. 如权利要求12所述的阵列基板，其中，所述阵列基板还具有第二区域，所述第二区域包围所述第一区域；
    所述多个驱动单元还包括栅极驱动单元，所述栅极驱动单元设于所述第二区域与所述非弯折区的重叠区域，所述栅极驱动单元连接对应行的多个所述第一像素驱动单元，以驱动对应的多个所述第一发光单元，或者每一所述栅极驱动单元连接对应行的多个所述第二像素驱动单元，以驱动对应的多个所述第二发光单元。
  16. 如权利要求15所述的阵列基板，其中，所述多条第一连接线包括：
    第二子连接线，所述第二子连接线设于所述弯折区，所述第二子连接线连接位于所述第二子连接线两侧的两所述栅极驱动单元。
  17. 一种显示面板，其中，所述显示面板包括阵列基板，所述显示面板具有弯折区域，所述阵列基板具有与所述弯折区域对应的弯折区，和位于所述弯折区两侧的非弯折区，所述阵列基板包括：
    多个驱动单元，所述多个驱动单元设于所述非弯折区；
    多条第一连接线，所述多条第一连接线设于所述弯折区，每一所述第一连接线连接位于所述第一连接线两侧的两所述驱动单元。
  18. 如权利要求17所述的显示面板，其中，所述阵列基板还包括：
    多条第二连接线，所述多条第二连接线位于所述非弯折区，每一所述第二连接线用于连接位于所述弯折区的所述多个驱动单元，所述第一连接线的宽度大于所述第二连接线的宽度。
  19. 如权利要求18所述的阵列基板，其中，所述显示面板具有显示区，所述阵列基板具有与所述显示区对应的第一区域；
    所述多个驱动单元包括第一像素驱动单元，所述第一像素驱动单元设于所述第一区域与所述非弯折区的重叠区域，所述第一像素驱动单元用于驱动对应的第一发光单元，所述第一发光单元设于所述弯折区域。
  20. 如权利要求19所述的阵列基板，其中，所述多条第一连接线包括：
    第一子连接线，所述第一子连接线设于所述弯折区，所述第一子连接线连接位于所述第一子连接线两侧的两所述第一像素驱动单元。
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