WO2021258828A1 - 薄膜晶体管阵列基板、显示面板和显示装置 - Google Patents

薄膜晶体管阵列基板、显示面板和显示装置 Download PDF

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WO2021258828A1
WO2021258828A1 PCT/CN2021/088315 CN2021088315W WO2021258828A1 WO 2021258828 A1 WO2021258828 A1 WO 2021258828A1 CN 2021088315 W CN2021088315 W CN 2021088315W WO 2021258828 A1 WO2021258828 A1 WO 2021258828A1
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Prior art keywords
layer
array substrate
thin film
film transistor
transistor array
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French (fr)
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朱正勇
赵欣
胡双
马志丽
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Kunshan Govisionox Optoelectronics Co Ltd
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Kunshan Govisionox Optoelectronics Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0312—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes
    • H10D30/0314—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] characterised by the gate electrodes of lateral top-gate TFTs comprising only a single gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
    • H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0221—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or patterning of TFT semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs

Definitions

  • This application belongs to the field of display technology, and specifically relates to a thin film transistor array substrate, a display panel, and a display device.
  • OLED Organic Light Emitting Diode
  • OLED Organic Light Emitting Diode
  • AMOLED Active Matrix Organic Light Emitting Diode
  • the present application provides a thin film transistor (TFT) array substrate, a display panel, and a display device that can reduce the afterimage phenomenon.
  • TFT thin film transistor
  • the first aspect of the present application provides a TFT array substrate, which includes a stacked semiconductor layer, a gate layer, and a source-drain layer, and between the semiconductor layer and the gate layer, and between the gate layer and the source-drain layer Separately separated by insulating layers, the semiconductor layer includes a source region, a drain region, and a channel region located between the source region and the drain region.
  • the channel region is doped with P-type impurities with a molecular weight ⁇ 25 and doped
  • the depth is 1nm-20nm
  • the gate layer includes the gate, the gate is arranged correspondingly to the channel region, the source-drain layer includes the source and drain arranged at intervals, the source is electrically connected to the source region, and the drain and the drain The polar regions are electrically connected.
  • a second aspect of the present application provides a display panel, which includes the TFT array substrate as in the first aspect of the present application.
  • a third aspect of the present application provides a display device, which includes the display panel as in the second aspect of the present application.
  • the application of this application is to dope P-type impurities with a molecular weight ⁇ 25 in the channel region of the semiconductor layer of the TFT array substrate, and control the doping depth to be 1 nm to 20 nm, so that the different TFTs in the TFT array substrate It has high electrical consistency and stability. Therefore, the use of the TFT array substrate can effectively reduce the afterimage phenomenon of the display panel and the display device, improve the uniformity of the display, and thereby improve the display effect.
  • FIG. 1 is a schematic structural diagram of a TFT array substrate provided by an embodiment of the application.
  • FIG. 2 is a step diagram of forming an initial semiconductor layer in a method for preparing a TFT array substrate provided by an embodiment of the application.
  • FIG. 3 is a step diagram of doping P-type impurities in an initial semiconductor layer in a method for preparing a TFT array substrate provided by an embodiment of the application.
  • FIG. 4 is a step diagram of forming an initial semiconductor layer doped with P-type impurities in a method for preparing a TFT array substrate provided by an embodiment of the application.
  • FIG. 5 is a step diagram of forming a gate layer in a method for preparing a TFT array substrate provided by an embodiment of the application.
  • FIG. 6 is a step diagram of forming a semiconductor layer in a method for manufacturing a TFT array substrate provided by an embodiment of the application.
  • FIG. 7 is a step diagram of forming an internal insulating layer and via holes in a method for manufacturing a TFT array substrate provided by an embodiment of the application.
  • Fig. 8 is a step diagram of forming a source and drain layer in a method for manufacturing a TFT array substrate provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a display panel provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of a display device provided by an embodiment of the application.
  • FIG. 11 is a schematic diagram of the display effect of the display panel of Embodiment 1.
  • FIG. 11 is a schematic diagram of the display effect of the display panel of Embodiment 1.
  • FIG. 12 is a schematic diagram of the display effect of the display panel of Comparative Example 1.
  • FIG. 12 is a schematic diagram of the display effect of the display panel of Comparative Example 1.
  • Each TFT in the thin film transistor (TFT) array substrate can "actively" control each independent pixel of the (AM)OLED display device to achieve the purpose of display.
  • the Demura function can be used to solve the problem, but Demura cannot improve the image retention caused by the display process.
  • the poor image retention (such as short-term image retention) of (AM)OLED display devices can be reduced by optimizing the channel doping of the TFT.
  • the embodiment of the first aspect of the present application provides a thin film transistor (TFT).
  • the thin film transistor is a P-channel TFT, which includes a stacked semiconductor layer, a gate layer and a source-drain layer, and the semiconductor layer and the gate layer, and between the gate layer and the source-drain layer pass through The insulating layers are spaced apart.
  • the semiconductor layer includes a source region, a drain region, and a channel region between the source region and the drain region.
  • the channel region is doped with P-type impurities with a molecular weight ⁇ 25, and the doping depth is 1 nm to 20 nm.
  • the gate layer includes a gate, and the gate is arranged corresponding to the channel region.
  • the source-drain layer includes a source electrode and a drain electrode arranged at intervals, the source electrode is electrically connected with the source electrode area, and the drain electrode is electrically connected with the drain area.
  • the TFT in the TFT array substrate can have higher electrical properties (such as threshold voltage, sub- Threshold swing, etc.) Consistency and stability. Therefore, the use of the TFT array substrate can effectively reduce the afterimage phenomenon of the display panel and the display device, improve the uniformity of the display, and thereby improve the display effect.
  • the TFT may be a top gate type TFT.
  • Fig. 1 shows a top-gate TFT 100 as an example.
  • the TFT 100 includes a semiconductor layer 10, a gate insulating layer 41, a gate layer 20, an internal insulating layer 42, and a source-drain layer 30 stacked in sequence.
  • the semiconductor layer 10 includes a source region 11, a drain region 12, and a channel region 13 located between the source region 11 and the drain region 12.
  • the channel region 13 is doped with P-type impurities with a molecular weight ⁇ 25, and the doping depth is 1 nm-20 nm.
  • the gate layer 20 includes a gate 21, and the gate 21 is arranged corresponding to the channel region 13.
  • the source-drain layer 30 includes a source electrode 31 and a drain electrode 32 arranged at intervals.
  • the source electrode 31 is electrically connected to the source region 11, and the drain electrode 32 is electrically connected to the drain region 12.
  • the doping depth of the channel region 13 doped with P-type impurities may be 2 nm to 18 nm, 3 nm to 15 nm, 4 nm to 12 nm, or 5 nm to 10 nm.
  • the thickness of the channel region 13 is, for example, 40 nm to 55 nm, for example, 40 nm to 45 nm, or 45 nm to 55 nm; such as 45 nm.
  • the doping depth of the P-type impurities in the channel region 13 is 1 nm-20 nm, and the P-type impurities are mainly doped in the surface layer 131 of the channel region 13.
  • this does not exclude the presence of a small number of P-type impurities in the depth range of the channel region 13 greater than 20 nm, but the P-type impurity content in the depth range of the channel region 13 greater than 20 nm is substantially close to the non-doped state.
  • the P-type impurity doping concentration of the channel region 13 may be 3 ⁇ 10 11 cm -2 -2 ⁇ 10 12 cm -2 , or 5 ⁇ 10 11 cm -2 -1 ⁇ 10 12 cm -2 .
  • the doping concentration of P-type impurities in the channel region 13 is within an appropriate range, which can improve the electron transport characteristics of the TFT, increase the stability of the TFT array substrate 100, and help reduce short-term image retention and improve the display effect.
  • the doping of the channel region 13 usually adopts an ion implantation process.
  • the implantation depth of the commonly used P-type impurity B in terms of the peak concentration of B
  • the implantation depth of B is still deep (about 36nm).
  • the industry has changed the doping of the channel region 13 to be performed after the formation of the gate insulating layer 41, which can control the doping distribution of B in the polysilicon layer (including the implantation depth) to a certain extent, but this will give the gate
  • the insulating layer 41 brings unavoidable damage, which affects the display effect and the life of the device.
  • the molecular weight of the P-type impurities is ⁇ 25, ⁇ 29, or ⁇ 45.
  • the molecular weight of the P-type impurity can be 25-200, 29-120, 29-85, or 45-50.
  • the P-type impurity can be selected from one or more of indium, BF, and BF 2 , further can be selected from one or more of BF, BF 2 , and further can be selected from BF 2 .
  • P-type impurities are beneficial to control the doping distribution (for example, the doping depth) in the channel region 13.
  • the use of F-containing P-type impurities for channel doping can form more stable Si-F bonds to repair the Si dangling bonds in the channel region 13, thereby further improving the stability of the TFT, thereby further reducing short-term residuals. Shadow phenomenon.
  • the semiconductor layer 10 may include one or more of amorphous silicon (a-Si) and P-Si. Further, the semiconductor layer 10 may be a polysilicon film layer. Furthermore, the semiconductor layer 10 may be a low temperature polysilicon (LTPS) film layer. The use of a suitable semiconductor layer 10 can improve the stability of the TFT and help improve short-term image retention of the display device.
  • a-Si amorphous silicon
  • P-Si amorphous silicon
  • the semiconductor layer 10 may be a polysilicon film layer.
  • the semiconductor layer 10 may be a low temperature polysilicon (LTPS) film layer.
  • LTPS low temperature polysilicon
  • the stability of the TFT can be further improved by controlling the particle size and hydrogen content of P-Si.
  • the particle size of the polycrystalline silicon in the polycrystalline silicon film layer is 0.2 ⁇ m ⁇ 0.4 ⁇ m, or 0.2 ⁇ m ⁇ 0.3 ⁇ m.
  • the hydrogen content (atomic percentage) of the polysilicon film layer is 0.01% to 3%, 0.01% to 2%, 0.1% to 3%, 0.1% to 2%, or 0.05% to 1.5%.
  • the insulating layer between the semiconductor layer 10 and the gate layer 20 is selected with an appropriate film quality composition, which is beneficial to improve the stability of the TFT.
  • the gate insulating layer 41 may include one or more of silicon oxide, silicon nitride, and silicon-based oxynitride. Further, the gate insulating layer 41 includes silicon oxide, or the gate insulating layer 41 is a silicon oxide film layer.
  • the gate layer 20 can be made of gate materials known in the art.
  • the gate layer 20 may include one or more of titanium, molybdenum, gold, platinum, aluminum, nickel, copper, and two or more alloys thereof.
  • the gate layer 20 may be a composite layer of two or more metal layers and/or alloy layers.
  • the source and drain layer 30 can be made of gate materials known in the art.
  • the source and drain layer 30 may include one or more of titanium, molybdenum, gold, platinum, aluminum, nickel, copper, and two or more alloys thereof.
  • the source and drain layer 30 may be a composite layer of two or more metal layers and/or alloy layers.
  • the internal insulating layer 42 can be made of insulating materials known in the art.
  • the internal insulating layer 42 may include one or more of silicon oxide, silicon nitride, and silicon-based oxynitride.
  • the internal insulating layer 42 may be a composite layer including two or more of a silicon oxide layer, a silicon nitride layer, and a silicon-based oxynitride layer.
  • the manufacturing method of the TFT array substrate may include a step S100 of forming a semiconductor layer, a step S200 of forming a gate layer, and a step of forming a source-drain layer S300.
  • the manufacturing method of the TFT array substrate will be described in detail below with reference to FIGS. 2 to 8.
  • S100 includes: S110, forming an initial semiconductor layer 10' on a substrate 50.
  • the substrate 50 may be a glass substrate.
  • the initial semiconductor layer 10' may be a P-Si layer.
  • the step of forming the initial semiconductor layer 10' can be performed using methods and equipment known in the art.
  • PECVD plasma enhanced chemical vapor deposition
  • a dehydrogenation treatment is performed at 400°C to 500°C (such as 450°C) to control the hydrogen content;
  • ELA excimer laser annealing
  • the P-Si film is etched to form a polysilicon pattern (such as using photoresist as a mask, using a dry method) Etching) to obtain a P-Si layer.
  • HF and ozone can also be used to clean the amorphous silicon layer.
  • Surface particles can be removed by cleaning, and SiO is formed on the surface of the amorphous silicon layer at the same time, which is beneficial to the subsequent ELA process.
  • a buffer layer 60 may also be formed on the substrate 50, and then the initial semiconductor layer 10' is formed on the buffer layer 60.
  • the buffer layer 60 may be a silicon oxide layer, a silicon nitride layer, or a composite layer of a silicon oxide layer and a silicon nitride layer.
  • the buffer layer 60 can be formed using methods and equipment known in the art. For example, the chemical vapor deposition (CVD) method, and then the PECVD method.
  • S100 also includes: S120, performing P-type impurity doping on the initial semiconductor layer 10'.
  • the P-type impurity may be as described herein.
  • An ion implantation process can be used to implant P-type impurities into the initial semiconductor layer 10' (as shown in FIG. 3).
  • the energy of ion implantation can be 5keV-20keV, or 8keV-15keV, or 10keV-15keV, or 10keV-12keV.
  • Dose of ion implantation may be 3 ⁇ 10 11 cm -2 ⁇ 2 ⁇ 10 12 cm -2, or 5 ⁇ 10 11 cm -2 ⁇ 1 ⁇ 10 12 cm - 2.
  • the gas source for ion implantation is, for example, BF 3 .
  • the currently used BF 3 can be used as the ion implantation gas source, so that only the magnetic field of the ion implantation device needs to be changed to select suitable ions for implantation without additional process cost.
  • P-type impurities are basically doped in the surface layer 131' of the initial semiconductor layer 10' (as shown in FIG. 4). That is, S120 makes the surface layer 131 mainly doped with P-type impurities in the channel region 13 of the semiconductor layer 10.
  • the gate layer 20 is formed first, that is, S200 is implemented.
  • S200 includes: S210, forming a gate insulating layer 41 on the initial semiconductor layer 10' doped with P-type impurities.
  • the gate insulating layer 41 can be formed using methods and equipment known in the art. For example, the chemical vapor deposition (CVD) method, and then the PECVD method.
  • CVD chemical vapor deposition
  • S200 further includes: S220, forming the gate layer 20.
  • the gate film can be formed using methods and equipment known in the art, such as a physical vapor deposition (PVD) method, and further, for example, a sputtering method.
  • PVD physical vapor deposition
  • the gate film is then patterned to form a gate layer 20 (as shown in FIG. 5).
  • a cleaning step of the initial semiconductor layer 10' is further included.
  • ozone and HF can be used for cleaning to remove the oxide layer on the surface of the initial semiconductor layer 10' and planarize the initial semiconductor layer 10'.
  • the preparation of the semiconductor layer 10 is continued to be completed. That is, S130, using the gate layer 20 as a mask, do P-type impurity doping on both sides of the initial semiconductor layer 10' to form the source region 11 and the drain region 12, respectively, to obtain the semiconductor layer 10 (as shown in FIG. Show).
  • the P-type impurity may be selected from indium, B, BF 2 and the like, such as B.
  • An ion implantation process may be used to implant P-type impurities into the initial semiconductor layer 10'.
  • the dose of ion implantation may be 5 ⁇ 10 14 cm -2 to 2 ⁇ 10 15 cm -2 .
  • the energy of ion implantation can be 10keV-40keV.
  • the gas source for ion implantation is, for example, BF 3 .
  • an internal insulating layer 42 is formed on the gate layer 20.
  • the internal insulating layer 42 can be formed using methods and equipment known in the art. For example, the chemical vapor deposition (CVD) method, and then the PECVD method.
  • CVD chemical vapor deposition
  • PECVD PECVD
  • via holes 33 corresponding to the source region 11 and the drain region 12 are formed on the inner insulating layer 42 and the gate insulating layer 41 (as shown in FIG. 7).
  • the via 33 may be formed by using methods and equipment known in the art. For example, using photoresist as a mask, dry etching is used to form the via 33.
  • the source and drain films can be formed by methods and equipment known in the art, such as a physical vapor deposition (PVD) method, and further, for example, a sputtering method.
  • PVD physical vapor deposition
  • the source and drain films extend into the via 33 and are electrically connected to the source region 11 and the drain region 12 respectively.
  • the source and drain film is patterned to form a source and drain layer 30 (as shown in FIG. 8).
  • a planarization layer 70, an electrode layer and a pixel definition layer 80 can be further formed on the source and drain layer 30 in sequence (as shown in FIG. 9).
  • the TFT array substrate may further include a storage capacitor area 90.
  • the storage capacitor region 90 includes a first electrode 91 and a second electrode 92, wherein the first electrode 91 and the second electrode 92 are separated by a capacitor dielectric layer 422.
  • the first electrode 91 and the second electrode 92 may each independently include one or more of titanium, molybdenum, gold, platinum, aluminum, nickel, copper, and two or more alloys thereof.
  • the capacitor dielectric layer 422 may include one or more of silicon oxide, silicon nitride, and silicon-based oxynitride, such as silicon nitride.
  • the first electrode 91 may be located on the gate layer 20.
  • the gate 21 is obtained and the first electrode 91 is formed at the same time.
  • the second electrode 92 can be formed using methods and equipment known in the art. For example, a physical vapor deposition (PVD) method (such as a sputtering method) is used to form the electrode film, and then the electrode film is patterned to form the second electrode 92.
  • PVD physical vapor deposition
  • the inner insulating layer 42 may include an interlayer insulating layer 421 and a capacitor dielectric layer 422, wherein the interlayer insulating layer 421 and the capacitor dielectric layer 422 isolate the gate layer 20 and the source and drain layers 30, and the capacitor dielectric layer 422 separates the first One electrode 91 is separated from the second electrode 92, and the interlayer insulating layer 421 separates the second electrode 92 from the source and drain layer 30.
  • the interlayer insulating layer 421 may include one or more of silicon oxide, silicon nitride, and silicon-based oxynitride.
  • the interlayer insulating layer 421 may be a composite layer including two or more of a silicon oxide layer, a silicon nitride layer, and a silicon-based oxynitride layer.
  • the capacitor dielectric layer 422 can be as described above.
  • TFT array substrate of the present application are also applicable to the manufacturing method of the present application, and will not be repeated here.
  • the application also provides a display panel, which includes any TFT array substrate of the application.
  • the display panel of the present application adopts the TFT array substrate of the present application, the afterimage phenomenon is small and the display uniformity is better.
  • FIG. 9 shows the display panel 1 as an example.
  • the display panel 1 includes a TFT array substrate 100, an organic light emitting display module 200 on the TFT array substrate 100, and an encapsulation layer 300 on the organic light emitting display module 200.
  • the TFT array substrate 100 may be any TFT array substrate described herein.
  • the organic light emitting display module 200 sequentially includes a first electrode layer 210, an organic thin film layer 220, and a second electrode layer 230, and the organic thin film layer 220 includes at least a light emitting layer.
  • the light-emitting layer may include organic light-emitting materials known in the art. Further, the organic light-emitting material may include a host material and a guest material.
  • the organic thin film layer 220 may also include other functional layers.
  • an electron injection layer for example, an electron transport layer, a hole blocking layer, an electron blocking layer, a hole transport layer, a hole injection layer, and the like.
  • materials known in the art can be used.
  • the present application also provides a display device, which includes any display panel of the present application.
  • the display device of the present application adopts the display panel of the present application, that is, it includes the TFT array substrate of the present application, the display defects of the display device are relatively small, and the display effect is better.
  • Examples of display devices may be mobile phones, tablet computers, smart learning machines, and so on.
  • FIG. 10 shows the display device 2 as an example.
  • the display device may be a mobile phone.
  • An OLED display panel includes a TFT array substrate and an organic light emitting display module on the TFT array substrate.
  • the organic light emitting display module sequentially includes a cathode layer, an electron injection layer, an electron transport layer, a hole blocking layer, a light emitting layer, an electron blocking layer, a hole transport layer, a hole injection layer, an anode layer, and a capping layer.
  • the TFT array substrate includes a substrate, a buffer layer, a semiconductor layer (P-Si layer), a gate insulating layer, a gate layer, an internal insulating layer, and a source and drain layer which are stacked in sequence.
  • the semiconductor layer includes a source region, a drain region, and a channel region located between the source region and the drain region.
  • the surface layer of the channel region close to the gate layer is doped with BF 2 and the doping depth is 10 nm.
  • the gate layer includes a gate, and the gate is arranged corresponding to the channel region.
  • the source drain layer includes a source electrode and a drain electrode arranged at intervals, the source electrode is electrically connected with the source electrode area, and the drain electrode is electrically connected with the drain area.
  • the ion implantation energy of doped BF 2 is 10keV
  • the implantation dose is 8 ⁇ 10 11 cm -2 .
  • the TFT array substrate also includes a storage capacitor.
  • the difference is that the P-type impurity in the channel region is B.
  • FIG. 11 and FIG. 12 The display effects of switching from images with different brightness to the same gray scale in Example 1 and Comparative Example 1 are shown in FIG. 11 and FIG. 12, respectively. It can be seen from FIG. 11 that, with the TFT array substrate of the present application, the display effect of the display panel is better without obvious residual image defects. It can be seen from FIG. 12 that the display panel of Comparative Example 1 has obvious residual image phenomenon.

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Abstract

一种薄膜晶体管阵列基板（100）、显示面板（1）和显示装置（2）。薄膜晶体管阵列基板（100）包括层叠设置的半导体层（10）、栅极层（20）和源漏极层（30），且半导体层（10）与栅极层（20）之间、以及栅极层（20）和源漏极层（30）之间分别通过绝缘层相间隔，半导体层（10）包括源极区（11）、漏极区（12）和位于源极区（11）和漏极区（12）之间的沟道区（13），沟道区（13）掺杂有分子量≥25的P型杂质，且掺杂深度为1nm～20nm。

Description

薄膜晶体管阵列基板、显示面板和显示装置
相关申请的交叉引用
本申请要求享有于2020年06月22日提交的名称为“薄膜晶体管阵列基板及其制备方法、显示面板和显示装置”的中国专利申请202010572184.4的优先权，该申请的全部内容通过引用并入本文中。
技术领域
本申请属于显示技术领域，具体涉及一种薄膜晶体管阵列基板、显示面板和显示装置。
背景技术
有机发光二极管(Organic Light Emitting Diode，OLED)显示可具有视角宽、驱动电压低、响应速度快、发光色彩丰富、可实现大面积柔性显示等优点，是目前被广泛关注的显示技术之一。有源矩阵有机发光二极管(Active Matrix Organic Light Emitting Diode，AMOLED)显示技术是起源于OLED的一种显示技术，其具有自发光、功耗低、可实现更大尺寸化等特点，在显示技术领域得到了高度重视。
然而，当(AM)OLED显示面板的不同区域像素电路工作在不同亮度画面显示一段时间后，切换到相同灰阶时，不同区域亮度会产生差异，即表现为残影不良，严重影响视觉效果。
申请内容
为了解决上述技术问题，本申请提供一种能减轻残影现象的薄膜晶体管(Thin Film Transistor，TFT)阵列基板、显示面板和显示装置。
本申请第一方面提供一种TFT阵列基板，其包括层叠设置的半导体层、栅极层和源漏极层，且半导体层与栅极层之间、以及栅极层和源漏极层之 间分别通过绝缘层相间隔，半导体层包括源极区、漏极区和位于源极区和漏极区之间的沟道区，沟道区掺杂有分子量≥25的P型杂质，且掺杂深度为1nm～20nm，栅极层包括栅极，栅极与沟道区对应设置，源漏极层包括相间隔设置的源极和漏极，源极与源极区电连接，漏极与漏极区电连接。
本申请第二方面提供一种显示面板，其包括如本申请第一方面的TFT阵列基板。
本申请第三方面提供一种显示装置，其包括如本申请第二方面的显示面板。
令人惊奇地发现，本申请通过在TFT阵列基板的半导体层的沟道区掺杂分子量≥25的P型杂质，且控制掺杂深度为1nm～20nm，能使TFT阵列基板中的不同TFT之间具有较高的电性一致性和稳定性。因此，采用该TFT阵列基板能有效降低显示面板和显示装置的残影现象，改善显示的均一性，从而提高显示效果。
附图说明
图1为本申请实施例提供的一种TFT阵列基板的结构示意图。
图2为本申请实施例提供的一种TFT阵列基板制备方法中形成初始半导体层的步骤图。
图3为本申请实施例提供的一种TFT阵列基板制备方法中初始半导体层掺杂P型杂质的步骤图。
图4为本申请实施例提供的一种TFT阵列基板制备方法中形成掺杂有P型杂质的初始半导体层的步骤图。
图5为本申请实施例提供的一种TFT阵列基板制备方法中形成栅极层的步骤图。
图6为本申请实施例提供的一种TFT阵列基板制备方法中形成半导体层的步骤图。
图7为本申请实施例提供的一种TFT阵列基板制备方法中形成内部绝缘层和过孔的步骤图。
图8为本申请实施例提供的一种TFT阵列基板制备方法中形成源漏极 层的步骤图。
图9为本申请实施例提供的一种显示面板的结构示意图。
图10为本申请实施例提供的一种显示装置的结构示意图。
图11为实施例1的显示面板的显示效果示意图。
图12为对比例1的显示面板的显示效果示意图。
具体实施方式
为了使本申请的发明目的、技术方案和有益技术效果更加清晰，以下结合实施例对本申请进行进一步详细说明。应当理解的是，本说明书中描述的实施例仅仅是为了解释本申请，并非为了限定本申请。
薄膜晶体管(TFT)阵列基板中的各个TFT可以“主动地”对(AM)OLED显示器件的各个独立的像素进行控制，达到显示的目的。发明人发现，(AM)OLED显示器件的显示不均较大程度上是由于TFT阵列基板的TFT特性差异所引起。对于因工艺导致的TFT电性不均引起的显示不均(mura)，可通过Demura功能解决，但Demura无法改善因显示过程中引起的残影不良。
可以通过优化TFT的沟道掺杂来降低(AM)OLED显示器件的残影不良(如短期残影)现象。
因此，本申请第一方面的实施方式提供一种薄膜晶体管(TFT)。该薄膜晶体管为P型沟道TFT，其包括层叠设置的半导体层、栅极层和源漏极层，且半导体层与栅极层之间、以及栅极层和源漏极层之间分别通过绝缘层相间隔。半导体层包括源极区、漏极区和位于源极区和漏极区之间的沟道区。沟道区掺杂有分子量≥25的P型杂质，且掺杂深度为1nm～20nm。栅极层包括栅极，栅极与沟道区对应设置。源漏极层包括相间隔设置的源极和漏极，源极与源极区电连接，漏极与漏极区电连接。
通过在TFT的半导体层的沟道区掺杂分子量≥25的P型杂质，且控制掺杂深度为1nm～20nm，能使TFT阵列基板中的TFT具有较高的电性(例如阈值电压、亚阈值摆幅等)一致性和稳定性。因此，采用该TFT阵列基板能有效降低显示面板和显示装置的残影现象，改善显示的均一性， 从而提高显示效果。
在一些实施方式中，TFT可以是顶栅型TFT。图1示出作为一个示例的顶栅型TFT 100。参照图1，该TFT 100包括依次层叠设置的半导体层10、栅极绝缘层41、栅极层20、内部绝缘层42和源漏极层30。半导体层10包括源极区11、漏极区12和位于源极区11和漏极区12之间的沟道区13。沟道区13掺杂有分子量≥25的P型杂质，且掺杂深度为1nm～20nm。栅极层20包括栅极21，栅极21与沟道区13对应设置。源漏极层30包括相间隔设置的源极31和漏极32，源极31与源极区11电连接，漏极32与漏极区12电连接。
在任意的实施方式中，沟道区13掺杂P型杂质的掺杂深度可以为2nm～18nm、3nm～15nm、4nm～12nm、或5nm～10nm。通过调控沟道区13的掺杂深度，能有效提高不同TFT的电性一致性和稳定性，从而使得(AM)OLED由不同灰阶向同一灰阶切换时的发光亮度基本一致，减轻短期残影现象。沟道区13的厚度例如为40nm～55nm，再例如40nm～45nm、或45nm～55nm；如45nm。
需要说明的是，沟道区13中P型杂质的掺杂深度在1nm～20nm，P型杂质主要掺杂于沟道区13的表面层131。但这并不排除在沟道区13大于20nm的深度范围内存在少数的P型杂质，而是在沟道区13大于20nm的深度范围内的P型杂质含量基本上接近非掺杂的状态。
在任意的实施方式中，沟道区13的P型杂质掺杂浓度可以为3×10 11cm -2～2×10 12cm -2，或5×10 11cm -2～1×10 12cm -2。P型杂质在沟道区13的掺杂浓度在适当范围内，能改善TFT的电子运输特性，提高TFT阵列基板100的稳定性，有利于减轻短期残影现象，提高显示效果。
沟道区13的掺杂通常采用离子注入工艺。然而，由于受到离子注入设备和工艺的限制，导致常用的P型杂质B的注入深度(以B的峰值浓度计)难以得到有效控制。即使在较低的注入能量(10keV)下，B的注入深度仍较深(约36nm)。业界将沟道区13的掺杂改为在如栅极绝缘层41成膜之后进行，可以一定程度上控制B在多晶硅层中的掺杂分布(包括注入深度)，但是这样将会给栅极绝缘层41带来无法避免的损伤，影响显示效 果和器件寿命。
为了更好地控制P型杂质在沟道区13的掺杂分布(包括掺杂深度)，在本申请任意的实施方式中，P型杂质的分子量≥25，≥29，或≥45。例如，P型杂质的分子量可以为25～200，29～120，29～85，或45～50。作为示例，P型杂质可选自铟、BF、BF 2中的一种或多种，进一步可选自BF、BF 2中的一种或多种，更进一步可选自BF 2。
采用适当的P型杂质，有利于控制其在沟道区13中的掺杂分布(例如掺杂深度)。尤其是，使用含F的P型杂质进行沟道掺杂，能形成更稳定的Si-F键来修复沟道区13的Si悬挂键，由此进一步提高TFT的稳定性，从而进一步减轻短期残影现象。
在任意的实施方式中，半导体层10可包括非晶硅(a-Si)、P-Si中的一种或多种。进一步地，半导体层10可以为多晶硅膜层。更进一步地，半导体层10可以为低温多晶硅(LTPS)膜层。采用合适的半导体层10，能改善TFT的稳定性，有利于改善显示器件的短期残影。
本申请的TFT阵列基板中，当半导体层10为多晶硅膜层时，通过控制P-Si的颗粒大小、氢含量等，能进一步提高TFT的稳定性。
可选地，多晶硅膜层中多晶硅的颗粒粒径为0.2μm～0.4μm、或0.2μm～0.3μm。
可选地，多晶硅膜层的氢含量(原子百分数)为0.01％～3％、0.01％～2％、0.1％～3％、0.1％～2％、或0.05％～1.5％。
本申请的TFT阵列基板中，介于半导体层10和栅极层20之间的绝缘层(即栅极绝缘层41)选用适当的膜质成分，有利于提高TFT的稳定性。作为示例，栅极绝缘层41可包括硅氧化物、硅氮化物和硅基氮氧化物中的一种或多种。进一步地，栅极绝缘层41包括硅氧化物，或者栅极绝缘层41是硅氧化物膜层。
本申请的TFT阵列基板中，栅极层20可采用本领域已知的栅极材料。作为示例，栅极层20可包括钛、钼、金、铂、铝、镍、铜、以及它们的两种以上的合金中的一种或多种。进一步地，栅极层20可以是两种以上的金属层和/或合金层的复合层。
本申请的TFT阵列基板中，源漏极层30可采用本领域已知的栅极材料。作为示例，源漏极层30可包括钛、钼、金、铂、铝、镍、铜、以及它们的两种以上的合金中的一种或多种。进一步地，源漏极层30可以是两种以上的金属层和/或合金层的复合层。
本申请的TFT阵列基板中，内部绝缘层42可采用本领域已知的绝缘材料。作为示例，内部绝缘层42可包括硅氧化物、硅氮化物和硅基氮氧化物中的一种或多种。或者，内部绝缘层42可以为包括硅氧化物层、硅氮化物层和硅基氮氧化物层中的两种以上的复合层。
接下来提供一种TFT阵列基板的制造方法。根据该方法能制造得到上述的TFT阵列基板。该TFT阵列基板的制造方法可包括形成半导体层的步骤S100、形成栅极层的步骤S200、以及形成源漏极层S300的步骤。下面结合图2至图8，对TFT阵列基板的制造方法进行详细说明。
S100包括：S110，在衬底50上形成初始半导体层10’。衬底50可以是玻璃衬底。初始半导体层10’可以是P-Si层。
形成初始半导体层10’的步骤可采用本领域已知的方法和设备进行。例如，可采用等离子体增强化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)获得非晶硅层；之后在400℃～500℃(如450℃)的条件下进行去氢处理，以调控氢含量；再通过准分子激光退火法(excimer laser annealing，ELA)使非晶硅结晶，形成P-Si膜；然后对P-Si膜刻蚀形成多晶硅图案(如以光刻胶为掩膜，采用干法刻蚀)，得到P-Si层。可选地，在ELA工序之前，还可以采用HF、臭氧对非晶硅层进行清洗。通过清洗可以去除表面颗粒，同时在非晶硅层表面形成SiO，有利于后续的ELA工序。
在一些实施方式中，在形成初始半导体层10’之前，还可以在衬底50上形成缓冲层60，之后将初始半导体层10’形成于缓冲层60上。例如图2所示。缓冲层60可以是硅氧化物层、硅氮化物层、或者硅氧化物层和硅氮化物层的复合层。可采用本领域已知的方法和设备形成缓冲层60。例如化学气相沉积(CVD)法，再如PECVD法。
S100还包括：S120，对初始半导体层10’进行P型杂质掺杂。
在S120，P型杂质可以如本文所述。可采用离子注入工艺将P型杂质注入初始半导体层10’(如图3所示)。离子注入的能量可以为5keV～20keV，或8keV～15keV，或10keV～15keV，或10keV～12keV。离子注入的剂量可以为3×10 11cm -2～2×10 12cm -2，或5×10 11cm -2～1×10 12cm - 2。离子注入的气源例如是BF 3。本申请可采用现有使用的BF 3作为离子注入气源，由此只需变更离子注入设备的磁场来选择合适的离子进行注入，而无需额外增加工艺成本。S120，P型杂质基本上是掺杂于初始半导体层10’的表面层131’(如图4所示)。也即，S120使得在半导体层10的沟道区13，P型杂质主要掺杂于表面层131。
接下来，先形成栅极层20，即实施S200。
S200包括：S210，在掺杂有P型杂质的初始半导体层10’上形成栅极绝缘层41。可采用本领域已知的方法和设备形成栅极绝缘层41。例如化学气相沉积(CVD)法，再如PECVD法。
S200还包括：S220，形成栅极层20。可采用本领域已知的方法和设备形成栅极膜，例如物理气相沉积(physical vapor deposition，PVD)法，进一步例如溅射法。再将栅极膜图案化，形成栅极层20(如图5所示)。
可选地，在S210之前，还包括对初始半导体层10’的清洗步骤。具体可采用臭氧、HF进行清洗，以除去初始半导体层10’表面的氧化层，并且平面化该初始半导体层10’。
接下来，继续完成半导体层10的制备。即S130，以栅极层20为掩膜，对初始半导体层10’的两侧部分进行P型杂质掺杂，分别形成源极区11和漏极区12，获得半导体层10(如图6所示)。在S130，P型杂质可选自铟、B、BF 2等，例如B。可采用离子注入工艺将P型杂质注入初始半导体层10’。离子注入的剂量可以为5×10 14cm -2～2×10 15cm -2。离子注入的能量可以为10keV～40keV。离子注入的气源例如是BF 3。
接下来，在栅极层20上形成内部绝缘层42。可采用本领域已知的方法和设备形成内部绝缘层42。例如化学气相沉积(CVD)法，再如PECVD法。
然后在内部绝缘层42和栅极绝缘层41上形成对应于源极区11和漏极 区12的过孔33(如图7所示)。可采用本领域已知的方法和设备形成所述过孔33。例如以光刻胶为掩膜，采用干法刻蚀形成过孔33。
接下来，形成源漏极层30，即实施S300。可采用本领域已知的方法和设备形成源漏极膜，例如物理气相沉积(physical vapor deposition，PVD)法，进一步例如溅射法。源漏极膜伸入过孔33内分别与源极区11和漏极区12电连接。再将源漏极膜图案化，形成源漏极层30(如图8所示)。
可选地，还可以进一步在源漏极层30上依次形成平坦化层70、电极层和像素定义层80(如图9所示)。
可选地，TFT阵列基板还可进一步包括存储电容区域90。如图9所示，存储电容区域90包括第一电极91和第二电极92，其中第一电极91和第二电极92之间通过电容介质层422相间隔。作为示例，第一电极91和第二电极92可分别独立地包括钛、钼、金、铂、铝、镍、铜、以及它们的两种以上的合金中的一种或多种。电容介质层422可包括硅氧化物、硅氮化物和硅基氮氧化物中的一种或多种，例如硅氮化物。
可选地，第一电极91可位于栅极层20。通过对栅极膜图案化，得到栅极21的同时形成第一电极91。第二电极92可采用本领域已知的方法和设备形成。例如采用物理气相沉积(physical vapor deposition，PVD)法(例如溅射法)形成电极膜层，再将电极膜层图案化，形成第二电极92。
内部绝缘层42可包括层间绝缘层421和电容介质层422，其中，层间绝缘层421和电容介质层422将栅极层20和源漏极层30相隔离，并且电容介质层422将第一电极91和第二电极92相隔离，层间绝缘层421将第二电极92和源漏极层30相隔离。层间绝缘层421可包括硅氧化物、硅氮化物和硅基氮氧化物中的一种或多种。进一步地，层间绝缘层421可以为包括硅氧化物层、硅氮化物层和硅基氮氧化物层中的两种以上的复合层。电容介质层422可以如前文所述。
本申请的TFT阵列基板的技术特征也适用于本申请的制造方法中，在此不再赘述。
本申请还提供一种显示面板，其包括本申请任意一种TFT阵列基板。
本申请的显示面板由于采用本申请的TFT阵列基板，因而其残影现象 较小，显示均一性较好。
图9示出作为一个示例的显示面板1。参照图9，显示面板1包括TFT阵列基板100、位于TFT阵列基板100上的有机发光显示模块200和位于有机发光显示模块200上的封装层300。TFT阵列基板100可以是本文描述的任意一种TFT阵列基板。
有机发光显示模块200依次包括第一电极层210、有机薄膜层220和第二电极层230，有机薄膜层220至少包括发光层。发光层可包含本领域已知的有机发光材料。进一步地，有机发光材料可包括主体材料和客体材料。
可以理解的是，有机薄膜层220还可以包括其它功能层。例如，电子注入层、电子传输层、空穴阻挡层、电子阻挡层、空穴传输层、空穴注入层等。各功能层的均可采用本领域已知的材料。
本申请还提供一种显示装置，其包括本申请任意一种显示面板。
本申请的显示装置由于采用本申请的显示面板，即其包含本申请的TFT阵列基板，因而其显示的残影不良现象较小，显示效果较好。
显示装置的示例可以是手机、平板电脑、智能学习机等。
图10示出作为一个示例的显示装置2。该显示装置可以是手机。
接下来结合具体实施例对本申请的TFT阵列基板进行进一步地说明。
实施例1
OLED显示面板，其包括TFT阵列基板和位于TFT阵列基板上的有机发光显示模块。有机发光显示模块依次包括阴极层、电子注入层、电子传输层、空穴阻挡层、发光层、电子阻挡层、空穴传输层、空穴注入层、阳极层和盖帽层。TFT阵列基板包括依次层叠设置的衬底、缓冲层、半导体层(P-Si层)、栅极绝缘层、栅极层、内部绝缘层和源漏极层。半导体层包括源极区、漏极区和位于源极区和漏极区之间的沟道区，沟道区靠近栅极层的表面层掺杂有BF 2，且掺杂深度为10nm。栅极层包括栅极，栅极与沟道区对应设置。源漏极层包括相间隔设置的源极和漏极，源极与源极区电连接，漏极与漏极区电连接。其中，掺杂BF 2的离子注入能量为10keV，注入剂量为8×10 11cm -2。TFT阵列基板还包括存储电容。
对比例1
与实施例1的显示面板类似，区别在于，沟道区的P型杂质为B。
实施例1和对比例1的由不同亮度画面切换至同一灰阶的显示效果分别如图11和图12所示。由图11可以看出，采用本申请的TFT阵列基板，显示面板的显示效果较好，无明显残影不良。而由图12可以看出，对比例1的显示面板发生明显的残影现象。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到各种等效的修改或替换，这些修改或替换都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以权利要求的保护范围为准。

Claims (16)

  1. 一种薄膜晶体管阵列基板，包括层叠设置的半导体层、栅极层和源漏极层，且所述半导体层与所述栅极层之间、以及所述栅极层和所述源漏极层之间分别通过绝缘层相间隔，
    所述半导体层包括源极区、漏极区和位于所述源极区和漏极区之间的沟道区，所述沟道区掺杂有分子量≥25的P型杂质，且掺杂深度为1nm～20nm，
    所述栅极层包括栅极，所述栅极与所述沟道区对应设置，
    所述源漏极层包括相间隔设置的源极和漏极，所述源极与所述源极区电连接，所述漏极与所述漏极区电连接。
  2. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述掺杂深度为3nm～15nm。
  3. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述沟道区的靠近所述栅极层的表面层掺杂有所述P型杂质。
  4. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述沟道区的P型杂质掺杂浓度为3×10 11cm -2～2×10 12cm -2，或5×10 11cm -2～1×10 12cm -2。
  5. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述P型杂质的分子量为25～200，或45～50。
  6. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述P型杂质选自铟、BF、BF 2中的一种或多种。
  7. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述P型杂质包括或是BF 2。
  8. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述半导体层为多晶硅膜层。
  9. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述多晶硅膜层的氢含量为0.01％～3％，或0.01％～2％。
  10. 根据权利要求8所述的薄膜晶体管阵列基板，其中，所述多晶硅 膜层中多晶硅的颗粒粒径为0.2μm～0.4μm，或0.2μm～0.3μm。
  11. 根据权利要求1所述的薄膜晶体管阵列基板，其中，所述沟道区的厚度为40nm～55nm，或40nm～45nm。
  12. 根据权利要求1-11任一项所述的薄膜晶体管阵列基板，其中，所述薄膜晶体管阵列基板包括依次层叠设置的半导体层、栅极绝缘层、栅极层、内部绝缘层和源漏极层。
  13. 根据权利要求12所述的薄膜晶体管阵列基板，其中，所述阵列基板采用顶栅型薄膜晶体管。
  14. 根据权利要求12所述的薄膜晶体管阵列基板，其中，所述栅极绝缘层包括硅氧化物、硅氮化物和硅基氮氧化物中的一种或多种。
  15. 一种显示面板，包括如权利要求1-14任一项所述的薄膜晶体管阵列基板。
  16. 一种显示装置，包括如权利要求15所述的显示面板。
PCT/CN2021/088315 2020-06-22 2021-04-20 薄膜晶体管阵列基板、显示面板和显示装置 Ceased WO2021258828A1 (zh)

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