WO2021258751A1 - 相位自纠正电路 - Google Patents

相位自纠正电路 Download PDF

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Publication number
WO2021258751A1
WO2021258751A1 PCT/CN2021/076934 CN2021076934W WO2021258751A1 WO 2021258751 A1 WO2021258751 A1 WO 2021258751A1 CN 2021076934 W CN2021076934 W CN 2021076934W WO 2021258751 A1 WO2021258751 A1 WO 2021258751A1
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Prior art keywords
signal
phase
switch tube
capacitor
voltage
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English (en)
French (fr)
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刘洁
王旭
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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Priority to US17/786,345 priority Critical patent/US11979149B2/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00323—Delay compensation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00286—Phase shifter, i.e. the delay between the output and input pulse is dependent on the frequency, and such that a phase difference is obtained independent of the frequency

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  • This application relates to the field of signal transmission technology, and in particular to a phase self-correcting circuit.
  • the magnitude of the signal phase change usually reflects a physical change caused by external interference in the transmission line.
  • the phase of the signal will change due to interference caused by various external factors such as electromagnetics. It is possible Leading may also produce lag, and the change of phase usually brings chaos in timing, which is not conducive to stable signal transmission. It can be seen that it is very necessary to correct the changed phase or prevent the phase change to ensure stable signal transmission.
  • Another related technology uses an integrated circuit chip (Integrated Circuit Chip) that adds a clock reconstruction to the terminal, and uses this chip to perform signal reconstruction processing at the terminal to achieve phase correction.
  • the integrated IC chip is expensive, Will increase the manufacturing cost of the entire circuit system.
  • the present application provides a phase self-correcting circuit, which realizes automatic correction of signal phase changes caused by various external reasons to meet the timing requirements in long-distance transmission scenarios.
  • the overall structure is simple, versatile and low in manufacturing cost. .
  • the embodiment of the present invention provides a phase self-correction circuit, which includes a trigger signal calculation module and a signal phase correction module; the trigger signal calculation module and the signal phase correction module are both composed of multiple discrete components;
  • the trigger signal calculation module is used to perform a logical calculation on the input phase standard reference signal and the actual transmission signal to obtain a target trigger signal that triggers the signal phase correction module;
  • the signal phase correction module is configured to output a self-correcting transmission signal with the same waveform as the phase standard reference signal based on the trigger mode of the target trigger signal and the actual transmission signal, so as to realize the phase correction of the actual transmission signal. Self-correcting.
  • the trigger signal calculation module includes an exclusive OR gate and an AND gate
  • the first input terminal of the XOR gate is connected to the phase standard reference signal, and the second input terminal of the XOR gate is connected to the actual transmission signal; the first input terminal of the AND gate is connected to the The output terminal of the exclusive OR gate is connected, the second input terminal of the AND gate is connected to the actual transmission signal, and the output terminal of the AND gate is connected to the signal phase correction module.
  • the trigger signal operation module further includes a first voltage operational amplifier
  • the positive pole of the first voltage operational amplifier is connected to the actual transmission signal, and the output terminal of the first voltage operational amplifier is connected to the second input terminal of the AND gate to pass the actual transmission signal through the first voltage operational amplifier.
  • a voltage operational amplifier inputs the AND gate after processing.
  • the trigger signal calculation module further includes a first capacitor and a second capacitor;
  • phase standard reference signal is input to the first input terminal of the XOR gate through the first capacitor; the actual transmission signal is input to the anode of the first voltage operational amplifier through the second capacitor.
  • the signal phase correction module includes a first switch tube, a second switch tube, and a voltage holding sub-module;
  • One end of the first switch tube is connected to the output terminal of the trigger signal calculation module, and the other end of the first switch tube is connected to the voltage holding submodule; one end of the second switch tube is connected to the In actual transmission of a signal, the other end of the second switch tube is connected to the voltage holding sub-module;
  • the voltage holding sub-module is used to adjust the output voltage to be consistent with the phase standard reference signal voltage based on the on and off states of the first switch tube or the second switch tube to make the actual transmission signal
  • the waveform of is adjusted to be the same as the waveform of the phase standard reference signal and then output.
  • the first switch tube and the second switch tube are both NMOS field effect transistors.
  • the voltage holding submodule includes a third capacitor, a fourth capacitor, a second resistor, and a fourth resistor;
  • Both ends of the third capacitor are respectively connected to the source of the first switch tube and one end of the fourth resistor; one end of the fourth capacitor is connected to the source of the second switch tube and the first end of the fourth resistor.
  • the four resistors are connected, and the other end of the fourth capacitor is grounded; both ends of the second resistor are respectively connected to the drain of the second switch tube and the trigger signal calculation module;
  • the resistance value of the second resistor is determined based on the phase standard reference signal or the period of the actual transmission signal and the capacitance of the fourth capacitor, so that the total time of one discharge of the fourth capacitor is not less than the Period value; the resistance value of the fourth resistor is not greater than a preset resistance threshold.
  • the signal phase correction module further includes a second voltage operational amplifier
  • the negative electrode of the second voltage operational amplifier is connected to one end of the third capacitor and the source electrode of the first switch tube, and the positive electrode of the second voltage operational amplifier is connected to the source electrode of the second switch tube, the The fourth capacitor is connected to the fourth resistor, and the output terminal of the second voltage operational amplifier is connected to the drain of the first switch tube to output the self-correcting transmission signal as an output terminal.
  • the signal phase correction module further includes a fifth capacitor for dc blocking and amplifying;
  • One end of the fifth capacitor is connected to the third capacitor, the source of the first switch tube, the negative electrode of the second voltage operational amplifier is connected, and the other end of the fifth capacitor is connected to the second voltage
  • the output terminal of the operational amplifier is connected to the drain of the first switch tube.
  • the signal phase correction module further includes a first resistor and a third resistor;
  • One end of the first resistor is connected to the output end of the trigger signal calculation module, the other end of the first resistor is connected to the gate of the first switch tube; one end of the third resistor is connected to the trigger The input end of the signal calculation module is connected, and the other end of the third resistor is connected to the gate of the second switch tube.
  • the advantage of the technical solution provided by this application is that the target trigger signal and the actual transmission signal obtained by logical operation of the trigger signal calculation module on the phase standard reference signal and the actual transmission signal after long-distance transmission determine the trigger mode, based on the trigger mode Adjust the waveform of the actual transmission signal to be consistent with the waveform of the phase standard reference signal, thereby realizing automatic correction of signal phase changes caused by various external reasons, meeting the timing requirements in long-distance transmission scenarios, and the entire structure is simple and reliable powerful. Since the phase self-correcting circuit is composed of multiple semiconductor discrete components, these discrete components are cheaper than the integrated IC chip. The manufacturing cost of the entire phase self-correcting circuit is much lower than that of the integrated IC chip. There are no requirements for application scenarios, and it has strong versatility.
  • FIG. 1 is a schematic structural diagram of an implementation manner of a phase self-correcting circuit provided by an embodiment of the present invention
  • FIG. 2 is a schematic diagram of the principle of phase self-correction provided by an embodiment of the present invention.
  • FIG. 3 is a schematic structural diagram of another implementation manner of a phase self-correcting circuit provided by an embodiment of the present invention.
  • FIG. 1 is a schematic flowchart of a phase self-correcting circuit method provided by an embodiment of the present invention.
  • the embodiment of the present invention may include the following content:
  • the phase self-correction circuit may include a trigger signal calculation module 1 and a signal phase correction module 2. Both the trigger signal calculation module 1 and the signal phase correction module 2 are composed of multiple discrete components.
  • the input of the trigger signal calculation module 1 is the phase standard reference signal and the actual transmission signal.
  • the phase standard reference signal is the standard signal with no phase change after the signal to be transmitted has been transmitted over a long distance.
  • the actual transmission signal is the signal to be transmitted over a long distance.
  • the actual signal in which the phase of the output after transmission changes, and the output of the trigger signal calculation module 1 is the target trigger signal.
  • the input of the signal phase correction module 2 is the target trigger signal and the actual transmission signal, and the output is the actual transmission signal after phase correction.
  • the phase self-correction circuit is used to process the actual transmission signal through the trigger signal calculation module 1 and the signal phase correction module 2 to output the same signal as the waveform of the phase standard reference signal to realize the phase self-correction of the actual transmission signal, as shown in the figure 2 shows the schematic diagram of the realization principle, the original signal in Fig. 2 is the actual transmission signal.
  • the trigger signal calculation module 1 can be used to perform logical calculations on the input phase standard reference signal and the actual transmission signal to obtain the target trigger signal of the trigger signal phase correction module 2.
  • Logical operations can be, for example, logical AND operations, exclusive OR operations, etc. Based on the logical operations to be performed, discrete components are selected to implement the corresponding logical operations, and logical operations are performed on the phase standard reference signal and the actual transmission signal to obtain the target trigger signal, target trigger signal
  • the waveform of the trigger signal phase correction module 2 is different in the final output signal line.
  • the signal phase correction module 2 can be used to output a self-correcting transmission signal with the same waveform as the phase standard reference signal based on the trigger mode of the target trigger signal and the actual transmission signal, so as to realize the phase self-correction of the actual transmission signal.
  • the signal phase correction module 2 may include a plurality of discrete devices that realize signal cut-off or signal conduction based on different waveforms, such as switch tubes.
  • the target trigger signal and the actual transmission signal jointly determine which device signal is cut off and which device signal is turned on.
  • the subsequent signal flow through the communication is modulated by discrete components so that the final output actual transmission signal is the same as the waveform of the phase standard reference signal.
  • the target trigger signal obtained by logical operation of the phase standard reference signal and the actual transmission signal after long-distance transmission and the actual transmission signal themselves determine the trigger mode based on the trigger signal calculation module.
  • Ways to adjust the waveform of the actual transmission signal to be consistent with the waveform of the phase standard reference signal thereby realizing automatic correction of signal phase changes caused by various external reasons, meeting the timing requirements in long-distance transmission scenarios, and the entire structure is simple and reliable Strong sex.
  • the phase self-correcting circuit is composed of multiple semiconductor discrete components, these discrete components are cheaper than the integrated IC chip.
  • the manufacturing cost of the entire phase self-correcting circuit is much lower than that of the integrated IC chip. There are no requirements for application scenarios, and it has strong versatility.
  • the structure of the trigger signal calculation module and the signal phase correction module is not limited.
  • the structure of the trigger signal calculation module and the signal phase correction module under one embodiment is given.
  • Pulse ref in Figure 3 is the normal phase standard reference signal
  • Pulse in is the actual transmission signal whose phase changes after long-distance transmission.
  • the phase difference between the actual transmission signal and the phase standard reference signal is ⁇ , ⁇ can be greater than 0 or less than 0.
  • the ⁇ shown in FIG. 3 is a state greater than 0, that is, the phase of the signal lags behind the phase of the normal reference signal. It can include the following:
  • the discrete components of the trigger signal arithmetic module 1 that implement logic operations include an exclusive OR gate Q1 and an AND gate Q2.
  • the exclusive OR gate Q1 outputs 1 with the same phase of the input waveform and outputs 0 with a different phase
  • the AND gate Q2 outputs 1 with the same phase of the input waveform and outputs 0 with a different phase.
  • the first input terminal of the XOR gate Q1 is connected to the phase standard reference signal, and the second input terminal of the XOR gate Q1 is connected to the actual transmission signal; the first input terminal of the AND gate Q2 is connected to the output terminal of the XOR gate Q1, and The second input terminal of the gate Q2 is connected to the actual transmission signal, and the output terminal of the AND gate Q2 is connected to the signal phase correction module 2.
  • the trigger signal operation module 1 may further include a first voltage operation amplifier U1.
  • the positive terminal of the first voltage operational amplifier U1 is connected to the actual transmission signal
  • the output terminal of the first voltage operational amplifier U1 is connected to the second input terminal of the AND gate Q2
  • the actual transmission signal is processed by the first voltage operational amplifier and then input to the AND gate Q2.
  • the trigger signal calculation module 1 for example also It may include a first capacitor C1 and a second capacitor C2.
  • the phase standard reference signal is input to the first input terminal of the XOR gate Q1 through the first capacitor C1; the actual transmission signal is input to the anode of the first voltage operational amplifier U1 through the second capacitor C2.
  • the discrete components in the signal phase correction module 2 that implement signal turn-on or turn-off may include a first switch tube D1 and a second switch tube D2.
  • the first switch tube D1 and the second switch tube D2 are, for example, NMOS field effect transistor.
  • the first switch tube D1 and the second switch tube D2 can also be other devices that realize the on and off functions, such as triodes, etc., which does not affect the implementation of this application.
  • One end of the first switch tube D1 is connected to the output terminal of the trigger signal calculation module 1, as shown in FIG.
  • the output terminal of the AND gate Q2 is connected, and the other end of the first switch tube is connected to the voltage holding sub-module;
  • One end of D2 is connected to the actual transmission signal, and the other end of the second switch tube D2 is connected to the voltage holding sub-module.
  • the voltage holding sub-module can be used to adjust the output voltage to be consistent with the phase standard reference signal voltage based on the on and off states of the first switching tube D1 or the second switching tube D2 so that the waveform of the actual transmission signal can be adjusted to the phase standard
  • the reference signal is output after the same waveform.
  • the voltage holding sub-module may include a third capacitor C3, a fourth capacitor C4, a second resistor R2, and a fourth resistor R4.
  • a switch tube D1 and a second switch tube D2 such as an NMOS field effect transistor, as an example to describe the connection relationship between the components
  • the two ends of the third capacitor C3 are respectively connected to the source and the fourth resistor of the first switch tube D1
  • One end of the fourth capacitor C4 is connected to the source of the second switch tube D2 and the fourth resistor R4, and the other end of the fourth capacitor C4 is grounded; both ends of the second resistor R2 are connected to the second switch tube D2.
  • the drain is connected to the output terminal of the first voltage operational amplifier UI of the trigger signal operation module 1.
  • the resistance value of the second resistor R2 is determined based on the phase standard reference signal or the period of the actual transmission signal and the capacitance of the fourth capacitor C4, so that the total time of one discharge of the fourth capacitor C4 is not less than the period value, and the fourth resistor R4 The resistance value of is not greater than the preset resistance threshold, so that it quickly becomes 0 when the fourth capacitor C4 is discharged.
  • D2 discharges, due to the small resistance value of R4, the output quickly becomes 0, which is the same as the ref voltage.
  • the voltage at b is 0, the voltage at c is 0, D1 is off, and the voltage at a is equal to
  • the output out and ref waveforms are exactly the same, so pulse in is corrected to the same phase state as ref.
  • the signal phase correction module 2 may further include a second voltage operational amplifier U2.
  • the cathode of the second voltage operational amplifier U2 is connected to one end of the third capacitor C3 and the source of the first switch tube D1.
  • the anode of the second voltage operational amplifier U2 is connected to the source of the second switch tube D1, the fourth capacitor C4, and the fourth capacitor C4.
  • the resistor R4 is connected, and the output terminal of the second voltage operational amplifier U2 is connected to the drain of the first switch tube D1 as an output terminal to output a self-correcting transmission signal.
  • the signal phase correction module 2 may further include a fifth capacitor C5 for dc blocking and amplifying.
  • One end of the fifth capacitor C5 is connected to the third capacitor C3, the source of the first switch tube D1, and the negative electrode of the second voltage operational amplifier U2.
  • the other end of the fifth capacitor C5 is connected to the output terminal of the second voltage operational amplifier U2, The drain of the first switch tube D1 is connected.
  • the signal phase correction module 2 may further include a first resistor R1 and a third resistor R3.
  • One end of the first resistor R1 is connected to the output end of the trigger signal calculation module 1, the other end of the first resistor R1 is connected to the gate of the first switch tube D1; one end of the third resistor R3 is connected to the input end of the trigger signal calculation module 1 Connected, the other end of the third resistor R3 is connected to the gate of the second switch tube D2.
  • this application also provides an illustrative example, which uses the phase self-correction circuit shown in Figure 3 to perform phase self-correction, where VCC is 3.3V, C1, C2 , C3, C4 are 1Uf, R4 is 1K, R1, R2, R3 can be 10K, and R2 can be selected according to actual circuit needs.
  • C5 is 0.47Uf, which plays the role of blocking and amplifying the input.
  • U1 and U2 are ordinary LM307 operational amplifiers
  • D1 and D2 are SI2302 NMOS transistors
  • Q1 is 7486 XOR gate
  • Q2 is 7408 model AND gate, which can include the following The content:
  • the voltage at terminal d passes through R4, C3, and D2 quickly Discharge, become 0V, and the output voltage is equal to ref is 0V at this time.
  • ref is 0V
  • in is 0V
  • D2 is off
  • D1 is off in the same way.
  • the output voltage remains at 0v and the magnitude is equal to ref.
  • the output voltage and ref are Equal, the phase is corrected.

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Abstract

一种相位自纠正电路，包括触发信号运算模块和信号相位纠正模块；触发信号运算模块和信号相位纠正模块均由多个分立元器件构成。触发信号运算模块用于对输入的相位标准参考信号和实际传输信号进行逻辑运算，得到触发信号相位纠正模块的目标触发信号；信号相位纠正模块用于基于目标触发信号和实际传输信号的触发方式输出与相位标准参考信号的波形相同的自纠正传输信号，以实现对实际传输信号的相位自纠正，从而实现了对外部各种原因引起的信号相位的改变进行自动纠正，满足长距离传输场景中的时序需求，整个电路结构简单、通用性强且制造成本低廉。

Description

相位自纠正电路
本申请要求于2020年6月24日提交中国专利局、申请号为CN202010589269.3、发明名称为“相位自纠正电路”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及信号传输技术领域，特别是涉及一种相位自纠正电路。
背景技术
众所周知，信号相位的大小改变通常反应该信号在传输线路中受到外界干扰而产生的一种物理性的变化，例如随着电磁等各种外界原因引起干扰，信号的相位会因此而改变，有可能超前，也有可能产生滞后，而相位的改变通常会带来时序上的混乱，不利于信号稳定传输。可见，对变化的相位进行纠正或者防止相位改变以确保信号稳定传输是非常有必要的。
相关技术中采用减少路径走线长度、增加电磁屏蔽组件或者对信号进行包地处理来防止信号传输过程中相位发生改变，而限制走线长度，增加PCB(Printed Circuit Board，印制电路板)走线的空间，增加额外的屏蔽措施不仅会限制实际应用场景，通用性差，而且不能完全的消除相位的改变，还会增加额外的制造成本。另外一种相关技术采用在终端增加一种时钟重构的集成IC芯片((Integrated Circuit Chip，集成电路芯片)，利用该芯片在终端进行信号重构处理来实现相位纠正。集成IC芯片价格昂贵，会增加整个电路系统的制造成本。
鉴于此，如何解决相关技术通用性差且制造成本高的问题，是所属领域技术人员需要解决的技术问题。
发明内容
本申请提供了一种相位自纠正电路，实现了对外部各种原因引起的信号相位的改变进行自动纠正，以满足长距离传输场景中的时序需求，整个结构简单、通用性强且制造成本低廉。
为解决上述技术问题，本发明实施例提供以下技术方案：
本发明实施例提供了一种相位自纠正电路，包括触发信号运算模块和信号相位纠正模块；所述触发信号运算模块和所述信号相位纠正模块均由多个分立元器件构成；
其中，所述触发信号运算模块用于对输入的相位标准参考信号和实际传输信号进行逻辑运算，得到触发所述信号相位纠正模块的目标触发信号；
所述信号相位纠正模块用于基于所述目标触发信号和所述实际传输信号的触发方式输出与所述相位标准参考信号的波形相同的自纠正传输信号，以实现对所述实际传输信号的相位自纠正。
可选的，所述触发信号运算模块包括异或门和与门；
其中，所述异或门的第一输入端接入所述相位标准参考信号，所述异或门的第二输入端接入所述实际传输信号；所述与门的第一输入端与所述异或门的输出端相连，所述与门的第二输入端接入所述实际传输信号，所述与门的输出端与所述信号相位纠正模块相连。
可选的，所述触发信号运算模块还包括第一电压运算放大器；
所述第一电压运算放大器的正极接入所述实际传输信号，所述第一电压运算放大器的输出端与所述与门的第二输入端相连，以将所述实际传输信号经所述第一电压运算放大器进行处理后输入所述与门。
可选的，所述触发信号运算模块还包括第一电容和第二电容；
所述相位标准参考信号经所述第一电容输入所述异或门的第一输入端；所述实际传输信号经所述第二电容输入所述第一电压运算放大器的正极。
可选的，所述信号相位纠正模块包括第一开关管、第二开关管和电压保持子模块；
所述第一开关管的一端与所述触发信号运算模块的输出端相连，所述第一开关管的另一端与所述电压保持子模块相连；所述第二开关管的一端接入所述实际传输信号，所述第二开关管的另一端与所述电压保持子模块相连；
所述电压保持子模块用于基于所述第一开关管或所述第二开关管的导 通、截止状态，通过调节输出电压与所述相位标准参考信号电压保持一致以使所述实际传输信号的波形被调整为与所述相位标准参考信号的波形相同后被输出。
可选的，所述第一开关管和所述第二开关管均为NMOS场效应晶体管。
可选的，所述电压保持子模块包括第三电容、第四电容、第二电阻和第四电阻；
所述第三电容的两端分别与所述第一开关管的源极、所述第四电阻的一端相连；所述第四电容的一端与所述第二开关管的源极、所述第四电阻相连，所述第四电容的另一端接地；所述第二电阻的两端分别与所述第二开关管的漏极、所述触发信号运算模块相连；
所述第二电阻的电阻值基于所述相位标准参考信号或所述实际传输信号的周期和所述第四电容的电容量确定，以使所述第四电容的一次放电总时间不小于所述周期值；所述第四电阻的电阻值不大于预设电阻阈值。
可选的，所述信号相位纠正模块还包括第二电压运算放大器；
所述第二电压运算放大器的负极与所述第三电容一端、所述第一开关管的源极相连，所述第二电压运算放大器的正极与所述第二开关管的源极、所述第四电容、所述第四电阻相连，所述第二电压运算放大器的输出端与所述第一开关管的漏极相连以作为输出端输出所述自纠正传输信号。
可选的，所述信号相位纠正模块还包括用于对隔直放大的第五电容；
所述第五电容的一端与所述第三电容、所述第一开关管的源极相连、所述第二电压运算放大器的负极相连，所述第五电容的另一端与所述第二电压运算放大器的输出端、所述第一开关管的漏极相连。
可选的，所述信号相位纠正模块还包括第一电阻和第三电阻；
所述第一电阻的一端与所述触发信号运算模块的输出端相连，所述第一电阻的另一端与所述第一开关管的栅极相连；所述第三电阻的一端与所述触发信号运算模块的输入端相连，所述第三电阻的另一端与所述第二开关管的栅极相连。
本申请提供的技术方案的优点在于，基于触发信号运算模块对相位标 准参考信号和经过长距离传输后的实际传输信号进行逻辑运算得到的目标触发信号和实际传输信号本身确定触发方式，基于触发方式调整实际传输信号的波形与相位标准参考信号的波形保持一致，从而实现了对外部各种原因引起的信号相位的改变进行自动纠正，满足长距离传输场景中的时序需求，整个结构简单、可靠性强。由于相位自纠正电路由多个半导体分立元器件构成，相比集成IC芯片来说，这些分立元器件价格低廉，整个相位自纠正电路制造成本相比集成IC芯片降低了很多，而且自纠正电路对应用场景没有任何要求，通用性强。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性的，并不能限制本公开。
附图说明
为了更清楚的说明本发明实施例或相关技术的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作简单的介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提供的相位自纠正电路的一种实施方式的结构框架示意图；
图2为本发明实施例提供的相位自纠正原理示意图；
图3为本发明实施例提供的相位自纠正电路的另一种实施方式的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本发明方案，下面结合附图和具体实施方式对本发明作进一步的详细说明。显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
本申请的说明书和权利要求书及上述附图中的术语“第一”、“第二”、“第三”“第四”等是用于区别不同的对象，而不是用于描述特定的顺序。此外术语“包括”和“具有”以及他们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可包括没有列出的步骤或单元。
在介绍了本发明实施例的技术方案后，下面详细的说明本申请的各种非限制性实施方式。
首先参见图1和图2，图1为本发明实施例提供的一种相位自纠正电路方法的流程示意图，本发明实施例可包括以下内容：
相位自纠正电路可包括触发信号运算模块1和信号相位纠正模块2，触发信号运算模块1和信号相位纠正模块2均由多个分立元器件构成。触发信号运算模块1的输入为相位标准参考信号和实际传输信号，相位标准参考信号为待传输信号经过长距离传输后的没有相位发生变化的标准信号，实际传输信号是为待传输信号经过长距离传输后的输出的相位发生变化的实际信号，触发信号运算模块1的输出为目标触发信号。信号相位纠正模块2的输入为目标触发信号和实际传输信号，输出为经过相位纠正的实际传输信号。也即相位自纠正电路用于将实际传输信号经过触发信号运算模块1和信号相位纠正模块2的处理输出与相位标准参考信号的波形相同信号，实现对实际传输信号的相位自纠正，在如图2所示的实现原理示意图，图2中的原始信号即为实际传输信号。
其中，触发信号运算模块1可用于对输入的相位标准参考信号和实际传输信号进行逻辑运算，得到触发信号相位纠正模块2的目标触发信号。逻辑运算例如可为逻辑与运算、异或运算等，基于所要进行的逻辑运算选取实现相应逻辑运算的分立元器件，对相位标准参考信号和实际传输信号进行逻辑运算得到目标触发信号，目标触发信号的波形不同触发信号相位纠正模块2最终输出信号的线路不同。
信号相位纠正模块2可用于基于目标触发信号和实际传输信号的触发方式输出与相位标准参考信号的波形相同的自纠正传输信号，以实现对实际传输信号的相位自纠正。信号相位纠正模块2可包括多个基于不同波形 实现信号截止或信号导通的分立器件，如开关管，目标触发信号和实际传输信号共同确定哪个器件信号截止、哪个器件信号导通，对于信号导通的后续信号流向经过分立元器件的调制使最终输出的实际传输信号与相位标准参考信号的波形相同。
在本发明实施例提供的技术方案中，基于触发信号运算模块对相位标准参考信号和经过长距离传输后的实际传输信号进行逻辑运算得到的目标触发信号和实际传输信号本身确定触发方式，基于触发方式调整实际传输信号的波形与相位标准参考信号的波形保持一致，从而实现了对外部各种原因引起的信号相位的改变进行自动纠正，满足长距离传输场景中的时序需求，整个结构简单、可靠性强。由于相位自纠正电路由多个半导体分立元器件构成，相比集成IC芯片来说，这些分立元器件价格低廉，整个相位自纠正电路制造成本相比集成IC芯片降低了很多，而且自纠正电路对应用场景没有任何要求，通用性强。
在上述实施例中，对于触发信号运算模块和所述信号相位纠正模块的结构组成并不做限定，本实施例中给出触发信号运算模块和信号相位纠正模块的一种实施方式下的结构组成，如图3所示，图3的Pulse ref为正常的相位标准参考信号，Pulse in为经过长距离传输后相位发生变化的实际传输信号，实际传输信号与相位标准参考信号之间的相位差为θ，θ可大于0也可小于0，图3示出的θ为大于0的状态，即信号的相位滞后于正常的参考信号相位。可包括如下内容：
触发信号运算模块1实现逻辑运算的分立元器件包括异或门Q1和与门Q2。异或门Q1对于输入波形相位相同的输出1，相位不同的输出0，与门Q2对于输入波形相位相同的输出1，相位不同的输出0。异或门Q1的第一输入端接入相位标准参考信号，异或门Q1的第二输入端接入实际传输信号；与门Q2的第一输入端与异或门Q1的输出端相连，与门Q2的第二输入端接入实际传输信号，与门Q2的输出端与信号相位纠正模块2相连。
作为一种可选的实施方式，为了实现电压跟随作用，使得实际传输信 号在输入与门Q2之前为低输出阻抗，触发信号运算模块1还可包括第一电压运算放大器U1。第一电压运算放大器U1的正极接入实际传输信号，第一电压运算放大器U1的输出端和与门Q2的第二输入端相连，将实际传输信号经第一电压运算放大器进行处理后输入与门Q2。
作为另外一种可选的实施方式，为了保证相位标准参考信号和实际传输信号这两路纯正的脉冲信号的输入，滤除外界引入到脉冲中的偏置直流电压，触发信号运算模块1例如还可包括第一电容C1和第二电容C2。相位标准参考信号经第一电容C1输入异或门Q1的第一输入端；实际传输信号经第二电容C2输入第一电压运算放大器U1的正极。
在本发明实施例中，信号相位纠正模块2中实现信号导通或截止的分立元器件可包括第一开关管D1、第二开关管D2，第一开关管D1和第二开关管D2例如为NMOS场效应晶体管。当然，第一开关管D1和第二开关管D2还可为其他实现导通和截止功能的器件，如三极管等，这均不影响本申请的实现。第一开关管D1的一端与触发信号运算模块1的输出端相连，如图3所示的与门Q2的输出端相连，第一开关管的另一端与电压保持子模块相连；第二开关管D2的一端接入实际传输信号，第二开关管D2的另一端与电压保持子模块相连。电压保持子模块可用于基于第一开关管D1或第二开关管D2的导通、截止状态，通过调节输出电压与相位标准参考信号电压保持一致以使实际传输信号的波形被调整为与相位标准参考信号的波形相同后被输出。
在本发明实施例的一些实施方式中，电压保持子模块可包括第三电容C3、第四电容C4、第二电阻R2和第四电阻R4。以一开关管D1和第二开关管D2例如为NMOS场效应晶体管为例描述各元器件之间的连接关系，第三电容C3的两端分别与第一开关管D1的源极、第四电阻的一端相连；第四电容C4的一端与第二开关管D2的源极、第四电阻R4相连，第四电容C4的另一端接地；第二电阻R2的两端分别与第二开关管D2的漏极、触发信号运算模块1的第一电压运算放大器UI的输出端相连。其中，第二电阻R2的电阻值基于相位标准参考信号或实际传输信号的周期和第四电容C4的电容量确定，以使第四电容C4的一次放电总时间不小于周期值， 第四电阻R4的电阻值不大于预设电阻阈值，以使在第四电容C4放电时迅速变为0。
基于上述触发信号运算模块和信号相位纠正模块的结构对实际输出信号的自纠正原理如下所述：
当θ大于0，m时段，pulse ref与pulse in均为高电平1，那么两路信号经过Q1异或门，输出电压a为0电平，经过Q2与门，e处电压也为0，D2截止，U1输出即b处电压为1，此时D1导通，所以d处电压的电平同样为高电平1，因此输出电压为高电平1。当时段在θ位置时，输入ref为0，输入in为1，同理可得，Q1输出a为1，b为1，D2导通，D1截止，此时C4上的电压迅速通过R4、C3、D2放电，由于R4电阻值较小，那么输出迅速变为0，与ref电压相同，同理，在n时段时，b处电压为0，c处电压为0，D1截止，a处电压和b处电压均为0，D2截止，C4电压保持为0，输出电压一直为0，低电平，同样与ref相等。综上，输出out与ref波形完全相同，因此pulse in被矫正为ref相同的相位状态。
当θ小于0，即pulse in超前ref时，同理可得，在m区间，与上述相同，输入输出同为1高电平，在θ时段时，b处电压为0，c处电压为1，D1导通，e处电压为0，D2截止，此时，C4通过D1、R2放电，由于R2阻值较大，放电很慢，C4会保持为高电平一段时间，此时输出out与ref相等同为高，相位被矫正，直到n时段，C4放电完成，变为低电平0，此时输出out也与ref相等，整体pulse in相位被矫正为ref相等。
在本发明实施例的另外一些实施方式中，为了实现电压跟随作用，使得校正后的实际传输信号为低输出阻抗，信号相位纠正模块2还可包括第二电压运算放大器U2。第二电压运算放大器U2的负极与第三电容C3一端、第一开关管D1的源极相连，第二电压运算放大器U2的正极与第二开关管D1的源极、第四电容C4、第四电阻R4相连，第二电压运算放大器U2的输出端与第一开关管D1的漏极相连以作为输出端输出自纠正传输信号。
作为一种可选的实施方式，为了使得输出信号不受其他信号影响，信 号相位纠正模块2还可包括用于对隔直放大的第五电容C5。第五电容C5的一端与第三电容C3、第一开关管D1的源极相连、第二电压运算放大器U2的负极相连，第五电容C5的另一端与第二电压运算放大器U2的输出端、第一开关管D1的漏极相连。
作为另外一种可选的实施方式，为了延长电路使用寿命，保护电路元器件不会在过大电流中损坏，信号相位纠正模块2还可包括第一电阻R1和第三电阻R3。第一电阻R1的一端与触发信号运算模块1的输出端相连，第一电阻R1的另一端与第一开关管D1的栅极相连；第三电阻R3的一端与触发信号运算模块1的输入端相连，第三电阻R3的另一端与第二开关管D2的栅极相连。
为了使所属领域技术人员更加清楚本申请的技术方案，本申请还提供了一个示意性例子，该例子以图3所示的相位自纠正电路进行相位自纠正，其中VCC为3.3V，C1、C2、C3、C4为1Uf，R4为1K，R1、R2、R3可为10K，R2可根据实际电路需要选取合适的电阻值。C5为0.47Uf，起到对输入进行隔直放大作用，U1、U2为普通的LM307运放，D1、D2为SI2302 NMOS管，Q1为7486异或门，Q2为7408型号与门，可包括下述内容：
当θ大于0，即图3中所示状态，在m时段，ref与in同为3.3V，高电平，此时a处电压为0，e处电压为0，D2截止，b处电压为3.3V，c处电压为3.3V，D1导通，则d处电压为3.3V，U2正向输入为3.3V，因此输出out为3.3V，大小等于ref电压。在θ时段时，in为3.3V，ref为0V，a＝b＝3.3V，因此e＝3.3V，D2导通，c＝0V，D1截止，因此，d端电压通过R4、C3、D2迅速放电，变为0V，此时输出电压等于ref为0V。在n时段，ref为0V，in为0V，a＝e＝0V，D2截止，同理D1截止，此时输出电压依旧保持为0v，大小等于ref，综上，这个时段，输出电压与ref大小相等，相位被矫正。
当θ小于0时，即in相位超前ref相位，在m时段，ref与in同为3.3V，此时与上述相同，输出电压为3.3V，大小等于ref。当在θ时段，in为0V，ref为3.3V，a处电压为3.3V，b处电压为0V，e处电压为0V，D2截止， 同理D1导通，此时d通过D1、R2放电，因为R2阻值较大，因此高电平会维持较长时间，直到n时段，变为0V，但在θ时段，输出电压依旧为3.3V，大小等于ref。在n时段期间，ref＝in＝0V，d处电压放电完成变为0V，此时out为0v，大小等于ref。整个时段区间，out与ref相等，因此in被矫正为ref。
由上可知，无论in超前还是滞后ref，最终输出信号都被矫正为ref，实现了自纠正的功能，无需采用专门的集成的芯片电路或者装置进行相位的矫正调节，通用性强，可靠性高，大大地节约了制造成本。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
专业人员还可以进一步意识到，结合本文中所公开的实施例描述的各示例的单元及算法步骤，能够以电子硬件、计算机软件或者二者的结合来实现，为了清楚地说明硬件和软件的可互换性，在上述说明中已经按照功能一般性地描述了各示例的组成及步骤。这些功能究竟以硬件还是软件方式来执行，取决于技术方案的特定应用和设计约束条件。专业技术人员可以对每个特定的应用来使用不同方法来实现所描述的功能，但是这种实现不应认为超出本发明的范围。
以上对本申请所提供的一种相位自纠正电路进行了详细介绍。本文中应用了具体个例对本发明的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本发明的方法及其核心思想。应当指出，对于本技术领域的普通技术人员来说，在不脱离本发明原理的前提下，还可以对本申请进行若干改进和修饰，这些改进和修饰也落入本申请权利要求的保护范围内。

Claims (10)

  1. 一种相位自纠正电路，其特征在于，包括触发信号运算模块和信号相位纠正模块；所述触发信号运算模块和所述信号相位纠正模块均由多个分立元器件构成；
    其中，所述触发信号运算模块用于对输入的相位标准参考信号和实际传输信号进行逻辑运算，得到触发所述信号相位纠正模块的目标触发信号；
    所述信号相位纠正模块用于基于所述目标触发信号和所述实际传输信号的触发方式输出与所述相位标准参考信号的波形相同的自纠正传输信号，以实现对所述实际传输信号的相位自纠正。
  2. 根据权利要求1所述的相位自纠正电路，其特征在于，所述触发信号运算模块包括异或门和与门；
    其中，所述异或门的第一输入端接入所述相位标准参考信号，所述异或门的第二输入端接入所述实际传输信号；所述与门的第一输入端与所述异或门的输出端相连，所述与门的第二输入端接入所述实际传输信号，所述与门的输出端与所述信号相位纠正模块相连。
  3. 根据权利要求2所述的相位自纠正电路，其特征在于，所述触发信号运算模块还包括第一电压运算放大器；
    所述第一电压运算放大器的正极接入所述实际传输信号，所述第一电压运算放大器的输出端与所述与门的第二输入端相连，以将所述实际传输信号经所述第一电压运算放大器进行处理后输入所述与门。
  4. 根据权利要求3所述的相位自纠正电路，其特征在于，所述触发信号运算模块还包括第一电容和第二电容；
    所述相位标准参考信号经所述第一电容输入所述异或门的第一输入端；所述实际传输信号经所述第二电容输入所述第一电压运算放大器的正极。
  5. 根据权利要求1-4任意一项所述的相位自纠正电路，其特征在于，所述信号相位纠正模块包括第一开关管、第二开关管和电压保持子模块；
    所述第一开关管的一端与所述触发信号运算模块的输出端相连，所述第一开关管的另一端与所述电压保持子模块相连；所述第二开关管的一端 接入所述实际传输信号，所述第二开关管的另一端与所述电压保持子模块相连；
    所述电压保持子模块用于基于所述第一开关管或所述第二开关管的导通、截止状态，通过调节输出电压与所述相位标准参考信号电压保持一致以使所述实际传输信号的波形被调整为与所述相位标准参考信号的波形相同后被输出。
  6. 根据权利要求5所述的相位自纠正电路，其特征在于，所述第一开关管和所述第二开关管均为NMOS场效应晶体管。
  7. 根据权利要求6所述的相位自纠正电路，其特征在于，所述电压保持子模块包括第三电容、第四电容、第二电阻和第四电阻；
    所述第三电容的两端分别与所述第一开关管的源极、所述第四电阻的一端相连；所述第四电容的一端与所述第二开关管的源极、所述第四电阻相连，所述第四电容的另一端接地；所述第二电阻的两端分别与所述第二开关管的漏极、所述触发信号运算模块相连；
    所述第二电阻的电阻值基于所述相位标准参考信号或所述实际传输信号的周期和所述第四电容的电容量确定，以使所述第四电容的一次放电总时间不小于所述周期值；所述第四电阻的电阻值不大于预设电阻阈值。
  8. 根据权利要求7所述的相位自纠正电路，其特征在于，所述信号相位纠正模块还包括第二电压运算放大器；
    所述第二电压运算放大器的负极与所述第三电容一端、所述第一开关管的源极相连，所述第二电压运算放大器的正极与所述第二开关管的源极、所述第四电容、所述第四电阻相连，所述第二电压运算放大器的输出端与所述第一开关管的漏极相连以作为输出端输出所述自纠正传输信号。
  9. 根据权利要求8所述的相位自纠正电路，其特征在于，所述信号相位纠正模块还包括用于对隔直放大的第五电容；
    所述第五电容的一端与所述第三电容、所述第一开关管的源极相连、所述第二电压运算放大器的负极相连，所述第五电容的另一端与所述第二电压运算放大器的输出端、所述第一开关管的漏极相连。
  10. 根据权利要求9所述的相位自纠正电路，其特征在于，所述信号 相位纠正模块还包括第一电阻和第三电阻；
    所述第一电阻的一端与所述触发信号运算模块的输出端相连，所述第一电阻的另一端与所述第一开关管的栅极相连；所述第三电阻的一端与所述触发信号运算模块的输入端相连，所述第三电阻的另一端与所述第二开关管的栅极相连。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111817701B (zh) 2020-06-24 2023-01-10 苏州浪潮智能科技有限公司 相位自纠正电路
CN113836071B (zh) 2021-11-26 2022-02-22 苏州浪潮智能科技有限公司 自纠正电路以及信号自纠正方法
CN115021742B (zh) * 2022-07-22 2024-05-10 苏州浪潮智能科技有限公司 一种高速串行信号非对称失真的自纠正电路和装置
CN117524029A (zh) * 2024-01-05 2024-02-06 武汉精立电子技术有限公司 一种测试信号生成系统和面板检测设备
CN118549691B (zh) * 2024-06-03 2025-02-18 湖北中盛电气有限公司 一种高压固态软起动设备过零检测装置及方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6167101A (en) * 1998-07-28 2000-12-26 Industrial Technology Research Institute Apparatus and method for correcting a phase of a synchronizing signal
CN1697036A (zh) * 2004-05-14 2005-11-16 联发科技股份有限公司 可校正相位的多相位波形产生器及相关的相位校正方法
CN201054649Y (zh) * 2007-06-29 2008-04-30 青岛海信电器股份有限公司 行相位调整电路
TW200939183A (en) * 2008-03-10 2009-09-16 Himax Tech Ltd Display driver and built-in-phase calibration circuit thereof
CN107872223A (zh) * 2016-09-27 2018-04-03 马维尔国际贸易有限公司 用于执行相位误差校正的系统和方法
CN108009112A (zh) * 2017-09-27 2018-05-08 上海玮舟微电子科技有限公司 一种高速时钟正交相位校准电路
CN111817701A (zh) * 2020-06-24 2020-10-23 苏州浪潮智能科技有限公司 相位自纠正电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6084930A (en) * 1998-09-16 2000-07-04 Credence Systems Corporation Triggered clock signal generator
US8854098B2 (en) * 2011-01-21 2014-10-07 Qualcomm Incorporated System for I-Q phase mismatch detection and correction
JP2017028489A (ja) * 2015-07-22 2017-02-02 富士通株式会社 スキュー補正回路、電子装置及びスキュー補正方法
US10248174B2 (en) 2016-05-24 2019-04-02 Hedvig, Inc. Persistent reservations for virtual disk using multiple targets
CN106788353A (zh) * 2016-11-18 2017-05-31 深圳市紫光同创电子有限公司 一种时钟偏斜纠正方法及电路、终端设备
CN206740856U (zh) * 2017-06-05 2017-12-12 西安电子科技大学 一种基于多周期平均的相位差测量装置
CN108173545B (zh) * 2018-01-17 2021-08-13 上海交通大学 锁相环电路、多锁相环系统及其输出相位同步方法
KR102549549B1 (ko) * 2018-03-12 2023-07-03 에스케이하이닉스 주식회사 듀티 싸이클 보정 회로
CN110324037B (zh) * 2018-03-31 2021-08-20 华为技术有限公司 一种倍频器、数字锁相环电路以及倍频方法

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6167101A (en) * 1998-07-28 2000-12-26 Industrial Technology Research Institute Apparatus and method for correcting a phase of a synchronizing signal
CN1697036A (zh) * 2004-05-14 2005-11-16 联发科技股份有限公司 可校正相位的多相位波形产生器及相关的相位校正方法
CN201054649Y (zh) * 2007-06-29 2008-04-30 青岛海信电器股份有限公司 行相位调整电路
TW200939183A (en) * 2008-03-10 2009-09-16 Himax Tech Ltd Display driver and built-in-phase calibration circuit thereof
CN107872223A (zh) * 2016-09-27 2018-04-03 马维尔国际贸易有限公司 用于执行相位误差校正的系统和方法
CN108009112A (zh) * 2017-09-27 2018-05-08 上海玮舟微电子科技有限公司 一种高速时钟正交相位校准电路
CN111817701A (zh) * 2020-06-24 2020-10-23 苏州浪潮智能科技有限公司 相位自纠正电路

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