WO2021258270A1 - 一种电路板、电子设备和电路板的加工方法 - Google Patents

一种电路板、电子设备和电路板的加工方法 Download PDF

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Publication number
WO2021258270A1
WO2021258270A1 PCT/CN2020/097558 CN2020097558W WO2021258270A1 WO 2021258270 A1 WO2021258270 A1 WO 2021258270A1 CN 2020097558 W CN2020097558 W CN 2020097558W WO 2021258270 A1 WO2021258270 A1 WO 2021258270A1
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WIPO (PCT)
Prior art keywords
circuit board
sublayer
metal sleeve
signal line
layer
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Application number
PCT/CN2020/097558
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English (en)
French (fr)
Inventor
吴伯平
罗丛德
冯辰辰
袁琦
吴加荣
陈涛
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2020/097558 priority Critical patent/WO2021258270A1/zh
Priority to CN202080102304.2A priority patent/CN115918269A/zh
Publication of WO2021258270A1 publication Critical patent/WO2021258270A1/zh

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits

Definitions

  • This application relates to the technical field of electronic equipment, and in particular to a circuit board, electronic equipment, and a processing method of the circuit board.
  • high-frequency signals with the highest frequency above 1 GHz such as millimeter waves (with the highest frequency in the range of 30 GHz to 300 GHz) have a large number of applications in mobile communications, positioning and navigation, satellite remote sensing, radio astronomy, meteorological physics and other fields.
  • the insertion loss and return loss of the high-frequency line play a vital role in the overall performance of the circuit board in the circuit board used to transmit high-frequency signals.
  • the high-frequency lines need to be laid out in different metal layers in the circuit board. In this way, metalized vias are usually used to realize the high-frequency lines in the two different metal layers. The electrical connection between.
  • the present application provides a circuit board, electronic equipment, and a processing method for a circuit board, which can reduce the insertion loss of metalized vias in the circuit board, and at the same time can reduce the return loss of the connection between the metalized vias and the signal line, and improve The performance of the circuit board.
  • some embodiments of the present application provide a circuit board, the circuit board includes a circuit board layer; the circuit board layer includes a circuit board layer main body, a first signal line, a second signal line, a metalized via and a metal sleeve
  • the main body of the circuit board layer has a first surface and a second surface opposite to each other.
  • the inside of the main body of the circuit board layer is provided with a reference ground; the first signal line is arranged on the first surface; the second signal line is arranged on the second surface; metallization
  • the via is arranged on the main body of the circuit board layer and penetrates the main body of the circuit board.
  • the wire is electrically connected; the metal sleeve is arranged in the main body of the circuit board layer and is sleeved around the periphery of the metalized via.
  • the metal sleeve is insulated from the metalized via, the first signal line, and the second signal line.
  • the metal sleeve is electrically connected with the reference ground in the main body of the circuit board layer.
  • the metal sleeve is arranged in the main body of the circuit board layer and is sleeved around the periphery of the metalized via, and the metal sleeve is electrically connected to the reference ground in the main body of the circuit board layer Therefore, the metal sleeve is equipotential with the reference ground in the main body of the circuit board layer, and the metal sleeve acts as a shield for the metalized vias.
  • the first aspect can prevent the electromagnetic waves generated by the metalized vias from radiating to the main body of the circuit board layer outside the metal sleeve, so that the electromagnetic energy is concentrated in the metal sleeve and directed to the second signal along the metalized vias.
  • Wire transmission which can reduce the electromagnetic energy loss and reduce the insertion loss of the metalized via.
  • the impedance continuity between the first signal line and the metallized via and between the metallized via and the second signal line can be increased, thereby reducing the signal transmission from the first signal line to the metal When the via is formed, and the reflection when transferred from the metallized via to the second signal line, the return loss is reduced.
  • the circuit board layer body includes a first circuit board sublayer, a second circuit board sublayer, and a third circuit board sublayer that are stacked and fixed together; the second circuit board sublayer is located between the first circuit board sublayer and the third circuit board sublayer And the second circuit board sublayer is provided with a reference ground; the surface of the first circuit board sublayer away from the second circuit board sublayer is the first surface of the circuit board layer main body, and the first circuit board sublayer forms at least the first The surface part is the insulating dielectric layer; the surface of the third circuit board sublayer away from the second circuit board sublayer is the second surface of the circuit board layer body, and at least the part of the third circuit board sublayer forming the second surface is the insulating dielectric layer The metal sleeve is arranged on the second circuit board sublayer and penetrates the second circuit board sublayer, and the metal sleeve is electrically connected to the reference ground in the second circuit board sublayer.
  • the two ends of the metal sleeve in the axial direction do not penetrate the first surface and the second surface, the metal sleeve and the first signal line are insulated and isolated by the first circuit board sublayer, and the metal sleeve is separated from the second signal line. They are insulated and isolated by the third circuit board sublayer.
  • the process of fabricating a metal sleeve in the main body of the circuit board layer can be as follows: first, fabricating a metal sleeve on the second circuit board sublayer, and making the metal sleeve penetrate the second circuit board sublayer to form a metal sleeve The second circuit board sublayer; then, the first circuit board sublayer, the second circuit board sublayer with a metal sleeve, and the third circuit board sublayer are laminated and fixed together, and the first circuit board sublayer and the third circuit board sublayer They are respectively located on opposite sides of the second circuit board sublayer with a metal sleeve.
  • the metal sleeve can be easily fabricated in the main body of the circuit board layer. Therefore, the relative positional relationship between the circuit board layer main body and the metal sleeve shown in this embodiment facilitates the production of the metal sleeve on the circuit board layer main body.
  • the metal sleeve penetrates the main body of the circuit board layer; the position of the metal sleeve corresponding to the first signal line is provided with a first notch, and the edge of the metal sleeve at the first notch is separated from the first signal line by an insulating material.
  • the metal sleeve is provided with a second gap at a position corresponding to the second signal line, and the edge of the metal sleeve at the second gap is separated from the second signal line by an insulating material.
  • the metal sleeve and the first signal line are separated by the insulating material in the first gap, and the metal sleeve and the second signal line are separated by the insulating material in the second gap. Since the metal sleeve penetrates the main body of the circuit board layer, the shielding path of the metal sleeve to the metalized via is longer, and the shielding effect is better.
  • the inner wall of the metal sleeve is separated from the outer wall of the metalized via by an insulating material.
  • the insulating material between the inner wall of the metal sleeve and the outer wall of the metalized via is a material with a dielectric constant lower than 2. In this way, the insulating performance of the insulating material is better.
  • the metal can still be realized by filling a smaller amount of insulating material in the smaller gap. Insulation between the sleeve and the metalized via.
  • the surface of the second circuit board sublayer facing the first circuit board sublayer is the third surface, and the surface of the second circuit board sublayer facing the third circuit board sublayer is the fourth surface;
  • the second circuit board sublayer is composed of a metal layer And insulating dielectric layers alternately and stacked in sequence, and the parts forming the third surface and the fourth surface of the second circuit board sublayer are all metal layers, and the metal reference surface in the metal layer is the reference ground;
  • the metal sleeve is along its own axis The upward end is electrically connected to the metal reference surface in the metal layer where the third surface is located, and the other end of the metal sleeve in its axial direction is connected to the metal reference surface in the metal layer where the fourth surface is located. Electric connection. In this way, the reflow performance of the metal sleeve is better, and the shielding effect of the metalized via is better.
  • the circuit board layer further includes: a plurality of metallized holes arranged on the main body of the circuit board layer and arranged around the periphery of the metal sleeve, and the plurality of metallized holes and the first signal line , The second signal lines are insulated, and a plurality of metallized holes are electrically connected to the reference ground.
  • the multiple metallized holes are equipotential with the metal reference surface in the metal layer in the main body of the circuit board layer, and the metallized vias can be secondarily shielded through the multiple metallized holes to avoid the occurrence of metal sleeves during the manufacturing process. Cracking causes leakage of electromagnetic energy.
  • the plurality of metallized holes includes a first metallized hole, the orthographic projection of the first metallized hole on the first surface does not overlap with the occupied area of the first signal line on the first surface, and the first metallized hole is The orthographic projection of the second surface does not overlap with the occupied area of the second signal line on the second surface, and the first metallized hole is a through hole penetrating the main body of the circuit board layer.
  • the first metallized hole can shield each position of the metallized via along its own length direction, and the shielding effect is better.
  • the plurality of metallized holes includes a second metallized hole, the orthographic projection of the second metallized hole on the first surface at least partially overlaps the occupied area of the first signal line on the first surface, and the second metallized hole The orthographic projection on the second surface does not overlap with the occupied area of the second signal line on the second surface.
  • the second metallized hole is a blind hole with one end penetrating the second surface and the other end not penetrating the first surface. In this way, the part of the metalized via near the second surface that is not shielded and protected by the metal sleeve can be shielded and protected by the second metalized hole, so that the shielding effect of the metalized via can be improved.
  • the second metallized hole is separated from the first signal line to achieve insulation between the second metallized hole and the first signal line.
  • the orthographic projection of the second metalized hole on the central axis of the metalized via is in contact with or partially overlaps with the orthographic projection of the metal sleeve on the central axis of the metalized via.
  • the second metallization hole penetrates at least the third circuit board sublayer in the circuit board layer main body.
  • the plurality of metallized holes includes a third metallized hole
  • the orthographic projection of the third metallized hole on the first surface does not overlap with the occupied area of the first signal line on the first surface
  • the third metallized hole is The orthographic projection of the second surface at least partially overlaps the occupied area of the second signal line on the second surface
  • the third metallized hole is a blind hole with one end penetrating the first surface and the other end not penetrating the second surface.
  • the part of the metalized via near the first surface that is not shielded and protected by the metal sleeve can be shielded and protected by the third metalized hole, so that the shielding effect of the metalized via can be improved.
  • the third metallized hole is separated from the second signal line to achieve insulation between the third metallized hole and the second signal line.
  • the orthographic projection of the third metalized hole on the central axis of the metalized via is in contact with or partially overlaps with the orthographic projection of the metal sleeve on the central axis of the metalized via.
  • the third metallized hole penetrates at least the first circuit board sublayer in the circuit board layer main body. In this way, the part of the metalized via near the first surface that is not shielded and protected by the metal sleeve can be effectively shielded through the third metalized hole, so that the shielding effect of the metalized via can be further improved.
  • the plurality of metallized holes includes a fourth metallized hole, and the orthographic projection of the fourth metallized hole on the first surface at least partially overlaps the occupied area of the first signal line on the first surface, and the fourth metallized hole
  • the orthographic projection on the second surface at least partially overlaps the occupied area of the second signal line on the second surface, and the fourth metallized hole is a buried hole whose two ends do not penetrate the first surface and the second surface.
  • the fourth metallized hole is separated from the first signal line and the second signal line, and the fourth metallized hole is insulated from the first signal line and the second signal line.
  • the inner diameter of the metal sleeve is 2.4 to 4 times the outer diameter of the metalized via.
  • the distance between the metal sleeve and the metalized via is moderate, which can take into account the electromagnetic energy loss of the metalized via and the processing difficulty of the circuit board at the same time.
  • the first signal line and the second signal line are both signal lines that transmit high-frequency signals with a highest frequency above 1 GHz.
  • an end of the metallized via located on the first surface and the first signal line is connected with a non-perforated disk or connected by a circular orifice disk, a shrinking orifice disk or a teardrop orifice disk.
  • an end of the metalized via located on the second surface and the second signal line are connected with a non-perforated disk or connected by a circular orifice disk, a shrinking orifice disk or a teardrop orifice disk.
  • some embodiments of the present application provide an electronic device that includes a processor, a circuit board as described in any of the above technical solutions, and an antenna.
  • the circuit board is a circuit board that realizes the function of transmitting and receiving antenna signals.
  • One of the antennas is coupled to the first signal line of the circuit board, and the other of the processor and the antenna is coupled to the second signal line of the circuit board.
  • the electronic device provided by the embodiments of the present application includes the circuit board as described in any of the above technical solutions, and the circuit board can realize the antenna signal transceiving function, it can reduce the energy loss of the antenna signal in the transceiving process, and improve the signal transmission and Receiving efficiency.
  • some embodiments of the present application provide a method for processing a circuit board, and the method for processing the circuit board includes:
  • the circuit board layer body has a first surface and a second surface.
  • the circuit board layer body is provided with a reference ground inside, and the metalized via hole penetrates the circuit board layer.
  • the main body, the metal sleeve is arranged in the circuit board layer main body and sleeved on the periphery of the metalized via hole, the metal sleeve is insulated from the metalized via hole, and the metal sleeve is electrically connected to the reference ground in the circuit board layer main body;
  • a first signal line is provided on the first surface of the circuit board layer body, and the first signal line is electrically connected to one end of the metalized via located on the first surface of the circuit board layer body, and the first signal line is insulated from the metal sleeve ;
  • a second signal line is provided on the second surface of the circuit board layer body, and the second signal line is electrically connected to one end of the metalized via located on the second surface of the circuit board layer body, and the second signal line is insulated from the metal sleeve .
  • the circuit board processing method provided by the embodiment of the present application includes manufacturing a circuit board layer body with a metalized via and a metal sleeve, and the metal sleeve is sleeved on the periphery of the metalized via, the metal sleeve and the circuit
  • the reference ground in the main body of the board layer is electrically connected, so the metal sleeve and the reference ground in the main body of the circuit board layer are at the same potential, and the metal sleeve acts as a shield for the metalized via.
  • the first aspect can prevent the electromagnetic waves generated by the metalized vias from radiating to the main body of the circuit board layer outside the metal sleeve, so that the electromagnetic energy is concentrated in the metal sleeve and directed to the second signal along the metalized vias.
  • Wire transmission which can reduce the electromagnetic energy loss and reduce the insertion loss of the metalized via.
  • the impedance continuity between the first signal line and the metallized via and between the metallized via and the second signal line can be increased, thereby reducing the signal transmission from the first signal line to the metal When the via is formed, and the reflection when transferred from the metallized via to the second signal line, the return loss is reduced.
  • the circuit board layer main body includes a first circuit board sublayer, a second circuit board sublayer, and a third circuit board sublayer, and the second circuit board sublayer is provided with a reference ground; making a metalized via and a metal sleeve
  • the circuit board layer main body includes: a metal sleeve is arranged on the second circuit board sublayer, the metal sleeve penetrates the second circuit board sublayer, the metal sleeve is electrically connected to the reference ground in the second circuit board sublayer, and is connected to the metal sleeve
  • An insulating material is arranged inside to form a second circuit board sublayer with a metal sleeve; the first circuit board sublayer, the second circuit board sublayer with the metal sleeve, and the third circuit board sublayer are laminated and fixed together,
  • the first circuit board sublayer and the third circuit board sublayer are respectively located on opposite sides of the second circuit board sublayer with a metal sleeve to form a circuit board layer body with
  • This method is simple and easy to implement, and can ensure the relative position accuracy of the metalized via and the metal sleeve in the circuit board main body.
  • the metalized via since the metallized via is provided on the main body of the circuit board layer with a metal sleeve, and the metalized via penetrates the main body of the circuit board layer, the metalized via can be formed by one-time drilling and electroplating instead of There are the upper and lower splicing of the hole column and the inner orifice plate structure.
  • disposing a metal sleeve on the second circuit board sublayer, and disposing an insulating material in the metal sleeve includes: disposing a through hole on the second circuit board sublayer; disposing a metal layer on the inner surface of the through hole to pass through The metal layer around the inner surface of the hole constitutes a metal sleeve; the hollow area of the metal sleeve is filled with insulating material.
  • This method is simple, easy to implement, and can ensure the position accuracy of the metal sleeve in the main body of the circuit board layer.
  • disposing a metal sleeve on the second circuit board sublayer, and disposing an insulating material in the metal sleeve includes: arranging a through hole on the second circuit board sublayer; Insulating cylinders, and make the end faces of the insulating cylinders along its own axis are flush with the two surfaces of the second circuit board sublayer.
  • the metal layer around the side walls of the insulating cylinders constitutes a metal sleeve, and the insulating cylinders It is an insulating material arranged in a metal sleeve. This method is simple, easy to implement, and has high operating efficiency.
  • making the circuit board layer body with metalized vias and metal sleeves includes: arranging a through hole on the circuit board layer body; installing a coaxial cylinder in the through hole, and making the coaxial cylinder The end faces at both ends in the axial direction are respectively flush with the first surface and the second surface of the main body of the circuit board layer.
  • the coaxial cylinder includes an inner conductor, an insulating layer and an outer conductor. The insulating layer surrounds the side wall of the inner conductor.
  • the outer conductor is arranged around the side wall of the insulating layer, the inner conductor constitutes a metalized via, and the outer conductor constitutes a metal sleeve; a first groove is provided on the first surface of the circuit board layer body corresponding to the end of the outer conductor , To remove part of the material on the first surface of the outer conductor; set a second groove on the second surface of the circuit board layer body at a position corresponding to the end of the outer conductor to remove part of the material on the second surface of the outer conductor; The first trench and the second trench are filled with insulating material to form a circuit board layer body with a metalized via and a metal sleeve. This method is simple and easy to implement.
  • the method further includes: arranging a plurality of metalized holes on the main body of the circuit board layer, and making the plurality of metalized holes surround the metal sleeve
  • the periphery of the cylinder is arranged in a circle, and the plurality of metallized holes are insulated from the first signal line and the second signal line, and the plurality of metallized holes are electrically connected with the reference ground in the main body of the circuit board layer.
  • the multiple metallized holes are equipotential with the reference ground in the main body of the circuit board layer, and the metallized vias can be secondarily shielded through the multiple metallized holes to prevent the metal sleeve from being broken during the manufacturing process and causing electromagnetic waves. Energy leakage.
  • FIG. 1 is a schematic diagram of the structure of a circuit board provided by some embodiments of the application.
  • FIG. 2 is a schematic diagram of the structure of a circuit board provided by some other embodiments of the application.
  • Fig. 3 is a top view of the circuit board layer in the circuit board shown in Fig. 1 or Fig. 2;
  • FIG. 4 is a schematic diagram of the first cross-sectional structure of the circuit board layer along A-A shown in FIG. 3;
  • Fig. 5 is a schematic diagram of a second cross-sectional structure of the circuit board layer along A-A shown in Fig. 3;
  • FIG. 6 is a schematic diagram of a third cross-sectional structure of the circuit board layer along A-A shown in FIG. 3;
  • FIG. 7 is a perspective view of the circuit board layer shown in FIG. 6 after the main body of the circuit board layer is removed;
  • FIG. 8 is a perspective view of the circuit board shown in FIG. 3 after the main body of the circuit board layer is removed;
  • FIG. 9 is one of the schematic diagrams of the connection structure between the first signal line, the metalized via and the second signal line in the circuit board provided by some embodiments of the application;
  • 10 is the second schematic diagram of the connection structure between the first signal line, the metallized via and the second signal line in the circuit board provided by some embodiments of the application;
  • 11 is the third schematic diagram of the connection structure between the first signal line, the metallized via and the second signal line in the circuit board provided by some embodiments of the application;
  • FIG. 12 is a flowchart of a circuit board processing method provided by some embodiments of the application.
  • FIG. 13 is a flow chart of manufacturing circuit board layers in the circuit board processing method shown in FIG. 12;
  • FIG. 14 is a schematic structural view of the circuit board layer body with metalized vias and metal sleeves obtained in the step of manufacturing the circuit board layer shown in FIG. 13;
  • circuit board layer body 15 is a flow chart of manufacturing the circuit board layer body with metalized vias and metal sleeves in the steps of manufacturing the circuit board layer shown in FIG. 13;
  • FIG. 16 is a schematic structural view of the second circuit board sublayer of the circuit board layer main body in the circuit board layer main body with metalized vias and metal sleeves shown in FIG. 15;
  • FIG. 17 is a schematic structural diagram of a second circuit board sublayer with a metal sleeve formed after a metal sleeve is disposed on the second circuit board sublayer shown in FIG. 16;
  • FIG. 18 is a flow chart of setting a metal sleeve on the second circuit board sublayer and filling the metal sleeve with insulating material in the step of manufacturing the circuit board layer body with metalized vias and metal sleeves shown in FIG. 15;
  • Fig. 19 is a circuit board layer body with a metal sleeve obtained by laminating and fixing the first circuit board sublayer, the second circuit board sublayer with a metal sleeve shown in Fig. 17, and the third circuit board sublayer together Schematic diagram of the structure;
  • FIG. 20 is a schematic structural diagram of a circuit board layer body with a metal sleeve and a metalized via obtained after the circuit board layer body with a metal sleeve shown in FIG. 19 is provided with a metalized via;
  • 21 is a schematic structural diagram of the circuit board layer body with metalized vias, metal sleeves and first signal lines obtained in the process of manufacturing the circuit board layer shown in FIG. 13;
  • FIG. 22 is a schematic diagram of the structure of the circuit board layer body with metalized vias, metal sleeves, first signal lines and second signal lines obtained in the process of manufacturing the circuit board layer shown in FIG. 13;
  • FIG. 23 is a structural block diagram of an electronic device provided by some embodiments of the application.
  • first”, “second”, and “third” are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first”, “second”, and “third” may explicitly or implicitly include one or more of these features.
  • Coupled is used to indicate electrical connection, including direct connection through wires or connecting ends or indirect connection through other devices. Therefore, “coupling” should be regarded as an electronic communication connection in a broad sense.
  • a circuit board is a carrier for electrical connection of electronic components.
  • the circuit board involved in this application is used to transmit high-frequency signals with a highest frequency above 1 GHz.
  • microwave, millimeter wave the highest frequency is in the range of 30GHz to 300GHz
  • terahertz wave the highest frequency is in the range of 100GHz-10THz
  • high dynamic Digital signals are all high-frequency signals with the highest frequency above 1GHz.
  • Applicable equipment for the circuit board used to transmit high-frequency signals includes, but is not limited to, wireless communication equipment, fixed-line communication equipment, IT high-power computers and interconnection equipment, radio frequency terminals, drones or vehicle-mounted products.
  • Circuit boards used to transmit high-frequency signals include, but are not limited to, printed circuit boards (PCBs), package carrier boards, and the like.
  • the package carrier can be a system in a package (SIP) carrier, a multichip module (MCM) package carrier, or a ball grid array package (BGA) carrier, etc. .
  • the circuit board is composed of a metal layer and an insulating dielectric layer alternately arranged in sequence, wherein the metal layer includes a signal line and/or a metal reference plane.
  • the signal lines in different metal layers are connected by metalized vias.
  • the impedance matching between the metallized via and the signal lines in two different metal layers is poor, resulting in the connection between the metallized via and the signal lines in the two different metal layers.
  • a large number of reflections of the signal are generated, so the return loss is relatively large.
  • this application provides an electronic device, which includes but is not limited to wireless communication devices, integrated circuits or chip products such as radio frequency integrated circuit (RFIC), millimeter wave antenna modules, Fixed-line communication equipment, IT high-energy computers and interconnection equipment, radio frequency terminals, drones or vehicle-mounted products.
  • wireless communication devices integrated circuits or chip products
  • RFIC radio frequency integrated circuit
  • millimeter wave antenna modules Fixed-line communication equipment
  • IT high-energy computers and interconnection equipment radio frequency terminals, drones or vehicle-mounted products.
  • FIG. 23 is a structural block diagram of an electronic device provided by some embodiments of the application.
  • the electronic device includes a processor 10, a circuit board 20, and an antenna 30.
  • the processor 10 is used to generate a transmission signal or process a reception signal, and the processor 10 may be a baseband processor, a digital signal processor, a microprocessor, or a central processing unit.
  • the circuit board 20 is a circuit board used to implement the antenna signal transceiving function, and is also called a transceiver, a radio frequency transceiver, a radio frequency circuit, or a signal transceiving circuit.
  • the circuit board 20 is used to receive the transmission signal from the processor 10, modulate and process the transmission signal, and transmit the transmission signal to the antenna 30. At the same time, the circuit board 20 is also used to demodulate, process and transmit the received signal received by the antenna 30 to the processing unit. ⁇ 10.
  • the present application also provides a circuit board, which is used to transmit high-frequency signals with a highest frequency above 1 GHz, and the circuit board includes but is not limited to a printed circuit board (PCB) and a package carrier board.
  • the circuit board is applied to the above-mentioned electronic equipment.
  • the circuit board is equipped with a grounded metal sleeve on the metalized via to concentrate the electromagnetic energy of the high-frequency signal in the metalized via for transmission, so that the energy can continue to be transmitted along the predetermined transmission direction. Reduce the insertion loss of metallized vias.
  • the impedance continuity between the metalized via and the signal line can be increased, and the reflection of the signal at the connection between the metalized via and the signal line can be reduced. , Reduce return loss.
  • FIG. 1 is a schematic diagram of the structure of a circuit board provided by some embodiments of the application.
  • the circuit board includes a circuit board layer 1. It can be known that the circuit board may only include the circuit board layer 1, or may include other circuit board layers in addition to the circuit board layer 1, which is not specifically limited here.
  • Fig. 1 shows an example in which the circuit board only includes the circuit board layer 1, which should not be considered as limiting the application.
  • FIG. 2 is a schematic diagram of the structure of a circuit board provided by some other embodiments of the application.
  • the circuit board in addition to the circuit board layer 1, the circuit board also includes a circuit board layer 2 and a circuit board layer 3.
  • the circuit board layer 1, the circuit board layer 2, and the circuit board layer 3 are laminated and fixed together.
  • the board layer 2 and the circuit board layer 3 are respectively located on opposite sides of the circuit board layer 1.
  • FIG. 3 is a top view of the circuit board layer of the circuit board shown in FIG. 1 or FIG. 2, and FIG. 4 is a schematic diagram of the first cross-sectional structure of the circuit board layer shown in FIG. 3 along A-A.
  • the circuit board layer 1 includes a circuit board layer main body 11, a first signal line 12, a second signal line 13, a metalized via 14 and a metal sleeve 15.
  • the circuit board layer main body 11 has a first surface 100 and a second surface 200 opposite to each other, and a reference ground is provided inside the circuit board layer main body 11.
  • the first signal line 12 is arranged on the first surface 100, and the second signal line 13 is arranged on the second surface 200.
  • the first signal line 12 and the second signal line 13 are used to transmit high frequency with the highest frequency above 1 GHz.
  • the signal specifically, the first signal line 12 and the second signal line 13 may be microstrip lines.
  • the circuit board is used as the circuit board 20 in the electronic device shown in FIG. 23, since the first signal line 12 and the second signal line 13 transmit high-frequency signals, the first signal line 12 and the second signal line 13 are in the circuit
  • the board 20 is connected to a part of the circuit of the antenna 30.
  • the processor 10 is coupled to the circuit board 20, and the first signal line 12 or the second signal line 13 of the circuit board 20 is coupled to the antenna 30.
  • the metallized via 14 is disposed on the circuit board layer main body 11 and penetrates the circuit board layer main body 11. One end of the metallized via 14 located on the first surface 100 is electrically connected to the first signal line 12, and one end of the metallized via 14 located on the second surface 200 is electrically connected to the second signal line 13.
  • first signal line 12 and the second signal line 13 are electrically connected through the metalized via 14.
  • the high-frequency signal can be transmitted from the first signal line 12 to the second signal line 13 through the metalized via 14, or
  • the second signal line 13 transmits to the first signal line 12 through the metalized via 14.
  • the metal sleeve 15 may be made of copper or copper alloys, or other metal conductive materials (such as iron, aluminum, and iron or aluminum alloys), which is not specifically limited herein.
  • the cross-sectional profile shape of the metal sleeve 15 is not limited to a circle, but can also be elliptical, triangular or polygonal, and the cross-sectional profile shape of each part of the metal sleeve 15 in the axial direction can be consistent or inconsistent. There is no specific limitation.
  • the metal sleeve 15 is disposed in the circuit board layer body 11 and sleeved around the periphery of the metalized via 14.
  • the metal sleeve 15 may be a ring-shaped metal layer formed in the circuit board main body 11, or a metal cylindrical structure embedded in the circuit board main body 11, which is not specifically limited here.
  • the metal sleeve 15 may be formed by ring-shaped metal layer units formed in a plurality of circuit board sublayers in the circuit board layer main body 11 along the circuit
  • the plate layer body 11 is formed by splicing in the thickness direction, and it can also be a whole ring-shaped metal layer, which is not specifically limited here.
  • the metal sleeve 15 is insulated from the metalized via 14, the first signal line 12, and the second signal line 13, and the metal sleeve 15 is electrically connected to the reference ground in the circuit board layer main body 11.
  • the metal sleeve 15 is equipotential with the reference ground in the circuit board layer main body 11, and the metal sleeve 15 forms the reference surface of the metalized via 14 and can shield the metalized via 14.
  • the metal sleeve The barrel 15 can prevent the electromagnetic wave generated when the high-frequency signal passes through the metalized via hole 14 from radiating into the circuit board layer body 11 outside the metal sleeve 15, so that the electromagnetic energy can be concentrated in the metal sleeve 15 and along the metalized
  • the hole 14 continues to transmit to the first signal line 12 or the second signal line 13, so that the electromagnetic energy loss can be reduced, and the insertion loss of the metalized via 14 can be reduced.
  • the metal sleeve 15 can improve the impedance continuity between the first signal line 12 and the metalized via 14 and between the metalized via 14 and the second signal line 13, thereby reducing the high frequency signal
  • the reflection when transmitted from the first signal line 12 to the metalized via 14 or when transmitted from the second signal line 13 to the metalized via 14 reduces the return loss.
  • the metal sleeve 15 can effectively avoid crosstalk between the metalized via 14 and other metalized vias outside the metal sleeve 15.
  • an insulating material 16 is passed between the inner wall of the metal sleeve 15 and the outer wall of the metalized via hole 14. Separate.
  • the insulating material 16 between the inner wall of the metal sleeve 15 and the outer wall of the metalized via 14 is a material with a dielectric constant lower than 2. In this way, the insulation performance of the insulating material 16 is better. When the distance between the inner wall of the metal sleeve 15 and the outer wall of the metalized via 14 is small, a smaller amount of insulation filled in the smaller gap can still be used. The material 16 realizes the insulation between the metal sleeve 15 and the metalized via 14.
  • the circuit board layer main body 11 includes a first circuit board sublayer 111, a second circuit board sublayer 112 and a third circuit board sublayer 113 laminated and fixed together.
  • the second circuit board sublayer 112 is located between the first circuit board sublayer 111 and the third circuit board sublayer 113, and the second circuit board sublayer 112 is provided with a reference ground.
  • the second circuit board sublayer 112 is formed by alternately stacking metal layers a and insulating dielectric layers b.
  • the second circuit board sublayer 112 consists of 8 metal layers a and 7 insulating layers.
  • the dielectric layers b are alternately arranged in sequence.
  • the metal reference plane in the metal layer a is the reference ground.
  • the surface of the first circuit board sublayer 111 away from the second circuit board sublayer 112 is the first surface 100, and at least the portion of the first circuit board sublayer 11 that forms the first surface 100 is an insulating dielectric layer.
  • the insulating dielectric layer can separate the first signal line 12 from the metal layer in the first circuit board sublayer 111 or the metal layer in the second circuit board sublayer 112, avoiding the first signal line 12 and the first circuit board.
  • the metal layers in the layer 111 or the metal layers in the second circuit board sublayer 112 are short-circuited.
  • the first circuit board sub-layer 111 may be composed of only one insulating dielectric layer, or may be formed by alternately stacking insulating dielectric layers and metal layers in turn. It is not specifically limited here, as long as the first circuit board sublayer 11 forms the first surface
  • the part 100 can be an insulating dielectric layer.
  • the first circuit board sublayer 111 is composed of two insulating dielectric layers and a metal layer disposed between the two insulating dielectric layers.
  • FIG. 5 is a schematic diagram of the second cross-sectional structure of the circuit board layer shown in FIG. 3 along A-A.
  • the first circuit board sublayer 111 is composed of only one insulating dielectric layer.
  • the metal layer in the first circuit board sub-layer 111 is insulated from the metalized via 14. In this way, a short circuit between the metal layer in the first circuit board sublayer 111 and the metalized via 14 can be avoided.
  • the surface of the third circuit board sublayer 113 away from the second circuit board sublayer 112 is the second surface 200, and at least the part of the third circuit board sublayer 113 forming the second surface 200 is an insulating dielectric layer.
  • the second signal line 13 can be separated from the metal layer in the third circuit board sublayer 113 or the metal layer in the second circuit board sublayer 112 through the insulating dielectric layer, avoiding the second signal line 13 and the third circuit board.
  • the metal layers in the layer 113 or the metal layers in the second circuit board sublayer 112 are short-circuited.
  • the third circuit board sub-layer 113 may be composed of only one insulating dielectric layer, or may be formed by alternately stacking insulating dielectric layers and metal layers in turn. It is not specifically limited here, as long as the third circuit board sub-layer 113 forms the second surface
  • the portion of 200 can be an insulating dielectric layer.
  • the third circuit board sublayer 113 is composed of only one insulating dielectric layer.
  • the metal layer in the third circuit board sublayer 113 is insulated from the metalized via 14. In this way, a short circuit between the metal layer in the third circuit board sublayer 113 and the metalized via 14 can be avoided.
  • the metal sleeve 15 is disposed on the second circuit board sublayer 112 and penetrates the second circuit board sublayer 112.
  • the metal sleeve 15 is only disposed on the second circuit board sublayer 112, not on the first circuit board sublayer. 111 and the third circuit board sublayer 113, and the metal sleeve 15 is electrically connected to the reference ground in the second circuit board sublayer 112.
  • the two ends of the metal sleeve 15 in the axial direction do not penetrate the first surface 100 and the second surface 200, and the metal sleeve 15 and the first signal line 12 are insulated and isolated by the first circuit board sublayer 111, and the metal sleeve The barrel 15 and the second signal line 13 are insulated and isolated by the third circuit board sublayer 113.
  • the process of fabricating the metal sleeve 15 in the circuit board layer body 11 may be as follows: first, fabricating the metal sleeve 15 on the second circuit board sub-layer 112, and making the metal sleeve 15 penetrate the second circuit board sub-layer 112 to The second circuit board sublayer 112 with the metal sleeve 15 is formed; then, the first circuit board sublayer 111, the second circuit board sublayer 112 with the metal sleeve 15 and the third circuit board sublayer 113 are laminated and fixed together, and The first circuit board sublayer 111 and the third circuit board sublayer 113 are respectively located on opposite sides of the second circuit board sublayer 112 with the metal sleeve 15.
  • the metal sleeve 15 can be easily fabricated in the main body 11 of the circuit board layer. Therefore, the relative positional relationship between the circuit board layer main body 11 and the metal sleeve 15 shown in this embodiment facilitates the production of the metal sleeve 15 on the circuit board layer main body 11.
  • the surface of the second circuit board sublayer 112 facing the first circuit board sublayer 111 is the third surface 300
  • the surface of 113 is the fourth surface 400.
  • the portions of the second circuit board sublayer 112 that form the third surface 300 and the fourth surface 400 are both metal layers.
  • One end of the metal sleeve 15 along its own axis is electrically connected to the metal reference surface in the metal layer where the third surface 300 is located, and the other end of the metal sleeve 15 along its own axis is connected to the fourth surface 400.
  • the metal reference surface in the metal layer is electrically connected. In this way, the reflow performance of the metal sleeve 15 is better, and the shielding effect of the metalized via 14 is better.
  • FIG. 6 is a schematic diagram of the third cross-sectional structure of the circuit board layer shown in FIG. 3 along A-A
  • FIG. 7 is a perspective view of the circuit board layer shown in FIG. 6 after the main body of the circuit board layer is removed. As shown in FIGS. 6 and 7, the metal sleeve 15 penetrates the main body 11 of the circuit board layer.
  • the metal sleeve 15 is provided with a first notch 151 at a position corresponding to the first signal line 12, and the edge of the metal sleeve at the first notch 151 is separated from the first signal line 12 by an insulating material.
  • the metal sleeve 15 is provided with a second notch 152 at a position corresponding to the second signal line 13, and the edge of the metal sleeve at the second notch 152 is separated from the second signal line 13 by an insulating material.
  • the metal sleeve 15 and the first signal line 12 are separated by the insulating material in the first gap 151, and the metal sleeve 15 and the second signal line 13 are separated by the insulating material in the second gap 152. Since the metal sleeve 15 penetrates the main body 11 of the circuit board layer, the shielding path of the metal sleeve 15 to the metalized via 14 is longer, and the shielding effect is better.
  • the circuit board layer 1 further includes a plurality of metalized holes 17.
  • a plurality of metallized holes 17 are arranged on the main body 11 of the circuit board layer and arranged around the periphery of the metal sleeve 15.
  • the plurality of metallized holes 17 are insulated from the first signal line 12 and the second signal line 13, and the plurality of metallized holes 17 are electrically connected to the reference ground.
  • the reference ground is the metal reference surface in the metal layer of the circuit board layer body 11, and the plurality of metalized holes 17 are electrically connected to the reference ground, that is, the plurality of metalized holes 17 at least penetrate the circuit board layer body A metal layer in 11, and is electrically connected to the metal reference plane in the metal layer.
  • the multiple metallized holes 17 are equipotential with the metal reference surface in the metal layer of the circuit board layer body 11, and the metallized vias 14 can be secondarily shielded through the multiple metallized holes 17 to prevent the metal sleeve 15 from being Electromagnetic energy leaks due to rupture during the manufacturing process.
  • the metallized hole 17 may be a through hole that penetrates the circuit board layer body 11, or may have one end that penetrates one of the first surface 100 and the second surface 200, and the other end does not penetrate the other of the first surface 100 and the second surface 200.
  • One blind hole may also be a buried hole whose two ends do not penetrate the first surface 100 and the second surface 200, which is not specifically limited here.
  • FIG. 8 is a perspective view of the circuit board shown in FIG. 3 after the main body of the circuit board layer is removed.
  • the plurality of metallized holes 17 includes a first metallized hole 17a.
  • the orthographic projection of the first metallized hole 17a on the first surface 100 is different from the area occupied by the first signal line 12 on the first surface 100. Overlap, and the orthographic projection of the first metalized hole 17a on the second surface 200 does not overlap with the occupied area of the second signal line 13 on the second surface 200, and the first metalized hole 17a penetrates the circuit board layer body 11 Through hole. In this way, the first metallized hole 17a can shield each position of the metallized via 14 along its own length direction, and the shielding effect is better.
  • the plurality of metallized holes 17 includes a second metallized hole 17b.
  • the occupied area of the surface 100 at least partially overlaps, and the orthographic projection of the second metalized hole 17b on the second surface 200 does not overlap with the occupied area of the second signal line 13 on the second surface 200, and the second metalized hole 17b is one end A blind hole that penetrates the second surface 200 and the other end does not penetrate the first surface 100.
  • the portion of the end of the metalized via 14 close to the second surface 200 that is not shielded and protected by the metal sleeve 15 can be shielded and protected by the second metalized hole 17b, so that the shielding effect of the metalized via 14 can be improved.
  • the second metallized hole 17b is separated from the first signal line 12 to achieve insulation between the second metallized hole 17b and the first signal line 12.
  • the depth of the second metallized hole 17b is not specifically limited.
  • the orthographic projection L1 of the second metallized hole 17b on the central axis O of the metallized via 14 and the metal sleeve 15 on the central axis O of the metallized via 14 Orthographic projections L2 meet or partially overlap.
  • the second metallized hole 17 b penetrates at least the third circuit board sub-layer 113 in the circuit board layer main body 11.
  • the portion of the end of the metalized via 14 close to the second surface 200 that is not shielded and protected by the metal sleeve 15 can be effectively shielded by the second metalized hole 17b, so that the shielding effect of the metalized via 14 can be improved.
  • the plurality of metallized holes 17 includes a third metallized hole 17c.
  • the orthographic projection of the third metallized hole 17c on the first surface 100 and the first signal line 12 in the The occupied area of the surface 100 does not overlap, and the orthographic projection of the third metalized hole 17c on the second surface 200 at least partially overlaps the occupied area of the second signal line 13 on the second surface 200, and the third metalized hole 17c is one end A blind hole passing through the first surface 100 and not passing through the second surface 200 at the other end.
  • the part of the metalized via 14 near the first surface 100 that is not shielded and protected by the metal sleeve 15 can be shielded and protected by the third metalized hole 17c, so that the shielding effect of the metalized via 14 can be improved.
  • the third metallized hole 17c is separated from the second signal line 13 to achieve insulation between the third metallized hole 17c and the second signal line 13.
  • the depth of the third metallized hole 17c is not specifically limited.
  • the orthographic projection L3 of the third metallized hole 17c on the central axis O of the metallized via 14 and the metal sleeve 15 on the central axis O of the metallized via 14 Orthographic projections L2 meet or partially overlap.
  • the third metallized hole 17c penetrates at least the first circuit board sub-layer 111 in the circuit board layer main body 11.
  • the third metalized hole 17c can effectively shield the part of the metalized via 14 that is not shielded and protected by the metal sleeve 15 at the end of the metalized via 14 close to the first surface 100, so that the shielding effect of the metalized via 14 can be improved.
  • the plurality of metallized holes includes a fourth metallized hole (not shown in the figure).
  • the orthographic projection of the fourth metallized hole on the first surface 100 is similar to the first signal line 12 on the first surface 100.
  • the occupied area of the fourth metalized hole at least partially overlaps, and the orthographic projection of the fourth metalized hole on the second surface 200 and the occupied area of the second signal line 13 on the second surface 200 at least partially overlap, and the fourth metalized hole does not penetrate through both ends Buried holes of the first surface 100 and the second surface 200.
  • the fourth metallized hole is separated from the first signal line and the second signal line, and the fourth metallized hole is insulated from the first signal line and the second signal line.
  • the inner diameter of the metal sleeve 15 should be designed as small as possible.
  • the inner diameter d2 of the metal sleeve 15 is the outer diameter d1 of the metalized via 14. 2.4 to 4 times of that. In this way, the distance between the metal sleeve 15 and the metalized via hole 14 is moderate, which can simultaneously take into account the electromagnetic energy loss of the metalized via hole 14 and the processing difficulty of the circuit board.
  • the end of the metalized via 14 located on the first surface 100 and the first signal line 12 may be directly electrically connected, or may be indirectly electrically connected through the first hole plate 500, which is not specifically limited herein.
  • the end of the metalized via 14 located on the first surface 100 is directly electrically connected to the first signal line 12, that is, a non-perforated disk connection.
  • FIG. 9 is one of the schematic diagrams of the connection structure between the first signal line, the metallized via and the second signal line in the circuit board provided by some embodiments of the application.
  • FIG. 10 is the second schematic diagram of the connection structure between the first signal line, the metallized via and the second signal line in the circuit board provided by some embodiments of the application.
  • FIG. 11 is the third schematic diagram of the connection structure between the first signal line, the metalized via and the second signal line in the circuit board provided by some embodiments of the application.
  • the first orifice plate 500 may be a circular orifice plate as shown in FIG. 9, or a shrinking orifice plate as shown in FIG. 10, or a teardrop orifice plate as shown in FIG. 11, which is not specifically limited herein.
  • the end of the metalized via 14 located on the second surface 200 and the second signal line 13 may be directly electrically connected, or may be indirectly electrically connected through the second hole plate, which is not specifically limited here.
  • the end of the metalized via 14 located on the second surface 200 and the second signal line 13 are directly electrically connected, that is, a non-perforated disk connection.
  • the end of the metalized via 14 located on the second surface 200 and the second signal line 13 are indirectly electrically connected through the second hole plate.
  • the second orifice disc may be a circular orifice disc, or a shrink orifice disc, or a teardrop orifice disc, which is not specifically limited here.
  • the application also provides a method for processing a circuit board, which is used for processing the circuit board as described in any of the above embodiments.
  • FIG. 12 is a flowchart of a circuit board processing method provided by some embodiments of the application. As shown in FIG. 12, the processing method of the circuit board includes: S100: making circuit board layer 1.
  • Step S100 may be the method of making the circuit board layer 1 shown in FIG. 4, the method of making the circuit board layer 1 shown in FIG. 5, the method of making the circuit board layer 1 shown in FIG. 6, or the method of making The method of the circuit board layer 1 in other structural forms in the foregoing embodiment is not specifically limited here.
  • the following examples for each sub-step in step S100 are introduced by taking the production of the circuit board layer 1 shown in FIG. 4 as an example, and should not be considered as a limitation on the composition of the application.
  • FIG. 13 is a flowchart of manufacturing circuit board layer 1 in the circuit board processing method shown in FIG. 12.
  • step S100 includes:
  • the circuit board layer main body 11 has a first surface 100 and a second surface 200 opposite to each other.
  • a reference ground is provided inside the main body 11 of the circuit board layer.
  • the metallized via 14 penetrates the main body 11 of the circuit board layer.
  • the metal sleeve 15 is disposed in the circuit board layer body 11 and sleeved around the periphery of the metalized via 14.
  • the metal sleeve 15 is insulated from the metalized via hole 14.
  • the metal sleeve 15 and the metalized via hole 14 are separated by an insulating material 16.
  • the metal sleeve 15 is electrically connected to the reference ground in the circuit board layer main body 11.
  • the structure of the circuit board layer body 11 with the metalized via 14 and the metal sleeve 15 obtained in step S101 may be the structure shown in FIG. 14.
  • the first signal line 12 is provided on the first surface 100 of the circuit board layer body 11, and the first signal line 12 is electrically connected to one end of the metalized via 14 located on the first surface 100 of the circuit board layer body 11,
  • the first signal line 12 is insulated from the metal sleeve 15.
  • the structure of the circuit board layer body 11 with the metallized via 14, the metal sleeve 15 and the first signal line 12 obtained in step S102 may be the structure shown in FIG. 21.
  • the second signal line 13 is provided on the second surface 200 of the circuit board layer body 11, and the second signal line 13 is electrically connected to the end of the metalized via 14 located on the second surface 200 of the circuit board layer body 11.
  • the second signal line 13 is insulated from the metal sleeve 15.
  • the structure of the circuit board layer body 11 with the metalized via 14, the metal sleeve 15, the first signal line 12, and the second signal line 13 obtained in step S103 may be the structure shown in FIG. 22.
  • the metal sleeve 15 is provided on the circuit board body 11, the metal sleeve 15 is arranged in the circuit board layer body 11 and sleeved on the metalized via 14 Around the periphery, the metal sleeve 15 is electrically connected to the reference ground in the circuit board layer body 11, so the metal sleeve 15 is equipotential with the reference ground in the circuit board layer body 11, and the metal sleeve 15 forms the metalized via 14
  • the reference plane can shield the metallized via 14.
  • the metal sleeve The barrel 15 can prevent the electromagnetic wave generated when the high-frequency signal passes through the metalized via hole 14 from radiating into the circuit board layer body 11 outside the metal sleeve 15, so that the electromagnetic energy can be concentrated in the metal sleeve 15 and along the metalized
  • the hole 14 continues to transmit to the first signal line 12 or the second signal line 13, so that the electromagnetic energy loss can be reduced, and the insertion loss of the metalized via 14 can be reduced.
  • the metal sleeve 15 can improve the impedance continuity between the first signal line 12 and the metalized via 14 and between the metalized via 14 and the second signal line 13, thereby reducing the high frequency signal
  • the reflection when transmitted from the first signal line 12 to the metalized via 14 or when transmitted from the second signal line 13 to the metalized via 14 reduces the return loss.
  • the metal sleeve 15 can effectively avoid crosstalk between the metalized via 14 and other metalized vias outside the metal sleeve 15.
  • step S101 may have multiple optional implementation manners, for example, it may be the following two optional implementation manners:
  • the circuit board layer main body includes a first circuit board sublayer 111, a second circuit board sublayer 112, and a third circuit board sublayer 113, and the second circuit board sublayer 112 is provided with a reference ground.
  • FIG. 15 is a flowchart of manufacturing the circuit board layer body with metalized vias and metal sleeves in the steps of manufacturing the circuit board layer shown in FIG. 13. As shown in Fig. 15, step S101 includes:
  • a metal sleeve 15 is provided on the second circuit board sublayer 112.
  • the metal sleeve 15 penetrates the second circuit board sublayer 112.
  • the metal sleeve 15 is electrically connected to the reference ground in the second circuit board sublayer 112, and is connected to the metal
  • An insulating material is arranged in the sleeve 12 to form the second circuit board sublayer 112 with the metal sleeve 15.
  • the second circuit board sublayer 112 is formed by alternately stacking metal layers a and insulating dielectric layers b in sequence.
  • the metal layer a includes signal lines and/or metal reference planes, and the reference ground in the second circuit board sublayer 112 is The metal reference plane in the metal layer a in the second circuit board sublayer 112.
  • the structure of the second circuit board sublayer 112 may be as shown in FIG. 16.
  • FIG. 17 is a schematic structural diagram of the second circuit board sublayer 112 with the metal sleeve 15 formed after the metal sleeve 15 is provided on the second circuit board sublayer 112 shown in FIG. 16. As shown in FIG. 17, the metal The sleeve 15 penetrates the second circuit board sublayer 112, and the metal sleeve 15 is filled with an insulating material 16.
  • step S1011 can have various embodiments.
  • step S1011 includes: providing a through hole on the second circuit board sublayer 112; installing an insulating column with a metal layer around the sidewall in the through hole , And make the two end faces of the insulating cylinder along its own axis are flush with the two surfaces of the second circuit board sublayer 112.
  • the metal layer around the side wall of the insulating cylinder constitutes a metal sleeve 15.
  • the body is an insulating material 16 filled in a metal sleeve.
  • This method is simple, easy to implement, and has high operating efficiency.
  • FIG. 18 is a step of manufacturing the circuit board layer body with metalized vias and metal sleeves as shown in FIG.
  • the flowchart of filling the insulating material is shown in FIG. 18.
  • Step S1011 includes: S10111: setting a through hole on the second circuit board sublayer 112; S10112: setting a metal layer on the inner surface of the through hole, and the inner surface of the through hole One round of the metal layer constitutes the metal sleeve 15; S10123: the hollow area of the metal sleeve 15 is filled with insulating material 16.
  • This method is simple and easy to implement, and can ensure the position accuracy of the metal sleeve 15 in the circuit board layer main body 11.
  • step S101 also includes: S1012: stacking and fixing the first circuit board sublayer 111, the second circuit board sublayer 112 with the metal sleeve 15 and the third circuit board sublayer 113 together, and making the A circuit board sublayer 111 and a third circuit board sublayer 113 are respectively located on opposite sides of the second circuit board sublayer 112 with the metal sleeve 15 to form the circuit board layer body 11 with the metal sleeve 15.
  • the metal sleeve with the metal sleeve shown in FIG. 19 can be obtained.
  • the surface of the first circuit board sublayer 111 away from the second circuit board sublayer 112 forms the first surface 100 of the circuit board layer main body 11, and the first circuit board sublayer 11 At least the part forming the first surface 100 is an insulating dielectric layer.
  • the insulating dielectric layer can separate the first signal line 12 from the metal layer in the first circuit board sublayer 111 and the metal layer in the second circuit board sublayer 112, avoiding the first signal line 12 and the first circuit board.
  • the first signal line 12 and the metal sleeve 15 can be separated by the insulating medium layer, and the insulation between the first signal line 12 and the metal sleeve 15 can be realized.
  • the surface of the third circuit board sublayer 113 away from the second circuit board sublayer 112 forms the second surface 200 of the circuit board layer main body 11, and the third circuit board sublayer 113 At least the portion forming the second surface 200 is an insulating dielectric layer.
  • the second signal line 13 can be separated from the metal layer in the third circuit board sublayer 113 and the metal layer in the second circuit board sublayer 112 through the insulating dielectric layer, avoiding the second signal line 13 and the third circuit board.
  • the second signal line 13 and the metal sleeve 15 can be separated by the insulating dielectric layer, so as to achieve insulation between the second signal line 13 and the metal sleeve 15.
  • first circuit board sub-layer 111, the second circuit board sub-layer 112 with the metal sleeve 15 and the third circuit board sub-layer 113 can be fixed together by processes such as gluing, lamination, etc., which will not be specifically described here. limited.
  • step S101 further includes: S1013: providing a metalized via 14 on the circuit board layer body 11 with a metal sleeve 15, and making the metalized via 14 pass through the insulation in the metal sleeve 15.
  • the material 16 penetrates the main body 11 of the circuit board layer.
  • FIG. 20 is a circuit board layer body with a metal sleeve 15 and a metalized via hole 14 obtained after the metalized via hole 14 is provided on the circuit board layer body 11 with the metal sleeve 15 shown in FIG. 19 11 Schematic diagram of the structure.
  • the method of manufacturing the circuit board layer body 11 with the metalized via 14 and the metal sleeve 15 shown in FIG. 15 is simple, easy to implement, and can ensure that the metalized via 14 and the metal sleeve 15 are in the circuit board body 11 Relative position accuracy.
  • the metalized via 14 since the metalized via 14 is provided on the circuit board layer body 11 with the metal sleeve 15, and the metalized via hole 14 penetrates the circuit board layer body 11, the metalized via hole 14 can be drilled at a time. Holes are formed by electroplating, without the upper and lower splicing of the hole pillars and the inner orifice plate structure.
  • Step S101 includes: setting a through hole on the circuit board layer main body 11; installing a coaxial cylinder in the through hole, and making the two ends of the coaxial cylinder along its own axis The end faces are respectively flush with the first surface 100 and the second surface 200 of the circuit board layer body 11.
  • the coaxial cylinder includes an inner conductor, an insulating layer and an outer conductor.
  • the insulating layer is arranged around the side wall of the inner conductor, and the outer conductor surrounds
  • the side wall of the insulating layer is set around, the inner conductor constitutes a metalized via, and the outer conductor constitutes a metal sleeve;
  • a first groove is provided on the first surface of the circuit board layer body at a position corresponding to the end of the outer conductor to remove the outer conductor Part of the material on the first surface of the circuit board layer body; set a second groove on the second surface of the circuit board layer body corresponding to the end of the outer conductor to remove part of the material on the second surface of the outer conductor; in the first groove
  • the second trench is filled with insulating material to form a circuit board layer body with metalized vias and metal sleeves.
  • step S101 it further includes: arranging a plurality of metallized holes 17 on the circuit board layer main body 11, and arranging the plurality of metallized holes 17 around the periphery of the metal sleeve 15, and more
  • the two metalized holes 17 are insulated from the first signal line 12 and the second signal line 13, and the multiple metalized holes 17 are electrically connected to the reference ground in the circuit board layer main body 11.
  • the multiple metalized holes 17 are equipotential with the reference ground in the circuit board layer body 11, and the metalized vias 14 can be secondarily shielded through the multiple metalized holes 17 to prevent the metal sleeve 15 from being damaged during the manufacturing process. A rupture occurs, causing leakage of electromagnetic energy.
  • the method further includes: stacking and fixing the circuit board layer 1 and other circuit board layers together to form a circuit board.

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Abstract

本申请提供一种电路板、电子设备和电路板的加工方法，涉及电子设备技术领域，能够降低电路板内金属化过孔的插入损耗。其中，电路板包括电路板层，该电路板层包括电路板层主体、第一信号线、第二信号线、金属化过孔和金属套筒；电路板层主体的内部设有参考地；电路板层主体具有相对的第一表面和第二表面，第一信号线和第二信号线分别设置于第一表面和第二表面；金属化过孔贯穿电路板层主体，且金属化过孔的两端分别与第一信号线和第二信号线电连接；金属套筒设置于电路板层主体内并套设于金属化过孔的外围一周，金属套筒与电路板层主体内的参考地电连接。本申请实施例提供的电路板用于PCB板或者封装载板。

Description

一种电路板、电子设备和电路板的加工方法 技术领域
本申请涉及电子设备技术领域，尤其涉及一种电路板、电子设备和电路板的加工方法。
背景技术
目前，最高频率在1GHz以上的高频信号，比如毫米波(最高频率在30GHz～300GHz范围内)，在移动通信、定位导航、卫星遥感、射电天文、气象物理等领域有大量的应用。
随着高频技术的快速发展，在用于传输高频信号的电路板内，高频线路的插入损耗和回波损耗对电路板的整体性能起到至关重要的作用。尤其是在有些电路板中，由于电路板布局的限制，高频线路需要布局在电路板内的不同金属层中，这样通常采用金属化过孔来实现两个不同金属层中的高频线路之间的电连接。这样，高频信号在经过金属化过孔时，一方面，容易向金属化过孔周围的电路板内辐射电磁波，从而将大量的电磁能量扩散到了电路板内，导致部分能量不能沿着预定的传递方向继续传递，因此金属化过孔的插入损耗较大；另一方面，金属化过孔与两个不同金属层中的高频线路之间的阻抗匹配度较差，导致在金属化过孔与两个不同金属层中的高频线路之间的连接处，会产生信号的大量反射，因此回波损耗较大。这两方面的因素导致了电路板的性能大幅下降，信号传输失真较大。
发明内容
本申请提供一种电路板、电子设备和电路板的加工方法，能够降低电路板内金属化过孔的插入损耗，同时能够降低金属化过孔与信号线之间连接处的回波损耗，提高电路板的性能。
为达到上述目的，本申请的实施例采用如下技术方案：
第一方面，本申请一些实施例提供一种电路板，该电路板包括电路板层；该电路板层包括电路板层主体、第一信号线、第二信号线、金属化过孔和金属套筒；电路板层主体具有相对的第一表面和第二表面，电路板层主体的内部设有参考地；第一信号线设置于第一表面；第二信号线设置于第二表面；金属化过孔设置于电路板层主体上并贯穿电路板层主体，金属化过孔的位于第一表面的一端与第一信号线电连接，金属化过孔的位于第二表面的一端与第二信号线电连接；金属套筒设置于电路板层主体内，并套设于金属化过孔的外围一周，金属套筒与金属化过孔、第一信号线、第二信号线之间均绝缘，金属套筒与电路板层主体内的参考地电连接。
在本申请实施例提供的电路板中，由于金属套筒设置于电路板层主体内，并套设于金属化过孔的外围一周，且金属套筒与电路板层主体内的参考地电连接，因此金属套筒与电路板层主体内的参考地等电位，该金属套筒对金属化过孔起到屏蔽作用。这样，第一方面，能够阻止金属化过孔产生的电磁波辐射到位于金属套筒外部的电路板层主体中去，使电磁能量集中在金属套筒内并沿着金属化过孔向第二信号线传递，从 而能够减小电磁能量损失，降低金属化过孔的插入损耗。第二方面，能够增大第一信号线与金属化过孔之间、以及金属化过孔与第二信号线之间的阻抗连续性，由此减小信号在由第一信号线传递至金属化过孔时，以及由金属化过孔传递至第二信号线时的反射，降低回波损耗。第三方面，能够有效避免金属化过孔与金属套筒外部的其他金属化过孔或者其他信号线之间产生串扰。
可选地，电路板层主体包括层叠并固定在一起的第一电路板子层、第二电路板子层和第三电路板子层；第二电路板子层位于第一电路板子层与第三电路板子层之间，且第二电路板子层内设有参考地；第一电路板子层的远离第二电路板子层的表面为电路板层主体的第一表面，第一电路板子层的至少形成该第一表面的部分为绝缘介质层；第三电路板子层的远离第二电路板子层的表面为电路板层主体的第二表面，第三电路板子层的至少形成该第二表面的部分为绝缘介质层；金属套筒设置于第二电路板子层上并贯穿该第二电路板子层，且金属套筒与第二电路板子层内的参考地电连接。这样，金属套筒沿自身轴向上的两端未贯穿第一表面和第二表面，金属套筒与第一信号线之间通过第一电路板子层绝缘隔离，金属套筒与第二信号线之间通过第三电路板子层绝缘隔离。而且，在电路板层主体内制作金属套筒的过程可以为：首先，在第二电路板子层上制作金属套筒，并使金属套筒贯穿第二电路板子层，以形成带金属套筒的第二电路板子层；然后，将第一电路板子层、带金属套筒的第二电路板子层、第三电路板子层层叠并固定在一起，并使第一电路板子层和第三电路板子层分别位于该带金属套筒的第二电路板子层的相对两侧。这样，就可以很容易地将金属套筒制作于电路板层主体内。因此，本实施例所示的电路板层主体与金属套筒之间的相对位置关系便于金属套筒在电路板层主体上的制作。
可选地，金属套筒贯穿电路板层主体；金属套筒的对应第一信号线的位置设有第一缺口，第一缺口处的金属套筒边沿与第一信号线之间通过绝缘材料隔开；金属套筒的对应第二信号线的位置设有第二缺口，第二缺口处的金属套筒边沿与第二信号线之间通过绝缘材料隔开。这样，金属套筒与第一信号线之间通过第一缺口内的绝缘材料隔开，金属套筒与第二信号线之间通过第二缺口内的绝缘材料隔开。由于金属套筒贯穿电路板层主体，因此金属套筒对金属化过孔的屏蔽路径较长，屏蔽效果较优。
可选地，金属套筒的内壁一周与金属化过孔的外壁之间通过绝缘材料隔开。
可选地，金属套筒的内壁一周与金属化过孔的外壁之间的绝缘材料为介电常数低于2的材料。这样，绝缘材料的绝缘性能较优，在金属套筒的内壁一周与金属化过孔的外壁之间的间距较小时，仍可以通过填充于该较小间隙内的较少量的绝缘材料实现金属套筒与金属化过孔之间的绝缘。
可选地，第二电路板子层的朝向第一电路板子层的表面为第三表面，第二电路板子层的朝向第三电路板子层的表面为第四表面；第二电路板子层由金属层和绝缘介质层依次交替并堆叠而成，且第二电路板子层的形成第三表面和第四表面的部分均为金属层，金属层中的金属参考面为参考地；金属套筒沿自身轴向上的一端端部与第三表面所处的金属层中的金属参考面电连接，金属套筒沿自身轴向上的另一端端部与第四表面所处的金属层中的金属参考面电连接。这样，金属套筒的回流性能较优，对金属化过孔的屏蔽效果较好。
可选地，电路板层还包括：多个金属化孔，该多个金属化孔设置于电路板层主体上并围绕金属套筒的外围一周排列，且多个金属化孔与第一信号线、第二信号线之间均绝缘，多个金属化孔与参考地电连接。这样，多个金属化孔与电路板层主体内金属层中的金属参考面等电位，可以通过多个金属化孔对金属化过孔进行二次屏蔽，避免金属套筒在制造过程中因出现破裂而造成电磁能量泄露。
可选地，多个金属化孔包括第一金属化孔，该第一金属化孔在第一表面的正投影与第一信号线在第一表面的占用区域不重叠，第一金属化孔在第二表面的正投影与第二信号线在第二表面的占用区域不重叠，第一金属化孔为贯穿电路板层主体的通孔。这样，第一金属化孔可以对金属化过孔沿自身长度方向上的各个位置进行屏蔽，屏蔽效果较优。
可选地，多个金属化孔包括第二金属化孔，该第二金属化孔在第一表面的正投影与第一信号线在第一表面的占用区域至少部分重叠，第二金属化孔在第二表面的正投影与第二信号线在第二表面的占用区域不重叠，第二金属化孔为一端贯穿第二表面，另一端未贯穿第一表面的盲孔。这样，可以通过第二金属化孔对金属化过孔的靠近第二表面的一端未被金属套筒屏蔽保护的部分进行屏蔽保护，因此能够提高对金属化过孔的屏蔽效果。同时，使第二金属化孔与第一信号线隔开，实现第二金属化孔与第一信号线之间的绝缘。
可选地，第二金属化孔在金属化过孔的中轴线上正投影与金属套筒在金属化过孔的中轴线上的正投影相接或者部分重叠。换句话说，也即是，该第二金属化孔至少贯穿电路板层主体中的第三电路板子层。这样，可以通过第二金属化孔对金属化过孔的靠近第二表面的一端未被金属套筒屏蔽保护的部分进行有效屏蔽，因此能够进一步提高对金属化过孔的屏蔽效果。
可选地，多个金属化孔包括第三金属化孔，该第三金属化孔在第一表面的正投影与第一信号线在第一表面的占用区域不重叠，第三金属化孔在第二表面的正投影与第二信号线在第二表面的占用区域至少部分重叠，第三金属化孔为一端贯穿第一表面，另一端未贯穿第二表面的盲孔。这样，可以通过第三金属化孔对金属化过孔的靠近第一表面的一端未被金属套筒屏蔽保护的部分进行屏蔽保护，因此能够提高对金属化过孔的屏蔽效果。同时，使第三金属化孔与第二信号线隔开，实现第三金属化孔与第二信号线之间的绝缘。
可选地，第三金属化孔在金属化过孔的中轴线上正投影与金属套筒在金属化过孔的中轴线上的正投影相接或者部分重叠。换句话说，也即是，第三金属化孔至少贯穿电路板层主体中的第一电路板子层。这样，可以通过第三金属化孔对金属化过孔的靠近第一表面的一端未被金属套筒屏蔽保护的部分进行有效屏蔽，因此能够进一步提高对金属化过孔的屏蔽效果。
可选地，多个金属化孔包括第四金属化孔，该第四金属化孔在第一表面的正投影与第一信号线在第一表面的占用区域至少部分重叠，第四金属化孔在第二表面的正投影与第二信号线在第二表面的占用区域至少部分重叠，第四金属化孔为两端未贯穿第一表面和第二表面的埋孔。这样，使第四金属化孔与第一信号线、第二信号线隔开，实现第四金属化孔与第一信号线、第二信号线之间的绝缘。
可选地，金属套筒的内径为金属化过孔的外径的2.4～4倍。这样，金属套筒与金属化过孔之间的间距适中，能够同时兼顾金属化过孔的电磁能量损失和电路板的加工难度。
可选地，第一信号线和第二信号线均为传输最高频率在1GHz以上的高频信号的信号线。
可选地，金属化过孔的位于第一表面的一端与第一信号线之间无孔盘连接或者通过圆形孔盘、缩紧孔盘或者泪滴孔盘连接。
可选地，金属化过孔的位于第二表面的一端与第二信号线之间无孔盘连接或者通过圆形孔盘、缩紧孔盘或者泪滴孔盘连接。
第二方面，本申请一些实施例提供一种电子设备，该电子设备包括处理器、如上任一技术方案所述的电路板和天线，该电路板为实现天线信号收发功能的电路板，处理器和天线中的一个与电路板的第一信号线耦合，处理器和天线中的另一个与电路板的第二信号线耦合。
由于本申请实施例提供的电子设备包括如上任一技术方案所述的电路板，且该电路板能够实现天线信号收发功能，因此能够减小天线信号在收发过程中的能量损失，提高信号发射和接收效率。
第三方面，本申请一些实施例提供一种电路板的加工方法，该电路板的加工方法包括：
制作带有金属化过孔和金属套筒的电路板层主体，该电路板层主体具有第一表面和第二表面，电路板层主体的内部设有参考地，金属化过孔贯穿电路板层主体，金属套筒设置于电路板层主体内并套设于金属化过孔的外围一周，金属套筒与金属化过孔绝缘，且金属套筒与电路板层主体内的参考地电连接；
在电路板层主体的第一表面设置第一信号线，并使第一信号线与金属化过孔的位于电路板层主体的第一表面的一端电连接，第一信号线与金属套筒绝缘；
在电路板层主体的第二表面设置第二信号线，并使第二信号线与金属化过孔的位于电路板层主体的第二表面的一端电连接，第二信号线与金属套筒绝缘。
由于本申请实施例提供的电路板的加工方法包括制作带有金属化过孔和金属套筒的电路板层主体，且金属套筒套设于金属化过孔的外围一周，金属套筒与电路板层主体内的参考地电连接，因此金属套筒与电路板层主体内的参考地等电位，该金属套筒对金属化过孔起到屏蔽作用。这样，第一方面，能够阻止金属化过孔产生的电磁波辐射到位于金属套筒外部的电路板层主体中去，使电磁能量集中在金属套筒内并沿着金属化过孔向第二信号线传递，从而能够减小电磁能量损失，降低金属化过孔的插入损耗。第二方面，能够增大第一信号线与金属化过孔之间、以及金属化过孔与第二信号线之间的阻抗连续性，由此减小信号在由第一信号线传递至金属化过孔时，以及由金属化过孔传递至第二信号线时的反射，降低回波损耗。第三方面，能够有效避免金属化过孔与金属套筒外部的其他金属化过孔或者其他信号线之间产生串扰。
可选地，电路板层主体包括第一电路板子层、第二电路板子层和第三电路板子层，第二电路板子层内设有参考地；制作带有金属化过孔和金属套筒的电路板层主体包括：在第二电路板子层上设置金属套筒，该金属套筒贯穿第二电路板子层，金属套筒与第 二电路板子层内的参考地电连接，并在金属套筒内设置绝缘材料，以形成带有金属套筒的第二电路板子层；将第一电路板子层、该带有金属套筒的第二电路板子层和第三电路板子层层叠并固定在一起，并使第一电路板子层和第三电路板子层分别位于带有金属套筒的第二电路板子层的相对两侧，以形成带有金属套筒的电路板层主体；在带有金属套筒的电路板层主体上设置金属化过孔，并使金属化过孔穿过金属套筒内的绝缘材料并贯穿电路板层主体。此方法简单，容易实现，且能够保证金属化过孔和金属套筒在电路板主体内的相对位置精度。同时，由于金属化过孔设置于带有金属套筒的电路板层主体上，且该金属化过孔贯穿该电路板层主体，因此金属化过孔可以通过一次性钻孔电镀成型，而不存在孔柱的上下拼接和内层的孔盘结构。
可选地，在第二电路板子层上设置金属套筒，并在金属套筒内设置绝缘材料包括：在第二电路板子层上设置通孔；在该通孔的内表面设置金属层，通孔的内表面一周的金属层构成金属套筒；在金属套筒的中空区域填充绝缘材料。此方法简单，容易实现，且能够保证金属套筒在电路板层主体内的位置精度。
可选地，在第二电路板子层上设置金属套筒，并在金属套筒内设置绝缘材料包括：在第二电路板子层上设置通孔；在通孔内安装侧壁一周具有金属层的绝缘柱体，并使绝缘柱体沿自身轴向上的两端端面分别与第二电路板子层的两个表面平齐，绝缘柱体的侧壁一周的金属层构成金属套筒，绝缘柱体为设置于金属套筒内的绝缘材料。此方法简单，容易实现，操作效率较高。
可选地，制作带有金属化过孔和金属套筒的电路板层主体包括：在电路板层主体上设置通孔；在该通孔内安装同轴柱体，并使该同轴柱体沿自身轴向上的两端端面分别与电路板层主体的第一表面和第二表面平齐，该同轴柱体包括内导体、绝缘层和外导体，绝缘层围绕内导体的侧壁一周设置，外导体围绕绝缘层的侧壁一周设置，内导体构成金属化过孔，外导体构成金属套筒；在电路板层主体的第一表面对应外导体的端部的位置设置第一沟槽，以去除外导体的位于第一表面的部分材料；在电路板层主体的第二表面对应外导体的端部的位置设置第二沟槽，以去除外导体的位于第二表面的部分材料；在第一沟槽和第二沟槽内填充绝缘材料，以形成带有金属化过孔和金属套筒的电路板层主体。此方法简单，容易实现。
可选地，在制作带有金属化过孔和金属套筒的电路板层主体之后，还包括：在电路板层主体上设置多个金属化孔，并使该多个金属化孔围绕金属套筒的外围一周排列，且多个金属化孔与第一信号线、第二信号线之间绝缘，多个金属化孔与电路板层主体内的参考地电连接。这样，多个金属化孔与电路板层主体内的参考地等电位，可以通过多个金属化孔对金属化过孔进行二次屏蔽，避免金属套筒在制造过程中因出现破裂而造成电磁能量泄露。
附图说明
图1为本申请一些实施例提供的电路板的结构示意图；
图2为本申请另一些实施例提供的电路板的结构示意图；
图3为图1或图2所示电路板中电路板层的俯视图；
图4为图3所示电路板层沿A-A的第一种截面结构示意图；
图5为图3所示电路板层沿A-A的第二种截面结构示意图；
图6为图3所示电路板层沿A-A的第三种截面结构示意图；
图7为图6所示电路板层在去除电路板层主体后的立体图；
图8为图3所示电路板在去除电路板层主体后的立体图；
图9为本申请一些实施例提供的电路板中第一信号线、金属化过孔和第二信号线之间的连接结构示意图之一；
图10为本申请一些实施例提供的电路板中第一信号线、金属化过孔和第二信号线之间的连接结构示意图之二；
图11为本申请一些实施例提供的电路板中第一信号线、金属化过孔和第二信号线之间的连接结构示意图之三；
图12为本申请一些实施例提供的电路板的加工方法的流程图；
图13为图12所示电路板的加工方法中制作电路板层的流程图；
图14为图13所示的制作电路板层的步骤中获得的带有金属化过孔和金属套筒的电路板层主体的结构示意图；
图15为图13所示制作电路板层的步骤中制作带有金属化过孔和金属套筒的电路板层主体的流程图；
图16为图15所示制作带有金属化过孔和金属套筒的电路板层主体中电路板层主体的第二电路板子层的结构示意图；
图17为在图16所示第二电路板子层上设置金属套筒后形成的带有金属套筒的第二电路板子层的结构示意图；
图18为图15所示制作带有金属化过孔和金属套筒的电路板层主体的步骤中在第二电路板子层上设置金属套筒并在金属套筒内填充绝缘材料的流程图；
图19为将第一电路板子层、图17所示的带有金属套筒的第二电路板子层、第三电路板子层层叠并固定在一起后获得的带有金属套筒的电路板层主体的结构示意图；
图20为在图19所示带有金属套筒的电路板层主体上设置金属化过孔之后获得的带有金属套筒和金属化过孔的电路板层主体的结构示意图；
图21为图13所示的制作电路板层的过程中获得的带有金属化过孔、金属套筒和第一信号线的电路板层主体的结构示意图；
图22为图13所示的制作电路板层的过程中获得的带有金属化过孔、金属套筒、第一信号线和第二信号线的电路板层主体的结构示意图；
图23为本申请一些实施例提供的电子设备的结构框图。
附图标记：
1-电路板层；11-电路板层主体；100-第一表面；200-第二表面；111-第一电路板子层；112-第二电路板子层；113-第三电路板子层；300-第三表面；400-第四表面；12-第一信号线；13-第二信号线；14-金属化过孔；15-金属套筒；151-第一缺口；152-第二缺口；16-绝缘材料；17-金属化孔；17a-金属化孔；17b-金属化孔；17c-金属化孔；500-第一孔盘；2-电路板层；3-电路板层；10-处理器；20-电路板；30-天线。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。
在本申请实施例中，术语“第一”、“第二”、“第三”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”、“第三”的特征可以明示或者隐含地包括一个或者更多个该特征。
在本申请的描述中，“和/或”，仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况。另外，本文中字符“/”，一般表示前后关联对象是一种“或”的关系。
在本申请的描述中，“耦合”一词用于表示电性连接，包括通过导线或连接端直接相连或通过其他器件间接相连。因此“耦合”应被视为是一种广义上的电子通信连接。
电路板是电子元件电气连接的载体，本申请涉及的电路板用于传输最高频率在1GHz以上的高频信号。应当知道的是，最高频率在1GHz～30GHz范围内的微波、毫米波(最高频率在30GHz～300GHz范围内)、太赫兹波(最高频率在100GHz-10THz范围内)以及最高频率在1GHz以上高动态数字信号均属于最高频率在1GHz以上的高频信号。
用于传输高频信号的电路板可应用的设备包括但不限于无线通讯设备、固网通讯设备、IT高能计算机和互连设备、射频终端、无人机或车载产品。
用于传输高频信号的电路板包括但不限于印制电路板(printed circuit board，PCB)、封装载板等。封装载板可以是系统级封装(system in a package，SIP)载板、多芯片模块(multichip module，MCM)封装载板或球状引脚栅格阵列封装(ball grid array package，BGA)载板等。
电路板由依次交替设置的金属层和绝缘介质层构成，其中，金属层包括信号线和/或金属参考面。在电路板内，不同金属层中的信号线之间采用金属化过孔实现连接。高频信号在经过金属化过孔时，一方面，容易向金属化过孔周围的电路板内辐射电磁波，从而将大量的电磁能量扩散到了电路板内，导致部分能量不能沿着预定的传递方向继续传递，因此金属化过孔的插入损耗较大。另一方面，金属化过孔与两个不同金属层中的信号线之间的阻抗匹配度较差，导致在金属化过孔与两个不同金属层中的信号线之间的连接处，会产生信号的大量反射，因此回波损耗较大。这两方面的因素导致了电路板的性能大幅下降，信号传输失真较大。
为了解决上述问题，本申请提供一种电子设备，该电子设备包括但不限于无线通讯设备、诸如射频集成电路(radio frequency integrated circuit，RFIC)这样的集成电路或芯片产品、毫米波天线模组、固网通讯设备、IT高能计算机和互连设备、射频终端、无人机或车载产品。
图23为本申请一些实施例提供的电子设备的结构框图。如图23所示，该电子设备包括处理器10、电路板20和天线30。处理器10用于生成发送信号或处理接收信号，该处理器10可以是基带处理器、数字信号处理器、微处理器或中央处理单元等。该电路板20为用于实现天线信号收发功能的电路板，也叫收发机、射频收发机、射频电路或者信号收发电路。该电路板20用于从处理器10接收发送信号、调制处理该发送信号并将该发送信号传输至天线30，同时该电路板20还用于解调处理并传输天线30接收的接收信号至处理器10。
本申请还提供一种电路板，该电路板用于传输最高频率在1GHz以上的高频信号， 且该电路板包括但不限于印制电路板(printed circuit board，PCB)、封装载板。可选地，该电路板应用于上述电子设备中。该电路板通过在金属化过孔外套设接地的金属套筒，以将高频信号的电磁能量集中在金属化过孔内进行传输，使得能量能够沿着预定的传递方向继续传递，由此可以降低金属化过孔的插入损耗。此外，通过在金属化过孔外套设接地的金属套筒，可以增大金属化过孔与信号线之间的阻抗连续性，减小信号在金属化过孔与信号线之间连接处的反射，降低回波损耗。
根据上述设计思路，图1为本申请一些实施例提供的电路板的结构示意图。如图1所示，电路板包括电路板层1。可以知道的是，电路板可以仅包括该电路板层1，也可以除了包括该电路板层1之外，还包括其他的电路板层，在此不做具体限定。
图1给出了电路板仅包括电路板层1的示例，并不能认为对本申请构成限定。
图2为本申请另一些实施例提供的电路板的结构示意图。如图2所示，电路板除了包括电路板层1之外，还包括电路板层2和电路板层3，电路板层1、电路板层2、电路板层3层叠并固定在一起，电路板层2、电路板层3分别位于电路板层1的相对两侧。
图3为图1或图2所示电路板中电路板层的俯视图，图4为图3所示电路板层沿A-A的第一种截面结构示意图。如图3和图4所示，电路板层1包括电路板层主体11、第一信号线12、第二信号线13、金属化过孔14和金属套筒15。
电路板层主体11具有相对的第一表面100和第二表面200，电路板层主体11的内部设有参考地。
第一信号线12设置于第一表面100，第二信号线13设置于第二表面200，可选地，第一信号线12和第二信号线13用于传输最高频率在1GHz以上的高频信号，具体地，第一信号线12和第二信号线13可以是微带线。当电路板用作图23所示的电子设备中的电路板20时，由于第一信号线12和第二信号线13传输高频信号，因此第一信号线12和第二信号线13处于电路板20的连接天线30的部分电路中。具体地，处理器10与电路板20耦合，电路板20的第一信号线12或第二信号线13与天线30耦合。
金属化过孔14设置于电路板层主体11上并贯穿该电路板层主体11。金属化过孔14的位于第一表面100的一端与第一信号线12电连接，金属化过孔14的位于第二表面200的一端与第二信号线13电连接。
这样，第一信号线12与第二信号线13之间通过金属化过孔14电连接，高频信号可以由第一信号线12经过金属化过孔14向第二信号线13传输，也可以由第二信号线13经过金属化过孔14向第一信号线12传输。
金属套筒15可以由铜或者铜的合金制作，也可以由其他金属导电材料(比如铁、铝以及铁或铝的合金)制作，在此不做具体限定。金属套筒15的横截面轮廓形状不限于圆形，也可以为椭圆形、三角形或者多边形，且金属套筒15沿轴向上的各个部分的横截面轮廓形状可以一致，也可以不一致，在此不做具体限定。金属套筒15设置于电路板层主体11内并套设于金属化过孔14的外围一周。金属套筒15可以为形成于电路板层主体11内的环形金属层，也可以为嵌设在电路板主体11内的一个金属筒状结构件，在此不做具体限定。当金属套筒15为形成于电路板层主体11内的环形金属层时，具体地，金属套筒15可以由电路板层主体11内的多个电路板子层内形成的环形金属 层单元沿电路板层主体11的厚度方向拼接形成，也可以为一个环形金属层整体，在此不做具体限定。
金属套筒15与金属化过孔14、第一信号线12、第二信号线13之间均绝缘，金属套筒15与电路板层主体11内的参考地电连接。
这样，金属套筒15与电路板层主体11内的参考地等电位，该金属套筒15构成金属化过孔14的参考面，能够对金属化过孔14起到屏蔽作用。
这样，在高频信号由第一信号线12和第二信号线13中的一个经过金属化过孔14传输到第一信号线12和第二信号线13中的另一个的过程中，金属套筒15能够阻止高频信号在经过金属化过孔14时产生的电磁波辐射到金属套筒15外部的电路板层主体11内，使电磁能量能够集中在金属套筒15内并沿着金属化过孔14向第一信号线12或第二信号线13继续传递，从而能够减小电磁能量损失，降低金属化过孔14的插入损耗。
同时，金属套筒15能够提高第一信号线12与金属化过孔14之间、以及金属化过孔14与第二信号线13之间的阻抗连续性，由此能够减小高频信号在由第一信号线12传递至金属化过孔14时，或者在由第二信号线13传递至金属化过孔14时的反射，降低回波损耗。
而且，金属套筒15能够有效避免金属化过孔14与金属套筒15外部的其他金属化过孔之间产生串扰。
为了实现金属套筒15与金属化过孔14之间的绝缘，在一些实施例中，如图4所示，金属套筒15的内壁一周与金属化过孔14的外壁之间通过绝缘材料16隔开。
可选地，金属套筒15的内壁一周与金属化过孔14的外壁之间的绝缘材料16为介电常数低于2的材料。这样，绝缘材料16的绝缘性能较优，在金属套筒15的内壁一周与金属化过孔14的外壁之间的间距较小时，仍可以通过填充于该较小间隙内的较少量的绝缘材料16实现金属套筒15与金属化过孔14之间的绝缘。
为了实现金属套筒15与第一信号线12之间、以及金属套筒15与第二信号线13之间的绝缘，具体地，可以通过以下两种绝缘方式实现：
第一种绝缘方式：如图4所示，电路板层主体11包括层叠并固定在一起的第一电路板子层111、第二电路板子层112和第三电路板子层113。
第二电路板子层112位于第一电路板子层111与第三电路板子层113之间，且第二电路板子层112内设有参考地。
具体地，第二电路板子层112由金属层a和绝缘介质层b依次交替并堆叠而成，示例的，如图4所示，第二电路板子层112由8个金属层a和7个绝缘介质层b依次交替设置。金属层a中的金属参考面为参考地。
第一电路板子层111的远离第二电路板子层112的表面为第一表面100，第一电路板子层11的至少形成第一表面100的部分为绝缘介质层。这样，通过该绝缘介质层能够将第一信号线12与第一电路板子层111内的金属层或者第二电路板子层112内的金属层隔开，避免第一信号线12与第一电路板子层111内的金属层或者第二电路板子层112内的金属层之间短路。
第一电路板子层111可以仅由一层绝缘介质层构成，也可以由绝缘介质层和金属 层依次交替并堆叠而成，在此不作具体限定，只要第一电路板子层11的形成第一表面100的部分为绝缘介质层即可。
示例的，如图4所示，第一电路板子层111由两层绝缘介质层以及设置于该两层绝缘介质层之间的金属层构成。
又示例的，图5为图3所示电路板层沿A-A的第二种截面结构示意图，如图5所示，第一电路板子层111仅由一层绝缘介质层构成。
需要说明的是，当第一电路板子层111由绝缘介质层和金属层依次交替并堆叠而成时，第一电路板子层111内的金属层与金属化过孔14之间绝缘。这样，能够避免第一电路板子层111内的金属层与金属化过孔14之间短路。
第三电路板子层113的远离第二电路板子层112的表面为第二表面200，第三电路板子层113的至少形成第二表面200的部分为绝缘介质层。这样，能够通过该绝缘介质层将第二信号线13与第三电路板子层113内的金属层或者第二电路板子层112内的金属层隔开，避免第二信号线13与第三电路板子层113内的金属层或者第二电路板子层112内的金属层之间短路。
第三电路板子层113可以仅由一层绝缘介质层构成，也可以由绝缘介质层和金属层依次交替并堆叠而成，在此不作具体限定，只要第三电路板子层113的形成第二表面200的部分为绝缘介质层即可。
示例的，如图4或图5所示，第三电路板子层113仅由一层绝缘介质层构成。
需要说明的是，当第三电路板子层113由绝缘介质层和金属层依次交替并堆叠而成时，第三电路板子层113内的金属层与金属化过孔14之间绝缘。这样，能够避免第三电路板子层113内的金属层与金属化过孔14之间短路。
金属套筒15设置于第二电路板子层112上并贯穿该第二电路板子层112，可选地，金属套筒15仅设置于第二电路板子层112上，未设置于第一电路板子层111和第三电路板子层113上，且金属套筒15与第二电路板子层112内的参考地电连接。
这样，金属套筒15沿自身轴向上的两端未贯穿第一表面100和第二表面200，金属套筒15与第一信号线12之间通过第一电路板子层111绝缘隔离，金属套筒15与第二信号线13之间通过第三电路板子层113绝缘隔离。
而且，在电路板层主体11内制作金属套筒15的过程可以为：首先，在第二电路板子层112上制作金属套筒15，并使金属套筒15贯穿第二电路板子层112，以形成带金属套筒15的第二电路板子层112；然后，将第一电路板子层111、带金属套筒15的第二电路板子层112、第三电路板子层113层叠并固定在一起，并使第一电路板子层111和第三电路板子层113分别位于该带金属套筒15的第二电路板子层112的相对两侧。这样，就可以很容易地将金属套筒15制作于电路板层主体11内。因此，本实施例所示的电路板层主体11与金属套筒15之间的相对位置关系便于金属套筒15在电路板层主体11上的制作。
在一些实施例中，如图4或图5所示，第二电路板子层112的朝向第一电路板子层111的表面为第三表面300，第二电路板子层112的朝向第三电路板子层113的表面为第四表面400。第二电路板子层112的形成第三表面300和第四表面400的部分均为金属层。金属套筒15沿自身轴向上的一端端部与第三表面300所处的金属层中的 金属参考面电连接，金属套筒15沿自身轴向上的另一端端部与第四表面400所处的金属层中的金属参考面电连接。这样，金属套筒15的回流性能较优，对金属化过孔14的屏蔽效果较好。
第二种绝缘方式：图6为图3所示电路板层沿A-A的第三种截面结构示意图，图7为图6所示电路板层在去除电路板层主体后的立体图。如图6和图7所示，金属套筒15贯穿电路板层主体11。
金属套筒15的对应第一信号线12的位置设有第一缺口151，第一缺口151处的金属套筒边沿与第一信号线12之间通过绝缘材料隔开。
金属套筒15的对应第二信号线13的位置设有第二缺口152，第二缺口152处的金属套筒边沿与第二信号线13之间通过绝缘材料隔开。
这样，金属套筒15与第一信号线12之间通过第一缺口151内的绝缘材料隔开，金属套筒15与第二信号线13之间通过第二缺口152内的绝缘材料隔开。由于金属套筒15贯穿电路板层主体11，因此金属套筒15对金属化过孔14的屏蔽路径较长，屏蔽效果较优。
为了进一步增大对金属化过孔14的屏蔽效果，在一些实施例中，如图3所示，电路板层1还包括多个金属化孔17。
多个金属化孔17设置于电路板层主体11上并围绕金属套筒15的外围一周排列。多个金属化孔17与第一信号线12、第二信号线13之间均绝缘，多个金属化孔17与参考地电连接。可以知道的是，参考地为电路板层主体11内金属层中的金属参考面，多个金属化孔17与参考地电连接，也即是，多个金属化孔17至少贯穿电路板层主体11内的一层金属层，并与该金属层中的金属参考面电连接。
这样，多个金属化孔17与电路板层主体11内金属层中的金属参考面等电位，可以通过多个金属化孔17对金属化过孔14进行二次屏蔽，避免金属套筒15在制造过程中因出现破裂而造成电磁能量泄露。
金属化孔17可以为贯穿电路板层主体11的通孔，也可以为一端贯穿第一表面100和第二表面200中的一个、另一端未贯穿第一表面100和第二表面200中的另一个的盲孔，还可以为两端未贯穿第一表面100和第二表面200的埋孔，在此不作具体限定。
在一些实施例中，图8为图3所示电路板在去除电路板层主体后的立体图。如图8所示，多个金属化孔17包括第一金属化孔17a，该第一金属化孔17a在第一表面100的正投影与第一信号线12在第一表面100的占用区域不重叠，且该第一金属化孔17a在第二表面200的正投影与第二信号线13在第二表面200的占用区域不重叠，该第一金属化孔17a为贯穿电路板层主体11的通孔。这样，第一金属化孔17a可以对金属化过孔14沿自身长度方向上的各个位置进行屏蔽，屏蔽效果较优。
在一些实施例中，如图8所示，多个金属化孔17包括第二金属化孔17b，该第二金属化孔17b在第一表面100的正投影与第一信号线12在第一表面100的占用区域至少部分重叠，且该第二金属化孔17b在第二表面200的正投影与第二信号线13在第二表面200的占用区域不重叠，第二金属化孔17b为一端贯穿第二表面200，另一端未贯穿第一表面100的盲孔。这样，可以通过第二金属化孔17b对金属化过孔14的靠近第二表面200的一端未被金属套筒15屏蔽保护的部分进行屏蔽保护，因此能够提高对 金属化过孔14的屏蔽效果。同时，使第二金属化孔17b与第一信号线12隔开，实现第二金属化孔17b与第一信号线12之间的绝缘。
在上述实施例中，对第二金属化孔17b的深度不做具体限定。
在一些实施例中，如图4所示，第二金属化孔17b在金属化过孔14的中轴线O上的正投影L1与金属套筒15在金属化过孔14的中轴线O上的正投影L2相接或者部分重叠。换句话说，也即是，第二金属化孔17b至少贯穿电路板层主体11中的第三电路板子层113。这样，可以通过第二金属化孔17b对金属化过孔14的靠近第二表面200的一端未被金属套筒15屏蔽保护的部分进行有效屏蔽，因此能够提高对金属化过孔14的屏蔽效果。
在一些实施例中，如图8所示，多个金属化孔17包括第三金属化孔17c，该第三金属化孔17c在第一表面100的正投影与第一信号线12在第一表面100的占用区域不重叠，且该第三金属化孔17c在第二表面200的正投影与第二信号线13在第二表面200的占用区域至少部分重叠，第三金属化孔17c为一端贯穿第一表面100，另一端未贯穿第二表面200的盲孔。这样，可以通过第三金属化孔17c对金属化过孔14的靠近第一表面100的一端未被金属套筒15屏蔽保护的部分进行屏蔽保护，因此能够提高对金属化过孔14的屏蔽效果。同时，使第三金属化孔17c与第二信号线13隔开，实现第三金属化孔17c与第二信号线13之间的绝缘。
在上述实施例中，对第三金属化孔17c的深度不做具体限定。
在一些实施例中，如图4所示，第三金属化孔17c在金属化过孔14的中轴线O上的正投影L3与金属套筒15在金属化过孔14的中轴线O上的正投影L2相接或者部分重叠。换句话说，也即是，第三金属化孔17c至少贯穿电路板层主体11中的第一电路板子层111。这样，可以通过第三金属化孔17c对金属化过孔14的靠近第一表面100的一端未被金属套筒15屏蔽保护的部分进行有效屏蔽，因此能够提高对金属化过孔14的屏蔽效果。
在一些实施例中，多个金属化孔包括第四金属化孔(图中未示出)，该第四金属化孔在第一表面100的正投影与第一信号线12在第一表面100的占用区域至少部分重叠，且该第四金属化孔在第二表面200的正投影与第二信号线13在第二表面200的占用区域至少部分重叠，第四金属化孔为两端未贯穿第一表面100和第二表面200的埋孔。这样，使第四金属化孔与第一信号线、第二信号线隔开，实现第四金属化孔与第一信号线、第二信号线之间的绝缘。
在金属化过孔14的外径不变的前提下，为了将高频信号的电磁能量集中在金属化过孔14内，金属套筒15的内径应设计得越小越好，而当金属套筒15的内径设计得越小，在电路板层主体11上制作金属化过孔14和金属套筒15时，金属套筒15与金属化过孔14之间的相对位置精度难以得到保证，容易导致金属套筒15与金属化过孔14之间短路，因此电路板的加工难度较大。为了同时兼顾金属化过孔14的电磁能量损失和金属套筒15的加工难度，在一些实施例中，如图4所示，金属套筒15的内径d2为金属化过孔14的外径d1的2.4～4倍。这样，金属套筒15与金属化过孔14之间的间距适中，能够同时兼顾金属化过孔14的电磁能量损失和电路板的加工难度。
金属化过孔14的位于第一表面100的一端与第一信号线12之间可以直接电连接， 也可以通过第一孔盘500间接电连接，在此不做具体限定。
示例的，如图4所示，金属化过孔14的位于第一表面100的一端与第一信号线12之间直接电连接，也即是无孔盘连接。
又示例的，图9为本申请一些实施例提供的电路板中第一信号线、金属化过孔和第二信号线之间的连接结构示意图之一。图10为本申请一些实施例提供的电路板中第一信号线、金属化过孔和第二信号线之间的连接结构示意图之二。图11为本申请一些实施例提供的电路板中第一信号线、金属化过孔和第二信号线之间的连接结构示意图之三。如图9、图10或图11所示，金属化过孔14的位于第一表面100的一端与第一信号线12之间通过第一孔盘500间接电连接。其中，第一孔盘500可以为图9所示圆形孔盘，也可以为图10所示缩紧孔盘，还可以为图11所示泪滴孔盘，在此不做具体限定。
金属化过孔14的位于第二表面200的一端与第二信号线13之间可以直接电连接，也可以通过第二孔盘间接电连接，在此不做具体限定。
示例的，如图4所示，金属化过孔14的位于第二表面200的一端与第二信号线13之间直接电连接，也即是无孔盘连接。
又示例的，金属化过孔14的位于第二表面200的一端与第二信号线13之间通过第二孔盘间接电连接。其中，第二孔盘可以为圆形孔盘，也可以为缩紧孔盘，还可以为泪滴孔盘，在此不做具体限定。
本申请还提供了一种电路板的加工方法，该加工方法用于加工如上任一实施例所述的电路板。
图12为本申请一些实施例提供的电路板的加工方法的流程图。如图12所示，该电路板的加工方法包括：S100：制作电路板层1。
步骤S100可以为制作图4所示电路板层1的方法，也可以为制作图5所示电路板层1的方法，还可以为制作图6所示电路板层1的方法，还可以为制作上述实施例中其他结构形式的电路板层1的方法，在此不做具体限定。以下针对步骤S100中的每个子步骤所举出的示例均是以制作图4所示电路板层1为例进行介绍，并不能认为是对本申请构成的限定。
可选地，图13为图12所示电路板的加工方法中制作电路板层1的流程图，如图13所示，步骤S100包括：
S101：制作带有金属化过孔14和金属套筒15的电路板层主体11。其中，电路板层主体11具有相对的第一表面100和第二表面200。电路板层主体11的内部设有参考地。金属化过孔14贯穿电路板层主体11。金属套筒15设置于电路板层主体11内并套设于金属化过孔14的外围一周。金属套筒15与金属化过孔14绝缘，可选地，金属套筒15与金属化过孔14之间通过绝缘材料16隔开。金属套筒15与电路板层主体11内的参考地电连接。示例的，通过步骤S101获得的带有金属化过孔14和金属套筒15的电路板层主体11的结构可以为图14所示结构。
S102：在电路板层主体11的第一表面100设置第一信号线12，并使第一信号线12与金属化过孔14的位于电路板层主体11的第一表面100的一端电连接，该第一信号线12与金属套筒15绝缘。示例的，通过步骤S102获得的带有金属化过孔14、金 属套筒15和第一信号线12的电路板层主体11的结构可以为图21所示结构。
S103：在电路板层主体11的第二表面200设置第二信号线13，并使第二信号线13与金属化过孔14的位于电路板层主体11的第二表面200的一端电连接，该第二信号线13与金属套筒15绝缘。示例的，通过步骤S103获得的带有金属化过孔14、金属套筒15、第一信号线12和第二信号线13的电路板层主体11的结构可以为图22所示结构。
在本申请实施例提供的电路板的加工方法中，由于在电路板主体11上设置了金属套筒15，金属套筒15设置于电路板层主体11内并套设于金属化过孔14的外围一周，金属套筒15与电路板层主体11内的参考地电连接，因此金属套筒15与电路板层主体11内的参考地等电位，该金属套筒15构成金属化过孔14的参考面，能够对金属化过孔14起到屏蔽作用。
这样，在高频信号由第一信号线12和第二信号线13中的一个经过金属化过孔14传输到第一信号线12和第二信号线13中的另一个的过程中，金属套筒15能够阻止高频信号在经过金属化过孔14时产生的电磁波辐射到金属套筒15外部的电路板层主体11内，使电磁能量能够集中在金属套筒15内并沿着金属化过孔14向第一信号线12或第二信号线13继续传递，从而能够减小电磁能量损失，降低金属化过孔14的插入损耗。
同时，金属套筒15能够提高第一信号线12与金属化过孔14之间、以及金属化过孔14与第二信号线13之间的阻抗连续性，由此能够减小高频信号在由第一信号线12传递至金属化过孔14时，或者在由第二信号线13传递至金属化过孔14时的反射，降低回波损耗。
而且，金属套筒15能够有效避免金属化过孔14与金属套筒15外部的其他金属化过孔之间产生串扰。
上述步骤S101可以有多种可选的实现方式，比如可以为以下两种可选的实现方式：
第一种可选的实现方式：电路板层主体包括第一电路板子层111、第二电路板子层112和第三电路板子层113，第二电路板子层112内设有参考地。图15为图13所示制作电路板层的步骤中制作带有金属化过孔和金属套筒的电路板层主体的流程图。如图15所示，步骤S101包括：
S1011：在第二电路板子层112上设置金属套筒15，该金属套筒15贯穿第二电路板子层112，金属套筒15与第二电路板子层112内的参考地电连接，并在金属套筒12内设置绝缘材料，以形成带有金属套筒15的第二电路板子层112。
可选地，第二电路板子层112由金属层a和绝缘介质层b依次交替并堆叠而成，金属层a包括信号线和/或金属参考面，第二电路板子层112内的参考地为第二电路板子层112内的金属层a中的金属参考面。示例的，第二电路板子层112的结构可以为图16所示。
示例的，图17为在图16所示第二电路板子层112上设置金属套筒15后形成的带有金属套筒15的第二电路板子层112的结构示意图，如图17所示，金属套筒15贯穿第二电路板子层112，且金属套筒15内填充有绝缘材料16。
具体地，步骤S1011可以有多种实施例，在一些实施例中，步骤S1011包括：在第二电路板子层112上设置通孔；在该通孔内安装侧壁一周具有金属层的绝缘柱体，并使该绝缘柱体沿自身轴向上的两端端面分别与第二电路板子层112的两个表面平齐，该绝缘柱体的侧壁一周的金属层构成金属套筒15，绝缘柱体为金属套筒内填充的绝缘材料16。由此，形成带有金属套筒15的第二电路板子层112，此方法简单，容易实现，操作效率较高。
在另一些实施例中，图18为图15所示制作带有金属化过孔和金属套筒的电路板层主体的步骤中在第二电路板子层上设置金属套筒并在金属套筒内填充绝缘材料的流程图，如图18所示，步骤S1011包括：S10111：在第二电路板子层112上设置通孔；S10112：在该通孔的内表面设置金属层，该通孔的内表面一周的金属层构成金属套筒15；S10123：在金属套筒15的中空区域填充绝缘材料16。由此，形成带有金属套筒15的第二电路板子层112，此方法简单，容易实现，且能够保证金属套筒15在电路板层主体11内的位置精度。
如图15所示，步骤S101还包括：S1012：将第一电路板子层111、带有金属套筒15的第二电路板子层112和第三电路板子层113层叠并固定在一起，并使第一电路板子层111和第三电路板子层113分别位于带有金属套筒15的第二电路板子层112的相对两侧，以形成带有金属套筒15的电路板层主体11。
示例的，将第一电路板子层、图17所示带有金属套筒的第二电路板子层、第三电路板子层层叠并固定在一起后，可以获得图19所示带有金属套筒的电路板层主体的结构示意图。
在带有金属套筒15的电路板层主体11中，第一电路板子层111的远离第二电路板子层112的表面形成电路板层主体11的第一表面100，第一电路板子层11的至少形成第一表面100的部分为绝缘介质层。这样，通过该绝缘介质层能够将第一信号线12与第一电路板子层111内的金属层以及第二电路板子层112内的金属层隔开，避免第一信号线12与第一电路板子层111内的金属层以及第二电路板子层112内的金属层之间短路。同时，通过该绝缘介质层能够将第一信号线12与金属套筒15隔开，实现第一信号线12与金属套筒15之间的绝缘。
在带有金属套筒15的电路板层主体11中，第三电路板子层113的远离第二电路板子层112的表面形成电路板层主体11的第二表面200，第三电路板子层113的至少形成第二表面200的部分为绝缘介质层。这样，通过该绝缘介质层能够将第二信号线13与第三电路板子层113内的金属层以及第二电路板子层112内的金属层隔开，避免第二信号线13与第三电路板子层113内的金属层以及第二电路板子层112内的金属层之间短路。同时，通过该绝缘介质层能够将第二信号线13与金属套筒15隔开，实现第二信号线13与金属套筒15之间的绝缘。
具体地，第一电路板子层111、带有金属套筒15的第二电路板子层112和第三电路板子层113之间可以通过胶粘、层压等工艺固定在一起，在此不做具体限定。
如图15所示，步骤S101还包括：S1013：在带有金属套筒15的电路板层主体11上设置金属化过孔14，并使金属化过孔14穿过金属套筒15内的绝缘材料16并贯穿电路板层主体11。示例的，图20为在图19所示带有金属套筒15的电路板层主体11 上设置金属化过孔14之后获得的带有金属套筒15和金属化过孔14的电路板层主体11的结构示意图。
图15所示制作带有金属化过孔14和金属套筒15的电路板层主体11的方法简单，容易实现，且能够保证金属化过孔14和金属套筒15在电路板主体11内的相对位置精度。同时，由于金属化过孔14设置于带有金属套筒15的电路板层主体11上，且该金属化过孔14贯穿该电路板层主体11，因此金属化过孔14可以通过一次性钻孔电镀成型，而不存在孔柱的上下拼接和内层的孔盘结构。
第二种可选的实现方式：步骤S101包括：在电路板层主体11上设置通孔；在该通孔内安装同轴柱体，并使该同轴柱体沿自身轴向上的两端端面分别与电路板层主体11的第一表面100和第二表面200平齐，该同轴柱体包括内导体、绝缘层和外导体，绝缘层围绕内导体的侧壁一周设置，外导体围绕绝缘层的侧壁一周设置，内导体构成金属化过孔，外导体构成金属套筒；在电路板层主体的第一表面对应外导体的端部的位置设置第一沟槽，以去除外导体的位于第一表面的部分材料；在电路板层主体的第二表面对应外导体的端部的位置设置第二沟槽，以去除外导体的位于第二表面的部分材料；在第一沟槽和第二沟槽内填充绝缘材料，以形成带有金属化过孔和金属套筒的电路板层主体。此方法简单，容易实现。
在一些实施例中，在步骤S101之后，还包括：在电路板层主体11上设置多个金属化孔17，并使该多个金属化孔17围绕金属套筒15的外围一周排列，且多个金属化孔17与第一信号线12、第二信号线13之间绝缘，多个金属化孔17与电路板层主体11内的参考地电连接。这样，多个金属化孔17与电路板层主体11内的参考地等电位，可以通过多个金属化孔17对金属化过孔14进行二次屏蔽，避免金属套筒15在制造过程中因出现破裂而造成电磁能量泄露。
在一些实施例中，在步骤S100之后，还包括：将电路板层1与其他电路板层层叠并固定在一起，以形成电路板。
在本说明书的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (17)

  1. 一种电路板，其特征在于，包括电路板层；
    所述电路板层包括：
    电路板层主体，具有相对的第一表面和第二表面，所述电路板层主体的内部设有参考地；
    第一信号线，设置于所述第一表面；
    第二信号线，设置于所述第二表面；
    金属化过孔，设置于所述电路板层主体上并贯穿所述电路板层主体，所述金属化过孔的位于所述第一表面的一端与所述第一信号线电连接，所述金属化过孔的位于所述第二表面的一端与所述第二信号线电连接；
    金属套筒，设置于所述电路板层主体内，并套设于所述金属化过孔的外围一周，所述金属套筒与所述金属化过孔、所述第一信号线、所述第二信号线之间均绝缘，所述金属套筒与所述电路板层主体内的参考地电连接。
  2. 根据权利要求1所述的电路板，其特征在于，所述电路板层主体包括层叠并固定在一起的第一电路板子层、第二电路板子层和第三电路板子层；
    所述第二电路板子层位于所述第一电路板子层与所述第三电路板子层之间，且所述第二电路板子层内设有参考地；
    所述第一电路板子层的远离所述第二电路板子层的表面为所述电路板层主体的第一表面，所述第一电路板子层的至少形成所述第一表面的部分为绝缘介质层；
    所述第三电路板子层的远离所述第二电路板子层的表面为所述电路板层主体的第二表面，所述第三电路板子层的至少形成所述第二表面的部分为绝缘介质层；
    所述金属套筒设置于所述第二电路板子层上并贯穿所述第二电路板子层，且所述金属套筒与所述第二电路板子层内的参考地电连接。
  3. 根据权利要求1或2所述的电路板，其特征在于，所述金属套筒的内壁一周与所述金属化过孔的外壁之间通过绝缘材料隔开。
  4. 根据权利要求2所述的电路板，其特征在于，所述第二电路板子层的朝向所述第一电路板子层的表面为第三表面，所述第二电路板子层的朝向所述第三电路板子层的表面为第四表面；
    所述第二电路板子层由金属层和绝缘介质层依次交替并堆叠而成，且所述第二电路板子层的形成所述第三表面和所述第四表面的部分均为金属层，所述金属层中的金属参考面为所述参考地；
    所述金属套筒沿自身轴向上的一端端部与所述第三表面所处的金属层中的金属参考面电连接，所述金属套筒沿自身轴向上的另一端端部与所述第四表面所处的金属层中的金属参考面电连接。
  5. 根据权利要求1～4中任一项所述的电路板，其特征在于，所述电路板层还包括：
    多个金属化孔，设置于所述电路板层主体上并围绕所述金属套筒的外围一周排列，且所述多个金属化孔与所述第一信号线、所述第二信号线之间均绝缘，所述多个金属化孔与所述参考地电连接。
  6. 根据权利要求5所述的电路板，其特征在于，所述多个金属化孔包括第一金属 化孔，所述第一金属化孔在所述第一表面的正投影与所述第一信号线在所述第一表面的占用区域不重叠，所述第一金属化孔在所述第二表面的正投影与所述第二信号线在所述第二表面的占用区域不重叠，所述第一金属化孔为贯穿所述电路板层主体的通孔。
  7. 根据权利要求5或6所述的电路板，其特征在于，所述多个金属化孔包括第二金属化孔，所述第二金属化孔在所述第一表面的正投影与所述第一信号线在所述第一表面的占用区域至少部分重叠，所述第二金属化孔在所述第二表面的正投影与所述第二信号线在所述第二表面的占用区域不重叠，所述第二金属化孔为一端贯穿所述第二表面，另一端未贯穿所述第一表面的盲孔。
  8. 根据权利要求7所述的电路板，其特征在于，所述第二金属化孔在所述金属化过孔的中轴线上的正投影与所述金属套筒在所述金属化过孔的中轴线上的正投影相接或者部分重叠。
  9. 根据权利要求5～7中任一项所述的电路板，其特征在于，所述多个金属化孔包括第三金属化孔，所述第三金属化孔在所述第一表面的正投影与所述第一信号线在所述第一表面的占用区域不重叠，所述第三金属化孔在所述第二表面的正投影与所述第二信号线在所述第二表面的占用区域至少部分重叠，所述第三金属化孔为一端贯穿所述第一表面，另一端未贯穿所述第二表面的盲孔。
  10. 根据权利要求9所述的电路板，其特征在于，所述第三金属化孔在所述金属化过孔的中轴线上的正投影与所述金属套筒在所述金属化过孔的中轴线上的正投影相接或者部分重叠。
  11. 根据权利要求1～10中任一项所述的电路板，其特征在于，所述金属套筒的内径为所述金属化过孔的外径的2.4～4倍。
  12. 根据权利要求1～11中任一项所述的电路板，其特征在于，所述第一信号线和所述第二信号线均为传输最高频率在1GHz以上的高频信号的信号线。
  13. 一种电子设备，其特征在于，包括处理器、天线和权利要求1～12中任一项所述的电路板，所述处理器与所述电路板耦合，所述电路板中的第一信号线或第二信号线与天线耦合，用于实现天线信号的收或发。
  14. 一种电路板的加工方法，其特征在于，包括：
    制作带有金属化过孔和金属套筒的电路板层主体，所述电路板层主体具有相对的第一表面和第二表面，所述电路板层主体的内部设有参考地，所述金属化过孔贯穿所述电路板层主体，所述金属套筒设置于所述电路板层主体内并套设于所述金属化过孔的外围一周，所述金属套筒与所述金属化过孔绝缘，且所述金属套筒与所述电路板层主体内的参考地电连接；
    在所述电路板层主体的第一表面设置第一信号线，并使所述第一信号线与所述金属化过孔的位于所述电路板层主体的第一表面的一端电连接，所述第一信号线与所述金属套筒绝缘；
    在所述电路板层主体的第二表面设置第二信号线，并使所述第二信号线与所述金属化过孔的位于所述电路板层主体的第二表面的一端电连接，所述第二信号线与所述金属套筒绝缘。
  15. 根据权利要求14所述的电路板的加工方法，其特征在于，所述电路板层主体 包括第一电路板子层、第二电路板子层和第三电路板子层，第二电路板子层内设有参考地；
    所述制作带有金属化过孔和金属套筒的电路板层主体包括：
    在所述第二电路板子层上设置金属套筒，所述金属套筒贯穿所述第二电路板子层，所述金属套筒与所述第二电路板子层内的参考地电连接，并在所述金属套筒内设置绝缘材料，以形成带有金属套筒的第二电路板子层；
    将所述第一电路板子层、所述带有金属套筒的第二电路板子层和所述第三电路板子层层叠并固定在一起，并使所述第一电路板子层和所述第三电路板子层分别位于所述带有金属套筒的第二电路板子层的相对两侧，以形成带有金属套筒的电路板层主体；
    在所述带有金属套筒的电路板层主体上设置金属化过孔，并使所述金属化过孔穿过所述金属套筒内的绝缘材料并贯穿所述电路板层主体。
  16. 根据权利要求15所述的电路板的加工方法，其特征在于，在所述第二电路板子层上设置金属套筒，并在所述金属套筒内设置绝缘材料包括：
    在第二电路板子层上设置通孔；
    在所述通孔的内表面设置金属层，所述通孔的内表面一周的金属层构成所述金属套筒；
    在所述金属套筒的中空区域填充绝缘材料。
  17. 根据权利要求15所述的电路板的加工方法，其特征在于，在所述第二电路板子层上设置金属套筒，并在所述金属套筒内设置绝缘材料包括：
    在第二电路板子层上设置通孔；
    在所述通孔内安装侧壁一周具有金属层的绝缘柱体，并使所述绝缘柱体沿自身轴向上的两端端面分别与所述第二电路板子层的两个表面平齐，所述绝缘柱体的侧壁一周的金属层构成金属套筒，所述绝缘柱体为设置于所述金属套筒内的绝缘材料。
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