WO2021249344A1 - 光电探测器及其制备方法 - Google Patents

光电探测器及其制备方法 Download PDF

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WO2021249344A1
WO2021249344A1 PCT/CN2021/098633 CN2021098633W WO2021249344A1 WO 2021249344 A1 WO2021249344 A1 WO 2021249344A1 CN 2021098633 W CN2021098633 W CN 2021098633W WO 2021249344 A1 WO2021249344 A1 WO 2021249344A1
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layer
electrode
type
intrinsic
amorphous silicon
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PCT/CN2021/098633
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French (fr)
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杜建华
李超
罗超
强朝辉
关峰
王治
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京东方科技集团股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
    • H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
    • H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
    • H01L31/1055—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type the devices comprising amorphous materials of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/0328—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032
    • H01L31/0336—Inorganic materials including, apart from doping materials or other impurities, semiconductor materials provided for in two or more of groups H01L31/0272 - H01L31/032 in different semiconductor regions, e.g. Cu2X/CdX hetero- junctions, X being an element of Group VI of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the technical field of semiconductor optoelectronic devices, and in particular to a photodetector and a preparation method thereof.
  • Amorphous silicon as a common photoelectric absorption conversion material is often used to prepare amorphous silicon homojunction PIN (Positive Intrinsic Negative) thin film photodetectors. Its preparation process is compatible with the thin film transistor (TFT) process and is integrated. TFT+PIN can be used for optical fingerprint recognition, etc.
  • TFT thin film transistor
  • the amorphous silicon material Since the amorphous silicon material has a strong quantum efficiency in the visible light range from 500 nanometers (nm) to 600 nanometers, this wavelength band is used for detection.
  • the visible light in the environment When the normal detection device works in the environment, in addition to the detected light reflected by the light source, the visible light in the environment will also be detected. However, the visible light in the environment is equivalent to noise, which will reduce the accuracy of detection, resulting in Multiple detections are required to improve accuracy and reduce detection efficiency.
  • the embodiments of the present disclosure provide a photodetector, which includes a semiconductor heterojunction formed by a wide-gap oxide semiconductor material and an amorphous silicon material, and the junction of the wide-gap oxide semiconductor material and the amorphous silicon material
  • the interface is provided with a barrier layer configured to block the diffusion of elements in the wide band gap oxide semiconductor material to the amorphous silicon material.
  • the semiconductor heterojunction includes: a P-type layer, an intrinsic layer, and an N-type layer, wherein: the P-type layer is a P-type amorphous silicon layer, and the intrinsic layer is based The characteristic amorphous silicon layer; the N-type layer is an N-type wide-bandgap oxide semiconductor layer; the barrier layer is disposed between the intrinsic layer and the N-type layer.
  • the photodetector further includes a substrate, a bottom electrode, a lateral electrode, a protective layer, and a top electrode, wherein: the substrate, the bottom electrode, the P-type layer, the intrinsic layer, and the barrier layer , The N-type layer, the lateral electrode and the top electrode are stacked in order from bottom to top; the protective layer covers the semiconductor heterojunction and the first and second sides of the lateral electrode, the first side and the The second side surface is opposite and perpendicular to the surface where the substrate is connected to the bottom electrode.
  • the protective layer also covers the surface of the lateral electrode away from the substrate; the protective layer is provided with a first through hole, and the top electrode passes through the first through hole and the substrate.
  • the horizontal electrode connection is provided.
  • the photodetector further includes a flat layer covering the third side surface and the fourth side surface of the protective layer, and the third side surface and the fourth side surface are opposite and parallel to the protective layer. Describe the first side and the second side.
  • the protective layer also covers the surface of the lateral electrode away from the substrate; the flat layer also covers the surface of the protective layer away from the substrate; the protective layer is provided with A first through hole, the flat layer is provided with a second through hole, the first through hole and the second through hole pass through, and the top electrode passes through the first through hole and the second through hole and the lateral electrode connect.
  • the wide bandgap oxide semiconductor material includes any one of the following: indium gallium zinc oxide IGZO, zinc oxide ZnO, titanium dioxide TiO2, indium gallium zinc Y oxide IGZYO, and indium gallium zinc X oxide IGZXO, where X and Y represent doped tin, and the ratio of X and Y doping is different.
  • the embodiment of the present disclosure also provides a method for preparing a photodetector, including: preparing a bottom electrode on a substrate; preparing a P-type layer and an intrinsic layer on the bottom electrode in sequence; preparing on the intrinsic layer Barrier layer; an N-type layer and a lateral electrode are sequentially prepared on the barrier layer, the P-type layer, the intrinsic layer and the N-type layer constitute a semiconductor heterogeneity formed by a wide band gap oxide semiconductor material and an amorphous silicon material
  • the barrier layer is configured to block the diffusion of elements in the wide-gap oxide semiconductor material to the amorphous silicon material; a protective layer and a top electrode are prepared on the lateral electrode, and the protective layer covers the semiconductor heterogeneous material.
  • the first side surface and the second side surface of the junction and the lateral electrode, the first side surface and the second side surface are opposite and perpendicular to the surface where the substrate connects with the bottom electrode.
  • the P-type layer is a P-type amorphous silicon layer
  • the intrinsic layer is an intrinsic amorphous silicon layer
  • the N-type layer is an N-type wide bandgap oxide semiconductor layer.
  • the P-type layer, the intrinsic layer and the barrier layer are prepared by a plasma enhanced chemical vapor deposition PECVD method; the P-type layer and the intrinsic layer are sequentially prepared on the bottom electrode, and
  • the preparation of the barrier layer on the intrinsic layer includes: depositing a P-type layer on the bottom electrode, and the deposition process temperature is between 200 degrees Celsius and 300 degrees Celsius; replacing the chamber to keep the replaced chamber under vacuum; The intrinsic layer and the barrier layer are continuously deposited in the chamber of, and the deposition process temperature is between 200 degrees Celsius and 300 degrees Celsius.
  • Figure 1 is a schematic diagram of the structure of an amorphous silicon homojunction PIN
  • FIG. 2 is a schematic structural diagram of a photodetector according to an embodiment of the disclosure
  • FIG. 3 is a schematic structural diagram of another photodetector according to an embodiment of the disclosure.
  • FIG. 4 is a schematic structural diagram of another photodetector according to an embodiment of the disclosure.
  • FIG. 5 is a schematic flowchart of a method for manufacturing a photodetector according to an embodiment of the disclosure
  • Figure 6 is a schematic diagram of the photodetector structure after the bottom electrode is prepared
  • Figure 7 is a schematic diagram of the photodetector structure after preparing the P-type layer and the intrinsic layer
  • Figure 8 is a schematic diagram of the photodetector structure after the barrier layer is prepared
  • Figure 9 is a schematic diagram of the photodetector structure after the N-type layer and lateral electrodes are prepared.
  • Figure 10 is a schematic diagram of the photodetector structure after the protective layer and the top electrode are prepared
  • FIG. 11 is a schematic diagram of external quantum efficiency (EQE) test results of three photodetectors
  • Figure 12 is a schematic diagram of the dark current density test results of three photodetectors.
  • the present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art.
  • the embodiments, features, and elements disclosed in the present disclosure can also be combined with any conventional features or elements to form a unique invention solution defined by the claims.
  • Any feature or element of any embodiment can also be combined with features or elements from other invention solutions to form another unique invention solution defined by the claims. Therefore, it should be understood that any feature shown and/or discussed in this disclosure can be implemented individually or in any suitable combination. Therefore, the embodiments are not subject to other restrictions except for the restrictions made according to the appended claims and their equivalents.
  • various modifications and changes can be made within the protection scope of the appended claims.
  • the intrinsic (Intrinsic, I) layer 13 absorbs incident light signals to generate photo-generated electron-hole pairs. Under the action of a reverse bias, the photo-generated electrons and voids The holes respectively drift to the N (Negative) type layer 15 and the P (Positive) type layer 12 to form a photocurrent. For short-wavelength optical signals, the photon energy is much greater than the band gap of amorphous silicon (a-Si).
  • the short-wavelength optical signals absorbed by the valence band electrons transition to a higher energy level position in the conduction band, and the photogenerated electrons will be in During the transition to the bottom of the conduction band, it interacts with the crystal lattice and transfers energy to the crystal lattice, causing the lattice vibration to be strengthened, and the carrier scattering is strengthened, resulting in that the contribution of the photogenerated electrons to the photocurrent is not as good as the light generated by the long-wavelength optical signal.
  • the current is significant, so the traditional amorphous silicon homojunction PIN is relatively weak in detecting short-wavelength optical signals.
  • the embodiments of the present disclosure provide a photodetector, which includes a semiconductor heterojunction formed by a wide band gap oxide semiconductor material and an amorphous silicon material, and the junction interface between the wide band gap oxide semiconductor material and the amorphous silicon material is arranged There is a barrier layer, and the barrier layer is configured to block the diffusion of elements in the wide band gap oxide semiconductor material to the amorphous silicon material.
  • the photodetector of the embodiment of the present disclosure adopts a semiconductor heterojunction (Heterojunction) structure formed of a wide band gap oxide semiconductor material and an amorphous silicon material.
  • Heterojunction semiconductor heterojunction
  • Light absorption and current conversion efficiency, high quantum efficiency, wide-band absorption characteristics are beneficial to increase the amount of signal collected by the photodetector, thereby increasing the signal-to-noise ratio; in addition, by adding a barrier layer structure in the junction interface, the photodetector
  • the dark current can remain stable under larger bias voltage and higher temperature, and the detection accuracy and stability are much higher than that of amorphous silicon homojunction PIN; and the preparation process is compatible with the current TFT backplane preparation process and meets mass production requirements .
  • the material of the wide-gap oxide semiconductor may include: indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO), zinc oxide (Zinc Oxide, ZnO), titanium dioxide (Titanium Dioxide, TiO2) , Indium Gallium Zinc Oxide (IGZYO), Indium Gallium Zinc X Oxide (IGZXO) and other wide-gap oxide semiconductors, X and Y indicate doped Metal: Tin (Stannum, Sn) and the ratio of doping between the two is different.
  • IGZO indium gallium Zinc Oxide
  • ZnO zinc oxide
  • TiO2 titanium dioxide
  • IGZYO Indium Gallium Zinc Oxide
  • IGZXO Indium Gallium Zinc X Oxide
  • X and Y indicate doped Metal: Tin (Stannum, Sn) and the ratio of doping between the two is different.
  • the semiconductor heterojunction includes: a P-type layer 12, an intrinsic layer 13 and an N-type layer 15, where: the P-type layer 12 is a P-type amorphous silicon layer , The intrinsic layer 13 is an intrinsic amorphous silicon layer; the N-type layer 15 is an N-type wide band gap oxide semiconductor layer; the barrier layer 14 is disposed between the intrinsic layer 13 and the N-type layer 15.
  • the light-facing surface of the semiconductor heterojunction in the embodiments of the present disclosure is an N-type wide bandgap oxide semiconductor layer, which can convert short-wavelength optical signals into effective photocurrent, thereby improving the detection capability of the photodetector for short-wavelength optical signals .
  • the photodetector further includes a substrate 10, a bottom electrode 11, a lateral electrode 16, a protective layer 18, and a top electrode 17, wherein: the substrate 10, the bottom electrode 11 The P-type layer 12, the intrinsic layer 13, the barrier layer 14, the N-type layer 15, the lateral electrode 16 and the top electrode 17 are stacked from bottom to top; the protective layer 18 covers the semiconductor heterojunction and the first side surface of the lateral electrode 16. And the second side surface, the first side surface and the second side surface are opposite and perpendicular to the surface where the substrate 10 and the bottom electrode 11 are connected.
  • the photodetector further includes a flat layer 19, the flat layer 19 covers the third side and the fourth side of the protective layer 18, the third side and the fourth side are opposite and parallel On the first side and the second side.
  • the protective layer 18 also covers the surface of the lateral electrode 16 away from the substrate 10; the protective layer 18 is provided with a first through hole through which the top electrode 17 passes. It is connected to the lateral electrode 16.
  • the flat layer 19 also covers the surface of the protective layer 18 away from the substrate 10; the flat layer 19 is provided with a second through hole, and the second through hole and the first through hole pass through , The top electrode 17 is connected to the lateral electrode 16 through the second through hole and the first through hole.
  • the photodetector In the photodetector of this embodiment, the photodetector is fully covered by the protective layer 19 and the flat layer 18, and only one electrode hole is left. This structure is conducive to the stability of the device reliability.
  • the photodetector further includes a buffer layer, wherein the buffer layer is disposed between the substrate 10 and the bottom electrode 11.
  • the material of the substrate 10 may be sapphire, glass, silicon wafer or other insulating materials; the material of the bottom electrode 11 may be gold, silver, nickel, titanium, platinum, palladium, Indium tin oxide One or more of Tin Oxide (ITO) electrodes.
  • ITO Tin Oxide
  • the material of the barrier layer 14 may be silicon nitride (SiNx) or silicon oxide (SiO2).
  • the material of the lateral electrode 16 may be an ITO electrode.
  • the top electrode 17 may be an ITO electrode.
  • the protective layer 18 may be provided by stacking one or more of silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • an embodiment of the present disclosure also provides a method for preparing a photodetector, and the method for preparing includes:
  • a bottom electrode 11 is prepared on the substrate 10, as shown in FIG. 6.
  • the preparation method before the bottom electrode 11 is prepared, the preparation method further includes: cleaning the substrate 10.
  • preparing the bottom electrode 11 on the substrate 10 includes: preparing a buffer layer on the substrate 10; and preparing the bottom electrode 11 on the buffer layer.
  • the material of the substrate 10 may be sapphire, glass, silicon wafer or other insulating materials.
  • the material of the bottom electrode 11 may be one or more of gold, silver, nickel, titanium, platinum, palladium, and indium tin oxide (ITO) electrodes.
  • ITO indium tin oxide
  • the preparation method further includes: etching the bottom electrode 11 based on the first mask to form a patterned bottom electrode layer.
  • a P-type layer 12 and an intrinsic layer 13 are sequentially formed on the bottom electrode 11, as shown in FIG. 7.
  • the P-type layer 12 is a P-type amorphous silicon layer
  • the intrinsic layer 13 is an intrinsic amorphous silicon layer.
  • the P-type layer 12 and the intrinsic layer 13 are prepared by a plasma enhanced chemical vapor deposition (Plasma Enhanced Chemical Vapor Deposition, PECVD) method. After the P-type layer 12 is deposited on the bottom electrode 11, it is replaced The intrinsic layer 13 is deposited in the chamber to avoid contamination of the intrinsic layer 13 by the doped boron (B+) ions of the P-type layer 12 during the deposition process of the P-type layer 12 and the intrinsic layer 13.
  • PECVD plasma enhanced chemical vapor deposition
  • the semiconductor heterojunction preparation sequence of the embodiments of the present disclosure is P/I/N sequential preparation, which is opposite to the N/I/P process sequence of PIN devices in some technologies.
  • the cleaning chamber can be cleaned more thoroughly when doped with phosphorus (P+) elements.
  • the N-type layer 15 can be deposited to clean the chamber or After the chamber is replaced, the intrinsic layer 13 and the P-type layer 12 are continuously deposited.
  • the levy layer 13 is deposited to ensure that it is not contaminated.
  • the temperature of the cavity of the PECVD device is set to be between 200 degrees Celsius (°C) and 300°C.
  • the PECVD device After setting the cavity temperature between 200°C and 230°C, the problem was solved.
  • the thickness of the P-type layer 12 may be 20 nanometers to 70 nanometers, and exemplary, the thickness of the P-type layer 12 may be 50 nanometers.
  • the thickness of the intrinsic layer 13 may be 300 nanometers to 1.2 micrometers (um), and exemplary, the thickness of the intrinsic layer 13 may be 900 nanometers.
  • the material of the barrier layer 14 may be silicon nitride (SiNx) or silicon oxide (SiO2).
  • the thickness of the barrier layer 14 may be 1 nanometer to 5 nanometers, and exemplary, the thickness of the barrier layer 14 may be 2 nanometers.
  • the barrier layer 14 is prepared by a PECVD method, and the barrier layer 14 and the intrinsic layer 13 are continuously deposited while the cavity of the PECVD device is kept in a vacuum (keeping vacuum).
  • the function of the barrier layer 14 is to prevent elements in the wide-gap oxide semiconductor material in the upper layer (N-type layer 15) from diffusing to the intrinsic layer 13.
  • the elements in the wide-gap oxide semiconductor material diffuse to the intrinsic layer 13 Will cause the leakage current of the device to increase; in the photodetector of the embodiment of the present disclosure, by providing the barrier layer 14, the dark current characteristics of the device are stabilized, and the characteristics of the device remain stable under high temperature and high pressure.
  • N-type layer 15 and a lateral electrode 16 are sequentially prepared on the barrier layer 14.
  • the P-type layer 12, the intrinsic layer 13 and the N-type layer 15 are composed of a wide band gap oxide semiconductor material and an amorphous
  • the barrier layer 14 is configured to block the diffusion of elements in the wide-gap oxide semiconductor material to the amorphous silicon material.
  • the N-type layer 15 may be an N-type wide band gap oxide semiconductor layer.
  • the material of the wide bandgap oxide semiconductor may include: indium gallium zinc oxide IGZO, zinc oxide ZnO, titanium dioxide TiO2, indium gallium zinc Y oxide IGZYO, indium gallium zinc X oxide IGZXO, etc.
  • X and Y represent doped metal: tin Sn, and the doping ratio of the two is different.
  • the material of the lateral electrode 16 may be an ITO electrode. Both the bottom electrode 11 and the lateral electrode 16 are used to collect the generated photo-generated carriers.
  • the N-type layer 15 and the lateral electrode 16 may be prepared by a magnetron sputtering method.
  • the magnetron sputtering preparation process parameters of the N-type layer 15 include: the working gas is argon (no oxygen, that is, the oxygen gas flow rate is 0 sccm), and the argon gas flow rate is 50 to 150 sccm,
  • the working pressure is controlled at 0.1-1Pa
  • the sputtering power is controlled at 4kw to 5kw
  • the number of magnet scans is 3 times or more.
  • the thickness of the N-type layer 15 may be 5 nanometers to 70 nanometers.
  • the thickness of the N-type layer 15 may be 30 nanometers.
  • the thickness of the lateral electrode 16 may be 10 nanometers to 70 nanometers.
  • the thickness of the lateral electrode 16 may be 30 nanometers.
  • the preparation method further includes:
  • dry etching is performed on the intrinsic layer 13 and the P-type layer 12 to form a patterned intrinsic layer 13 and the P-type layer 12.
  • the protective layer 18 covers the semiconductor heterojunction and the first and second sides of the lateral electrode 16, the first and second Opposite and perpendicular to the surface where the substrate 10 and the bottom electrode 11 are connected.
  • the thickness of the protective layer 18 may be 50 nanometers to 200 nanometers, and exemplary, the thickness of the protective layer 18 may be 100 nanometers.
  • the protective layer 18 may be used to protect the sidewalls of the semiconductor heterojunction.
  • the protective layer 18 may be provided by stacking one or more of silicon oxide, silicon nitride, silicon oxynitride, and the like.
  • the preparation method further includes: preparing a flat (Resin) layer on the protective layer 18, and the flat layer 19 covers the second layer of the protective layer 18.
  • the three side surfaces and the fourth side surface, the third side surface and the fourth side surface are opposite and parallel to the first side surface and the second side surface, so that subsequent electrodes overlap.
  • the thickness of the flat layer 19 can be set according to the actual requirements of the device.
  • the preparation method further includes: based on the fourth mask, etching the protective layer 18 and the planarization layer 19 together, and etch away the lateral electrodes 16 away from the liner.
  • preparing the top electrode 17 includes depositing a transparent electrode, and etching the transparent electrode based on the fifth mask to form the top electrode trace.
  • the top electrode 17 may be an ITO electrode.
  • the thickness of the top electrode 17 may be 20 nanometers to 700 nanometers.
  • the thickness of the top electrode 17 may be 40 nanometers.
  • the protective layer 18 also covers the surface of the lateral electrode 16 away from the substrate 10; the protective layer 18 is provided with a first through hole, and the top electrode 17 is connected to the lateral electrode 16 through the first through hole.
  • the flat layer 19 also covers the surface of the protective layer 18 away from the substrate 10; the flat layer 19 is provided with a second through hole, the second through hole and the first through hole penetrate through the top electrode 17 The second through hole and the first through hole are connected to the lateral electrode 16.
  • the experimental results show that the photodetector of the embodiment of the present disclosure has a high quantum efficiency in the wavelength range of 300 to 650 nanometers, and it is tested at 70°C and 10V bias for 2 hours
  • the dark current is stable and has no offset, which indicates that the photodetector of the embodiment of the present disclosure has very good applicability to a long-term, high-precision, high-temperature and high-pressure environment, and has a comprehensive performance improvement compared with traditional amorphous silicon PIN devices.
  • the photodetector and the preparation method thereof in the embodiments of the present disclosure adopt a semiconductor heterojunction structure formed by a wide-bandgap oxide semiconductor material and an amorphous silicon material, and have a higher wavelength in the wavelength range of 300 nanometers to 650 nanometers.
  • High light absorption and current conversion efficiency, high quantum efficiency at the same time, by adding a barrier structure to the junction interface, the dark current of the photodetector can be kept stable under larger bias voltage and higher temperature, and the detection accuracy and stability
  • the performance is much higher than that of amorphous silicon homojunction PIN; and the embodiments of the present disclosure can be realized by the current mature manufacturing equipment, and can be well compatible with the current manufacturing process, with low manufacturing cost, easy process realization, high production efficiency and good products. It has the advantages of high rate and good application prospects.
  • connection should be interpreted broadly, for example, it may be a fixed connection or a detachable connection, or Integrally connected; it can be mechanical connection or electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.
  • connection should be interpreted broadly, for example, it may be a fixed connection or a detachable connection, or Integrally connected; it can be mechanical connection or electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication between two components.

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Abstract

一种光电探测器及其制备方法，该光电探测器包括由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结，且宽禁带氧化物半导体材料与非晶硅材料的结界面设置有阻挡层，该阻挡层被配置为阻挡宽禁带氧化物半导体材料中的元素向非晶硅材料扩散。

Description

光电探测器及其制备方法
本申请要求于2020年6月10日提交中国专利局、申请号为202010522969.0、发明名称为“一种光电探测器及其制备方法”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本公开实施例涉及但不限于半导体光电子器件技术领域，尤其涉及一种光电探测器及其制备方法。
背景技术
近年来，显示装置被制作成集成光电探测器以实现各种功能，例如：光感测、生物信息检测和人机交互等。非晶硅作为常见的光电吸收转换材料常用于制备非晶硅同质结PIN(Positive IntrinsicNegative)型薄膜光电探测器，其制备流程与薄膜晶体管(Thin Film Transistor，TFT)工艺兼容性好，集成的TFT+PIN可以用于光学指纹识别等。
由于非晶硅材料在500纳米(nanometer，nm)至600纳米的可见光范围内有较强的量子效率，因此，使用该波段进行探测。通常的探测器件在环境中工作时，除了光源反射后的被检测光以外，环境中的可见光也会被检测到，但是，环境中的可见光相当于噪声，它会降低探测的准确度，从而导致需要多次探测来提高准确度，降低了探测效率。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
本公开实施例提供了一种光电探测器，包括由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结，且所述宽禁带氧化物半导体材料与非晶硅材料的结界面设置有阻挡层，所述阻挡层被配置为阻挡宽禁带氧化物半导体材料中的元素向非晶硅材料扩散。
在一些可能的实现方式中，所述半导体异质结包括：P型层、本征层和N型层，其中：所述P型层为P型非晶硅层，所述本征层为本征非晶硅层；所述N型层为N型宽禁带氧化物半导体层；所述阻挡层设置在所述本征层和N型层之间。
在一些可能的实现方式中，所述光电探测器还包括衬底、底电极、横向电极、保护层和顶电极，其中：所述衬底、底电极、P型层、本征层、阻挡层、N型层、横向电极和顶电极从下至上依次层叠设置；所述保护层覆盖所述半导体异质结以及所述横向电极的第一侧面和第二侧面，所述第一侧面和所述第二侧面相对且垂直于衬底与底电极连接的表面。
在一些可能的实现方式中，所述保护层还覆盖所述横向电极远离所述衬底的表面；所述保护层设有第一通孔，所述顶电极通过所述第一通孔和所述横向电极连接。
在一些可能的实现方式中，所述光电探测器还包括平坦层，所述平坦层覆盖所述保护层的第三侧面和第四侧面，所述第三侧面和第四侧面相对且平行于所述第一侧面和第二侧面。
在一些可能的实现方式中，所述保护层还覆盖所述横向电极远离所述衬底的表面；所述平坦层还覆盖所述保护层远离所述衬底的表面；所述保护层设有第一通孔，所述平坦层设有第二通孔，所述第一通孔和第二通孔贯通，所述顶电极通过所述第一通孔和第二通孔与所述横向电极连接。
在一些可能的实现方式中，所述宽禁带氧化物半导体材料包括以下任意一种：铟镓锌氧化物IGZO、氧化锌ZnO、二氧化钛TiO2、铟镓锌Y氧化物IGZYO和铟镓锌X氧化物IGZXO，其中，X和Y表示掺杂锡，且X和Y掺杂的比例不同。
本公开实施例还提供了一种光电探测器的制备方法，包括：在衬底上制备底电极；在所述底电极上依次制备P型层和本征层；在所述本征层上制备阻挡层；在所述阻挡层上依次制备N型层和横向电极，所述P型层、本征层和N型层构成由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结，所述阻挡层被配置为阻挡宽禁带氧化物半导体材料中的元素向非晶硅材料扩散；在所述横向电极上制备保护层和顶电极，所述保护层覆盖所述半导体异 质结以及所述横向电极的第一侧面和第二侧面，所述第一侧面和所述第二侧面相对且垂直于衬底与底电极连接的表面。
在一些可能的实现方式中，所述P型层为P型非晶硅层，所述本征层为本征非晶硅层；所述N型层为N型宽禁带氧化物半导体层。
在一些可能的实现方式中，所述P型层、本征层和阻挡层采用等离子体增强化学气相沉积PECVD法制备；所述在所述底电极上依次制备P型层和本征层，在所述本征层上制备阻挡层，包括：在所述底电极上沉积P型层，沉积的工艺温度在200摄氏度到300摄氏度之间；更换腔室，使更换的腔室保持真空；在更换的腔室内连续沉积所述本征层和所述阻挡层，沉积的工艺温度在200摄氏度到300摄氏度之间。
在阅读并理解了附图和详细描述后，可以明白其他方面。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种非晶硅同质结PIN的结构示意图；
图2为本公开实施例的一种光电探测器的结构示意图；
图3为本公开实施例的另一种光电探测器的结构示意图；
图4为本公开实施例的又一种光电探测器的结构示意图；
图5为本公开实施例的一种光电探测器的制备方法的流程示意图；
图6为制备底电极之后的光电探测器结构示意图；
图7为制备P型层和本征层之后的光电探测器结构示意图；
图8为制备阻挡层之后的光电探测器结构示意图；
图9为制备N型层和横向电极之后的光电探测器结构示意图；
图10为制备保护层和顶电极之后的光电探测器结构示意图；
图11为三种光电探测器的外量子效率(External Quantum Efficiency，EQE) 测试结果示意图；
图12为三种光电探测器的暗电流密度测试结果示意图。
具体实施方式
本公开描述了多个实施例，但是该描述是示例性的，而不是限制性的，并且对于本领域的普通技术人员来说显而易见的是，在本公开所描述的实施例包含的范围内可以有更多的实施例和实现方案。尽管在附图中示出了许多可能的特征组合，并在具体实施方式中进行了讨论，但是所公开的特征的许多其它组合方式也是可能的。除非特意加以限制的情况以外，任何实施例的任何特征或元件可以与任何其它实施例中的任何其他特征或元件结合使用，或可以替代任何其它实施例中的任何其他特征或元件。
本公开包括并设想了与本领域普通技术人员已知的特征和元件的组合。本公开已经公开的实施例、特征和元件也可以与任何常规特征或元件组合，以形成由权利要求限定的独特的发明方案。任何实施例的任何特征或元件也可以与来自其它发明方案的特征或元件组合，以形成另一个由权利要求限定的独特的发明方案。因此，应当理解，在本公开中示出和/或讨论的任何特征可以单独地或以任何适当的组合来实现。因此，除了根据所附权利要求及其等同替换所做的限制以外，实施例不受其它限制。此外，可以在所附权利要求的保护范围内进行各种修改和改变。
此外，在描述具有代表性的实施例时，说明书可能已经将方法和/或过程呈现为特定的步骤序列。然而，在该方法或过程不依赖于本文所述步骤的特定顺序的程度上，该方法或过程不应限于所述的特定顺序的步骤。如本领域普通技术人员将理解的，其它的步骤顺序也是可能的。因此，说明书中阐述的步骤的特定顺序不应被解释为对权利要求的限制。此外，针对该方法和/或过程的权利要求不应限于按照所写顺序执行它们的步骤，本领域技术人员可以容易地理解，这些顺序可以变化，并且仍然保持在本公开实施例的精神和范围内。
如图1所示，在非晶硅同质结PIN中，由本征(Intrinsic，I)层13吸收入射光信号，产生光生电子-空穴对，在反向偏压作用下，光生电子和空穴分 别向N(Negative)型层15和P(Positive)型层12漂移，形成光电流。对于短波长的光信号，其光子能量远大于非晶硅(a-Si)禁带宽度，价带电子吸收的短波长的光信号跃迁至导带较高的能级位置，该光生电子会在跃迁至导带底的过程中与晶格相互作用，将能量转移至晶格，引起晶格震动加强，载流子散射增强，导致该光生电子对光电流的贡献不如长波长光信号产生的光电流显著，因此，传统非晶硅同质结PIN对短波长光信号的探测能力相对较弱。
本公开实施例提供了一种光电探测器，包括由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结，且宽禁带氧化物半导体材料与非晶硅材料的结界面设置有阻挡层，阻挡层被配置为阻挡宽禁带氧化物半导体材料中的元素向非晶硅材料扩散。
本公开实施例的光电探测器，采用由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结(Heterojunction)结构，在300纳米至650纳米的波长范围内，都有较高的光吸收和电流转化效率，量子效率高，宽波段的吸收特性有利于增加光电探测器收集到的信号量，从而增加信噪比；此外，通过在结界面中加入阻挡层结构，使得光电探测器在较大偏压与较高温度下的暗电流能保持稳定，探测准确性、稳定性远高于非晶硅同质结PIN；并且制备工艺与当前TFT背板制备工艺兼容，满足量产要求。
在一种示例性实施例中，宽禁带氧化物半导体的材料可以包括：铟镓锌氧化物(Indium Gallium Zinc Oxide，IGZO)、氧化锌(Zinc Oxide，ZnO)、二氧化钛(Titanium Dioxide，TiO2)、铟镓锌Y氧化物(Indium Gallium Zinc Oxide，IGZYO)、铟镓锌X氧化物(Indium Gallium Zinc X Oxide，IGZXO)等宽禁带氧化物半导体中的任意一种，X和Y表示掺杂金属：锡(Stannum，Sn)且两者掺杂的比例不同。
在一种示例性实施例中，如图2所示，该半导体异质结包括：P型层12、本征层13和N型层15，其中：P型层12为P型非晶硅层，本征层13为本征非晶硅层；N型层15为N型宽禁带氧化物半导体层；阻挡层14设置在本征层13和N型层15之间。
本公开实施例的半导体异质结的迎光面为N型宽禁带氧化物半导体层， 可以将短波长光信号转化为有效的光电流，从而提高光电探测器对短波长光信号的探测能力。
在一种示例性实施例中，如图3所示，该光电探测器还包括衬底10、底电极11、横向电极16、保护层18和顶电极17，其中：衬底10、底电极11、P型层12、本征层13、阻挡层14、N型层15、横向电极16和顶电极17从下至上依次层叠设置；保护层18覆盖半导体异质结以及横向电极16的第一侧面和第二侧面，第一侧面和第二侧面相对且垂直于衬底10与底电极11连接的表面。
在一种示例性实施例中，如图3所示，光电探测器还包括平坦层19，平坦层19覆盖保护层18的第三侧面和第四侧面，第三侧面和第四侧面相对且平行于第一侧面和第二侧面。
在另一种示例性实施例中，如图4所示，保护层18还覆盖横向电极16远离衬底10的表面；保护层18设有第一通孔，顶电极17通过该第一通孔与横向电极16连接。
在一种示例性实施例中，如图4所示，平坦层19还覆盖保护层18远离衬底10的表面；平坦层19设有第二通孔，第二通孔和第一通孔贯通，顶电极17通过该第二通孔和第一通孔，与横向电极16连接。
本实施例的光电探测器，通过将保护层19与平坦层18对光电探测器进行全覆盖，只留一个电极孔，该结构有利于器件信赖性稳定。
在一种示例性实施例中，光电探测器还包括缓冲层，其中：缓冲层设置在衬底10和底电极11之间。
在一种示例性实施例中，衬底10的材料可以为蓝宝石、玻璃、硅片或其他绝缘材料；底电极11的材料可以是金、银、镍、钛、铂、钯、Indium铟锡氧化物(Tin Oxide，ITO)电极中的一种或多种。
在一种示例性实施例中，阻挡层14的材料可以为氮化硅(SiNx)或者氧化硅(SiO2)。
在一种示例性实施例中，横向电极16的材料可以为ITO电极。
在一种示例性实施例中，顶电极17可以为ITO电极。
在一种示例性实施例中，保护层18可以通过氧化硅、氮化硅、氮氧化硅等中的一种或多种叠层设置。
如图5所示，本公开实施例还提供了一种光电探测器的制备方法，该制备方法包括：
S1、在衬底10上制备底电极11，如图6所示。
在一种示例性实施例中，在制备底电极11之前，该制备方法还包括：对衬底10进行清洗。
在一种示例性实施例中，在衬底10上制备底电极11，包括：在衬底10上制备缓冲层；在缓冲层上制备底电极11。
在一种示例性实施例中，该衬底10的材料可以为蓝宝石、玻璃、硅片或其他绝缘材料。
在一种示例性实施例中，底电极11的材料可以是金、银、镍、钛、铂、钯、Indium铟锡氧化物(Tin Oxide，ITO)电极中的一种或多种。
在一种示例性实施例中，该制备方法还包括：基于第一掩膜版，对底电极11进行刻蚀，形成图案化的底电极层。
S2、在底电极11上依次制备P型层12和本征层13，如图7所示。
在一种示例性实施例中，P型层12为P型非晶硅层，本征层13为本征非晶硅层。
在一种示例性实施例中，P型层12和本征层13采用等离子体增强化学气相沉积(Plasma Enhanced Chemical Vapor Deposition，PECVD)法制备，在底电极11上沉积P型层12后，更换腔室沉积本征层13，以避免在P型层12与本征层13沉积过程中本征层13被P型层12的掺杂硼(B+)离子污染。
本公开实施例的半导体异质结制备顺序为P/I/N顺序制备，与一些技术中的PIN器件的N/I/P工艺顺序相反。由于与掺杂硼(B+)元素相比，掺杂磷(P+)元素时清洁腔室能够清洁的更彻底，一些技术中PIN器件沉积时，N型层15沉积后可以对腔室进行清洁或者更换腔室后，再进行本征层13与P型层12连续沉积；而本公开实施例的半导体异质结在P型层12沉积后， 由于B+很难清除彻底，需要更换腔室进行本征层13沉积以确保不被污染。
在一种示例性实施例中，在P型层12和本征层13采用PECVD法制备时，PECVD装置的腔体温度设置为200摄氏度(℃)至300℃之间。
当PECVD装置的腔体温度设置为250℃(传统PIN沉积温度)时，P型层12和本征层13会存在剥落(peeling)问题，因此，在一种示例性实施例中，将PECVD装置的腔体温度设置为200℃到230℃之间后解决了该问题。
在一种示例性实施例中，P型层12的厚度可以为20纳米至70纳米，示例性的，P型层12的厚度可以为50纳米。
在一种示例性实施例中，本征层13的厚度可以为300纳米至1.2微米(um)，示例性的，本征层13的厚度可以为900纳米。
S3、在本征层13上制备阻挡层14，如图8所示。
在一种示例性实施例中，阻挡层14的材料可以为氮化硅(SiNx)或者氧化硅(SiO2)。
在一种示例性实施例中，阻挡层14的厚度可以为1纳米到5纳米，示例性的，阻挡层14的厚度可以为2纳米。
在一种示例性实施例中，阻挡层14采用PECVD法制备，且阻挡层14与本征层13在PECVD装置的腔体保持真空(keeping vacuum)的情况下，连续沉积。
阻挡层14的作用是防止上层(N型层15)中宽禁带氧化物半导体材料中的元素向本征层13扩散，当宽禁带氧化物半导体材料中的元素向本征层13扩散时，会导致器件的漏电流增大；本公开实施例的光电探测器，通过设置阻挡层14，稳定了器件的暗电流特性，使器件在高温高压下特性保持稳定。
S4、在阻挡层14上依次制备N型层15和横向电极16，如图9所示，P型层12、本征层13和N型层15构成由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结，阻挡层14被配置为阻挡宽禁带氧化物半导体材料中的元素向非晶硅材料扩散。
在一种示例性实施例中，N型层15可以为N型宽禁带氧化物半导体层。
在一种示例性实施例中，宽禁带氧化物半导体的材料可以包括：铟镓锌 氧化物IGZO、氧化锌ZnO、二氧化钛TiO2、铟镓锌Y氧化物IGZYO、铟镓锌X氧化物IGZXO等宽禁带氧化物半导体中的任意一种，X和Y表示掺杂金属：锡Sn且两者掺杂的比例不同。
在一种示例性实施例中，横向电极16的材料可以为ITO电极。底电极11和横向电极16均用于收集产生的光生载流子。
在一种示例性实施例中，N型层15和横向电极16可以采用磁控溅射法制备。
在一种示例性实施例中，N型层15的磁控溅射法制备工艺参数包括：工作气体为氩气(无氧气，即氧气气流量为0sccm)，氩气气流量为50～150sccm，工作气压控制在0.1～1Pa，溅射功率控制在4千瓦至5千瓦，磁铁扫描次数为3次或3次以上。
在一种示例性实施例中，N型层15的厚度可以为5纳米至70纳米。示例性的，N型层15的厚度可以为30纳米。
在一种示例性实施例中，横向电极16的厚度可以为10纳米至70纳米。示例性的，横向电极16的厚度可以为30纳米。
在一种示例性实施例中，该制备方法还包括：
基于第二掩膜版，对N型层15和横向电极16进行湿法刻蚀，形成图案化的N型层15和横向电极16；
基于第三掩膜版，对本征层13和P型层12进行干法刻蚀，形成图案化的本征层13和P型层12。
S5、在横向电极16上制备保护层18和顶电极17，如图10所示，保护层18覆盖半导体异质结以及横向电极16的第一侧面和第二侧面，第一侧面和第二侧面相对且垂直于衬底10与底电极11连接的表面。
在一种示例性实施例中，保护层18的厚度可以为50纳米至200纳米，示例性的，保护层18的厚度可以为100纳米。保护层18可以用于保护半导体异质结的侧壁。
在一种示例性实施例中，保护层18可以通过氧化硅、氮化硅、氮氧化硅等中的一种或多种叠层设置。
在一种示例性实施例中，在制备保护层18之后且在制备顶电极17之前，该制备方法还包括：在保护层18上制备平坦(Resin)层，平坦层19覆盖保护层18的第三侧面和第四侧面，第三侧面和第四侧面相对且平行于第一侧面和第二侧面，以便后续电极搭接。平坦层19的厚度可以根据器件实际需求进行设置。
在一种示例性实施例中，在制备平坦层19之后，该制备方法还包括：基于第四掩膜版，对保护层18和平坦层19一起进行刻蚀，刻蚀掉横向电极16远离衬底10表面的保护层18和平坦层19。
在一种示例性实施例中，制备顶电极17，包括：沉积透明电极，基于第五掩膜版，对透明电极进行刻蚀，形成顶电极走线。
在一种示例性实施例中，顶电极17可以为ITO电极。
在一种示例性实施例中，顶电极17的厚度可以为20纳米至700纳米。示例性的，顶电极17的厚度可以为40纳米。
在一种示例性实施例中，保护层18还覆盖横向电极16远离衬底10的表面；保护层18设有第一通孔，顶电极17通过第一通孔和横向电极16连接。
在一种示例性实施例中，平坦层19还覆盖保护层18远离衬底10的表面；平坦层19设有第二通孔，第二通孔和第一通孔贯通，顶电极17通过该第二通孔和第一通孔，与横向电极16连接。
如图11和图12所示，实验结果表明，本公开实施例的光电探测器，在300至650纳米的波长范围内都有较高的量子效率，并且在70℃、10V偏压下测试2h暗电流稳定无偏移，这表明本公开实施例的光电探测器对长时间、高精度、高温高压环境具有非常好的适用性，相比传统的非晶硅PIN器件有全面的性能提升。
本公开实施例的光电探测器及其制备方法，采用由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结结构，在300纳米至650纳米的波长范围内，都有较高的光吸收和电流转化效率，量子效率高；同时，通过在结界面中加入阻挡层结构，使得光电探测器在较大偏压与较高温度下的暗电流能保持稳定，探测准确性、稳定性远高于非晶硅同质结PIN；并且本公开实 施例可以利用当前成熟的制备设备实现，能够很好地与当前制备工艺兼容，具有制作成本低、易于工艺实现、生产效率高和良品率高等优点，具有良好的应用前景。
在本公开实施例的描述中，术语“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开实施例的描述中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解，例如，可以是固定连接，也可以是可拆卸连接，或一体地连接；可以是机械连接，也可以是电连接；可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的专利保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (16)

  1. 一种光电探测器，包括由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结，且所述宽禁带氧化物半导体材料与非晶硅材料的结界面设置有阻挡层，所述阻挡层被配置为阻挡宽禁带氧化物半导体材料中的元素向非晶硅材料扩散。
  2. 根据权利要求1所述的光电探测器，其中，所述半导体异质结包括：P型层、本征层和N型层，其中：
    所述P型层为P型非晶硅层，所述本征层为本征非晶硅层；
    所述N型层为N型宽禁带氧化物半导体层；
    所述阻挡层设置在所述本征层和N型层之间。
  3. 根据权利要求2所述的光电探测器，还包括衬底、底电极、横向电极、保护层和顶电极，其中：
    所述衬底、底电极、P型层、本征层、阻挡层、N型层、横向电极和顶电极从下至上依次层叠设置；
    所述保护层覆盖所述半导体异质结以及所述横向电极的第一侧面和第二侧面，所述第一侧面和所述第二侧面相对且垂直于所述衬底与底电极连接的表面。
  4. 根据权利要求3所述的光电探测器，其中，所述保护层还覆盖所述横向电极远离所述衬底的表面；
    所述保护层设有第一通孔，所述顶电极通过所述第一通孔和所述横向电极连接。
  5. 根据权利要求3所述的光电探测器，还包括平坦层，所述平坦层覆盖所述保护层的第三侧面和第四侧面，所述第三侧面和第四侧面相对且平行于所述第一侧面和第二侧面。
  6. 根据权利要求5所述的光电探测器，其中，所述保护层还覆盖所述横 向电极远离所述衬底的表面；所述平坦层还覆盖所述保护层远离所述衬底的表面；
    所述保护层设有第一通孔，所述平坦层设有第二通孔，所述第一通孔和第二通孔贯通，所述顶电极通过所述第一通孔和第二通孔与所述横向电极连接。
  7. 根据权利要求3所述的光电探测器，还包括缓冲层，所述缓冲层设置在所述衬底和底电极之间。
  8. 根据权利要求3所述的光电探测器，其中，所述衬底的材料为蓝宝石、玻璃或硅片；所述底电极的材料为金、银、镍、钛、铂、钯、铟锡氧化物电极中的一种或多种。
  9. 根据权利要求3所述的光电探测器，其中，所述横向电极的材料为铟锡氧化物ITO电极。
  10. 根据权利要求3所述的光电探测器，其中，所述保护层包括以下任意一种或多种：氧化硅、氮化硅、氮氧化硅。
  11. 根据权利要求3所述的光电探测器，其中，所述顶电极的材料为铟锡氧化物ITO电极。
  12. 根据权利要求1至11任一所述的光电探测器，其中，所述宽禁带氧化物半导体材料包括以下任意一种：铟镓锌氧化物IGZO、氧化锌ZnO、二氧化钛TiO2、铟镓锌Y氧化物IGZYO和铟镓锌X氧化物IGZXO，其中，X和Y表示掺杂锡，且X和Y掺杂的比例不同。
  13. 根据权利要求1至11任一所述的光电探测器，其中，所述阻挡层的材料为氮化硅或者氧化硅。
  14. 一种光电探测器的制备方法，包括：
    在衬底上制备底电极；
    在所述底电极上依次制备P型层和本征层；
    在所述本征层上制备阻挡层；
    在所述阻挡层上依次制备N型层和横向电极，所述P型层、本征层和N型层构成由宽禁带氧化物半导体材料与非晶硅材料形成的半导体异质结，所述阻挡层被配置为阻挡宽禁带氧化物半导体材料中的元素向非晶硅材料扩散；
    在所述横向电极上制备保护层和顶电极，所述保护层覆盖所述半导体异质结以及所述横向电极的第一侧面和第二侧面，所述第一侧面和所述第二侧面相对且垂直于所述衬底与底电极连接的表面。
  15. 根据权利要求14所述的制备方法，其中，所述P型层为P型非晶硅层，所述本征层为本征非晶硅层；所述N型层为N型宽禁带氧化物半导体层。
  16. 根据权利要求14所述的制备方法，其中，所述在所述底电极上依次制备P型层和本征层，在所述本征层上制备阻挡层，包括：
    采用等离子体增强化学气相沉积PECVD法在所述底电极上沉积P型层，沉积的工艺温度在200摄氏度到300摄氏度之间；
    更换腔室，使更换的腔室保持真空；
    采用等离子体增强化学气相沉积PECVD法在更换的腔室内连续沉积所述本征层和所述阻挡层，沉积的工艺温度在200摄氏度到300摄氏度之间。
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