WO2021248503A1 - 超声换能器制备方法、超声换能器及信息采集元件 - Google Patents

超声换能器制备方法、超声换能器及信息采集元件 Download PDF

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Publication number
WO2021248503A1
WO2021248503A1 PCT/CN2020/095981 CN2020095981W WO2021248503A1 WO 2021248503 A1 WO2021248503 A1 WO 2021248503A1 CN 2020095981 W CN2020095981 W CN 2020095981W WO 2021248503 A1 WO2021248503 A1 WO 2021248503A1
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Prior art keywords
electrode
layer
opening
ultrasonic transducer
piezoelectric
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PCT/CN2020/095981
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English (en)
French (fr)
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王文轩
沈健
王红超
纪登鑫
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深圳市汇顶科技股份有限公司
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Priority to PCT/CN2020/095981 priority Critical patent/WO2021248503A1/zh
Publication of WO2021248503A1 publication Critical patent/WO2021248503A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/01—Manufacture or treatment
    • H10N30/07—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base
    • H10N30/072—Forming of piezoelectric or electrostrictive parts or bodies on an electrical element or another base by laminating or bonding of piezoelectric or electrostrictive bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/20—Piezoelectric or electrostrictive devices with electrical input and mechanical output, e.g. functioning as actuators or vibrators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/50—Piezoelectric or electrostrictive devices having a stacked or multilayer structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N30/00—Piezoelectric or electrostrictive devices
    • H10N30/80—Constructional details
    • H10N30/87—Electrodes or interconnections, e.g. leads or terminals

Definitions

  • the embodiments of the present application relate to the field of electronic information technology, and in particular to a method for preparing an ultrasonic transducer, an ultrasonic transducer, and an information acquisition element.
  • Ultrasonic transducer is a device that converts sound energy and electrical energy.
  • the piezoelectric material in the ultrasonic transducer can produce a voltage difference between both ends when deformed. When there is a voltage difference between both ends, the piezoelectric material can deform . Using this characteristic of piezoelectric materials can realize the mutual conversion of mechanical vibration and alternating current.
  • An ultrasonic transducer generally includes a piezoelectric layer composed of a piezoelectric material, a first electrode disposed above the piezoelectric layer, and a second electrode disposed below the piezoelectric layer.
  • the second electrode layer is prepared first, and the second electrode layer is patterned to form the second electrode , Preparing a piezoelectric layer on the second electrode, preparing a first electrode layer on the piezoelectric layer, and patterning the first electrode layer to form the first electrode.
  • the piezoelectric layer is prepared on the second electrode that has been patterned, the growth surface condition of the piezoelectric material in the piezoelectric layer is different, which affects the growth of the piezoelectric material and causes the growth of the piezoelectric material.
  • the crystal phase of the piezoelectric material is not uniform, and the piezoelectric performance of the piezoelectric material in the piezoelectric layer will be affected. Therefore, the piezoelectric performance of the piezoelectric material in the piezoelectric layer of the ultrasonic transducer prepared by this method is easily affected.
  • one of the technical problems solved by the embodiments of the present application is to provide a method for manufacturing an ultrasonic transducer, an ultrasonic transducer, and an information acquisition element to overcome the defects in the prior art.
  • an embodiment of the present application provides a method for manufacturing an ultrasonic transducer, including:
  • a first electrode layer without patterning treatment is formed on the carrier wafer; a piezoelectric layer is formed on the first surface of the first electrode layer, and the first surface of the first electrode layer is far from the carrier crystal on the first electrode layer. One side of the circle; a second electrode layer is formed on the first surface of the piezoelectric layer, and the second electrode layer is patterned to form a second electrode.
  • the first surface of the piezoelectric layer is far away from the first piezoelectric layer
  • One side of the electrode layer bond the supporting diaphragm layer formed on the first surface of the second electrode with the first surface of the base layer, and remove the carrier wafer, the first surface of the second electrode is on the second The side of the electrode away from the piezoelectric layer; the first electrode layer is patterned to form the first electrode.
  • an embodiment of the present application provides an ultrasonic transducer, which is prepared by using the ultrasonic transducer manufacturing method described in the first aspect.
  • an embodiment of the present application provides an information acquisition element.
  • the information acquisition element includes an ultrasonic transducer array, and the ultrasonic transducer array is an array composed of at least two ultrasonic transducers as described in the second aspect.
  • the piezoelectric layer is formed on the surface of the first electrode layer that has not been patterned, it is ensured that the surface of the piezoelectric layer is flat It reduces the interference factors in the piezoelectric material growth process in the piezoelectric layer, does not affect the growth of the piezoelectric material in the piezoelectric layer, so that the piezoelectric performance of the piezoelectric material in the piezoelectric layer will not be affected;
  • the first electrode layer is patterned, the first electrode layer is not covered by other layers, and when the second electrode layer is patterned, the second electrode layer is also not covered by other layers, which can double-sided electrode layers for the piezoelectric layer.
  • the preparation method of the ultrasonic transducer provided by the embodiments of the present application can ensure the integrity of the piezoelectric structure of the piezoelectric layer and ensure that the piezoelectric performance of the piezoelectric material in the piezoelectric layer will not be affected. All areas of the double-sided electrode layer are patterned.
  • Figure 1 is a schematic longitudinal cross-sectional view of an ultrasonic transducer provided by the related art
  • Figure 2 is a schematic longitudinal cross-sectional view of an ultrasonic transducer provided by the related art
  • FIG. 3 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application
  • Fig. 4 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application;
  • Fig. 5 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application;
  • Fig. 6 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application;
  • Fig. 7 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 8 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 9 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 10 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 11 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 12 is a schematic structural diagram of an ultrasonic transducer provided by an embodiment of the application.
  • FIG. 13 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application
  • FIG. 14 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • 15 is a schematic flowchart of a method for manufacturing an ultrasonic transducer provided by an embodiment of the application.
  • FIG. 16 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 17 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application.
  • FIG. 18 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 19 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application.
  • FIG. 20 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 21 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application.
  • FIG. 22 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 23 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 24 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application.
  • FIG. 25 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 26 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application.
  • FIG. 27 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • Figure 28 is a schematic structural diagram of an ultrasonic transducer in a manufacturing process provided by an embodiment of the application.
  • FIG. 29 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application.
  • FIG. 30 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 31 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application.
  • FIG. 32 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 33 is a schematic flowchart of a method for manufacturing an ultrasonic transducer according to an embodiment of the application.
  • FIG. 34 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • FIG. 35 is a schematic structural diagram of an ultrasonic transducer in a preparation process provided by an embodiment of the application.
  • the ultrasonic transducer is a device that converts sound energy and electrical energy.
  • the ultrasonic transducer usually includes a piezoelectric layer composed of piezoelectric material, a first electrode arranged above the piezoelectric layer, and a first electrode arranged below the piezoelectric layer. Two electrodes.
  • the second electrode layer, the piezoelectric layer, and the first electrode layer stacked from bottom to top are formed first, and the first electrode layer above the piezoelectric layer is patterned to form The first electrode is etched or patterned on the piezoelectric layer, and the second electrode layer is patterned to form the second electrode.
  • Figure 1 is a schematic longitudinal cross-sectional view of an ultrasonic transducer.
  • the area covered by the piezoelectric layer 11 by the first electrode 12 is not patterned.
  • the area of the two electrodes 13 covered by the piezoelectric layer 11 is not patterned.
  • the above-mentioned ultrasonic transducer preparation method cannot pattern all the areas of the double-sided electrode layer of the piezoelectric layer 11, and because the piezoelectric layer 11 is patterned before the second electrode layer is patterned. , The piezoelectric material in the piezoelectric layer 11 is structurally damaged, which affects the integrity of the piezoelectric structure, and causes the ultrasonic performance of the ultrasonic working area of the piezoelectric layer 11 to be affected.
  • the second electrode layer is prepared first, and the second electrode layer is patterned to form the second electrode , Preparing a piezoelectric layer on the second electrode, preparing a first electrode layer on the piezoelectric layer, and patterning the first electrode layer to form the first electrode.
  • Figure 2 is a schematic longitudinal cross-sectional view of an ultrasonic transducer.
  • the piezoelectric layer 23 is prepared on the second electrode 22 that has been patterned. .
  • a seed layer needs to be prepared when the piezoelectric material is grown.
  • the seed layer needs to have a flat, unpatterned surface as the growth substrate, and the surface of the piezoelectric layer 23 has been patterned.
  • the chemical treatment will result in uneven growth of the piezoelectric material surface, affect the growth of the piezoelectric material, and make the piezoelectric material in the formed piezoelectric layer 23 non-uniform, and cause the piezoelectric performance of the piezoelectric material to be affected. Therefore, the piezoelectric performance of the piezoelectric material in the piezoelectric layer 23 of the ultrasonic transducer prepared by the ultrasonic transducer preparation method is easily affected.
  • the first embodiment of the present application provides a method for preparing an ultrasonic transducer, as shown in FIG. 3, which is a schematic flow chart of the method for preparing an ultrasonic transducer provided by an embodiment of the present application
  • the preparation method of the ultrasonic transducer includes:
  • a first electrode layer without patterning treatment is formed on the carrier wafer.
  • FIG. 4 the direction from the carrier wafer 200 to the first electrode layer 2021 is upward, or the orientation of the operation area can also be regarded as the upper direction.
  • FIG. 4 is only an exemplary illustration.
  • the carrier wafer is a structure used to carry the first electrode layer and subsequently formed on the first electrode layer.
  • the material constituting the carrier wafer includes silicon (Si), silicon oxide (SiO 2 ), glass, etc.
  • the embodiments of the present application do not specifically limit the material constituting the carrier wafer, and those skilled in the art can select the material constituting the carrier wafer according to the process platform used.
  • the thickness of the carrier wafer can be in the range of 100um to 1000um.
  • the thickness of the carrier wafer is set by those skilled in the art as required.
  • the material constituting the first electrode layer may include platinum (Pt), gold (Au), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), strontium ruthenate (SrRuO) 3 ) Conductive materials such as lanthanum nickelate (LaNiO 3 ), cerium oxide (CeO 2 ), etc.
  • platinum Pt
  • Au gold
  • Cu copper
  • Al aluminum
  • Ti titanium
  • TiN titanium nitride
  • SrRuO strontium ruthenate
  • Conductive materials such as lanthanum nickelate (LaNiO 3 ), cerium oxide (CeO 2 ), etc.
  • the embodiments of the present application do not specifically limit the materials constituting the first electrode layer, and the materials constituting the first electrode layer and the second electrode layer It can be selected by those skilled in the art according to the preparation process of the first electrode layer and the performance requirements of the ultrasonic transducer.
  • the structure of the first electrode layer may be a single-layer structure composed of one material, or a multi-layer structure composed of multiple materials.
  • the embodiment of the present application does not specifically limit the structure of the first electrode layer.
  • the value range of the thickness of the first electrode layer may be 30 nm to 1 um.
  • the first electrode layer is prepared on the carrier wafer, and the embodiment of the present application does not specifically limit the preparation process of the first electrode layer.
  • the first surface of the first electrode layer is on the side of the first electrode layer away from the carrier wafer.
  • a piezoelectric layer 203 is formed over the first electrode layer 2021.
  • the materials constituting the piezoelectric layer include Lead Zirconate Titanate Piezoelectric Ceramics (PZT) materials, aluminum nitride (AlN), polyvinylidene fluoride (Poly Vinyli Dene Fluoride, PVDF), etc.
  • PZT materials include PZT materials with different zirconium-titanium composition ratios, manganese lead zirconate titanate piezoelectric ceramics PMnZT, etc., in which PMnZT is doped with manganese (Mn) and other materials used to adjust piezoelectric properties.
  • PMnZT manganese lead zirconate titanate piezoelectric ceramics
  • Mn manganese
  • This application is implemented The examples do not specifically limit the material constituting the piezoelectric layer.
  • the piezoelectric layer can be prepared by a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, a coating process, a sol-gel method, etc.
  • the embodiment of this application does not specifically describe the preparation process of the piezoelectric layer limited.
  • the thickness of the piezoelectric layer may range from 200 nm to 3 um.
  • a second electrode layer is formed on the first surface of the piezoelectric layer, and the second electrode layer is patterned to form a second electrode.
  • the first surface of the piezoelectric layer is on the side of the piezoelectric layer away from the first electrode layer.
  • a second electrode layer 2022 is formed on the first surface of the piezoelectric layer 203.
  • the second electrode layer is patterned to form a second electrode 2122.
  • the thickness of the second electrode layer may be 30 nm to 1 um.
  • the second electrode layer can be patterned by photolithography and etching to form the second electrode.
  • the second electrode can also be formed by other processes, which is not limited in this application.
  • the first surface of the second electrode is on the side of the second electrode away from the piezoelectric layer. As shown in FIG. 8, a supporting diaphragm layer 204 and a base layer 205 are formed above the second electrode 2122.
  • the supporting diaphragm layer is made of dielectric material.
  • the supporting diaphragm layer can improve the mechanical strength of the ultrasonic transducer, increase the service life of the ultrasonic transducer, and can also adjust the stiffness of the ultrasonic transducer to enhance the emission of the ultrasonic transducer /Receiving performance, you can also adjust the thickness and neutral plane position of the ultrasonic transducer to adjust the vibration frequency and vibration mode of the ultrasonic transducer.
  • the material constituting the supporting diaphragm layer includes silicon, silicon oxide, silicon nitride, aluminum oxide (Al 2 O2), etc.
  • the structure supporting the diaphragm layer may be a single-layer structure or a multilayer stacked structure.
  • the value range of the thickness of the supporting diaphragm layer may be between 1 um and 10 um. Of course, this is only an exemplary description, and does not mean that the application is limited to this. It should be noted that when the structure supporting the diaphragm layer is a multilayer stack structure, the thickness of each layer in the multilayer stack structure and the specific stack structure can be determined according to the mechanical performance requirements and the ultrasonic performance requirements of the supporting diaphragm layer.
  • the base layer is used to support the diaphragm layer, the second electrode, the piezoelectric layer and the first electrode layer.
  • the material constituting the base layer includes silicon, glass, polyimide (PI), etc.
  • the base layer can also be a printed circuit board (Printed Circuit Board, PCB). Specific restrictions. It should be noted that when the material constituting the base layer is any one of silicon, glass, and polyimide, or the base layer is a printed circuit board, it is prepared according to the ultrasonic transducer preparation method provided in the embodiment of the present application The ultrasonic transducer does not include the corresponding control circuit.
  • the ultrasonic transducer When the substrate layer includes a standard complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) wafer, a thin film transistor (Thin Film Transistor, TFT) substrate, etc., a structure including a control circuit, the ultrasonic transducer provided according to the embodiment of the present application
  • the ultrasonic transducer prepared by the preparation method includes a control circuit, and the ultrasonic transducer can be used as a fingerprint identification integrated unit.
  • the bonding process for bonding the supporting diaphragm layer and the first surface of the base layer can be determined according to the bonding surface of the supporting diaphragm layer and the base layer. For example, when the first surface of the base layer and the side of the supporting diaphragm layer opposite to the first surface of the base layer include regions made of silicon or silicon oxide, a fusion bonding process can be used to support the diaphragm. The layer is bonded to the first surface of the base layer.
  • a hybrid bonding process may be used to bond the supporting diaphragm layer and the first surface of the base layer.
  • the embodiments of the present application do not specifically limit the bonding process. Those skilled in the art can set the bonding process according to the material constituting the bonding surface of the supporting diaphragm layer and the base layer, and the form of the bonding surface of the supporting diaphragm layer and the base layer.
  • the support diaphragm layer prepared above the second electrode and the first surface of the base layer may be bonded and turned over, which may be the support diaphragm prepared above the second electrode.
  • the bonded structure is turned over.
  • the carrier wafer 200 is located on the upper surface of the ultrasonic transducer during the manufacturing process after being turned over .
  • the removal process for removing the carrier wafer can be determined according to the material constituting the carrier wafer.
  • the carrier wafer can be removed by using a polishing process and an etching process (first use the polishing The process grinds the carrier wafer.
  • a polishing process and an etching process first use the polishing The process grinds the carrier wafer.
  • an etching process can be used to remove the remaining carrier wafer.
  • different removal processes can be selected to remove the carrier wafer, and the specific process flow of the removal process is not specifically limited in the embodiment of the present application.
  • a cavity can be provided on the supporting diaphragm layer or the base layer, so that the piezoelectric layer is more likely to deform to the side close to the cavity, and the transmitting/receiving performance of the ultrasonic transducer is enhanced.
  • two specific examples are listed as follows:
  • bonding the supporting diaphragm layer formed on the second surface of the second electrode to the first surface of the base layer and removing the carrier wafer includes:
  • a supporting diaphragm layer is formed on the first surface of the second electrode; a first groove is formed on the supporting diaphragm layer; the supporting diaphragm layer is bonded to the first surface of the base layer to make the supporting diaphragm layer and The base layer forms a cavity at the first groove and removes the carrier wafer.
  • a first groove 2041 is formed on the supporting diaphragm layer 204, and the supporting diaphragm layer 204 and the base layer 205 form a cavity at the first groove 2041.
  • the first groove may be prepared by a photolithography process and an etching process.
  • the depth of the first groove may be in the range of 500 nm to 5 um, and the depth of the first groove can be set by those skilled in the art as required.
  • the first groove may be a through hole or a blind hole.
  • a plurality of ultrasonic transducers prepared according to the ultrasonic transducer preparation method provided in the embodiment of the present application are arranged in the information collection element, and one cavity may be connected to one ultrasonic transducer.
  • one cavity can also correspond to multiple ultrasonic transducers.
  • bonding the supporting diaphragm layer formed on the second surface of the second electrode with the base layer and removing the carrier wafer includes:
  • a supporting diaphragm layer is formed on the first surface of the second electrode; the supporting diaphragm layer is bonded to the first surface of the base layer with the second groove, so that the supporting diaphragm layer and the base layer are in the second A cavity is formed at the groove, and the carrier wafer is removed.
  • the supporting diaphragm layer 204 and the base layer 205 form a cavity at the second groove 2052.
  • the second groove may be prepared by a photolithography process and an etching process.
  • the depth of the second groove may range from 500 nm to 5 um, and the depth of the second groove can be set by those skilled in the art as required.
  • the second groove may be a through hole or a blind hole.
  • a plurality of ultrasonic transducers prepared according to the ultrasonic transducer preparation method provided in the embodiment of the present application are arranged in the information collection element, and one cavity may be connected to one ultrasonic transducer.
  • one cavity can also correspond to multiple ultrasonic transducers.
  • an isolation layer may be formed on the carrier wafer to reduce the removal of the carrier wafer. It is difficult to round, and the first electrode layer is protected by an isolation layer during the process of removing the carrier wafer.
  • forming the first electrode layer without patterning treatment on the carrier wafer includes:
  • An isolation layer is formed on the carrier wafer; a first electrode layer that has not been patterned is formed on the isolation layer.
  • Bonding the supporting diaphragm layer formed on the second surface of the second electrode with the first surface of the base layer and removing the carrier wafer includes:
  • the supporting diaphragm layer is bonded to the first surface of the base layer, and the carrier wafer and the isolation layer are removed.
  • the material constituting the isolation layer is different from the material constituting the carrier wafer, and the material constituting the isolation layer may be silicon oxide, silicon nitride, silicon, or the like.
  • the process of forming the isolation layer may include a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, a coating process, and the like.
  • the thickness of the isolation layer can range from 50 nm to 1 um, and the thickness of the isolation layer can be set by those skilled in the art as required.
  • the process of removing the isolation layer can be determined according to the material constituting the isolation layer. For example, when the material constituting the isolation layer is silicon oxide, hydrofluoric acid may be selected to remove the isolation layer.
  • the horizontal distance between the first electrode and the second electrode is greater than or equal to a preset distance, and the preset distance is greater than zero.
  • the piezoelectric layer vibrates under the influence of mechanical waves.
  • the mechanical wave can be ultrasonic.
  • the deformation caused by the vibration of the piezoelectric layer makes the first electrode and the second electrode located on the two surfaces of the piezoelectric layer.
  • a voltage difference is generated between the two electrodes.
  • the horizontal distance between the first electrode and the second electrode is greater than or equal to the preset distance, so that the voltage difference is larger, the detection is easier, and the sensitivity of the ultrasonic transducer is higher.
  • the process of forming the first electrode is the same as the process of forming the second electrode, and will not be repeated here.
  • the first electrode layer is patterned to form the first electrode 2121.
  • the piezoelectric layer is formed on the surface of the first electrode layer that has not been patterned, the surface of the piezoelectric layer is guaranteed to be flat and the medium pressure of the piezoelectric layer is reduced.
  • Interference factors in the growth process of the electrical material will not affect the growth of the piezoelectric material in the piezoelectric layer, so that the piezoelectric performance of the piezoelectric material in the piezoelectric layer will not be affected; when the first electrode layer is patterned The first electrode layer is not covered by other layers, and when the second electrode layer is patterned, the second electrode layer is also not covered by other layers, so that the entire area of the double-sided electrode layer of the piezoelectric layer can be patterned; The piezoelectric layer is not patterned before the first electrode layer and the second electrode layer are patterned, which will not cause structural damage to the piezoelectric material in the piezoelectric layer, and can ensure the integrity of the piezoelectric structure in the piezoelectric layer sex.
  • the preparation method of the ultrasonic transducer provided by the embodiments of the present application can ensure the integrity of the piezoelectric structure of the piezoelectric layer and ensure that the piezoelectric performance of the piezoelectric material in the piezoelectric layer will not be affected. All areas of the double-sided electrode layer are patterned.
  • the second embodiment of the present application provides a preparation method of the ultrasonic transducer.
  • the preparation method of the ultrasonic transducer described in the second embodiment of the present application is described in the first embodiment
  • steps 306-312 are added. It should be noted that steps 306-312 are not all steps to be performed, but are optional steps on the basis of steps 301-305.
  • the method further includes step 306.
  • the second surface of the first electrode is the side of the first electrode away from the piezoelectric layer.
  • the thickness of the passivation protection layer can range from 300 nm to 2 um.
  • the material constituting the passivation protection layer may include materials such as silicon nitride, silicon oxide, and aluminum oxide.
  • the structure of the passivation protection layer can be a single-component single-layer structure or a multi-component multilayer film structure. The specific structure of the passivation protection layer can be determined by the process platform used.
  • a passivation protection layer 206 is formed on the side of the first electrode 2121 away from the piezoelectric layer 203.
  • the first electrode By forming a passivation protection layer on the second surface of the first electrode, the first electrode can be protected, and the probability of failure of the ultrasonic transducer due to damage to the first electrode can be reduced.
  • the method may further include steps 307-308.
  • a first opening that penetrates the passivation protection layer and reaches the first electrode is formed at a position where the passivation protection layer covers the first electrode.
  • the first opening may be formed by using a photolithography process and an etching process. As shown in FIG. 16, the first opening 2081 penetrates the passivation protection layer 206 and reaches the first electrode 2121.
  • the circuit layer can be composed of metal conductors, conductive metal oxides, such as indium tin oxide (ITO) and other conductors.
  • the metal conductors can be single-component materials such as gold, silver, platinum, aluminum, and copper, or they can be Alloy materials.
  • the process of performing circuit layer deposition may include a physical vapor deposition process, a chemical vapor deposition process, an atomic layer deposition process, a coating process, and the like.
  • the first electrode is connected to the outside through the first opening, and the first electrode can be connected to an external control circuit, which is convenient for the external control circuit to control the first electrode.
  • the method may further include steps 309-310.
  • the second opening may be formed by using a photolithography process and an etching process. As shown in FIG. 18, the second opening 2082 penetrates the passivation protection layer 206 and the piezoelectric layer 203, and reaches the second electrode 2122.
  • the constituent materials of the circuit layer and the process of depositing the circuit layer can refer to step 308, which will not be repeated here.
  • the second electrode is connected to the outside through the second opening, and the second electrode can be connected to an external control circuit, which is convenient for the external control circuit to control the second electrode.
  • the method may further include steps 311-312.
  • a third opening is formed that penetrates the passivation protection layer, the piezoelectric layer, and the electrode that supports the diaphragm layer and reaches the base layer, so that the base layer The first surface of the electrode is exposed in the third opening.
  • the third opening may be formed by using a photolithography process and an etching process. As shown in FIG. 20, the third opening 2083 penetrates the passivation protection layer 206, the piezoelectric layer 203, and the supporting diaphragm layer 204, and reaches the electrode 2051 of the base layer 205, exposing the first surface of the electrode 205 of the base layer 205 In the third opening 2083.
  • the constituent materials of the circuit layer and the process of depositing the circuit layer can refer to step 308, which will not be repeated here.
  • the electrodes of the base layer are connected to the outside through the third opening, and the electrodes of the base layer can be connected to the external control circuit, which facilitates the connection of the external circuit to the circuit in the base layer through the electrodes of the base layer.
  • the first electrode can be connected to the outside through the first opening, the second electrode is connected to the outside through the second opening, and the electrode of the base layer is connected to the outside through the third opening to realize the first electrode ,
  • the second electrode and the electrode of the base layer are respectively connected to the outside, which is convenient for the external control circuit to control the first electrode, the second electrode and the electrode of the base layer. It is also possible to connect the first electrode, the second electrode and the upper surface of the ultrasonic transducer
  • the surface wiring layer is conductive, which is convenient for subsequent circuit wiring design.
  • a passivation protection layer can be prepared, and then the first opening, the second opening and the third opening are formed, and finally the circuit layer deposition and patterning are performed.
  • the first electrode is connected to the outside through the first opening
  • the second electrode is connected to the outside through the second opening
  • the electrode of the base layer is connected to the outside through the third opening.
  • the third embodiment of the application provides a preparation method of the ultrasonic transducer.
  • the described ultrasonic transducer preparation method adds steps 313-320 on the basis of the method described in the first embodiment. It should be noted that steps 313-320 are not all steps to be performed, and they are all in step 301- Optional steps based on 305.
  • the method further includes steps 313-316.
  • a fourth opening extending to the second electrode is formed at a position where the piezoelectric layer does not cover the first electrode, so that the first surface of the second electrode is exposed in the fourth opening.
  • a fourth opening 2084 is formed at a position where the piezoelectric layer 203 does not cover the first electrode 2121, and the first surface of the second electrode 2122 is exposed in the fourth opening 2084.
  • a fifth opening that penetrates the passivation protection layer and communicates with the fourth opening is formed.
  • the fifth opening 2085 penetrates the passivation protection layer 206 and communicates with the fourth opening 2084.
  • a process suitable for drilling on the piezoelectric layer can be used when forming the fourth opening, and a process suitable for drilling on the passivation layer can be used when forming the fifth opening.
  • using different processes for perforating can reduce the difficulty of perforating and improve the accuracy of perforating.
  • the method further includes steps 317-318.
  • a sixth opening that penetrates the passivation protection layer and reaches the first electrode is formed at a position where the passivation protection layer covers the first electrode.
  • the sixth opening 2086 penetrates the passivation protection layer 206 and reaches the first electrode 2121.
  • the second electrode is connected to the outside through the fourth opening and the fifth opening, the first electrode is connected to the outside through the sixth opening, and the first electrode and the second electrode can be controlled by an external control circuit.
  • the method for manufacturing the ultrasonic transducer provided in the third embodiment of the present application is shown in FIG. 26. After steps 301-305, the method further includes steps 319-321.
  • a seventh opening is formed that penetrates the piezoelectric layer and supports the diaphragm layer and reaches the electrode of the base layer, so that the first surface of the electrode of the base layer Exposed in the seventh opening.
  • the seventh opening 2087 penetrates the piezoelectric layer 209 and the supporting diaphragm layer 204 and reaches the electrode 2051 of the base layer 205.
  • the first surface of the electrode 2051 of the base layer 205 is exposed in the seventh opening 2087.
  • a passivation protection layer is formed on the second surface of the first electrode; at a position where the passivation protection layer corresponds to the seventh opening, an eighth opening that penetrates the passivation protection layer and communicates with the seventh opening is formed.
  • the eighth opening 2088 penetrates the passivation protection layer 206 and communicates with the seventh opening 2087.
  • a process suitable for perforating the piezoelectric layer, the supporting diaphragm layer and the base layer can be used.
  • a process suitable for perforating the passivation protection layer can be used. Considering the different materials of the piezoelectric layer, supporting diaphragm layer, base layer and passivation protection layer, the use of different processes for perforation can reduce the difficulty of perforation. Improve the accuracy of punching.
  • the first electrode can be connected to the outside through the sixth opening
  • the second electrode can be connected to the outside through the fourth opening and the fifth opening
  • the electrode of the base layer can be connected to the outside through the seventh opening and the second opening.
  • the eight openings are connected to the outside to realize that the first electrode, the second electrode and the electrode of the base layer are respectively connected to the outside, and the first electrode, the second electrode and the electrode of the base layer can be controlled by the external control circuit.
  • the electrode, the second electrode and the surface wiring layer on the upper surface of the ultrasonic transducer are connected to facilitate subsequent circuit wiring design.
  • a fourth opening and a seventh opening can be formed in the piezoelectric layer, and then a passivation protection layer is formed on the second surface of the first electrode, and a passivation protection layer is formed on the passivation protection layer.
  • the fifth opening, the sixth opening and the eighth opening, and finally the circuit layer deposition and patterning are performed, so that the first electrode is connected to the outside through the sixth opening, and the second electrode is passed through the fourth opening and the fifth opening.
  • the hole is connected to the outside, and the electrode of the base layer is connected to the outside through the seventh opening and the eighth opening.
  • the fourth embodiment of the present application provides a preparation method of the ultrasonic transducer.
  • the preparation method of the ultrasonic transducer described in the fourth embodiment of the present application is described in the first embodiment
  • steps 322-327 are added. It should be noted that steps 322-327 are not all steps to be performed, but are optional steps on the basis of steps 301-305.
  • the method for manufacturing the ultrasonic transducer provided in the fourth embodiment of the present application is shown in FIG. 29. After steps 301-305, the method further includes steps 322-323.
  • a ninth opening is formed that penetrates the base layer, supports the diaphragm layer and the piezoelectric layer, and reaches the first electrode.
  • the process of forming the ninth opening may include a photolithography process and an etching process.
  • the etching method of the etching process may include dry etching, wet etching, and the like.
  • the etching process can be single-step etching or multi-step etching. When the etching process is multi-step etching, different layers can be made to correspond to different etching steps, and different etching steps can be used differently. ⁇ etching method.
  • the ninth opening 2089 penetrates the base layer 205, the supporting diaphragm layer 204 and the piezoelectric layer 203, and reaches the first electrode 2121.
  • the first electrode is connected to the outside through the ninth opening, so that the external circuit can be connected to the first electrode through the trace located on the side of the base layer away from the supporting diaphragm layer, so that the piezoelectric layer is located on the side close to the first electrode
  • the first electrode can be controlled under the premise of ensuring the integrity of the ultrasonic working area of the ultrasonic transducer.
  • the method for manufacturing the ultrasonic transducer provided in the fourth embodiment of the present application is shown in FIG. 31. After steps 301-305, the method further includes steps 324-325.
  • the process of forming the tenth opening may include a photolithography process and an etching process.
  • the etching method of the etching process may include dry etching, wet etching, and the like.
  • the etching process can be single-step etching or multi-step etching. When the etching process is multi-step etching, different layers can be made to correspond to different etching steps, and different etching steps can be used differently. ⁇ etching method.
  • the tenth opening 2180 penetrates the base layer 205 and the supporting diaphragm layer 204, and reaches the second electrode 2122.
  • the second electrode is connected to the outside through the tenth opening, so that the external circuit can be connected to the second electrode through the trace located on the side of the base layer away from the supporting diaphragm layer, so that the piezoelectric layer of the ultrasonic transducer is close to the first There will not be many traces on one side of the electrode during the subsequent packaging process, and the second electrode can be controlled under the premise of ensuring the integrity of the ultrasonic working area of the ultrasonic transducer.
  • the method for manufacturing the ultrasonic transducer provided in the fourth embodiment of the present application is shown in FIG. 33. After steps 301-305, the method further includes steps 326-327.
  • the eleventh opening of the electrode reaching the base layer is formed on the second surface of the base layer, and the second surface of the base layer is on the side of the base layer away from the supporting diaphragm layer.
  • the process of forming the eleventh opening may include a photolithography process and an etching process.
  • the etching method of the etching process may include dry etching, wet etching, and the like.
  • the etching process can be single-step etching or multi-step etching. When the etching process is multi-step etching, different layers can be made to correspond to different etching steps, and different etching steps can be used differently. ⁇ etching method. For example, when the material constituting the base layer is silicon, a standard deep silicon etching process can be used to form the eleventh opening.
  • the eleventh opening 2181 penetrates the base layer 205 to reach the electrode 2051 of the base layer 205.
  • the electrode of the base layer is connected to the outside through the eleventh opening, so that the external circuit can be connected to the electrode of the base layer through the trace on the side of the base layer away from the supporting diaphragm layer, so that the piezoelectric layer is close to the first electrode.
  • the electrodes of the base layer can be controlled under the premise of ensuring the integrity of the ultrasonic working area of the ultrasonic transducer.
  • the first electrode can be connected to the outside through the ninth opening
  • the second electrode can be connected to the outside through the tenth opening
  • the electrode of the base layer can be connected to the outside through the eleventh opening.
  • the first electrode, the second electrode, and the electrode of the base layer are respectively connected to the outside, which is convenient for controlling the first electrode, the second electrode and the electrode of the base layer through an external control circuit, and the first electrode, the second electrode and the base layer
  • the trace on the side away from the supporting diaphragm layer is conductive, which is convenient for subsequent trace design.
  • a hole may be punched in the piezoelectric layer to form the ninth hole, the tenth hole, and the eleventh hole.
  • steps 326-327 in the fourth embodiment can be combined with steps 319-321 in the third embodiment, so that the electrodes of the base layer are connected to the outside through the seventh opening and the eighth opening, and the base The bottom electrode is connected to the outside through the eleventh opening, so that the trace on the side of the piezoelectric layer close to the first electrode can be connected to the electrode of the base layer through the seventh and eighth openings.
  • the electrode can be connected to the outside through the eleventh opening to lead the trace to the side of the base layer away from the supporting diaphragm layer, so that the trace located on the side of the piezoelectric layer close to the first electrode can be led to the base layer far away Support the side of the diaphragm layer so that the side of the piezoelectric layer close to the first electrode will not have many traces in the subsequent packaging process, so as to ensure the integrity of the ultrasonic working area of the ultrasonic transducer.
  • the electrode 2051 of the base layer 205 is connected to the outside through the seventh opening 2087 and the eighth opening 2088, and the electrode 2051 of the base layer 205 is connected to the outside through the eleventh opening 2181.
  • the fifth embodiment of the present application provides an ultrasonic transducer, which adopts any one of the first to fourth embodiments.
  • the preparation method of the ultrasonic transducer is described in the first to fourth embodiments.
  • the sixth embodiment of the present application provides an information collection element that includes an ultrasonic transducer
  • the ultrasonic transducer array is an array composed of at least two ultrasonic transducers as provided in the fifth embodiment.

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Abstract

本申请实施例提供了一种超声换能器制备方法、超声换能器及信息采集元件，超声换能器制备方法包括在载片晶圆上形成未经图形化处理的第一电极层；在第一电极层的第一表面上形成压电层；在压电层的第一表面上形成第二电极层，并对第二电极层进行图形化处理，形成第二电极；将在第二电极的第一表面上形成的支撑振膜层与基底层的第一表面进行键合，并去除载片晶圆；对第一电极层进行图形化处理，以形成第一电极。该方案能够在保证压电层压电结构的完整性以及保证压电层中压电材料的压电性能不会受到影响的前提下，对压电层双面电极层的全部区域进行图形化处理。

Description

超声换能器制备方法、超声换能器及信息采集元件 技术领域
本申请实施例涉及电子信息技术领域，尤其涉及超声换能器制备方法、超声换能器及信息采集元件。
背景技术
超声换能器是将声能和电能互相转换的器件，超声换能器中的压电材料，在发生形变时两端可以产生电压差，在两端有电压差时，压电材料可以发生形变。利用压电材料的这种特性可以实现机械振动和交流电的互相转换。超声换能器通常包括由压电材料构成的压电层、设置在压电层上方的第一电极以及设置在压电层下方的第二电极。
通常情况下在制备超声换能器时，无法对压电层双面电极层的全部区域进行图形化处理，并且容易对压电层中压电材料造成结构破坏。为了能够对压电层双面电极层的全部区域进行图形化处理，在一种超声换能器制备方法中，先制备第二电极层，对第二电极层进行图形化处理以形成第二电极，在第二电极上制备压电层，在压电层上制备第一电极层，对第一电极层进行图形化以形成第一电极。
上述超声换能器制备方法中，由于压电层制备在已经过图形化处理的第二电极上，导致压电层中压电材料的生长表面状况不一，影响压电材料的生长，使生长的压电材料的晶相不均匀，压电层中压电材料的压电性能会受到影响。因此该方法所制备的超声换能器的压电层中压电材料的压电性能容易受到影响。
发明内容
有鉴于此，本申请实施例所解决的技术问题之一在于提供一种超声换能器制备方法、超声换能器及信息采集元件，用以克服现有技术中存在的缺陷。
第一方面，本申请实施例提供一种超声换能器制备方法，包括：
在载片晶圆上形成未经图形化处理的第一电极层；在第一电极层的第一表面上形成压电层，第一电极层的第一表面在第一电极层远离载片晶圆的一侧；在压电层的第一表面上形成第二电极层，并对第二电极层进行图形化处理，形成第二电极，压电层的第一表面在压电层远离第一电极层的一侧；将在第二电 极的第一表面上形成的支撑振膜层与基底层的第一表面进行键合，并去除载片晶圆，第二电极的第一表面在第二电极远离压电层的一侧；对第一电极层进行图形化处理，以形成第一电极。
第二方面，本申请实施例提供一种超声换能器，该超声换能器采用如第一方面所描述的超声换能器制备方法制备。
第三方面，本申请实施例提供一种信息采集元件，信息采集元件包括超声换能器阵列，超声换能器阵列是由至少两个如第二方面所描述的超声换能器组成的阵列。
本申请实施例所提供的超声换能器制备方法、超声换能器及信息采集元件，由于压电层形成于第一电极层上未经过图形化处理的表面，保证压电层的表面是平整的，减少了压电层中压电材料生长过程中的干扰因素，不会影响压电层中压电材料的生长，使压电层中压电材料的压电性能不会受到影响；在对第一电极层进行图形化处理时第一电极层未被其他层覆盖，在对第二电极层进行图形化处理时第二电极层也未被其他层覆盖，能够对压电层双面电极层的全部区域进行图形化处理；在对第一电极层以及第二电极层进行图形化处理前未对压电层进行图形化处理，不会对压电层中压电材料造成结构破坏，能够保证压电层中压电结构的完整性。因此本申请实施例提供的超声换能器制备方法能够在保证压电层压电结构的完整性以及保证压电层中压电材料的压电性能不会受到影响的前提下，对压电层双面电极层的全部区域进行图形化处理。
附图说明
后文将参照附图以示例性而非限制性的方式详细描述本申请实施例的一些具体实施例。附图中相同的附图标记标示了相同或类似的部件或部分。本领域技术人员应该理解，这些附图未必是按比例绘制的。附图中：
图1为相关技术提供的一种超声换能器的示意性纵向剖视图；
图2为相关技术提供的一种超声换能器的示意性纵向剖视图；
图3为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图4为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图5为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图6为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图7为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图8为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图9为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图10为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图11为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图12为本申请实施例提供的一种超声换能器的示意性结构图；
图13为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图14为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图15为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图16为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图17为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图18为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图19为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图20为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图21为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图22为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图23为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图24为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图25为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图26为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图27为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图28为本申请实施例提供的一种制备过程中超声换能器的示意性结构 图；
图29为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图30为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图31为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图32为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图33为本申请实施例提供的一种超声换能器制备方法的示意性流程图；
图34为本申请实施例提供的一种制备过程中超声换能器的示意性结构图；
图35为本申请实施例提供的一种制备过程中超声换能器的示意性结构图。
具体实施方式
为了使本领域的人员更好地理解本申请实施例中的技术方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅是本申请实施例一部分实施例，而不是全部的实施例。基于本申请实施例中的实施例，本领域普通技术人员所获得的所有其他实施例，都应当属于本申请实施例保护的范围。
超声换能器是将声能和电能互相转换的器件，超声换能器通常包括由压电材料构成的压电层、设置在压电层上方的第一电极以及设置在压电层下方的第二电极。
通常情况下，在制备超声换能器时，先形成从下至上层叠设置的第二电极层、压电层以及第一电极层，对压电层上方的第一电极层进行图形化处理以形成第一电极，对压电层进行刻蚀或图形化处理，对第二电极层进行图形化处理以形成第二电极。
在上述超声换能器制备方法中，压电层被第一电极覆盖的部分无法进行刻蚀或图形化处理，压电层另一面的电极层被压电层覆盖的区域无法进行图形化处理。如图1所示，图1为一种超声换能器的示意性纵向剖视图，在所制备的超声换能器中，压电层11被第一电极12覆盖的区域未经图形化处理，第二电极13被压电层11覆盖的区域未经图形化处理。因此上述超声换能器制备方 法无法对压电层11双面电极层的全部区域进行图形化处理，而且由于在对第二电极层进行图形化处理前，对压电层11进行了图形化处理，使压电层11中压电材料受到了结构破坏，影响了压电结构的完整性，导致压电层11超声工作区域的超声性能受到了影响。
为了能够对压电层双面电极层的全部区域进行图形化处理，在一种超声换能器制备方法中，先制备第二电极层，对第二电极层进行图形化处理以形成第二电极，在第二电极上制备压电层，在压电层上制备第一电极层，对第一电极层进行图形化形成第一电极。如图2所示，图2为一种超声换能器的示意性纵向剖视图，在根据上述方法制备的超声换能器中，压电层23制备于已经过图形化处理的第二电极22上。由于压电材料的生长条件较为苛刻，在压电材料生长时需要先制备种子层，种子层需要平整的、未经过图形化处理的表面作为生长衬底，制备压电层23的表面已经过图形化处理，会导致压电材料生长表面状况不一，影响压电材料的生长，使所形成的压电层23中压电材料的晶相不均匀，导致压电材料的压电性能受到影响。因此该超声换能器制备方法所制备的超声换能器的压电层23中压电材料的压电性能容易受到影响。
实施例一
鉴于上述技术方案中的不足，本申请实施例一提供一种超声换能器制备方法，如图3所示，图3为本申请实施例提供的一种超声换能器制备方法的示意性流程图，该超声换能器制备方法包括：
301、在载片晶圆上形成未经图形化处理的第一电极层。
如图4所示，图4中，将从载片晶圆200到第一电极层2021的方向为上方，或者，也可以将操作区域所在的方位作为上方，当然，图4只是示例性说明。
载片晶圆是用于承载第一电极层以及后续形成于第一电极层上的结构，可选地，构成载片晶圆(Carrier Wafer)的材料包括硅(Si)、氧化硅(SiO 2)、玻璃等，本申请实施例对构成载片晶圆的材料不做具体限定，本领域技术人员可以根据所使用的工艺平台选取构成载片晶圆的材料。
载片晶圆的厚度的取值范围可以为100um～1000um。载片晶圆的厚度为本领域技术人员根据需要进行设置。
可选地，构成第一电极层的材料可以包括铂(Pt)、金(Au)、铜(Cu)，铝(Al)，钛(Ti)，氮化钛(TiN)、钌酸锶(SrRuO 3)、镍酸镧(LaNiO 3)、 氧化铈(CeO 2)等导电材料，本申请实施例对构成第一电极层的材料不做具体限定，构成第一电极层以及第二电极层的材料可以由本领域技术人员根据第一电极层的制备工艺、超声换能器的性能需求选取。第一电极层的结构可以是由一种材料构成的单层结构，也可以是由多种材料构成的多层结构，本申请实施例对第一电极层的结构不做具体限定。可选地，第一电极层的厚度的取值范围可以是30nm～1um。
可选地，可以利用物理气相沉积(Physical Vapor Deposition，PVD)工艺、化学气相沉积(Chemical Vapor Deposition，CVD)工艺、原子层沉积(Atomic Layer Deposition，ALD)工艺或涂覆(Coating)工艺等，在载片晶圆上制备第一电极层，本申请实施例对第一电极层的制备工艺不做具体限定。
302、在第一电极层的第一表面上形成压电层。
第一电极层的第一表面在第一电极层远离载片晶圆的一侧。基于图4，如图5所示，在第一电极层2021上方形成压电层203。可选地，构成压电层的材料包括锆钛酸铅压电陶瓷(Lead Zirconate Titanate Piezoelectric Ceramics，PZT)类材料、氮化铝(AlN)，聚偏氟乙烯(Poly Vinyli Dene Fluoride，PVDF)等，其中PZT类材料包括不同锆钛组分配比的PZT材料、锰锆钛酸铅压电陶瓷PMnZT等，其中PMnZT中掺杂了锰(Mn)等用于调节压电性能的材料，本申请实施例对构成压电层的材料不做具体限定。
可选地，可以通过物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、涂覆工艺、溶胶凝胶法等，制备压电层，本申请实施例对压电层的制备工艺不做具体限定。可选地，压电层的厚度的取值范围可以是200nm～3um。
303、在压电层的第一表面上形成第二电极层，并对第二电极层进行图形化处理，形成第二电极。
压电层的第一表面在压电层远离第一电极层的一侧。如图6和图7所示，图6中，在压电层203的第一表面形成第二电极层2022，图7中，对第二电极层进行图形化处理形成第二电极2122。
需要说明的是，第二电极层的制备工艺和材料与第一电极层相同，此处不再赘述。第二电极层的厚度可以是30nm～1um。
可选地，可以通过光刻加刻蚀的方法对第二电极层进行图形化处理，以形成第二电极。当然，此处只是示例性说明，也可以通过其他工艺形成第二电极，本申请对此不做限定。
304、将在第二电极的第一表面上形成的支撑振膜层与基底层的第一表面进行键合，并去除载片晶圆。
第二电极的第一表面在第二电极远离压电层的一侧。如图8所示，第二电极2122的上方形成了支撑振膜层204以及基底层205。
支撑振膜层由介质材料制成，支撑振膜层可以提高超声换能器的机械强度，增加超声换能器的使用寿命，还可以调整超声换能器的刚度，增强超声换能器的发射/接收性能，还可以调整超声换能器的厚度和中性平面位置，以调节超声换能器的振动频率和振动模式。可选地，构成支撑振膜层的材料包括硅、氧化硅、氮化硅、氧化铝(Al 2O2)等，支撑振膜层的结构可以是单层结构，也可以是多层堆叠结构，支撑振膜层的厚度的取值范围可以为1um～10um之间，当然，此处只是示例性说明，并不代表本申请局限于此。需要说明的是，当支撑振膜层的结构为多层堆叠结构时，多层堆叠结构中每一层的厚度以及具体堆叠结构可以根据支撑振膜层的机械性能需求以及超声性能需求来确定。
基底层用于承载支撑振膜层、第二电极、压电层以及第一电极层。构成基底层的材料包括硅、玻璃、聚酰亚胺(Polyimide，PI)等，基底层也可以为印制电路板(Printed Circuit Board，PCB)，本申请实施例对构成基底层的材料不做具体限定。需要说明的是，当构成基底层的材料为硅、玻璃、聚酰亚胺中任一种，或基底层为印制电路板时，根据本申请实施例提供的超声换能器制备方法所制备的超声换能器不包括相应的控制电路。当基底层包括标准互补金属氧化物半导体(Complementary Metal Oxide Semiconductor，CMOS)晶圆，薄膜晶体管(Thin Film Transistor，TFT)基底等包括控制电路的结构时，根据本申请实施例提供的超声换能器制备方法所制备的超声换能器包括控制电路，该超声换能器可以作为指纹识别集成单元。
支撑振膜层与基底层的第一表面进行键合的键合工艺，可以根据支撑振膜层与基底层的键合面情况来确定。例如，当基底层的第一表面以及支撑振膜层与基底层的第一表面相对的一面包括由硅或氧化硅构成的区域时，可以使用融熔键合(Fusion Bonding)工艺对支撑振膜层与基底层的第一表面进行键合。又例如，当基底层的第一表面包括由硅、氧化硅以及金属构成的区域，支撑振膜层与基底层的第一表面相对的一面也包括由硅、氧化硅以及金属构成的区域时，可以使用混合键合(Hybrid Bonding)工艺对支撑振膜层与基底层的第一表面进行键合。本申请实施例对键合工艺不做具体限定。本领域技术人员可以 根据构成支撑振膜层与基底层的键合面的材料、支撑振膜层与基底层的键合面的形态对键合工艺进行设置。
可选地，为了方便去除载片晶圆，可以令第二电极的上方制备的支撑振膜层与基底层的第一表面进行键合并翻面，可以为在第二电极的上方制备的支撑振膜层与基底层的第一表面进行键合后，对键合得到的结构进行翻面，如图9所示，载片晶圆200在翻面后位于制备过程中超声换能器的上表面。
去除载片晶圆的去除工艺可以根据构成载片晶圆的材料确定，例如，当构成载片晶圆的材料为硅时，可以使用研磨工艺配合刻蚀工艺去除载片晶圆(先使用研磨工艺对载片晶圆进行研磨，当载片晶圆的厚度小于一定厚度阈值时，例如小于100nm时，可以使用刻蚀工艺去除剩余的载片晶圆)。构成载片晶圆的材料不相同时，可以选用不同的去除工艺去除载片晶圆，本申请实施例对去除工艺的具体工艺流程不做具体限定。
可选地，可以在支撑振膜层或者基底层上设置空腔，使压电层更容易向靠近空腔的一侧产生形变，增强超声换能器的发射/接收性能。此处，列举两个具体示例进行说明如下：
可选地，在第一个示例中，将在第二电极的第二表面形成的支撑振膜层与基底层的第一表面进行键合，并去除载片晶圆，包括：
在第二电极的第一表面上形成支撑振膜层；在支撑振膜层上形成第一凹槽；将支撑振膜层与基底层的第一表面进行键合，以使得支撑振膜层与基底层在第一凹槽处形成空腔，并去除载片晶圆。如图10所示，支撑振膜层204上形成第一凹槽2041，支撑振膜层204与基底层205在第一凹槽2041处形成空腔。
具体地，第一凹槽可以通过光刻工艺与刻蚀工艺制备。第一凹槽的深度的取值范围可以是500nm～5um，第一凹槽的深度为本领域技术人员根据需要进行设置。第一凹槽可以为通孔或盲孔。
可选的，在本申请的一个实施例中，根据本申请实施例提供的超声换能器制备方法所制备的多个超声换能器设置于信息采集元件中，其中一个空腔可以与一个超声换能器对应，一个空腔也可以与多个超声换能器对应。
可选地，在第二个示例中，将在第二电极的第二表面形成的支撑振膜层与基底层进行键合，并去除载片晶圆，包括：
在第二电极的第一表面上形成支撑振膜层；将支撑振膜层与带有第二凹槽的基底层的第一表面进行键合，以使得支撑振膜层与基底层在第二凹槽处形 成空腔，并去除载片晶圆。如图11所示，支撑振膜层204与基底层205在第二凹槽2052处形成空腔。
具体地，第二凹槽可以通过光刻工艺与刻蚀工艺制备。第二凹槽的深度的取值范围可以是500nm～5um，第二凹槽的深度为本领域技术人员根据需要进行设置。第二凹槽可以为通孔或盲孔。
可选的，在本申请的一个实施例中，根据本申请实施例提供的超声换能器制备方法所制备的多个超声换能器设置于信息采集元件中，其中一个空腔可以与一个超声换能器对应，一个空腔也可以与多个超声换能器对应。
在一种实现方式中，为了便于去除载片晶圆，并且避免第一电极层在去除载片晶圆的过程中受损，可以在载片晶圆上形成隔离层，以降低去除载片晶圆的难度，并且在去除载片晶圆的过程中通过隔离层保护第一电极层。
例如，在载片晶圆上方形成未经图形化处理的第一电极层，包括：
在载片晶圆上形成隔离层；在隔离层上形成未经图形化处理的第一电极层。
将在第二电极的第二表面形成的支撑振膜层与基底层的第一表面进行键合，并去除载片晶圆，包括：
将支撑振膜层与基底层的第一表面进行键合，并去除载片晶圆与隔离层。
其中，构成隔离层的材料与构成载片晶圆的材料不同，构成隔离层的材料可以为氧化硅、氮化硅、硅等。形成隔离层的工艺可以包括物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、涂覆工艺等。隔离层的厚度的取值范围可以是50nm～1um，隔离层的厚度为本领域技术人员根据需要进行设置。去除隔离层的工艺可以根据构成隔离层的材料确定，例如，当构成隔离层的材料为氧化硅时，可以选用氢氟酸去除隔离层。
305、对第一电极层进行图形化处理，以形成第一电极。
可选地，第一电极和第二电极的水平距离大于或等于预设距离，预设距离大于0。
在机械振动的能量转换为电能的过程中，压电层在机械波的影响下振动，机械波可以是超声波，压电层振动所产生的形变使得分别位于压电层两个表面的第一电极和第二电极之间产生电压差。第一电极和第二电极的水平距离大于或等于预设距离，使得电压差更大，易于检测，超声换能器的灵敏度更高。
需要说明的是，形成第一电极的工艺与形成第二电极的工艺相同，此处 不再赘述。如图12所示，对第一电极层进行图形化处理形成第一电极2121。
本申请实施例所提供的超声换能器制备方法，由于压电层形成于第一电极层上未经过图形化处理的表面，保证压电层的表面是平整的，减少了压电层中压电材料生长过程中的干扰因素，不会影响压电层中压电材料的生长，使压电层中压电材料的压电性能不会受到影响；在对第一电极层进行图形化处理时第一电极层未被其他层覆盖，在对第二电极层进行图形化处理时第二电极层也未被其他层覆盖，能够对压电层双面电极层的全部区域进行图形化处理；在对第一电极层以及第二电极层进行图形化处理前未对压电层进行图形化处理，不会对压电层中压电材料造成结构破坏，能够保证压电层中压电结构的完整性。因此本申请实施例提供的超声换能器制备方法能够在保证压电层压电结构的完整性以及保证压电层中压电材料的压电性能不会受到影响的前提下，对压电层双面电极层的全部区域进行图形化处理。
实施例二
基于上述实施例一所描述的超声换能器制备方法，本申请实施例二提供一种超声换能器制备方法，本申请实施例二所描述的超声换能器制备方法在实施例一所描述的方法的基础上，增加步骤306-312，需要说明的是，步骤306-312并不是都要执行的步骤，都是在步骤301-305的基础上可选地步骤。
可选地，如图13所示，本申请实施例二提供的超声换能器制备方法，在步骤301-305之后，该方法还包括步骤306。
306、在第一电极的第二表面形成钝化保护层。
第一电极的第二表面为所述第一电极远离所述压电层的一面。
钝化保护层的厚度的取值范围可以为300nm～2um之间。构成钝化保护层的材料可以包括氮化硅，氧化硅，氧化铝等材料。钝化保护层的结构可以是单组份的单层结构，也可以是多组分的多层膜结构，钝化保护层的具体结构可以所使用的工艺平台确定。
如图14所示，第一电极2121远离压电层203的一面形成钝化保护层206。
通过在第一电极的第二表面形成钝化保护层，可以保护第一电极，降低超声换能器因第一电极受损而出现故障的几率。
可选地，如图15所示，在步骤306之后，该方法还可以包括步骤307-308。
307、在钝化保护层覆盖第一电极的位置上形成贯穿钝化保护层，并到达第一电极的第一开孔。
可以使用光刻工艺加刻蚀工艺形成所述第一开孔。如图16所示，第一开孔2081贯穿钝化保护层206，并到达第一电极2121。
308、在第一开孔处进行线路层沉积和图形化处理，使得第一电极通过第一开孔与外部连接。
线路层可以由金属导体、导电金属氧化物，例如氧化铟锡(Indium Tinoxide，ITO)以及其他导体构成，其中金属导体可以为金，银，铂，铝，铜等单组分材料，也可以为合金材料。进行线路层沉积的工艺可以包括物理气相沉积工艺、化学气相沉积工艺、原子层沉积工艺、涂覆工艺等。第一电极通过第一开孔与外部连接，可以第一电极与外部的控制电路连接，方便外部的控制电路控制第一电极。
可选地，如图17所示，在步骤306之后，该方法还可以包括步骤309-310。
309、在钝化保护层覆盖第二电极且未覆盖第一电极的位置上，形成贯穿钝化保护层和压电层，并到达第二电极的第二开孔。
可以使用光刻工艺加刻蚀工艺形成所述第二开孔。如图18所示，第二开孔2082贯穿钝化保护层206以及压电层203，并到达第二电极2122。
310、在第二开孔处进行线路层沉积和图形化处理，使得第二电极通过第二开孔与外部连接。
线路层的构成材料以及进行线路层沉积的工艺可参照步骤308，在此不再赘述。
第二电极通过第二开孔与外部连接，可以第二电极与外部的控制电路连接，方便外部的控制电路控制第二电极。
可选地，如图19所示，在步骤306之后，该方法还可以包括步骤311-312。
311、在钝化保护层未覆盖第一电极及第二电极的位置上形成贯穿钝化保护层、压电层和支撑振膜层并到达基底层的电极的第三开孔，以使基底层的电极的第一表面暴露在第三开孔内。
可以使用光刻工艺加刻蚀工艺形成所述第三开孔。如图20所示，第三开孔2083贯穿钝化保护层206、压电层203、支撑振膜层204，并到达基底层205的电极2051，使基底层205的电极205的第一表面暴露在第三开孔2083内。
312、在第三开孔处进行线路层沉积和图形化处理，以使得基底层的电极通过第三开孔与外部连接。
线路层的构成材料以及进行线路层沉积的工艺可参照步骤308，在此不 再赘述。
基底层的电极通过第三开孔与外部连接，可以基底层的电极与外部的控制电路连接，方便外部电路通过基底层的电极与基底层中的电路连接。
结合步骤306-312，可以使第一电极通过第一开孔与外部连接，第二电极通过第二开孔与外部连接、基底层的电极通过第三开孔与外部连接，以实现第一电极、第二电极以及基底层的电极分别与外部连接，便于外部的控制电路控制第一电极、第二电极以及基底层的电极，还可以将第一电极、第二电极与超声换能器上表面的表面走线层导通，方便后续电路走线设计。
此处列举一个具体的应用场景进行说明，在该场景中，可以制备钝化保护层，然后形成第一开孔、第二开孔以及第三开孔，最后进行线路层沉积和图形化处理，使第一电极通过第一开孔与外部连接，第二电极通过第二开孔与外部连接、基底层的电极通过第三开孔与外部连接。
需要说明的是，对于不同的层，因为材料不同，可以采用不同的工艺进行打孔，例如，当采用刻蚀的方式进行打孔时，对于不同的层可以采用不同的刻蚀方式(干法刻蚀或湿法刻蚀)、不同的刻蚀化学试剂、不同的刻蚀时间、不同的刻蚀电压或不同的刻蚀功率等，可以是其中的一项或多项不同，本申请对此不做限制。例如，在形成第二开孔时，贯穿钝化保护层所使用的工艺与贯穿压电层所使用的工艺可以不同。
实施例三
基于上述实施例一所描述的超声换能器制备方法，结合本申请实施例二提供的超声换能器制备方法，本申请实施例三提供一种超声换能器制备方法，本申请实施例三所描述的超声换能器制备方法在实施例一所描述的方法的基础上，增加步骤313-320，需要说明的是，步骤313-320并不是都要执行的步骤，都是在步骤301-305的基础上可选地步骤。
可选地，如图21所示，本申请实施例三提供的超声换能器制备方法，在步骤301-305之后，该方法还包括步骤313-316。
313、在压电层未覆盖第一电极的位置上形成延伸至第二电极的第四开孔，以使第二电极的第一表面暴露在第四开孔内。
如图22所示，压电层203未覆盖第一电极2121的位置上形成第四开孔2084，第二电极2122的第一表面暴露在第四开孔2084内。
314、在第一电极的第二表面形成钝化保护层。
315、在钝化保护层与第四开孔对应的位置，形成贯穿钝化保护层，并与第四开孔连通的第五开孔。
如图23所示，第五开孔2085贯穿钝化保护层206与第四开孔2084连通。
316、在第四开孔及第五开孔处进行线路层沉积和图形化处理，使得第二电极通过第四开孔及第五开孔与外部连接。
在不影响第二电极与外部连接的前提下，在形成第四开孔时可以使用适合在压电层上进行打孔的工艺，在形成第五开孔时可以使用适合在钝化保护层上进行打孔的工艺，考虑到压电层以及钝化保护层材料不同，采用不同的工艺进行打孔可以降低打孔的难度，提高打孔的精度。
可选地，本申请实施例三提供的超声换能器制备方法，在第一电极的第一表面形成钝化保护层之后，如图24所示，该方法还包括步骤317-318。
317、在钝化保护层覆盖第一电极的位置上形成贯穿钝化保护层，并到达第一电极的第六开孔。
如图25所示，第六开孔2086贯穿钝化保护层206并到达第一电极2121。
318、在第六开孔处进行线路层沉积和图形化处理，使得第一电极通过第六开孔与外部连接。
第二电极通过第四开孔及第五开孔与外部连接，第一电极通过第六开孔与外部连接，可以通过外部的控制电路控制第一电极与第二电极。
可选地，本申请实施例三提供的超声换能器制备方法，如图26所示，在步骤301-305之后，该方法还包括步骤319-321。
319、在压电层未覆盖第一电极及第二电极的位置上形成贯穿压电层和支撑振膜层并到达基底层的电极的第七开孔，以使基底层的电极的第一表面暴露在第七开孔内。
如图27所示，第七开孔2087贯穿压电层209和支撑振膜层204并到达基底层205的电极2051，基底层205的电极2051的第一表面暴露在第七开孔2087内。
320、在第一电极的第二表面形成钝化保护层；在钝化保护层与第七开孔对应的位置，形成贯穿钝化保护层，并与第七开孔连通的第八开孔。
如图28所示，第八开孔2088贯穿钝化保护层206并与第七开孔2087连通。
321、在第七开孔及第八开孔处进行线路层沉积和图形化处理，使得基底 层的电极通过第七开孔及第八开孔与外部连接。
在不影响基底层的电极与外部连接的前提下，在形成第七开孔时可以使用适合在压电层、支撑振膜层以及基底层上进行打孔的工艺，在形成第八开孔时可以使用适合在钝化保护层上进行打孔的工艺，考虑到压电层、支撑振膜层、基底层以及钝化保护层材料不同，采用不同的工艺进行打孔可以降低打孔的难度，提高打孔的精度。
结合上述步骤313-321，可以使第一电极通过第六开孔与外部连接、第二电极通过第四开孔及第五开孔与外部连接、且基底层的电极通过第七开孔及第八开孔与外部连接，以实现第一电极、第二电极以及基底层的电极分别与外部连接，通过外部的控制电路控制第一电极、第二电极以及基底层的电极，还可以将第一电极、第二电极与超声换能器上表面的表面走线层导通，方便后续电路走线设计。
可选地，在一种具体的应用场景中，可以在压电层形成第四开孔与第七开孔，然后在第一电极的第二表面形成钝化保护层，在钝化保护层形成第五开孔、第六开孔以及第八开孔，最后进行线路层沉积和图形化处理，使第一电极通过第六开孔与外部连接、第二电极通过第四开孔及第五开孔与外部连接、基底层的电极通过第七开孔及第八开孔与外部连接。
实施例四
基于上述实施例一所描述的超声换能器制备方法，本申请实施例四提供一种超声换能器制备方法，本申请实施例四所描述的超声换能器制备方法在实施例一所描述的方法的基础上，增加步骤322-327，需要说明的是，步骤322-327并不是都要执行的步骤，都是在步骤301-305的基础上可选地步骤。
可选地，本申请实施例四提供的超声换能器制备方法，如图29所示，在步骤301-305之后，该方法还包括步骤322-323。
322、在基底层覆盖第一电极，且未覆盖第二电极的位置上，形成贯穿基底层、支撑振膜层和压电层，并到达第一电极的第九开孔。
形成第九开孔的工艺可以包括光刻工艺与刻蚀工艺。刻蚀工艺的刻蚀方式可以包括干法刻蚀、湿法刻蚀等。刻蚀工艺可以是单步刻蚀，也可以是多步刻蚀，其中刻蚀工艺为多步刻蚀时，可以使不同的层分别对应不同的刻蚀步骤，不同的刻蚀步骤分别使用不同的刻蚀方式。
如图30所示，第九开孔2089贯穿基底层205、支撑振膜层204和压电 层203，并到达第一电极2121。
323、在第九开孔处进行线路层沉积和图形化处理，使得第一电极通过第九开孔与外部连接。
第一电极通过第九开孔与外部连接，可以使外部电路能够通过位于基底层远离支撑振膜层的一侧的走线与第一电极连接，使位于压电层靠近第一电极的一侧在后续封装过程中不会出现较多走线，在保证超声换能器的超声工作区域的完整性的前提下，实现对第一电极进行控制。
可选地，本申请实施例四提供的超声换能器制备方法，如图31所示，在步骤301-305之后，该方法还包括步骤324-325。
324、在基底层覆盖第二电极，且未覆盖第一电极的位置上，形成贯穿基底层和支撑振膜层，并到达第二电极的第十开孔。
形成第十开孔的工艺可以包括光刻工艺与刻蚀工艺。刻蚀工艺的刻蚀方式可以包括干法刻蚀、湿法刻蚀等。刻蚀工艺可以是单步刻蚀，也可以是多步刻蚀，其中刻蚀工艺为多步刻蚀时，可以使不同的层分别对应不同的刻蚀步骤，不同的刻蚀步骤分别使用不同的刻蚀方式。
如图32所示，第十开孔2180贯穿基底层205和支撑振膜层204，并到达第二电极2122。
325、在第十开孔处进行线路层沉积和图形化处理，使得第二电极通过第十开孔与外部连接。
第二电极通过第十开孔与外部连接，可以使外部电路能够通过位于基底层远离支撑振膜层的一侧的走线与第二电极连接，使超声换能器的压电层靠近第一电极的一侧在后续封装过程中不会出现较多走线，在保证超声换能器的超声工作区域的完整性的前提下，实现对第二电极进行控制。
可选地，本申请实施例四提供的超声换能器制备方法，如图33所示，在步骤301-305之后，该方法还包括步骤326-327。
326、在基底层的第二表面形成到达基底层的电极的第十一开孔，基底层的第二表面在基底层远离支撑振膜层的一侧。
形成第十一开孔的工艺可以包括光刻工艺与刻蚀工艺。刻蚀工艺的刻蚀方式可以包括干法刻蚀、湿法刻蚀等。刻蚀工艺可以是单步刻蚀，也可以是多步刻蚀，其中刻蚀工艺为多步刻蚀时，可以使不同的层分别对应不同的刻蚀步骤，不同的刻蚀步骤分别使用不同的刻蚀方式。例如，当构成基底层的材料为 硅时，可以使用标准深硅刻蚀工艺形成第十一开孔。
如图34所示，第十一开孔2181贯穿基底层205到达基底层205的电极2051。
327、在第十一开孔处进行线路层沉积和图形化处理，使得基底层的电极通过第十一开孔与外部连接。
基底层的电极通过第十一开孔与外部连接，可以使外部电路能够通过位于基底层远离支撑振膜层的一侧的走线与基底层的电极连接，使压电层靠近第一电极的一侧在后续封装过程中不会出现较多走线，在保证超声换能器的超声工作区域的完整性的前提下，实现对基底层的电极进行控制。
结合上述步骤322-327，可以使第一电极通过第九开孔与外部连接、第二电极通过第十开孔与外部连接、且基底层的电极通过第十一开孔与外部连接，以实现第一电极、第二电极以及基底层的电极分别与外部连接，便于通过外部的控制电路控制第一电极、第二电极以及基底层的电极，还可以将第一电极、第二电极与基底层远离支撑振膜层的一侧的走线导通，方便后续走线设计。
可选地，在一种具体的应用场景中，可以在压电层打孔以形成第九开孔、第十开孔以及第十一开孔。
在一种实现方式中，实施例四中步骤326-327可以与实施例三中的步骤319-321结合，使基底层的电极通过第七开孔及第八开孔与外部连接，并使基底层的电极通过第十一开孔与外部连接，以便于位于压电层靠近第一电极的一侧的走线能够通过第七开孔及第八开孔与基底层的电极连接，基底层的电极通过第十一开孔与外部连接可以将该走线引至基底层远离支撑振膜层的一侧，从而实现将位于压电层靠近第一电极的一侧的走线引至基底层远离支撑振膜层的一侧，使压电层靠近第一电极的一侧在后续封装过程中不会出现较多走线，保证超声换能器的超声工作区域的完整性。如图35所示，基底层205的电极2051通过第七开孔2087及第八开孔2088与外部连接，并且基底层205的电极2051通过第十一开孔2181与外部连接。
实施例五
基于上述实施例一至实施例四所描述的超声换能器制备方法，本申请实施例五提供一种超声换能器，该超声换能器采用实施例一至实施例四中任一个实施例所提供的超声换能器制备方法制备。
实施例六
基于上述实施例一至实施例四所描述的超声换能器制备方法，以及上述实施例五所描述的超声换能器，本申请实施例六提供一种信息采集元件，该信息采集元件包括超声换能器阵列，该超声换能器阵列是由至少两个如实施例五所提供的超声换能器组成的阵列。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于系统实施例而言，由于其基本相似于方法实施例，所以描述的比较简单，相关之处参见方法实施例的部分说明即可。
以上所述仅为本申请实施例而已，并不用于限制本申请。对于本领域技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原理之内所作的任何修改、等同替换、改进等，均应包含在本申请的权利要求范围之内。

Claims (17)

  1. 一种超声换能器制备方法，其特征在于，包括：
    在载片晶圆上形成未经图形化处理的第一电极层；
    在所述第一电极层的第一表面上形成压电层，所述第一电极层的第一表面在所述第一电极层远离所述载片晶圆的一侧；
    在所述压电层的第一表面上形成第二电极层，并对所述第二电极层进行图形化处理，形成第二电极，所述压电层的第一表面在所述压电层远离所述第一电极层的一侧；
    将在所述第二电极的第一表面上形成的支撑振膜层与基底层的第一表面进行键合，并去除所述载片晶圆，所述第二电极的第一表面在所述第二电极远离所述压电层的一侧；
    对所述第一电极层进行图形化处理，以形成第一电极。
  2. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述将在所述第二电极的第二表面形成的支撑振膜层与基底层的第一表面进行键合，并去除所述载片晶圆，包括：
    在所述第二电极的第一表面上形成支撑振膜层；
    在所述支撑振膜层上形成第一凹槽；
    将所述支撑振膜层与所述基底层的第一表面进行键合，以使得所述支撑振膜层与所述基底层在所述第一凹槽处形成空腔，并去除所述载片晶圆。
  3. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述将在所述第二电极的第二表面形成的支撑振膜层与基底层进行键合，并去除所述载片晶圆，包括：
    在所述第二电极的第一表面上形成支撑振膜层；
    将所述支撑振膜层与带有第二凹槽的基底层的第一表面进行键合，以使得所述支撑振膜层与所述基底层在所述第二凹槽处形成空腔，并去除所述载片晶圆。
  4. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述对所述第一电极层进行图形化处理，以形成第一电极之后，所述方法还包括：
    在所述第一电极的第二表面形成钝化保护层。
  5. 根据权利要求4所述的超声换能器制备方法，其特征在于，所述在所述第一电极的第二表面形成钝化保护层之后，所述方法还包括：
    在所述钝化保护层覆盖所述第一电极的位置上形成贯穿所述钝化保护层， 并到达所述第一电极的第一开孔；
    在所述第一开孔处进行线路层沉积和图形化处理，使得所述第一电极通过所述第一开孔与外部连接。
  6. 根据权利要求4所述的超声换能器制备方法，其特征在于，所述在所述第一电极的第二表面形成钝化保护层之后，所述方法还包括：
    在所述钝化保护层覆盖所述第二电极且未覆盖所述第一电极的位置上，形成贯穿所述钝化保护层和所述压电层，并到达所述第二电极的第二开孔；
    在所述第二开孔处进行线路层沉积和图形化处理，使得所述第二电极通过所述第二开孔与外部连接。
  7. 根据权利要求4所述的超声换能器制备方法，其特征在于，所述在所述第一电极的第二表面形成钝化保护层之后，所述方法还包括：
    在所述钝化保护层未覆盖所述第一电极及所述第二电极的位置上形成贯穿所述钝化保护层、所述压电层和所述支撑振膜层并到达所述基底层的电极的第三开孔，以使所述基底层的电极的第一表面暴露在所述第三开孔内；
    在所述第三开孔处进行线路层沉积和图形化处理，以使得所述基底层的电极通过所述第三开孔与外部连接。
  8. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述对所述第一电极层进行图形化处理，以形成第一电极之后，所述方法还包括：
    在所述压电层未覆盖所述第一电极的位置上形成延伸至所述第二电极的第四开孔，以使所述第二电极的第一表面暴露在所述第四开孔内；
    在所述第一电极的第二表面形成钝化保护层，并在所述钝化保护层与所述第四开孔对应的位置，形成贯穿所述钝化保护层，并与所述第四开孔连通的第五开孔；
    在所述第四开孔及所述第五开孔处进行线路层沉积和图形化处理，使得所述第二电极通过所述第四开孔及所述第五开孔与外部连接。
  9. 根据权利要求8所述的超声换能器制备方法，其特征在于，所述在所述第一电极的第二表面形成钝化保护层之后，所述方法还包括：
    在所述钝化保护层覆盖所述第一电极的位置上形成贯穿所述钝化保护层，并到达所述第一电极的第六开孔；
    在所述第六开孔处进行线路层沉积和图形化处理，使得所述第一电极通过所述第六开孔与外部连接。
  10. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述对所述第一电极层进行图形化处理，以形成第一电极之后，所述方法还包括：
    在所述压电层未覆盖所述第一电极及所述第二电极的位置上形成贯穿所述压电层和所述支撑振膜层并到达所述基底层的电极的第七开孔，以使所述基底层的电极的第一表面暴露在所述第七开孔内；
    在所述第一电极的第二表面形成钝化保护层；在所述钝化保护层与所述第七开孔对应的位置，形成贯穿所述钝化保护层，并与所述第七开孔连通的第八开孔；
    在所述第七开孔及所述第八开孔处进行线路层沉积和图形化处理，使得所述基底层的电极通过所述第七开孔及所述第八开孔与外部连接。
  11. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述对所述第一电极层进行图形化处理，以形成第一电极之后，所述方法还包括：
    在所述基底层覆盖所述第一电极，且未覆盖所述第二电极的位置上，形成贯穿所述基底层、所述支撑振膜层和所述压电层，并到达所述第一电极的第九开孔；在所述第九开孔处进行线路层沉积和图形化处理，使得所述第一电极通过所述第九开孔与外部连接。
  12. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述对所述第一电极层进行图形化处理，以形成第一电极之后，所述方法还包括：
    在所述基底层覆盖所述第二电极，且未覆盖所述第一电极的位置上，形成贯穿所述基底层和所述支撑振膜层，并到达所述第二电极的第十开孔；
    在所述第十开孔处进行线路层沉积和图形化处理，使得所述第二电极通过所述第十开孔与外部连接。
  13. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述对所述第一电极层进行图形化处理，以形成第一电极之后，所述方法还包括：
    在所述基底层的第二表面形成到达所述基底层的电极的第十一开孔，所述基底层的第二表面在所述基底层远离所述支撑振膜层的一侧；
    在所述第十一开孔处进行线路层沉积和图形化处理，使得所述基底层的电极通过所述第十一开孔与外部连接。
  14. 根据权利要求1所述的超声换能器制备方法，其特征在于，所述在载片晶圆上方形成未经图形化处理的第一电极层，包括：
    在所述载片晶圆上形成隔离层；
    在所述隔离层上形成未经图形化处理的所述第一电极层；
    所述将在所述第二电极的第二表面形成的支撑振膜层与基底层的第一表面进行键合，并去除所述载片晶圆，包括：
    将所述支撑振膜层与所述基底层的第一表面进行键合，并去除所述载片晶圆与所述隔离层。
  15. 根据权利要求1-14任一项所述的超声换能器制备方法，其特征在于，所述第一电极和所述第二电极的水平距离大于或等于预设距离，所述预设距离大于0。
  16. 一种超声换能器，其特征在于，所述超声换能器采用权利要求1-15中任一项所述的超声换能器制备方法制备。
  17. 一种信息采集元件，其特征在于，所述信息采集元件包括超声换能器阵列，所述超声换能器阵列是由至少两个如权利要求16所述的超声换能器组成的阵列。
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CN101877356A (zh) * 2008-12-18 2010-11-03 株式会社东芝 半导体装置及其制造方法
CN107093994A (zh) * 2017-03-24 2017-08-25 杭州左蓝微电子技术有限公司 薄膜体声波谐振器及其加工方法
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101877356A (zh) * 2008-12-18 2010-11-03 株式会社东芝 半导体装置及其制造方法
CN107093994A (zh) * 2017-03-24 2017-08-25 杭州左蓝微电子技术有限公司 薄膜体声波谐振器及其加工方法
DE102018112705A1 (de) * 2018-05-28 2019-11-28 RF360 Europe GmbH Verfahren zum Herstellen eines akustischen Volumenwellenresonators und akustische Volumenwellenresonatorvorrichtung
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