WO2021244279A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2021244279A1
WO2021244279A1 PCT/CN2021/094383 CN2021094383W WO2021244279A1 WO 2021244279 A1 WO2021244279 A1 WO 2021244279A1 CN 2021094383 W CN2021094383 W CN 2021094383W WO 2021244279 A1 WO2021244279 A1 WO 2021244279A1
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WIPO (PCT)
Prior art keywords
wire
display panel
pixel
wires
display area
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Application number
PCT/CN2021/094383
Other languages
English (en)
French (fr)
Inventor
黄耀
黄炜赟
龙跃
王彬艳
杨国波
王本莲
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to EP21818977.7A priority Critical patent/EP4106001A4/en
Priority to JP2022533191A priority patent/JP2023529038A/ja
Priority to US17/760,461 priority patent/US20230091142A1/en
Publication of WO2021244279A1 publication Critical patent/WO2021244279A1/zh
Priority to US17/936,533 priority patent/US20240114731A1/en
Priority to US18/166,874 priority patent/US20230189596A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0266—Details of the structure or mounting of specific components for a display module assembly
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/123—Connection of the pixel electrodes to the thin film transistors [TFT]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/02—Constructional features of telephone sets
    • H04M1/0202—Portable telephone sets, e.g. cordless phones, mobile phones or bar type handsets
    • H04M1/026—Details of the structure or mounting of specific components
    • H04M1/0264—Details of the structure or mounting of specific components for a camera module assembly
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/30—Devices specially adapted for multicolour light emission
    • H10K59/35—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels
    • H10K59/351—Devices specially adapted for multicolour light emission comprising red-green-blue [RGB] subpixels comprising more than three subpixels, e.g. red-green-blue-white [RGBW]

Definitions

  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • the display panel usually includes a high pixel density (Pixels Per Inch, PPI) area and a low PPI area.
  • PPI Pixel Density
  • the light transmittance of the usual display panel in the low PPI area is low, which is not conducive to improving the camera’s performance.
  • the display effect of the imaging area is not conducive to improving the camera’s performance.
  • At least one embodiment of the present disclosure relates to a display panel and a display device.
  • At least one embodiment of the present disclosure provides a display panel including: a first display area; a second display area located at least on one side of the first display area; a plurality of pixel units located in the first display area and In the second display area, the density of pixel units in the first display area is less than the density of pixel units in the second display area, and the pixel units include pixel circuits; and a first power supply line configured to The pixel circuit provides a first voltage signal; the first power line includes a plurality of first wires, a plurality of second wires, and a plurality of third wires, and the first wires extend from the second display area to the In the first display area, the plurality of second wires are located in the first display area and between adjacent first wires, the second wires extend in a first direction, and the third wires extend in a second direction Extending, the first direction intersects the second direction, the third wire extends from the second display area to the first display area, and adjacent second wires are spaced apart from each other along the
  • the plurality of second conductive lines are sequentially arranged along the first direction.
  • the adjacent second wires are not directly connected.
  • the length of the portion of the first wire located in the first display area in the first direction is greater than the length of the second wire in the first direction. length.
  • the first wire includes portions located in different layers, and the portions located in the different layers are connected by via holes penetrating the insulating layer.
  • the first power cord further includes a fourth wire, the fourth wire extends along the second direction, and the second wire is connected to The length of the first wire and the fourth wire in the second direction is less than or equal to the length of the third wire in the second direction.
  • a display panel provided according to some embodiments of the present disclosure includes a plurality of fourth wires, the plurality of fourth wires are located between adjacent third wires, and the plurality of fourth wires are arranged in sequence along the second direction , Adjacent fourth wires are spaced apart from each other in the second direction.
  • a part of the first wire and the third wire are located on the same layer, and the fourth wire and the third wire are located on the same layer.
  • the pixel units located in the first display area constitute a plurality of pixel islands
  • the pixel islands include at least two pixel units located in two adjacent rows
  • the first wire And the second conductive line respectively overlap with two pixel units located in the two adjacent rows.
  • the pixel unit further includes a light-emitting element
  • the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, and the first transistor is connected to the second transistor.
  • Two transistors are connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected by a conductive portion
  • the second wire further includes A connecting arm, the connecting arm and the conductive portion of a pixel unit overlapping the second wire in the pixel island are spaced apart from each other in the third direction and partially overlapped in the third direction, the The third direction is perpendicular to the first direction and perpendicular to the second direction.
  • the shape of the connecting arm includes a C shape.
  • the first conductive line has a branch, and the conductive portion of a pixel unit that overlaps the first conductive line in the pixel island is in the pixel island.
  • the third directions are spaced apart from each other and partially overlap in the third direction.
  • the first direction is perpendicular to the second direction.
  • the first power cord further includes a fifth wire extending along the first direction, and the fifth wire is located in the second display area, The fifth wire is located between adjacent first wires, and the fifth wire and the second wire adjacent to the fifth wire are spaced apart from each other along the first direction.
  • the display panel further includes an initialization signal line configured to provide an initialization signal to the pixel circuit, and the second wire is part of the initialization signal line. surround.
  • the first wire includes a first portion and a second portion, the first portion of the first wire and the second wire are located on the same layer, and the first wire of the first wire The two parts are not on the same layer as the second wire, and the first part of the first wire is surrounded by a part of the initialization signal wire.
  • the first portion of the first wire has a first sub-portion extending in the first direction and a second sub-portion extending in the second direction, so The second sub-portion has a branch, and the branch extends along the first direction.
  • the length of the branch in the first direction is smaller than the length of the first sub-part in the first direction.
  • the pixel unit further includes a light-emitting element
  • the pixel circuit includes a first transistor and a second transistor, the first transistor is connected to the second transistor, and the first transistor is connected to the second transistor.
  • Two transistors are connected to the light-emitting element, the first transistor includes a first channel and a second channel, the first channel and the second channel are connected by a conductive portion, and the branch is connected to the pixel
  • the conductive portions of a pixel unit in the island that overlap the first conductive line are spaced apart from each other in the third direction, and partially overlap in the third direction, and the third direction is perpendicular to the first Direction, and perpendicular to the second direction.
  • the second wire further includes a connecting arm, and the connecting arm is connected to the conductive portion of a pixel unit in the pixel island that overlaps the second wire Spaced apart from each other in the third direction, and partially overlapped in the third direction.
  • the display panel further includes a base substrate and a data line
  • the data line is configured to provide a data signal to the pixel circuit
  • the data line includes a first data line, wherein The first data line extends from the first display area to the second display area, and the first data line overlaps the orthographic projection of the third wire on the base substrate.
  • the first data line includes a first part and a second part, the first part of the first data line overlaps the third wire part, and the second The second part of a data line and the third conductive line do not overlap, and the first part of the first data line and the second part of the first data line are respectively located in different layers.
  • the display panel provided by some embodiments of the present disclosure, there is a light-transmitting area between adjacent pixel islands, and the first part of the first data line is located between the adjacent pixel islands.
  • two first data lines are provided, and the two first data lines are respectively connected to two adjacent columns of pixel units, and the two first data lines are connected to the same first data line.
  • the orthographic projections of the three wires on the base substrate overlap.
  • the display panel further includes a gate line configured to provide a scan signal to a row of pixel units, the gate line includes a first gate line, and the first gate line Extending from the second display area to the first display area, the light-transmitting area is surrounded by two adjacent first gate lines and two adjacent first data lines.
  • Some embodiments of the present disclosure also provide a display device including any of the above-mentioned display panels.
  • FIGS. 1A to 1C are schematic diagrams of display panels provided by some embodiments of the present disclosure.
  • FIG. 2 is a schematic diagram of a second display area of a display panel provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic diagram of a first display area of a display panel provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a pixel unit in a display panel and a signal line that provides signals for the pixel unit according to an embodiment of the present disclosure
  • Figure 5 is a schematic diagram of a display panel
  • 6A to 6E are schematic diagrams of display panels provided by some embodiments of the present disclosure.
  • FIG. 7A is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a plan view of a semiconductor pattern in a display panel provided by an embodiment of the present disclosure.
  • FIG. 10 is a plan view of a first conductive pattern layer in a display panel provided by an embodiment of the present disclosure
  • FIG. 11 is a plan view of a second conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a plan view of a first insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 13 is a plan view of a third conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a plan view of a second insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a plan view of a pixel electrode layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 16 is a plan view of a pixel definition layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 17 is a schematic diagram of forming an active layer of a thin film transistor in a display panel according to an embodiment of the present disclosure
  • FIG. 18 is a schematic plan view of a display panel after forming a second conductive pattern layer and a first insulating layer in an embodiment of the present disclosure
  • FIG. 19 is a schematic plan view of a display panel after forming a third conductive pattern layer according to an embodiment of the present disclosure
  • FIG. 20 is a schematic plan view after forming a second insulating layer in a display panel provided by an embodiment of the present disclosure
  • FIG. 21 is a schematic plan view of a display panel after forming a pixel electrode layer according to an embodiment of the present disclosure
  • FIG. 22 is a schematic plan view of a display panel after forming pixel definitions according to an embodiment of the present disclosure
  • FIG. 23 is a schematic plan view of adjacent pixel islands in a second direction in a first display area of a display panel according to an embodiment of the present disclosure
  • FIG. 24 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 25 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • the first power line adopts a mesh structure.
  • the display panel provided by the embodiments of the present disclosure optimizes the signal line in the low PPI area to achieve higher transmittance, for example, The embodiment of the present disclosure optimizes the horizontal and vertical wires of the first power cord in the form of a mesh.
  • FIGS. 1A to 1C are schematic diagrams of display panels provided by some embodiments of the present disclosure.
  • the display panel includes a first display area R1 and a second display area R2.
  • the first display area R1 is a high pixel density (Pixels Per Inch, PPI) area
  • the second display area R2 is a low PPI area.
  • the second display area R2 is a partial light-transmitting area.
  • the second display area R2 is located at least on one side of the first display area R1.
  • the display panel shown in FIGS. 1A and 1B further includes a third region R3.
  • a sensor such as a camera may be arranged in the first display area R1 (as shown in FIG.
  • the third region R3 shown in FIGS. 1A and 1B may be a hole-digging region, that is, the material at the position corresponding to the third region R3 is removed to form a through hole.
  • the sensor can receive ambient light. Taking the sensor as the camera as an example, the under-screen camera is realized, so that when the screen is used normally, the first display area corresponding to the sensor can display the picture normally, and when the camera is shooting, the first display area can transmit ambient light, supporting normal usage of.
  • the sensor is provided on the non-display side of the display panel.
  • the sensor can also be called an under-screen device.
  • FIG. 1A also shows a plurality of gate lines 113 and a plurality of data lines 313.
  • the plurality of gate lines 113 include a first gate line GL1, and the plurality of data lines 313 include a first data line DL1.
  • the first gate line GL1 extends from the second display area R2 to the first display area R1.
  • the first data line DL1 extends from the first display area R1 to the second display area R2.
  • a certain element extending from the first display area R1 to the second display area R2 can be understood as the element located in the first display area R1 and the second display area R2, or it can be said that a certain element extends from the first display area R1 and the second display area R2.
  • the second display area R2 extends to the first display area R1.
  • FIG. 1A schematically shows several gate lines 113 and several data lines 313, and the number of gate lines 113 and data lines 313 can be determined according to needs.
  • the plurality of gate lines 113 and the plurality of data lines 313 cross each other and are insulated from each other.
  • FIG. 2 is a schematic diagram of a second display area of a display panel provided by an embodiment of the present disclosure.
  • FIG. 3 is a schematic diagram of a first display area of a display panel provided by an embodiment of the present disclosure.
  • the display panel includes a plurality of pixel units P0, and the plurality of pixel units P0 includes a first pixel unit 101, a second pixel unit 102, a third pixel unit 103, and a fourth pixel unit 104.
  • One first pixel unit 101, one second pixel unit 102, one third pixel unit 103, and one fourth pixel unit 104 constitute a pixel group P1.
  • a pixel group P1 includes two pixels.
  • a first pixel unit 101 and a second pixel unit 102 constitute a pixel
  • a third pixel unit 103 and a fourth pixel unit 104 constitute a pixel.
  • One pixel group P1 forms two virtual pixels to improve the display effect.
  • a pixel group P1 is a repeating unit arranged in an array in the second display area R2.
  • one pixel group P1 is called a pixel island A1.
  • the first display area R1 includes a plurality of light-transmitting areas R0; the light-transmitting area R0 is located between adjacent pixel islands A1.
  • the light-transmitting area R0 can transmit ambient light.
  • the light-transmitting area R0 may include a base substrate and a transparent insulating layer on the base substrate, and the light-transmitting area R0 does not have a light shielding structure, for example, does not have a metal wiring.
  • the light-transmitting area R0 is located in the area surrounded by four adjacent pixel islands A1, but it is not limited to this. For example, as shown in FIG. 3, adjacent pixel islands A1 are arranged at intervals.
  • the first pixel unit 101 is a red pixel unit
  • the second pixel unit 102 is a green pixel unit
  • the third pixel unit 103 is a blue pixel unit
  • the fourth pixel unit 104 is a green pixel unit as an example.
  • the pixel group may also use pixel units of other colors.
  • the arrangement of the multiple pixel units P0 in the display panel is not limited to those shown in FIGS. 2 and 3.
  • a plurality of pixel units P0 are located in the first display area R1 and the second display area R2, and the density of the pixel units in the first display area R1 is less than the density of the pixel units in the second display area R2.
  • the density of pixels in the first display area R1 is less than the density of pixels in the second display area R2.
  • the density of the pixel units in the first display area R1 shown in FIG. 3 is one quarter of the density of the pixel units in the second display area R2. That is, the density of pixels in the first display region R1 shown in FIG. 3 is one-fourth of the density of pixels in the second display region R2.
  • the arrangement of the light-transmitting area R0 and the pixel units in the first display area R1 is not limited to that shown in FIG. 3, and can be set as required.
  • the density of the pixel units in the first display area R1 is one-half, one-third, one-sixth, or eighth of the density of the pixel units in the second display area R2.
  • One grade is different from other values of one quarter.
  • the display panel further includes gate lines 113 and data lines 313.
  • the gate line 113 and the data line 313 are insulated from each other.
  • Each gate line 113 is connected to a row of pixel units, and each data line 313 is connected to a column of pixel units.
  • the gate line 113 is configured to provide a scan signal to a row of pixel units.
  • the data line 313 includes a first data line DL1.
  • the first data line DL1 is located at least in the first display area R1.
  • the first data line DL1 extends from the first display area R1 to the second display area R2.
  • the gate line includes a first gate line GL1, and the first gate line GL1 extends from the second display region R2 to the first display region R1.
  • the light-transmitting area R0 is surrounded by two adjacent first gate lines GL1 and two adjacent first data lines DL1, but is not limited thereto.
  • FIG. 4 is a schematic diagram of a pixel unit in a display panel and a signal line that provides a signal for the pixel unit according to an embodiment of the present disclosure.
  • the display panel includes a plurality of pixel units P0.
  • Each pixel unit P0 includes a light-emitting element EMC and a pixel circuit 10 that provides a driving current for the light-emitting element EMC.
  • the light-emitting element EMC may be an electroluminescent element, for example,
  • the organic electroluminescence element for example, may be an organic light emitting diode (OLED).
  • the display panel further includes an initialization signal line 210, a light emission control signal line 110, a data line 313, a first power line 311, and a second power line 312.
  • the gate line 113 is configured to provide the scan signal SCAN to the pixel circuit 10.
  • the emission control signal line 110 is configured to provide an emission control signal EM to the pixel unit P0.
  • the data line 313 is configured to provide a data signal DATA to the pixel circuit 10
  • the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10
  • the second power line 312 is configured to provide a constant voltage signal to the pixel circuit 10.
  • the second voltage signal ELVSS is greater than the second voltage signal ELVSS, and the first voltage signal ELVDD is greater than the second voltage signal ELVSS.
  • the initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10.
  • the initialization signal Vint is a constant voltage signal, and its magnitude may be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto. For example, the initialization signal Vint may be less than or equal to the second voltage signal ELVSS.
  • the pixel circuit 10 outputs a driving current under the control of the scan signal SCAN, the data signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, the light emission control signal EM and other signals to drive the light emitting element EMC to emit light.
  • the light-emitting element EMC includes a pixel electrode E1 and a common electrode E2.
  • the pixel electrode E1 is connected to the pixel circuit 10, and the common electrode E2 is connected to the second power line 312.
  • Fig. 5 is a schematic diagram of a display panel. As shown in FIG. 5, whether in the first display area R1 or the second display area R2, the first power line 3110 adopts a mesh structure, and the lateral part of the first power line 3110 is directly connected, and the first power line 3110 The vertical parts are directly connected. However, the wiring method of the first power supply line with the mesh structure makes the light transmittance of the first display region R1 low.
  • the first power line 311 includes a plurality of first wires L1, a plurality of second wires L2, and a plurality of third wires L3, and the first wires L1 extend from the second display area R2 to the first In the display area R1, a plurality of second conductive lines L2 are located in the first display area R1 and between adjacent first conductive lines L1.
  • Each second conductive line L2 extends along the first direction D1, and the third conductive line L3 is at least located in the first display area.
  • the area R1 for example, the third wire L3 extends from the second display area R2 to the first display area R1, the third wire L3 extends along the second direction D2, the first direction D1 intersects the second direction D2, and is adjacent to the second
  • the wires L2 are spaced apart from each other along the first direction D1, and the second wire L2 is connected to the first wire L1 through the third wire L3.
  • the first direction D1 is perpendicular to the second direction D2, but it is not limited thereto.
  • the first conductive line L1 extends along the first direction D1.
  • the second wire L2 is only located in the first display area R1.
  • the element extending along a certain direction is not necessarily a straight line, but may also have a curved or broken line part.
  • the extension direction of a certain element refers to the general extension trend of the element, for example, the element Each part of does not necessarily extend in this direction.
  • the display panel provided by the embodiment of the present disclosure adjusts the structure of the first power line in the first display area, which is equivalent to removing part of the first power line arranged along the second direction in the common display panel, which simplifies the configuration of the first display area.
  • the first power line improves the light transmittance of the first display area.
  • the first wire L1 and the second wire L2 are respectively connected to two adjacent rows of pixel units in a pixel island A1, but it is not limited to this.
  • the pixel island A1 It may also include more than two rows of pixel units.
  • the pixel island A1 includes at least two pixel units located in two adjacent rows, and the first wire L1 and the second wire L2 overlap with the two pixel units located in two adjacent rows, respectively. .
  • the first wire L1 overlaps the first pixel unit 101
  • the second wire L2 overlaps the third pixel unit 103.
  • the first wire L1 also overlaps the second pixel unit 102
  • the second wire L2 also overlaps the fourth pixel unit 104.
  • a plurality of second conductive lines L2 are sequentially arranged along the first direction D1.
  • adjacent second conductive lines L2 are not directly connected, and a plurality of second conductive lines L2 that are not directly connected are formed by removing part of the first power line arranged along the first direction.
  • the length of the portion of the first wire L1 located in the first display area R1 in the first direction D1 is greater than the length of the second wire L2 in the first direction D1. The length in the first direction D1.
  • the first power line 311 further includes a fourth wire L4, the fourth wire L4 extends along the second direction D2, and the second wire L2 is connected to the first wire L1 through the fourth wire L4,
  • the length of the fourth wire L4 in the second direction D2 is less than or equal to the length of the third wire L3 in the second direction D2.
  • the length of the fourth wire L4 in the second direction D2 is smaller than the length of the third wire L3 in the second direction D2.
  • the length of the fourth wire L4 in the second direction D2 is equal to the length of the third wire L3 in the second direction D2.
  • a plurality of fourth conductive lines L4 are provided, and the plurality of fourth conductive lines L4 are arranged in sequence along the second direction D2, and are adjacent to the fourth conductive line L4.
  • the wires L4 are spaced apart from each other in the second direction D2.
  • a plurality of fourth wires L41 are located between the third wire L31 and the third wire L32, and the third wire L31 and the third wire L32 are adjacent third wires L3.
  • FIG. 6A shows three fourth conductive lines L41, but the number of fourth conductive lines L4 located between adjacent third conductive lines L3 is not limited to that shown in the figure, and can be determined according to needs. Because the multiple fourth wires L4 are spaced apart from each other in the second direction D2, it is equivalent to removing part of the first power line in the common display panel that is arranged along the second direction, thereby reducing wiring, optimizing the wiring space, and improving The transmittance of light.
  • the first power line 311 further includes a fifth wire L5, the fifth wire L5 extends along the first direction D1, the fifth wire L5 is located in the second display area R2, and the fifth wire L5 is located in Between adjacent first conductive lines L1, the fifth conductive line L5 and the second conductive line L2 adjacent thereto are spaced apart from each other along the first direction D1. Therefore, at the boundary position of the first display area and the second display area, the wiring is reduced, and the light transmittance is improved.
  • each pixel island includes two rows and three columns of pixel units.
  • the number of pixel units included in each pixel island and the arrangement of the pixel units are not limited. As long as the number of pixel units included in each pixel island is greater than or equal to two rows, the present invention can be used.
  • the arrangement of the first power cord provided by the disclosed embodiment.
  • the first power line 311 further includes a plurality of sixth wires L6, the sixth wires L6 are located in the second display area R2, and the sixth wires L6 extend along the second direction D2.
  • a plurality of fifth wires L5 and a plurality of sixth wires L6 are intersectedly arranged.
  • the fifth wire L5 and the sixth wire L6 are both located only in the second display area R2.
  • FIG. 7A is a schematic diagram of a display panel provided by an embodiment of the present disclosure.
  • the same gate line 113 connects the pixel units located in the second display area on both sides of the first display area R1 and the pixel units located in the first display area R1 to form a row of pixel units.
  • the embodiment of the present disclosure does not limit the form of the first wire, as long as it can extend from the second display area R2 to the first display area R1.
  • the first power line in FIG. 7A can also be replaced with the first power line in other embodiments of the present disclosure.
  • the extending manner of the gate line 113 is not limited to that shown in FIG. 7A, as long as the arrangement of the gate line 113 can connect the pixels in the second display region R2 and the pixels in the first display region R1.
  • FIG. 7B is a schematic diagram of a display panel provided by an embodiment of the present disclosure. Compared with the display panel shown in FIG. 7A, the display panel shown in FIG. 7B has adjusted the position of the partial gate lines in the first display area. That is, in the display panel shown in FIG. 7B, one gate line is respectively provided above and below the pixel island. In the display panel shown in FIG. 7A, two gate lines are provided under the pixel island.
  • FIGS. 6A to 6E, FIGS. 7A and 7B take as examples that the second wire is connected to one of the two adjacent first wires, but is not directly connected to the other.
  • the fourth wire is in contact with one of the two adjacent first wires, for example, through a via hole penetrating the insulating layer.
  • a row of pixel units are pixel units connected to the same gate line 113
  • a column of pixel units are pixel units connected to the same data line 313.
  • the first wire L1, the second wire L2, and the fifth wire L5 all extend in the row direction
  • the third wire L3, the fourth wire L4, and the sixth wire L6 extend in the column direction as an example To explain, but not limited to this.
  • the first wire L1, the second wire L2, and the fifth wire L5 may all extend in the column direction
  • the third wire L3, the fourth wire L4, and the sixth wire L6 may extend in the row direction.
  • Ground, the second direction D2 and the first direction D1 also replace each other.
  • the pixel island may also include three rows or more than three rows of pixel units.
  • the above-mentioned multiple second conductive lines may It is understood as the second wire connected to the pixel unit in the same row.
  • the plurality of second wires described above The wire can be understood as a second wire connected to the pixel unit of the same column.
  • FIGS. 8 to 25 take the pixel circuit of 7T1C as an example for description.
  • FIG. 8 is a schematic diagram of a pixel circuit of a display panel provided by an embodiment of the present disclosure.
  • FIG. 9 is a plan view of a semiconductor pattern in a display panel provided by an embodiment of the disclosure.
  • FIG. 10 is a plan view of a first conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 11 is a plan view of a second conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 12 is a plan view of a first insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 13 is a plan view of a third conductive pattern layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 14 is a plan view of a second insulating layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 15 is a plan view of a pixel electrode layer in a display panel provided by an embodiment of the present disclosure.
  • FIG. 16 is a plan view of a pixel definition layer in a display panel provided by an embodiment of the disclosure.
  • FIG. 17 is a schematic diagram of forming an active layer of a thin film transistor in a display panel provided by an embodiment of the present disclosure.
  • FIG. 18 is a schematic plan view of a display panel after forming a second conductive pattern layer and a first insulating layer in an embodiment of the present disclosure.
  • FIG. 19 is a schematic plan view of a display panel after forming a third conductive pattern layer according to an embodiment of the present disclosure.
  • FIG. 20 is a schematic plan view after forming a second insulating layer in a display panel according to an embodiment of the present disclosure.
  • FIG. 21 is a schematic plan view of a display panel after forming a pixel electrode layer according to an embodiment of the present disclosure.
  • FIG. 22 is a schematic plan view of a display panel after forming pixel definitions according to an embodiment of the present disclosure.
  • FIG. 23 is a schematic plan view of adjacent pixel islands in a second direction in a first display area of a display panel according to an embodiment of the present disclosure.
  • FIG. 24 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • FIG. 25 is a schematic cross-sectional view of a display panel provided by an embodiment of the present disclosure.
  • the insulating layer is shown in the form of via holes in the plan view, and the insulating layer itself is transparent.
  • the gate line 113 is configured to provide the scan signal SCAN to the pixel circuit 10.
  • the emission control signal line 110 is configured to provide an emission control signal EM to the pixel unit P0.
  • the data line 313 is configured to provide a data signal DATA to the pixel circuit 10
  • the first power line 311 is configured to provide a constant first voltage signal ELVDD to the pixel circuit 10
  • the second power line 312 is configured to provide a constant voltage signal to the pixel circuit 10.
  • the second voltage signal ELVSS is greater than the second voltage signal ELVSS
  • the first voltage signal ELVDD is greater than the second voltage signal ELVSS.
  • the initialization signal line 210 is configured to provide an initialization signal Vint to the pixel circuit 10.
  • the initialization signal Vint is a constant voltage signal, and its magnitude may be between the first voltage signal ELVDD and the second voltage signal ELVSS, but is not limited thereto.
  • the initialization signal Vint may be less than or equal to the second voltage signal ELVSS.
  • the pixel circuit outputs a driving current to drive the light-emitting element 20 to emit light under the control of the scan signal SCAN, the data signal DATA, the initialization signal Vint, the first voltage signal ELVDD, the second voltage signal ELVSS, and the light emission control signal EM.
  • the light-emitting element 20 emits red light, green light, blue light, or white light under the driving of its corresponding pixel circuit 10.
  • the pixel circuit 10 includes a driving transistor T1, a data writing transistor T2, a threshold compensation transistor T3, a first light emission control transistor T4, a second light emission control transistor T5, a first reset transistor T6, and a second reset transistor T7 and storage capacitor C1.
  • the driving transistor T1 is electrically connected to the light-emitting element 20, and outputs a driving current to drive the light-emitting element 20 to emit light under the control of the scan signal SCAN, the data signal DATA, the first voltage signal ELVDD, and the second voltage signal ELVSS.
  • the display panel provided by the embodiment of the present disclosure further includes: a data driving circuit and a scan driving circuit.
  • the data driving circuit is configured to provide a data signal DATA to the pixel unit P0 according to an instruction of the control circuit;
  • the scan driving circuit is configured to provide a light emission control signal EM, a scan signal SCAN, a reset control signal RESET, etc. to the pixel unit P0 according to an instruction of the control circuit Signal.
  • the control circuit includes an external integrated circuit (IC), but is not limited thereto.
  • the scan driving circuit is a GOA (Gate Driver On Array) structure mounted on the display panel, or a driver chip (IC) structure that is bonded to the display panel.
  • GOA Gate Driver On Array
  • the display panel further includes a power supply (not shown in the figure) to provide the above-mentioned voltage signal, which can be a voltage source or a current source as required, and the power source is configured to pass through the first power line 311, the second power line 312, and the And the initialization signal line 210 provides the first voltage signal ELVDD, the second power supply voltage ELVSS, and the initialization signal Vint to the pixel unit P0.
  • a power supply (not shown in the figure) to provide the above-mentioned voltage signal, which can be a voltage source or a current source as required, and the power source is configured to pass through the first power line 311, the second power line 312, and the And the initialization signal line 210 provides the first voltage signal ELVDD, the second power supply voltage ELVSS, and the initialization signal Vint to the pixel unit P0.
  • the second electrode C12 of the storage capacitor C1 is electrically connected to the first power line 311, and the first electrode C11 of the storage capacitor C1 is electrically connected to the second electrode T32 of the threshold compensation transistor T3.
  • the gate T20 of the data writing transistor T2 is electrically connected to the gate line 113, and the first electrode T21 and the second electrode T22 of the data writing transistor T2 are electrically connected to the data line 313 and the first electrode T11 of the driving transistor T1, respectively.
  • the gate T30 of the threshold compensation transistor T3 is electrically connected to the gate line 113, the first pole T31 of the threshold compensation transistor T3 is electrically connected to the second pole T12 of the drive transistor T1, and the second pole T32 of the threshold compensation transistor T3 is electrically connected to the drive transistor T1.
  • the gate T10 is electrically connected.
  • the gate T40 of the first light emission control transistor T4 and the gate T50 of the second light emission control transistor T5 are both connected to the light emission control signal line 110.
  • the first pole T41 and the second pole T42 of the first light-emitting control transistor T4 are electrically connected to the first power line 311 and the first pole T11 of the driving transistor T1, respectively.
  • the first electrode T51 and the second electrode T52 of the second light-emitting control transistor T5 are electrically connected to the second electrode T12 of the driving transistor T1 and the pixel electrode E1 (which may be the anode of the OLED) of the light-emitting element 20, respectively.
  • the common electrode E2 (which may be a common electrode of an OLED, such as a cathode) of the light-emitting element 20 is electrically connected to the second power line 312.
  • the gate T60 of the first reset transistor T6 is electrically connected to the first reset control signal line 111, and the first pole T61 of the first reset transistor T6 is connected to the initialization signal line 210 (the first initialization signal line 211). ) Is electrically connected, and the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1.
  • the gate T70 of the second reset transistor T7 is electrically connected to the second reset control signal line 112, the first pole T71 of the second reset transistor T7 is electrically connected to the initialization signal line 210 (the second initialization signal line 212), and the second reset transistor The second pole T72 of T7 is electrically connected to the pixel electrode E1 of the light-emitting element 20.
  • FIG. 9 shows the semiconductor pattern SCP
  • FIG. 10 shows the first conductive pattern layer LY1, and a first gate insulating layer is provided between the first conductive pattern layer LY1 and the semiconductor pattern SCP.
  • the semiconductor pattern SCP is doped with the first conductive pattern layer LY1 as a mask, so that the area of the semiconductor pattern SCP that is not covered by the first conductive pattern layer LY1 retains the semiconductor characteristics, forming the channel of the thin film transistor, and the semiconductor pattern SCP
  • the area covered by the first conductive pattern layer LY1 is made conductive to form the source or drain of the thin film transistor.
  • Figure 17 shows the active layer ALT formed after the semiconductor pattern SCP is partially conductive.
  • the first conductive pattern layer LY1 includes a first reset control signal line 111, a second reset control signal line 112, a light emission control signal line 110, a gate line 113, and a first electrode C11 of a storage capacitor C1.
  • FIG. 10 also shows the first portion DL11 (wire 114) of the first data line DL1.
  • FIG. 10 also shows a gate line GL0, which is a part of the gate line extending from the second display area to the first display area.
  • the first reset control signal line 111 and the second reset control signal line 112 are connected.
  • FIG. 11 shows the second conductive pattern layer LY2, and a second gate insulating layer is provided between the second conductive pattern layer LY2 and the first conductive pattern layer LY1.
  • the second conductive pattern layer LY2 includes a stopper BK0, a stopper BK1, an initialization signal line 210, and a second pole C12 of the storage capacitor C1.
  • the second pole C12 of the storage capacitor C1 has an opening OPN.
  • the initialization signal line 210 includes a first initialization signal line 211 and a second initialization signal line 212.
  • the second conductive pattern layer LY2 includes a first portion L11 and a third portion L13 of the first conductive line L1.
  • the stopper BK0 extends from the first wire L1.
  • Figure 12 shows the pattern of the first insulating layer ISL1.
  • the dots in the figure are via holes in the first insulating layer ISL1.
  • the first insulating layer ISL1 includes a first gate insulating layer, a second gate insulating layer and interlayers. At least one of the insulating layers.
  • the interlayer insulating layer is located between the second conductive pattern layer LY2 and the third conductive pattern layer LY3.
  • FIGS. 24 and 25 For the first gate insulating layer, the second gate insulating layer and the interlayer insulating layer, the first conductive pattern layer LY1, the second conductive pattern layer LY2, and the third conductive pattern layer LY3, please refer to FIGS. 24 and 25.
  • FIG. 18 shows a schematic plan view after forming the first insulating layer ISL1.
  • FIG. 13 shows the third conductive pattern layer LY3.
  • the third conductive pattern layer LY3 includes a third wire L3 (a part of the first power line 311), a second part DL12 of the data line (a part of the data line 313), and the first The connection electrode 31a, the second connection electrode 31b, the third connection electrode 31c, and the fourth connection electrode 31d.
  • the third conductive pattern layer LY3 further includes a second portion L12 of the first conductive line L1.
  • the first part L11 and the third part L13 of the first wire L1 are connected by the second part L12.
  • the data line 313 is electrically connected to the first pole T21 of the data writing transistor T2 through the via hole V4, and the first power line 311 is electrically connected to the first light emitting control transistor T4 through the via hole V3.
  • the first pole T41 is electrically connected, the first power line 311 is electrically connected to the second pole C12 of the storage capacitor C1 through the via hole V6, and the first power line 311 is electrically connected to the conductive block BK1 through the via hole V5.
  • One end of the first connection electrode 31a is electrically connected to the first initialization signal line 211 through the via hole V11, and the other end of the first connection electrode 31a is connected to the first electrode T61 of the first reset transistor T6 through the via hole V12, so that the first The first pole T61 of the reset transistor T6 is electrically connected to the first initialization signal line 211.
  • One end of the second connection electrode 31b is electrically connected to the second electrode T62 of the first reset transistor T6 through the via hole V21, and the other end of the second connection electrode 31b is electrically connected to the gate T10 of the driving transistor T1 (that is, the storage capacitor) through the via hole V22.
  • the first electrode C11 of C1 is electrically connected, so that the second electrode T62 of the first reset transistor T6 is electrically connected to the gate T10 of the driving transistor T1 (that is, the first electrode C11 of the storage capacitor C1).
  • One end of the third connection electrode 31c is electrically connected to the second initialization signal line 212 through the via hole V31, and the other end of the third connection electrode 31c is connected to the first electrode T71 of the second reset transistor T7 through the via hole V32, so that the second The first pole T71 of the reset transistor T7 is electrically connected to the first initialization signal line 211.
  • the fourth connection electrode 31d is electrically connected to the second electrode T52 of the second light emission control transistor T5 through the via hole V1.
  • the fourth connection electrode 31d can be used to electrically connect with the pixel electrode E1 (refer to FIG. 8) of the light-emitting element 20 to be formed later.
  • FIG. 14 shows the second insulating layer ISL2, and the dots in FIG. 14 are via holes V1 in the second insulating layer ISL2.
  • the via V1 includes a via V10, a via V20, a via V30, and a via V40.
  • Fig. 20 is a plan view after forming the second insulating layer.
  • Fig. 15 shows the electrode layer ETL.
  • the electrode layer ETL includes a plurality of pixel electrodes E1.
  • the electrode layer ETL includes the pixel electrode E11 of the first pixel unit 101, the pixel electrode E12 of the second pixel unit 102, the pixel electrode E13 of the third pixel unit 103, and the pixel electrode E14 of the fourth pixel unit 104.
  • FIG. 21 is a plan view of the display panel after forming the electrode layer.
  • the pixel electrode E14 of the fourth pixel unit 104 includes a supplementary part E0, and the orthographic projection of the supplementary part E0 on the base substrate can cover the common electrode (
  • the second pole T22 of the data writing transistor T2 and the second pole T42 of the first light emitting control transistor T4) are projected onto the base substrate to improve the stability and stability of the data writing transistor T2 and the first light emitting control transistor T4. Life, thereby improving the long-term luminous stability and life of the display panel.
  • FIG. 16 shows a plan view of the pixel definition layer.
  • the pixel definition layer PDL includes a plurality of openings, and the plurality of openings includes an opening OPN1, an opening OPN2, an opening OPN3, and an opening OPN4.
  • FIG. 22 shows a schematic diagram of the display panel after forming the pixel definition layer.
  • the opening OPN1 exposes a part of the pixel electrode E11
  • the opening OPN2 exposes a part of the pixel electrode E12
  • the opening OPN3 exposes a part of the pixel electrode E13
  • the opening OPN4 exposes a part of the pixel electrode E14.
  • the light-emitting functional layer and the common electrode are formed, and then the light-emitting element EMC is formed.
  • the transistors used in an embodiment of the present disclosure may be thin film transistors, field effect transistors, or other switching devices with the same characteristics.
  • the source and drain of the transistor used here can be symmetrical in structure, so the source and drain of the transistor can be structurally indistinguishable.
  • one pole is directly described as the first pole and the other pole is the second pole. Therefore, all or part of the first pole of the transistor in the embodiment of the present disclosure And the second pole is interchangeable according to needs.
  • the first electrode of the transistor described in the embodiments of the present disclosure may be a source electrode, and the second electrode may be a drain electrode; or, the first electrode of the transistor may be a drain electrode and the second electrode of the transistor may be a source electrode.
  • transistors can be divided into N-type and P-type transistors according to their characteristics.
  • the transistors all adopt P-type transistors as an example for description. Based on the description and teaching of the implementation in the present disclosure, those of ordinary skill in the art can easily think of using N-type transistors for at least part of the transistors in the pixel circuit of the embodiments of the present disclosure without creative work, that is, using N-type transistors. The implementation of the transistor or the combination of the N-type transistor and the P-type transistor, therefore, these implementations are also within the protection scope of the present disclosure.
  • FIGS. 8 to 25 take a 7T1C pixel circuit as an example for description, and the embodiments of the present disclosure include but are not limited to this. It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in the pixel circuit.
  • the pixel circuit of the display base panel may also be a structure including other numbers of transistors, such as a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.
  • FIG. 25 is a schematic cross-sectional view of a display panel provided by an embodiment of the disclosure.
  • the display panel includes a thin film transistor 50 and a storage capacitor C1.
  • the thin film transistor 50 includes an active layer ATL1 located on the base substrate BS, a first gate insulating layer GI1 located on the side of the active layer ATL1 away from the base substrate BS, and located on the side of the first gate insulating layer GI1 away from the base substrate BS The gate GE.
  • the display panel further includes a second gate insulating layer GI2 located on the side of the gate GE away from the base substrate BS, an interlayer insulating layer ILD located on the side of the second gate insulating layer GI2 away from the base substrate BS, and an interlayer insulating layer
  • the ILD is away from the connection electrode CNE1 on the side of the base substrate BS.
  • the active layer ATL1 includes a channel CN11 and a first electrode ET1 and a second electrode ET2 respectively located on both sides of the channel CN11.
  • the connection electrode CNE1 passes through the first gate insulating layer GI1, the second gate insulating layer GI2, and the interlayer insulation.
  • the via hole of the layer ILD is connected to the second pole ET2.
  • the storage capacitor C1 includes a first electrode C11 and a second electrode C12.
  • the first electrode C11 and the gate GE are located on the same layer, and both are located on the first conductive pattern layer LY1, and the second electrode C12 is located on the second gate insulating layer GI2 and the interlayer insulation Between the layers ILD, the second conductive pattern layer LY2 is located.
  • One of the first electrode ET1 and the second electrode ET2 is a source, and the other of the first electrode ET1 and the second electrode ET2 is a drain.
  • the connection electrode CNE1 is located on the third conductive pattern layer LY3.
  • the display panel also includes a passivation layer PVX and a planarization layer PLN.
  • the connection electrode CNE1 is the aforementioned fourth connection electrode 31d
  • the thin film transistor 50 can be the aforementioned second light emission control transistor T5.
  • the display panel also includes a light-emitting element EMC.
  • the light-emitting element EMC includes a pixel electrode E1, a light-emitting functional layer EML, and a common electrode E2.
  • the pixel electrode E1 is connected to the through hole through the passivation layer PVX and the planarization layer PLN
  • the electrode CNE1 is connected.
  • the display panel further includes an encapsulation layer CPS, and the encapsulation layer CPS includes a first encapsulation layer CPS1, a second encapsulation layer CPS2, and a third encapsulation layer CPS3.
  • the first encapsulation layer CPS1 and the third encapsulation layer CPS3 are inorganic material layers, and the second encapsulation layer CPS2 is an organic material layer.
  • the pixel electrode E1 is an anode
  • the common electrode E2 is a cathode, but it is not limited thereto.
  • the light-emitting element EMC includes an organic light-emitting diode.
  • the light-emitting function layer is located between the common electrode E2 and the pixel electrode E1.
  • the light-emitting functional layer EML includes at least a light-emitting layer, and may also include at least one of a hole transport layer, a hole injection layer, an electron transport layer, and an electron injection layer.
  • the display panel further includes a pixel definition layer PDL and spacers PS.
  • the pixel defining layer PDL has an opening configured to define the light emitting area (light emitting area, effective light emitting area) of the pixel unit, and the spacer PS is configured to support the fine metal mask when forming the light emitting function layer EML.
  • FIG. 25 shows that spacers PS are provided on opposite sides of the light-emitting element, but it is not limited to this.
  • the data line is configured to input a data signal to the pixel unit
  • the first power signal line is configured to input a first power voltage to the driving transistor.
  • the second power signal line is configured to input a second power voltage to the pixel unit.
  • the first power supply voltage is a constant voltage
  • the second power supply voltage is a constant voltage.
  • the first power supply voltage is a positive voltage
  • the second power supply voltage is a negative voltage, but it is not limited thereto.
  • the first power supply voltage is a positive voltage
  • the second power supply signal line is grounded.
  • the first insulating layer ISL1 includes at least one of a first gate insulating layer GI1, a second gate insulating layer GI2, and an interlayer insulating layer ILD, and the second insulating layer ISL2 includes a planarization Layer PLN.
  • the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, the passivation layer PVX, the planarization layer PLN, the pixel definition layer PDL and the spacer PS are all made of insulating materials.
  • the material of the first gate insulating layer GI1, the second gate insulating layer GI2, the interlayer insulating layer ILD, and the passivation layer PVX includes at least one of SiOx and SiNx, but is not limited thereto.
  • the planarization layer PLN, the pixel definition layer PDL, and the spacer PS may be made of organic insulating materials, for example, resin may be used, but not limited thereto.
  • the threshold compensation transistor T3 includes a first channel CN1 and a second channel CN2, and the first channel CN1 and the second channel CN2 are connected by a conductive portion CP.
  • the second wire L2 further includes a connecting arm L21.
  • the threshold compensation transistor T3 is a double-gate transistor, and the conductive part CP is in a floating state when the threshold compensation transistor T3 is turned off. It is easily affected by the surrounding line voltage and jumps. The voltage jump of the conductive part CP will affect the threshold compensation transistor.
  • the leakage current of T3 affects the light-emitting brightness of the pixel unit. Therefore, it is necessary to keep the voltage of the conductive part CP stable.
  • the stopper and the conductive part CP can be designed to form a capacitor, and the stopper can have a constant voltage signal to make it in a floating state.
  • the voltage of the conductive part CP also remains stable.
  • the stopper BK0, the stopper BK, and the connecting arm L21 mentioned in the embodiment of the present disclosure all play a role in stabilizing the voltage of the conductive portion CP.
  • the connecting arm L21 partially overlaps the conductive portion CP of the threshold compensation transistor T3 to form a capacitor C0, and a first gate insulating layer GI1 and a second gate insulating layer GI2 are provided between the connecting arm L21 and the conductive portion CP.
  • Fig. 24 also shows the second channel CN2.
  • the capacitor C0 can be referred to as a stable capacitor, and the connecting arm L21 and the conductive portion CP are the two plates of the capacitor C0.
  • the gate GE2 and the second channel CN2 overlap in a direction perpendicular to the base substrate BS.
  • the gate GE2 is a gate of the threshold compensation transistor T3.
  • the second connection electrode 31b is connected to the second electrode T32 of the threshold compensation transistor T3.
  • the second wire L2 further includes a connecting arm L21, and the connecting arm L21 and the conductive portion CP are spaced apart from each other in the third direction D3 and partially overlapped in the third direction D3 (refer to FIG. 24).
  • the shape of the connecting arm L21 includes a C shape.
  • the connecting arm L21 may be substantially C-shaped.
  • the connecting arm L21 may also adopt other shapes as long as it can stabilize the threshold compensation transistor T3.
  • the third direction D3 is perpendicular to the first direction D1 and perpendicular to the second direction D2, the third direction D3 is a direction perpendicular to the base substrate BS, and a first gate insulation is provided between the connecting arm L21 and the conductive portion CP.
  • the first direction D1 and the second direction D2 are directions parallel to the main surface of the base substrate BS
  • the third direction D3 is a direction perpendicular to the main surface of the base substrate BS.
  • Various elements are fabricated on the main surface of the base substrate BS.
  • the first portion L11 includes a first sub-portion La extending in the first direction D1 and a second sub-portion Lb extending in the second direction.
  • the second sub-portion Lb has branches that extend along the first direction. Extending in one direction D1, the stop BK0 is a branch of the second sub-part Lb.
  • the branch (stop BK0) of the second sub-portion Lb and the conductive portion of one pixel unit overlapping the first conductive line L1 in the pixel island are spaced apart from each other in the third direction D3, And partly overlap in the third direction D3. Referring to FIG. 17, FIG. 19 and FIG.
  • the branch (stop BK0) of the second sub-portion Lb is connected to a pixel unit (the pixel unit in the upper left corner of FIG. 24) that overlaps with the first wire L1 in the pixel island.
  • the parts CP are spaced apart from each other in the third direction D3, and partially overlap in the third direction D3.
  • the length of the branch (stop BK0) in the first direction D1 is smaller than the length of the first sub-portion La in the first direction D1.
  • the pixel circuit 10 includes a first transistor and a second transistor.
  • the first transistor is connected to the second transistor, the second transistor is connected to the light-emitting element, and the first transistor includes a first transistor.
  • the channel CN1 and the second channel CN2, the first channel CN1 and the second channel CN2 are connected by the conductive portion CP, the second wire L2 further includes a connecting arm L21, the connecting arm L21 and the second wire L2 in the pixel island
  • the conductive portions CP of an overlapping pixel unit (the pixel unit located at the lower left corner in FIG. 19) are spaced apart from each other in the third direction D3, and partially overlap in the third direction D3.
  • the above-mentioned first transistor and the second transistor are the threshold compensation transistor T3 and the light emission control transistor connected to the light emitting element in the pixel circuit 10, respectively.
  • the light-emission control transistor connected to the light-emitting element is the above-mentioned second light-emission control transistor T5.
  • the stopper or the connecting arm that forms a capacitor with the conductive portion CP in the first transistor in the pixel island can also take other forms, which are not limited here.
  • the stopper BK0 (the branch of the second sub-part Lb) and the connecting arm L21 are both connected to the third wire L3 of the pixel unit of this column, and the stopper BK is connected to it.
  • the initialization signal line 210 includes a plurality of hollow areas HP
  • the second wire L2 is located in a hollow area HP and is surrounded by the portion of the initialization signal line that surrounds the hollow area HP
  • the second wire L2 It does not overlap with the part of the initialization signal line that surrounds the hollowed-out area. That is, the second wire L2 is completely surrounded by the part of the initialization signal line that surrounds the hollow area HP.
  • the hollow area HP is a position corresponding to the part of the thin film that is removed when the initialization signal line 210 is made.
  • the first wire L1 includes a first portion L11 and a second portion L12, the first portion L11 of the first wire L1 and the second wire L2 are located on the same layer, and the second wire L1 The portion L12 is not located on the same layer as the second wire L2, and the second portion L12 of the first wire L1 at least partially overlaps the initialization signal line 210.
  • the first portion L11 of the first wire L1 and the second wire L2 are located on the second conductive pattern layer LY2, and the second portion L12 of the first wire L1 is located on the third conductive pattern layer LY3.
  • the second wire L2 is surrounded by a part of the initialization signal line 210, and the first portion L11 of the first wire L1 is surrounded by a part of the initialization signal line 210.
  • the second wire L2 is surrounded by the lower portion 210 a of the initialization signal line 210, and the first portion L11 of the first wire L1 is surrounded by the upper portion 210 b of the initialization signal line 210.
  • the data line 313 includes a first data line DL1.
  • the first data line DL1 extends from the first display area R1 to the second display area R2.
  • the orthographic projections on the base substrate BS partially overlap. This arrangement is beneficial to reduce the wiring area and increase the light transmittance.
  • the first data line DL1 includes a first portion DL11 and a second portion DL12, the first portion DL11 of the first data line DL1 partially overlaps the third conductive line L3, and the first data line DL1
  • the second portion DL12 and the third conductive line L4 do not overlap, and the first portion DL11 of the first data line DL1 and the second portion DL12 of the first data line DL1 are respectively located in different layers.
  • FIG. 19 is located on the second conductive pattern layer, and the second portion DL12 of the first data line DL1 on the left is located on the third conductive pattern layer, FIG. 19
  • the first portion DL11 (wire 114) of the first data line DL1 on the right side is located on the first conductive pattern layer, and the second portion DL12 of the first data line DL1 on the right side is located on the third conductive pattern layer.
  • the first portion DL11 of the first data line DL1 is located between adjacent pixel islands A1.
  • two first data lines DL1 are provided, the two first data lines DL1 are respectively connected to two adjacent columns of pixel units, and the two first data lines DL1 are connected to the same third conductive line L3.
  • the orthographic projections on the base substrate BS overlap. This arrangement allows the data lines located between the pixel islands in two adjacent columns of pixel units to be hidden under the third wire, thereby reducing the wiring area and improving the light transmittance.
  • the first wire L1 includes portions located in different layers, and the portions located in the different layers are connected by via holes penetrating the insulating layer.
  • the first wire L1 includes a first portion L11, a second portion L12, and a third portion L13.
  • the first portion L11 and the third portion L13 are located on the second conductive pattern layer LY2, and the second portion L12 is located on the third conductive pattern layer LY3.
  • the first part L11 and the second part L12 are connected through a via hole V41 that penetrates the insulating layer, and the third part L13 and the second part L12 are connected through a via hole V42 that penetrates the insulating layer.
  • an interlayer dielectric layer ILD is provided between the second conductive pattern layer LY2 and the third conductive pattern layer LY3, that is, the via hole V41 penetrates the interlayer dielectric layer ILD, and the via hole V42 penetrates the interlayer dielectric. Electric layer ILD.
  • a part of the first conductive line L1 (the second portion L12) and the third conductive line L3 are located on the same layer, and both are located on the third conductive pattern layer LY3.
  • the fourth conductive line L4 and the third conductive line L3 are located on the same layer, and both are located on the third conductive pattern layer LY3.
  • the display device can be a display device such as an Organic Light-Emitting Diode (OLED) display, as well as any TV, digital camera, mobile phone, watch, tablet computer, notebook computer, navigator, etc. that include these display devices. Products or parts.
  • OLED Organic Light-Emitting Diode
  • the first conductive line L1 may include a portion located in the first conductive pattern layer and a portion located in the second conductive pattern layer
  • the second conductive line L2 is composed of only the portion located in the second conductive pattern layer.
  • the third wire L3 is only composed of a portion located on the third conductive pattern layer
  • the fourth wire L43 is only composed of a portion located on the third conductive pattern layer
  • the fifth wire L5 may include a portion located on the first conductive pattern layer and a portion located on the second conductive pattern layer.
  • the part of the conductive pattern layer constitutes, but is not limited to this, and can be set as required.
  • the second pole C12 of the storage capacitor C1 of the pixel unit P0 is a part of the second wire L2 or a part of the first wire L1.

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Abstract

一种显示面板和显示装置，显示面板包括：第一显示区域；第二显示区域，至少位于第一显示区域的一侧；多个像素单元，第一显示区域的像素单元的密度小于第二显示区域的像素单元的密度，像素单元包括像素电路；以及第一电源线，被配置为向像素电路提供第一电压信号；第一电源线包括多条第一导线、多条第二导线和多条第三导线，第一导线从第二显示区域延伸至第一显示区域，多条第二导线位于第一显示区域，并且位于相邻第一导线之间，第二导线沿第一方向延伸，第三导线沿第二方向延伸，第一方向与第二方向相交，第三导线从第二显示区域延伸至第一显示区域，并且相邻第二导线沿第一方向彼此间隔，第二导线通过第三导线与第一导线相连。

Description

显示面板和显示装置
相关申请的交叉引用
出于所有目的，本专利申请要求于2020年06月04日递交的中国专利申请第202010498518.8号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开至少一实施例涉及一种显示面板和显示装置。
背景技术
基于屏下摄像头的设计，显示面板通常包括高像素密度(Pixels Per Inch，PPI)区域和低PPI区域，然而，通常的显示面板在低PPI区域的光透过率较低，不利于提高摄像头在成像区域的显示效果。
发明内容
本公开的至少一实施例涉及一种显示面板和显示装置。
本公开的至少一实施例提供一种显示面板，包括：第一显示区域；第二显示区域，至少位于所述第一显示区域的一侧；多个像素单元，位于所述第一显示区域和所述第二显示区域，所述第一显示区域的像素单元的密度小于所述第二显示区域的像素单元的密度，所述像素单元包括像素电路；以及第一电源线，被配置为向所述像素电路提供第一电压信号；所述第一电源线包括多条第一导线、多条第二导线和多条第三导线，所述第一导线从所述第二显示区域延伸至所述第一显示区域，所述多条第二导线位于所述第一显示区域，并且位于相邻第一导线之间，所述第二导线沿第一方向延伸，所述第三导线沿第二方向延伸，所述第一方向与所述第二方向相交，所述第三导线从所述第二显示区域延伸至所述第一显示区域，并且相邻第二导线沿所述第一方向彼此间隔，所述第二导线通过所述第三导线与所述第一导线相连。
根据本公开的一些实施例提供的显示面板，所述多条第二导线沿所述第一方向依次排列。
根据本公开的一些实施例提供的显示面板，所述相邻第二导线不直接相连。
根据本公开的一些实施例提供的显示面板，所述第一导线的位于所述第一显示区域的部分在所述第一方向上的长度大于所述第二导线在所述第一方向上的长度。
根据本公开的一些实施例提供的显示面板，所述第一导线包括位于不同层的部分，所述位于不同层的部分通过贯穿绝缘层的过孔相连。
根据本公开的一些实施例提供的显示面板，所述第一电源线还包括第四导线，所述第四导线沿所述第二方向延伸，所述第二导线通过所述第四导线连接至所述第一导线，所述第四导线在所述第二方向上的长度小于或等于所述第三导线在所述第二方向上的长度。
根据本公开的一些实施例提供的显示面板，包括多条第四导线，所述多条第四导线位于相邻第三导线之间，所述多条第四导线沿所述第二方向依次排列，相邻第四导线在所述第二方向上彼此间隔。
根据本公开的一些实施例提供的显示面板，所述第一导线的一部分与所述第三导线位于同一层， 所述第四导线与所述第三导线位于同一层。
根据本公开的一些实施例提供的显示面板，位于所述第一显示区域的像素单元构成多个像素岛，所述像素岛至少包括位于相邻两行的两个像素单元，所述第一导线和所述第二导线分别与位于所述相邻两行的两个像素单元交叠。
根据本公开的一些实施例提供的显示面板，所述像素单元还包括发光元件，所述像素电路包括第一晶体管和第二晶体管，所述第一晶体管与所述第二晶体管相连，所述第二晶体管与所述发光元件相连，所述第一晶体管包括第一沟道和第二沟道，所述第一沟道和所述第二沟道通过导电部相连，所述第二导线还包括连接臂，所述连接臂与所述像素岛中的与所述第二导线交叠的一个像素单元的所述导电部在第三方向上彼此间隔，且在所述第三方向上部分重叠，所述第三方向垂直于所述第一方向，并且垂直于所述第二方向。
根据本公开的一些实施例提供的显示面板，所述连接臂的形状包括C型。
根据本公开的一些实施例提供的显示面板，所述第一导线具有分支，所述分支与所述像素岛中的与所述第一导线交叠的一个像素单元的所述导电部在所述第三方向上彼此间隔，且在所述第三方向上部分重叠。
根据本公开的一些实施例提供的显示面板，所述第一方向垂直于所述第二方向。
根据本公开的一些实施例提供的显示面板，所述第一电源线还包括第五导线，所述第五导线沿所述第一方向延伸，所述第五导线位于所述第二显示区域，所述第五导线位于相邻第一导线之间，所述第五导线和与其相邻的第二导线沿所述第一方向彼此间隔。
根据本公开的一些实施例提供的显示面板，显示面板还包括初始化信号线，所述初始化信号线被配置为向所述像素电路提供初始化信号，所述第二导线被所述初始化信号线的一部分环绕。
根据本公开的一些实施例提供的显示面板，所述第一导线包括第一部分和第二部分，所述第一导线的第一部分与所述第二导线位于同一层，所述第一导线的第二部分不与所述第二导线位于同一层，所述第一导线的所述第一部分被所述初始化信号线的一部分环绕。
根据本公开的一些实施例提供的显示面板，所述第一导线的所述第一部分具有沿所述第一方向延伸的第一子部和沿所述第二方向延伸的第二子部，所述第二子部具有分支，所述分支沿所述第一方向延伸。
根据本公开的一些实施例提供的显示面板，所述分支在所述第一方向上的长度小于所述第一子部在所述第一方向上的长度。
根据本公开的一些实施例提供的显示面板，所述像素单元还包括发光元件，所述像素电路包括第一晶体管和第二晶体管，所述第一晶体管与所述第二晶体管相连，所述第二晶体管与所述发光元件相连，所述第一晶体管包括第一沟道和第二沟道，所述第一沟道和所述第二沟道通过导电部相连，所述分支与所述像素岛中的与所述第一导线交叠的一个像素单元的所述导电部在所述第三方向上彼此间隔，且在所述第三方向上部分重叠，所述第三方向垂直于所述第一方向，并且垂直于所述第二方向。
根据本公开的一些实施例提供的显示面板，所述第二导线还包括连接臂，所述连接臂与所述像素岛中的与所述第二导线交叠的一个像素单元的所述导电部在第三方向上彼此间隔，且在所述第三方向上部分重叠。
根据本公开的一些实施例提供的显示面板，显示面板还包括衬底基板和数据线，所述数据线被配置为向所述像素电路提供数据信号，所述数据线包括第一数据线，其中，所述第一数据线从所述第一显示区域延伸至所述第二显示区域，所述第一数据线与所述第三导线在所述衬底基板上的正投影部分交叠。
根据本公开的一些实施例提供的显示面板，所述第一数据线包括第一部分和第二部分，所述第一数据线的所述第一部分与所述第三导线部分交叠，所述第一数据线的所述第二部分与所述第三导线不交叠，所述第一数据线的所述第一部分和所述第一数据线的所述第二部分分别位于不同的层。
根据本公开的一些实施例提供的显示面板，相邻像素岛之间具有透光区域，所述第一数据线的所述第一部分位于相邻像素岛之间。
根据本公开的一些实施例提供的显示面板，提供两条第一数据线，所述两条第一数据线分别与相邻两列像素单元相连，所述两条第一数据线与同一条第三导线在所述衬底基板上的正投影部分交叠。
根据本公开的一些实施例提供的显示面板，显示面板还包括栅线，所述栅线被配置为向一行像素单元提供扫描信号，所述栅线包括第一栅线，所述第一栅线从所述第二显示区域延伸至所述第一显示区域，所述透光区域由两条相邻第一栅线以及两条相邻第一数据线围设而成。
本公开的一些实施例还提供一种显示装置，包括上述任一显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A至图1C为本公开的一些实施例提供的显示面板的示意图；
图2为本公开一实施例提供的显示面板的第二显示区域的示意图；
图3为本公开一实施例提供的显示面板的第一显示区域的示意图；
图4为本公开一实施例提供的一种显示面板中的像素单元以及为像素单元提供信号的信号线的示意图；
图5为一种显示面板的示意图；
图6A至图6E为本公开一些实施例提供的显示面板的示意图；
图7A为本公开一实施例提供的显示面板的示意图；
图7B为本公开一实施例提供的显示面板的示意图；
图8为本公开一实施例提供的一种显示面板的像素电路的原理图；
图9为本公开一实施例提供的一种显示面板中的半导体图形的平面图；
图10为本公开一实施例提供的一种显示面板中的第一导电图案层的平面图；
图11为本公开一实施例提供的一种显示面板中的第二导电图案层的平面图；
图12为本公开一实施例提供的一种显示面板中的第一绝缘层的平面图；
图13为本公开一实施例提供的一种显示面板中的第三导电图案层的平面图；
图14为本公开一实施例提供的一种显示面板中的第二绝缘层的平面图；
图15为本公开一实施例提供的一种显示面板中的像素电极层的平面图；
图16为本公开一实施例提供的一种显示面板中的像素定义层的平面图；
图17为本公开一实施例提供的一种显示面板中形成薄膜晶体管的有源层的示意图；
图18为本公开一实施例提供的一种显示面板中形成第二导电图案层以及第一绝缘层后的平面示意图；
图19为本公开一实施例提供的一种显示面板中形成第三导电图案层后的平面示意图；
图20为本公开一实施例提供的一种显示面板中的形成第二绝缘层后的平面示意图；
图21为本公开一实施例提供的一种显示面板中在形成像素电极层后的平面示意图；
图22为本公开一实施例提供的一种显示面板中在形成像素定义后的平面示意图；
图23为本公开一实施例提供的一种显示面板中第一显示区域内的在第二方向上相邻像素岛的平面示意图；
图24为本公开一实施例提供的一种显示面板的剖视示意图；以及
图25为本公开一实施例提供的一种显示面板的剖视示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
通常的显示面板中，不论是在高PPI区域还是在低PPI区域，第一电源线都是采用网状结构。为了提高低PPI区域的光透过率，提高摄像头在成像区域的显示效果，本公开的实施例提供的显示面板对低PPI区域的信号线进行优化，以达到更高的透过率，例如，本公开的实施例通过对网状的第一电源线的横纵排列的导线进行优化。
图1A至图1C为本公开的一些实施例提供的显示面板的示意图。如图1A至图1C所示，显示面板包括第一显示区域R1和第二显示区域R2。第一显示区域R1为高像素密度(Pixels Per Inch，PPI)区域，第二显示区域R2为低PPI区域。第二显示区域R2为局部透光区域。如图1A至图1C所示，第二显示区域R2至少位于第一显示区域R1的一侧。图1A和图1B所示的显示面板还包括第三区域R3。传感器例如摄像头可以设置在第一显示区域R1(如图1C所示)，或者设置在第一显示区域R1和第三区域R3(如图1A和图1B所示)。图1A和图1B所示的第三区域R3可为挖孔区域，即，第三区域R3所对应的位置的材料被去除，形成通孔。传感器可接收环境光。以传感器为摄像头为例，实现屏下 摄像头，使得在正常使用屏幕时，传感器对应的第一显示区域能够正常显示画面，而在进行摄像头拍摄时，第一显示区域能够透过环境光，支持正常的使用。例如，传感器设置在显示面板的非显示侧。传感器也可称作屏下器件。
图1A还示出了多条栅线113和多条数据线313。多条栅线113包括第一栅线GL1，多条数据线313包括第一数据线DL1。第一栅线GL1从第二显示区域R2延伸至第一显示区域R1。第一数据线DL1从第一显示区域R1延伸至第二显示区域R2。本公开的实施例中，某一元件从第一显示区域R1延伸至第二显示区域R2可以理解为该元件位于第一显示区域R1和第二显示区域R2，也可以说成某一元件从第二显示区域R2延伸至第一显示区域R1。为了图示清晰，图1A示意性的示出了几条栅线113和几条数据线313，栅线113和数据线313的个数可根据需要而定。多条栅线113和多条数据线313相互交叉且彼此绝缘。
图2为本公开一实施例提供的显示面板的第二显示区域的示意图。图3为本公开一实施例提供的显示面板的第一显示区域的示意图。如图2和图3所示，显示面板包括多个像素单元P0，多个像素单元P0包括第一像素单元101、第二像素单元102、第三像素单元103和第四像素单元104。一个第一像素单元101、一个第二像素单元102、一个第三像素单元103和一个第四像素单元104构成像素组P1。例如，一个像素组P1包括两个像素，在像素组P1中，一个第一像素单元101和一个第二像素单元102构成一个像素，一个第三像素单元103和一个第四像素单元104构成一个像素。一个像素组P1形成两个虚拟像素，以提高显示效果。例如，一个像素组P1为一个重复单元，在第二显示区域R2阵列排布。如图3所示，在第一显示区域R1中，一个像素组P1称作一个像素岛A1。第一显示区域R1包括多个透光区域R0；透光区域R0位于相邻像素岛A1之间。透光区域R0可透过环境光。例如，透光区域R0可包括衬底基板以及位于衬底基板上的透明绝缘层，透光区域R0不具有光遮挡结构，例如，不具有金属走线。例如，透光区域R0位于四个相邻像素岛A1围设的区域内，但不限于此。例如，如图3所示，相邻像素岛A1间隔设置。
本公开的实施例以第一像素单元101为红色像素单元，第二像素单元102为绿色像素单元，第三像素单元103为蓝色像素单元，第四像素单元104为绿色像素单元为例，在其他的实施例中，像素组也可以采用其他颜色的像素单元。当然，在其他的实施例中，显示面板中多个像素单元P0的排列方式也不限于图2和图3所示。
参考图2和图3，多个像素单元P0位于第一显示区域R1和第二显示区域R2，第一显示区域R1的像素单元的密度小于第二显示区域R2的像素单元的密度。或者说，第一显示区域R1的像素的密度小于第二显示区域R2的像素的密度。图3所示的第一显示区域R1中的像素单元的密度为第二显示区域R2中的像素单元的密度的四分之一。即，图3所示的第一显示区域R1中的像素的密度为第二显示区域R2中的像素的密度的四分之一。第一显示区域R1内的透光区域R0和像素单元的排布方式不限于图3所示，可根据需要进行设置。例如，在其他的实施例中，第一显示区域R1中的像素单元的密度为第二显示区域R2中的像素单元的密度的二分之一、三分之一、六分之一或者八分之一等不同于四分之一的其他的数值。
例如，如图1A和图3所示，显示面板还包括栅线113和数据线313。栅线113和数据线313彼此绝缘。每条栅线113连接一行像素单元，每条数据线313连接一列像素单元。例如，栅线113被配置 为向一行像素单元提供扫描信号。
例如，如图1A和图3所示，数据线313包括第一数据线DL1。第一数据线DL1至少位于第一显示区域R1。例如，第一数据线DL1从第一显示区域R1延伸至第二显示区域R2。
例如，如图1A和图3所示，栅线包括第一栅线GL1，第一栅线GL1从第二显示区域R2延伸至第一显示区域R1。如图3所示，透光区域R0由两条相邻第一栅线GL1、两条相邻第一数据线DL1围设而成，但不限于此。
图4为本公开一实施例提供的一种显示面板中的像素单元以及为像素单元提供信号的信号线的示意图。如图4所示，显示面板包括：多个像素单元P0，每个像素单元P0包括发光元件EMC和为发光元件EMC提供驱动电流的像素电路10，发光元件EMC可为电致发光元件，例如，有机电致发光元件，例如可为有机发光二极管(OLED)。
如图4所示，显示面板还包括初始化信号线210、发光控制信号线110、数据线313、第一电源线311以及第二电源线312。例如，栅线113被配置为向像素电路10提供扫描信号SCAN。发光控制信号线110被配置为向像素单元P0提供发光控制信号EM。数据线313被配置为向像素电路10提供数据信号DATA，第一电源线311被配置为向像素电路10提供恒定的第一电压信号ELVDD，第二电源线312被配置为向像素电路10提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。初始化信号线210被配置为向像素电路10提供初始化信号Vint。初始化信号Vint为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vint可小于或等于第二电压信号ELVSS。例如，像素电路10在扫描信号SCAN、数据信号DATA、初始化信号Vint、第一电压信号ELVDD、第二电压信号ELVSS、发光控制信号EM等信号的控制下输出驱动电流以驱动发光元件EMC发光。如图4所示，发光元件EMC包括像素电极E1和公共电极E2。像素电极E1与像素电路10相连，公共电极E2与第二电源线312相连。
图5为一种显示面板的示意图。如图5所示，不论是在第一显示区域R1还是在第二显示区域R2，第一电源线3110均采用网状结构，第一电源线3110的横向的部分直接相连，第一电源线3110的竖向的部分直接相连。然而，这种网状结构的第一电源线的布线方式使得第一显示区域R1的光透过率较低。
图6A至图6E为本公开一些实施例提供的显示面板的示意图。如图6A至图6E所示，第一电源线311包括多条第一导线L1、多条第二导线L2和多条第三导线L3，第一导线L1从第二显示区域R2延伸至第一显示区域R1，多条第二导线L2位于第一显示区域R1，并且位于相邻第一导线L1之间，每条第二导线L2沿第一方向D1延伸，第三导线L3至少位于第一显示区域R1，例如，第三导线L3从第二显示区域R2延伸至第一显示区域R1，第三导线L3沿第二方向D2延伸，第一方向D1与第二方向D2相交，并且相邻第二导线L2沿第一方向D1彼此间隔，第二导线L2通过第三导线L3与第一导线L1相连。例如，第一方向D1垂直于第二方向D2，但不限于此。例如，第一导线L1沿第一方向D1延伸。例如，在本公开的实施例中，第二导线L2仅位于第一显示区域R1。本公开的实施例中，沿着某一方向延伸的元件不一定为直线，也可以具有曲线或者折线的部分，例如，某一元件的延伸方向是指该元件的大体延伸趋势，例如，该元件的每个部分不一定都沿该方向延伸。
本公开的实施例提供的显示面板，调整第一显示区域的第一电源线的构造，相当于去除通常的显示面板中部分沿第二方向设置的第一电源线，简化了第一显示区域的第一电源线，提高了第一显示区 域的光透过率。
例如，如图6A至图6E所示，第一导线L1和第二导线L2分别连接一个像素岛A1中的相邻两行像素单元，但不限于此，在其他的实施例中，像素岛A1还可以包括两行以上的像素单元。例如，如图6A至图6E所示，像素岛A1至少包括位于相邻两行的两个像素单元，第一导线L1和第二导线L2分别与位于相邻两行的两个像素单元交叠。例如，如图6A至图6E所示，第一导线L1与第一像素单元101交叠，第二导线L2与第三像素单元103交叠。例如，如图6A至图6E所示，第一导线L1还与第二像素单元102交叠，第二导线L2还与第四像素单元104交叠。
例如，如图6A至图6E所示，多条第二导线L2沿第一方向D1依次排列。例如，如图6A至图6E所示，相邻第二导线L2不直接相连，通过去除部分沿第一方向设置的第一电源线，来形成不直接相连的多条第二导线L2。
例如，如图6A至图6E所示，为了提高第一显示区域的光透过率，第一导线L1的位于第一显示区域R1的部分在第一方向D1上的长度大于第二导线L2在第一方向D1上的长度。
例如，如图6A至图6E所示，第一电源线311还包括第四导线L4，第四导线L4沿第二方向D2延伸，第二导线L2通过第四导线L4连接至第一导线L1，第四导线L4在第二方向D2上的长度小于或等于第三导线L3在第二方向D2上的长度。在图6A、图6B和图6E所示的显示面板中，第四导线L4在第二方向D2上的长度小于第三导线L3在第二方向D2上的长度。在图6C所示的显示面板中，第四导线L4在第二方向D2上的长度等于第三导线L3在第二方向D2上的长度。
例如，如图6A至图6E所示，为了进一步提高第一显示区域的光透过率，提供多条第四导线L4，多条第四导线L4沿第二方向D2依次排列，相邻第四导线L4在第二方向D2上彼此间隔。例如，如图6A所示，多条第四导线L41位于第三导线L31和第三导线L32之间，第三导线L31和第三导线L32为相邻的第三导线L3。图6A示出了三条第四导线L41，但位于相邻第三导线L3之间的第四导线L4的个数不限于图中所示，可根据需要而定。因为多条第四导线L4在第二方向D2上彼此间隔，相当于去除了通常的显示面板中的部分第一电源线的沿第二方向设置的部分，从而减少布线，优化走线空间，提高光的透过率。
例如，如图6A至图6E所示，第一电源线311还包括第五导线L5，第五导线L5沿第一方向D1延伸，第五导线L5位于第二显示区域R2，第五导线L5位于相邻第一导线L1之间，第五导线L5和与其相邻的第二导线L2沿第一方向D1彼此间隔。从而，在第一显示区域和第二显示区域的交界位置处，减小布线，提高光的透过率。
图6E所示的显示面板中，每个像素岛包括两行三列像素单元。本公开的实施例中，对每个像素岛包括的像素单元的个数以及像素单元的排列方式不做限定，只要是每个像素岛包括的像素单元的个数大于等于两行即可采用本公开的实施例提供的第一电源线的排布方式。
如图6A和图6B所示，在显示面板中，第一电源线311还包括多条第六导线L6，第六导线L6位于第二显示区域R2，第六导线L6沿第二方向D2延伸。在第二显示区域R2，多条第五导线L5和多条第六导线L6交叉设置。在本公开的实施例中，第五导线L5和第六导线L6均仅位于第二显示区域R2。
图7A为本公开一实施例提供的显示面板的示意图。如图7A所示，同一条栅线113连接位于第一 显示区域R1的两侧的第二显示区域内的像素单元以及位于第一显示区域R1内的像素单元，构成一行像素单元。本公开的实施例对于第一导线的形态不做限定，只要其可以从第二显示区域R2延伸至第一显示区域R1即可。图7A中的第一电源线也可以替换为本公开的其他实施例中的第一电源线。并且，栅线113的延伸方式也不限于图7A所示，只要栅线113的排布方式可以使得第二显示区域R2中的像素和第一显示区域R1中的像素相连即可。
图7B为本公开一实施例提供的显示面板的示意图。与图7A所示的显示面板相比，图7B所示的显示面板调整了位于第一显示区域的部分栅线的设置位置。即，在图7B所示的显示面板中，像素岛的上方和下方分别设置一条栅线。而在图7A所示的显示面板中，在像素岛的下方设置了两条栅线。
图6A至图6E、图7A和图7B以第二导线与相邻两条第一导线中的一条相连，而与另一条不直接相连为例。图6A至图6E、图7A和图7B所示的显示面板中，第四导线与两条相邻第一导线中的一条相接触，例如通过贯穿绝缘层的过孔接触。
例如，在本公开的实施例中，一行像素单元为连接至同一条栅线113的像素单元，而一列像素单元为连接至同一条数据线313的像素单元。在本公开的实施例中，以第一导线L1、第二导线L2、以及第五导线L5均沿行方向延伸，第三导线L3、第四导线L4和第六导线L6沿列方向延伸为例进行说明，但不限于此。在其他的实施例中，还可以第一导线L1、第二导线L2、以及第五导线L5均沿列方向延伸，第三导线L3、第四导线L4和第六导线L6沿行方向延伸，相应地，第二方向D2和第一方向D1也相互替换。
图6A至图6E以像素岛包括两行像素单元为例，在其他的实施例中，像素岛还可以包括三行或者三行以上的像素单元，该情况下，上述的多个第二导线可以理解为与同一行像素单元相连的第二导线。在第一导线L1、第二导线L2、以及第五导线L5均沿列方向延伸，第三导线L3、第四导线L4和第六导线L6沿行方向延伸的情况下，上述的多个第二导线可以理解为与同一列像素单元相连的第二导线。
以下结合图8至图25对本公开的一些实施例进行描述。图8至图24以7T1C的像素电路为例进行说明。
图8为本公开一实施例提供的一种显示面板的像素电路的原理图。图9为本公开一实施例提供的一种显示面板中的半导体图形的平面图。图10为本公开一实施例提供的一种显示面板中的第一导电图案层的平面图。图11为本公开一实施例提供的一种显示面板中的第二导电图案层的平面图。图12为本公开一实施例提供的一种显示面板中的第一绝缘层的平面图。图13为本公开一实施例提供的一种显示面板中的第三导电图案层的平面图。图14为本公开一实施例提供的一种显示面板中的第二绝缘层的平面图。图15为本公开一实施例提供的一种显示面板中的像素电极层的平面图。图16为本公开一实施例提供的一种显示面板中的像素定义层的平面图。图17为本公开一实施例提供的一种显示面板中形成薄膜晶体管的有源层的示意图。图18为本公开一实施例提供的一种显示面板中形成第二导电图案层以及第一绝缘层后的平面示意图。图19为本公开一实施例提供的一种显示面板中形成第三导电图案层后的平面示意图。图20为本公开一实施例提供的一种显示面板中的形成第二绝缘层后的平面示意图。图21为本公开一实施例提供的一种显示面板中在形成像素电极层后的平面示意图。图22为本公开一实施例提供的一种显示面板中在形成像素定义后的平面示意图。图23为本公开一实施例提供的一种显示面板中第一显示区域内的在第二方向上相邻像素岛的平面示意图。图24为本公开一实施例提供的一 种显示面板的剖视示意图。图25为本公开一实施例提供的一种显示面板的剖视示意图。本公开的实施例中，为了图示清晰，平面图中，绝缘层以过孔的形式示出，绝缘层本身采用了透明化处理。
例如，参考图8，栅线113被配置为向像素电路10提供扫描信号SCAN。发光控制信号线110被配置为向像素单元P0提供发光控制信号EM。数据线313被配置为向像素电路10提供数据信号DATA，第一电源线311被配置为向像素电路10提供恒定的第一电压信号ELVDD，第二电源线312被配置为向像素电路10提供恒定的第二电压信号ELVSS，并且第一电压信号ELVDD大于第二电压信号ELVSS。初始化信号线210被配置为向像素电路10提供初始化信号Vint。初始化信号Vint为恒定的电压信号，其大小例如可以介于第一电压信号ELVDD和第二电压信号ELVSS之间，但不限于此，例如，初始化信号Vint可小于或等于第二电压信号ELVSS。例如，像素电路在扫描信号SCAN、数据信号DATA、初始化信号Vint、第一电压信号ELVDD、第二电压信号ELVSS、发光控制信号EM等信号的控制下输出驱动电流以驱动发光元件20发光。发光元件20在其对应的像素电路10的驱动下发出红光、绿光、蓝光，或者白光等。
如图8所示，该像素电路10包括驱动晶体管T1、数据写入晶体管T2、阈值补偿晶体管T3、第一发光控制晶体管T4、第二发光控制晶体管T5、第一复位晶体管T6、第二复位晶体管T7以及存储电容C1。驱动晶体管T1与发光元件20电连接，并在扫描信号SCAN、数据信号DATA、第一电压信号ELVDD、第二电压信号ELVSS等信号的控制下输出驱动电流以驱动发光元件20发光。
例如，本公开实施例提供的显示面板还包括：数据驱动电路和扫描驱动电路。数据驱动电路被配置为根据控制电路的指令向像素单元P0提供数据信号DATA；扫描驱动电路被配置为根据控制电路的指令向像素单元P0提供发光控制信号EM、扫描信号SCAN以及复位控制信号RESET等信号。例如，控制电路包括外部集成电路(IC)，但不限于此。例如，扫描驱动电路为安装于该显示面板上的GOA(Gate driver On Array)结构，或者为与该显示面板进行绑定(Bonding)的驱动芯片(IC)结构。例如，还可以采用不同的驱动电路分别提供发光控制信号EM和扫描信号SCAN。例如，显示面板还包括电源(图中未示出)以提供上述电压信号，根据需要可以为电压源或电流源，所述电源被配置为分别通过第一电源线311、第二电源线312、以及初始化信号线210向像素单元P0提供第一电压信号ELVDD、第二电源电压ELVSS、以及初始化信号Vint等。
如图8所示，存储电容C1的第二极C12与第一电源线311电连接，存储电容C1的第一极C11与阈值补偿晶体管T3的第二极T32电连接。数据写入晶体管T2的栅极T20与栅线113电连接，数据写入晶体管T2的第一极T21与第二极T22分别与数据线313、驱动晶体管T1的第一极T11电连接。阈值补偿晶体管T3的栅极T30与栅线113电连接，阈值补偿晶体管T3的第一极T31与驱动晶体管T1的第二极T12电连接，阈值补偿晶体管T3的第二极T32与驱动晶体管T1的栅极T10电连接。
例如，如图8所示，第一发光控制晶体管T4的栅极T40和第二发光控制晶体管T5的栅极T50均与发光控制信号线110相连。
例如，如图8所示，第一发光控制晶体管T4的第一极T41与第二极T42分别与第一电源线311和驱动晶体管T1的第一极T11电连接。第二发光控制晶体管T5的第一极T51与第二极T52分别与驱动晶体管T1的第二极T12、发光元件20的像素电极E1(可为OLED的阳极)电连接。发光元件20的公共电极E2(可为OLED的公共电极，例如阴极)与第二电源线312电连接。
例如，如图8所示，第一复位晶体管T6的栅极T60与第一复位控制信号线111电连接，第一复位晶体管T6的第一极T61与初始化信号线210(第一初始化信号线211)电连接，第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极T10电连接。第二复位晶体管T7的栅极T70与第二复位控制信号线112电连接，第二复位晶体管T7的第一极T71与初始化信号线210(第二初始化信号线212)电连接，第二复位晶体管T7的第二极T72与发光元件20的像素电极E1电连接。
图9示出了半导体图形SCP，图10示出了第一导电图案层LY1，第一导电图案层LY1和半导体图形SCP之间设置有第一栅绝缘层。以第一导电图案层LY1为掩模版对半导体图形SCP进行掺杂，使得半导体图形SCP的未被第一导电图案层LY1覆盖的区域保留半导体特性，形成薄膜晶体管的沟道，而半导体图形SCP的被第一导电图案层LY1覆盖的区域被导体化，形成薄膜晶体管的源极或者漏极。如17示出了半导体图形SCP被部分导体化之后形成的有源层ALT。
如图10所示，第一导电图案层LY1包括第一复位控制信号线111、第二复位控制信号线112、发光控制信号线110、栅线113和存储电容C1的第一极C11。图10还示出了第一数据线DL1的第一部分DL11(导线114)。图10还示出了栅线GL0，栅线GL0为从第二显示区域延伸至第一显示区域的栅线的一部分。例如，参考图19，在本公开的实施例中，第一复位控制信号线111和第二复位控制信号线112相连。
图11示出了第二导电图案层LY2，第二导电图案层LY2和第一导电图案层LY1之间设置有第二栅极绝缘层。第二导电图案层LY2包括挡块BK0、挡块BK1、初始化信号线210和存储电容C1的第二极C12。存储电容C1的第二极C12具有开口OPN。初始化信号线210包括第一初始化信号线211和第二初始化信号线212。如图11所示，第二导电图案层LY2包括第一导线L1的第一部分L11和第三部分L13。如图11所示，挡块BK0从第一导线L1延伸而出。图12示出了第一绝缘层ISL1的图形，图中的点状物为第一绝缘层ISL1中的过孔，第一绝缘层ISL1包括第一栅绝缘层、第二栅绝缘层和层间绝缘层至少之一。层间绝缘层位于第二导电图案层LY2和第三导电图案层LY3之间。有关于第一栅绝缘层、第二栅绝缘层和层间绝缘层、第一导电图案层LY1、第二导电图案层LY2和第三导电图案层LY3可参照图24和图25所示。图18示出了形成第一绝缘层ISL1后的平面示意图。
图13示出了第三导电图案层LY3，第三导电图案层LY3包括第三导线L3(第一电源线311的一部分)、数据线的第二部分DL12(数据线313的一部分)，第一连接电极31a、第二连接电极31b、第三连接电极31c和第四连接电极31d。如图13所示，第三导电图案层LY3还包括第一导线L1的第二部分L12。第一导线L1的第一部分L11和第三部分L13通过第二部分L12相连。
参考图13、图17、图18、图19，数据线313通过过孔V4与数据写入晶体管T2的第一极T21电连接，第一电源线311通过过孔V3与第一发光控制晶体管T4的第一极T41电连接，第一电源线311通过过孔V6与存储电容C1的第二极C12电连接，第一电源线311通过过孔V5与导电块BK1电连接。第一连接电极31a的一端通过过孔V11与第一初始化信号线211电连接，第一连接电极31a的另一端通过过孔V12与第一复位晶体管T6的第一极T61相连，进而使得第一复位晶体管T6的第一极T61与第一初始化信号线211电连接。第二连接电极31b的一端通过过孔V21与第一复位晶体管T6的第二极T62电连接，第二连接电极31b的另一端通过过孔V22与驱动晶体管T1的栅极T10(也即存储电容C1的第一极C11)电连接，从而使得第一复位晶体管T6的第二极T62与驱动晶体管T1的栅极 T10(也即存储电容C1的第一极C11)电连接。第三连接电极31c的一端通过过孔V31与第二初始化信号线212电连接，第三连接电极31c的另一端通过过孔V32与第二复位晶体管T7的第一极T71相连，进而使得第二复位晶体管T7的第一极T71与第一初始化信号线211电连接。第四连接电极31d通过过孔V1与第二发光控制晶体管T5的第二极T52电连接。第四连接电极31d可用来与后续形成的发光元件20的像素电极E1(参照图8)电连接。
图14示出了第二绝缘层ISL2，图14中的点状物为第二绝缘层ISL2中的过孔V1。如图14所示，过孔V1包括过孔V10、过孔V20、过孔V30和过孔V40。图20为形成第二绝缘层后的平面图。
图15示出了电极层ETL。电极层ETL包括多个像素电极E1。电极层ETL包括第一像素单元101的像素电极E11、第二像素单元102的像素电极E12、第三像素单元103的像素电极E13和第四像素单元104的像素电极E14。第一像素单元101的像素电极E11通过过孔V10与对应的第四连接电极31d相连，第二像素单元102的像素电极E12通过过孔V20与对应的第四连接电极31d相连，第三像素单元103的像素电极E13通过过孔V30与对应的第四连接电极31d相连，第四像素单元104的像素电极E14通过过孔V40与对应的第四连接电极31d相连。图21为形成电极层后的显示面板的平面图。
参考图15和图22，第四像素单元104的像素电极E14包括增补部E0，增补部E0在衬底基板上的正投影可以覆盖数据写入晶体管T2和第一发光控制晶体管T4的共用电极(数据写入晶体管T2的第二极T22和第一发光控制晶体管T4的第二极T42)在衬底基板上的正投影，以提高数据写入晶体管T2和第一发光控制晶体管T4的稳定性和寿命，从而可提高该显示面板的长期发光稳定性和寿命。
图16示出了像素定义层的平面图。如图16所示，像素定义层PDL包括多个开口，多个开口包括开口OPN1、开口OPN2、开口OPN3和开口OPN4。图22示出了形成像素定义层后的显示面板的示意图。如图22所示，开口OPN1暴露像素电极E11的一部分，开口OPN2暴露像素电极E12的一部分，开口OPN3暴露像素电极E13的一部分，开口OPN4暴露像素电极E14的一部分。在后续的工艺中，形成发光功能层和公共电极，进而形成发光元件EMC。
需要说明的是，本公开一实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开一实施例中，为了区分晶体管除栅极之外的两极，直接描述了其中一极为第一极，另一极为第二极，所以本公开实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。例如，本公开实施例所述的晶体管的第一极可以为源极，第二极可以为漏极；或者，晶体管的第一极为漏极，第二极为源极。
此外，按照晶体管的特性区分可以将晶体管分为N型和P型晶体管。本公开实施例以晶体管均采用P型晶体管为例进行说明。基于本公开对该实现方式的描述和教导，本领域普通技术人员在无需做出创造性劳动前提下，能够容易想到将本公开实施例的像素电路中至少部分晶体管采用N型晶体管，即采用N型晶体管或N型晶体管和P型晶体管组合的实现方式，因此，这些实现方式也是在本公开的保护范围内的。
图8至图25以7T1C的像素电路为例进行说明，本公开的实施例包括但不限于此。需要说明的是，本公开的实施例对像素电路包括的薄膜晶体管的个数以及电容的个数不做限定。例如，在另外的一些实施例中，显示基面板的像素电路还可以为包括其他数量的晶体管的结构，如7T2C结构、6T1C结构、 6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图25为本公开一实施例提供的显示面板的剖视示意图。例如，如图25所示，显示面板包括薄膜晶体管50和存储电容C1。薄膜晶体管50包括位于衬底基板BS上的有源层ATL1，位于有源层ATL1远离衬底基板BS一侧的第一栅绝缘层GI1，位于第一栅绝缘层GI1远离衬底基板BS一侧的栅极GE。显示面板还包括位于栅极GE远离衬底基板BS一侧的第二栅绝缘层GI2，位于第二栅绝缘层GI2远离衬底基板BS一侧的层间绝缘层ILD，以及位于层间绝缘层ILD远离衬底基板BS一侧的连接电极CNE1。有源层ATL1包括沟道CN11以及分别位于沟道CN11两侧的第一极ET1和第二极ET2，连接电极CNE1通过贯穿的第一栅绝缘层GI1、第二栅绝缘层GI2以及层间绝缘层ILD的过孔与第二极ET2相连。存储电容C1包括第一极C11和第二极C12，第一极C11和栅极GE位于同一层，均位于第一导电图案层LY1，第二极C12位于第二栅绝缘层GI2和层间绝缘层ILD之间，位于第二导电图案层LY2。第一极ET1和第二极ET2之一为源极，第一极ET1和第二极ET2之另一为漏极。连接电极CNE1位于第三导电图案层LY3。显示面板还包括钝化层PVX和平坦化层PLN。例如，连接电极CNE1为上述第四连接电极31d，薄膜晶体管50可为上述第二发光控制晶体管T5。
如图25所示，显示面板还包括发光元件EMC，发光元件EMC包括像素电极E1、发光功能层EML和公共电极E2，像素电极E1通过贯穿钝化层PVX和平坦化层PLN的过孔与连接电极CNE1相连。显示面板还包括封装层CPS，封装层CPS包括第一封装层CPS1、第二封装层CPS2以及第三封装层CPS3。例如，第一封装层CPS1和第三封装层CPS3为无机材料层，第二封装层CPS2为有机材料层。例如，像素电极E1为阳极，公共电极E2为阴极，但不限于此。
例如，发光元件EMC包括有机发光二极管。发光功能层位于公共电极E2和像素电极E1之间。发光功能层EML至少包括发光层，还可以包括空穴传输层、空穴注入层，电子传输层、电子注入层至少之一。
如图25所示，显示面板还包括像素定义层PDL和隔垫物PS。像素定义层PDL具有开口，开口被配置为限定像素单元的发光面积(出光区域，有效发光面积)，隔垫物PS被配置为在形成发光功能层EML时支撑精细金属掩膜。图25示出了发光元件相对的两侧均设置隔垫物PS，但不限于此。
例如，数据线被配置为向像素单元输入数据信号，第一电源信号线被配置为向驱动晶体管输入第一电源电压。第二电源信号线被配置为向像素单元输入第二电源电压。第一电源电压为恒定电压，第二电源电压为恒定电压，例如，第一电源电压为正电压，第二电源电压为负电压，但不限于此。例如，在一些实施例中，第一电源电压为正电压，第二电源信号线接地。
参考图25，本公开的实施例中，第一绝缘层ISL1包括第一栅极绝缘层GI1、第二栅极绝缘层GI2和层间绝缘层ILD至少之一，第二绝缘层ISL2包括平坦化层PLN。
例如，第一栅极绝缘层GI1、第二栅极绝缘层GI2、层间绝缘层ILD、钝化层PVX、平坦化层PLN、像素定义层PDL和隔垫物PS均采用绝缘材料制作。例如，第一栅极绝缘层GI1、第二栅极绝缘层GI2、层间绝缘层ILD和钝化层PVX的材料包括SiOx和SiNx至少之一，但不限于此。例如，平坦化层PLN、像素定义层PDL和隔垫物PS可采用有机绝缘材料制作，例如，可采用树脂，但不限于此。
参考图17，阈值补偿晶体管T3包括第一沟道CN1和第二沟道CN2，第一沟道CN1和第二沟道CN2通过导电部CP相连。参考图18，第二导线L2还包括连接臂L21。阈值补偿晶体管T3为双栅晶 体管，导电部CP在阈值补偿晶体管T3关闭时处于浮接(floating)状态，易受周围线路电压的影响而跳变，导电部CP的电压跳变会影响阈值补偿晶体管T3的漏电流，进而影响像素单元的发光亮度，从而，需要保持导电部CP的电压稳定，可以设计挡块与导电部CP形成电容，挡块可具有恒定的电压信号，以使得处于浮接状态的导电部CP的电压亦保持稳定。本公开的实施例中提及的挡块BK0、挡块BK以及连接臂L21都起到稳定导电部CP的电压的作用。
参考图24，连接臂L21与阈值补偿晶体管T3的导电部CP部分重叠以形成电容C0，连接臂L21与导电部CP之间设置有第一栅绝缘层GI1和第二栅绝缘层GI2。图24还示出了第二沟道CN2。电容C0可称作稳定电容，连接臂L21与导电部CP为电容C0的两个极板。如图24所示，栅极GE2与第二沟道CN2在垂直于衬底基板BS的方向上重叠。栅极GE2为阈值补偿晶体管T3的一个栅极。如图24所示，第二连接电极31b与阈值补偿晶体管T3的第二极T32相连。
参考图19，第二导线L2还包括连接臂L21，连接臂L21与导电部CP在第三方向D3上彼此间隔，且在第三方向D3上部分重叠(参照图24)。例如，连接臂L21的形状包括C型。需要说明的是，连接臂L21大体呈C型即可，当然，连接臂L21也可以采用其他形状，只要能够起到稳定阈值补偿晶体管T3的作用即可。
例如，第三方向D3垂直于第一方向D1，并且垂直于第二方向D2，第三方向D3为垂直于衬底基板BS的方向，连接臂L21与导电部CP之间设置有第一栅绝缘层GI1和第二栅绝缘层GI2。例如，第一方向D1和第二方向D2为平行于衬底基板BS的主表面的方向，第三方向D3为垂直于衬底基板BS的主表面的方向。在衬底基板BS的主表面上制作各种元件。
参考图11、图19和图24，第一部分L11包括沿第一方向D1延伸的第一子部La和沿第二方向延伸的第二子部Lb，第二子部Lb具有分支，分支沿第一方向D1延伸，挡块BK0即为第二子部Lb的分支。参考图17、图19和图24，第二子部Lb的分支(挡块BK0)与像素岛中的与第一导线L1交叠的一个像素单元的导电部在第三方向D3上彼此间隔，且在第三方向D3上部分重叠。参考图17、图19和图24，第二子部Lb的分支(挡块BK0)与像素岛中的与第一导线L1交叠的一个像素单元(图24中左上角的像素单元)的导电部CP在第三方向D3上彼此间隔，且在第三方向D3上部分重叠。例如，分支(挡块BK0)在第一方向D1上的长度小于第一子部La在第一方向D1上的长度。
例如，参考图8、图17、图19和图24，像素电路10包括第一晶体管和第二晶体管，第一晶体管与第二晶体管相连，第二晶体管与发光元件相连，第一晶体管包括第一沟道CN1和第二沟道CN2，第一沟道CN1和第二沟道CN2通过导电部CP相连，第二导线L2还包括连接臂L21，连接臂L21与像素岛中的与第二导线L2交叠的一个像素单元(图19中位于左下角的像素单元)的导电部CP在第三方向D3上彼此间隔，且在第三方向D3上部分重叠。例如，上述的第一晶体管和第二晶体管分别为像素电路10中的阈值补偿晶体管T3和与发光元件相连的发光控制晶体管。例如，与发光元件相连的发光控制晶体管为上述的第二发光控制晶体管T5。当然，在本公开的其他实施例中，与像素岛中的第一晶体管中的导电部CP形成电容的挡块或者连接臂也可以采用其他的形式，在此不做限定。
例如，参考图19，在本公开的实施例中，挡块BK0(第二子部Lb的分支)和连接臂L21均连接至本列像素单元的第三导线L3，而挡块BK连接至其所遮挡的导电部所在的像素单元列的相邻列的第三导线。即，如图19所示，挡块BK0(第二子部Lb的分支)、连接臂L21和挡块BK均连接至同一 第三导线L3。
例如，如图11所示，初始化信号线210包括多个镂空区域HP，第二导线L2位于一个镂空区域HP内，并被初始化信号线的围成该镂空区域HP的部分包围，第二导线L2与初始化信号线的围成该镂空区域的部分不交叠。即，第二导线L2被初始化信号线的围成该镂空区域HP的部分完全包围。在本公开的实施例中，镂空区域HP为在制作初始化信号线210时，去除的薄膜的部分对应的位置。
例如，参考图11、图13和图19，第一导线L1包括第一部分L11和第二部分L12，第一导线L1的第一部分L11与第二导线L2位于同一层，第一导线L1的第二部分L12不与第二导线L2位于同一层，第一导线L1的第二部分L12与初始化信号线210至少部分交叠。参考图11、图13和图19，第一导线L1的第一部分L11与第二导线L2位于均位于第二导电图案层LY2，第一导线L1的第二部分L12位于第三导电图案层LY3。
例如，参考图11、图13和图19，第二导线L2被初始化信号线210的一部分环绕，第一导线L1的第一部分L11被初始化信号线210的一部分环绕。参考图11、图13和图19，第二导线L2被初始化信号线210的位于下侧的部分210a环绕，第一导线L1的第一部分L11被初始化信号线210的位于上侧的部分210b环绕。
例如，参考图3和图19，数据线313包括第一数据线DL1，第一数据线DL1从第一显示区域R1延伸至第二显示区域R2，第一数据线DL1与第三导线L3在衬底基板BS上的正投影部分交叠。该种设置方式利于减少布线面积，提高光的透过率。
例如，参考图13、图18、图19，第一数据线DL1包括第一部分DL11和第二部分DL12，第一数据线DL1的第一部分DL11与第三导线L3部分交叠，第一数据线DL1的第二部分DL12与第三导线L4不交叠，第一数据线DL1的第一部分DL11和第一数据线DL1的第二部分DL12分别位于不同的层。例如，图19中左侧的第一数据线DL1的第一部分DL11(导线214)位于第二导电图案层，左侧的第一数据线DL1的第二部分DL12位于第三导电图案层，图19中右侧的第一数据线DL1的第一部分DL11(导线114)位于第一导电图案层，右侧的第一数据线DL1的第二部分DL12位于第三导电图案层。例如，参考图3、图19和图23，第一数据线DL1的第一部分DL11位于相邻像素岛A1之间。
例如，参考图13和图19，提供两条第一数据线DL1，两条第一数据线DL1分别与相邻两列像素单元相连，两条第一数据线DL1与同一条第三导线L3在衬底基板BS上的正投影部分交叠。该种设置方式使得相邻两列像素单元中位于像素岛之间的数据线可以藏在第三导线之下，从而，减小布线面积，提高光的透过率。
例如，第一导线L1包括位于不同层的部分，位于不同层的部分通过贯穿绝缘层的过孔相连。参考图19，第一导线L1包括第一部分L11、第二部分L12和第三部分L13。第一部分L11和第三部分L13位于第二导电图案层LY2，第二部分L12位于第三导电图案层LY3。第一部分L11和第二部分L12通过贯穿绝缘层的过孔V41相连，第三部分L13和第二部分L12通过贯穿绝缘层的过孔V42相连。参考图24和图25，第二导电图案层LY2和第三导电图案层LY3之间设置有层间介电层ILD，即过孔V41贯穿层间介电层ILD，过孔V42贯穿层间介电层ILD。
例如，参考图19，第一导线L1的一部分(第二部分L12)与第三导线L3位于同一层，均位于第三导电图案层LY3。第四导线L4与第三导线L3位于同一层，均位于第三导电图案层LY3。
本公开至少一实施例还提供一种显示装置，包括上述任一显示面板。例如，显示装置可以为有机发光二极管(Organic Light-Emitting Diode，OLED)显示器等显示器件以及包括这些显示器件的电视、数码相机、手机、手表、平板电脑、笔记本电脑、导航仪等任何具有显示功能的产品或者部件。
例如，在本公开的实施例中，第一导线L1可包括位于第一导电图案层的部分和位于第二导电图案层的部分，第二导线L2仅由位于第二导电图案层的部分构成，第三导线L3仅由位于第三导电图案层的部分构成，第四导线L43仅由位于第三导电图案层的部分构成，第五导线L5可包括位于第一导电图案层的部分和位于第二导电图案层的部分构成，但不限于此，可根据需要进行设置。
例如，参考图11和图19，在本公开的实施例中，像素单元P0的存储电容C1的第二极C12为第二导线L2的一部分或者为第一导线L1的一部分。
有以下几点需要说明：
(1)除非另作定义，本公开实施例以及附图中，同一附图标记代表同一含义。
(2)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(3)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(4)在不冲突的情况下，本公开的同一实施例及不同实施例中的特征可以相互组合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种显示面板，包括：
    第一显示区域；
    第二显示区域，至少位于所述第一显示区域的一侧；
    多个像素单元，位于所述第一显示区域和所述第二显示区域，所述第一显示区域的像素单元的密度小于所述第二显示区域的像素单元的密度，所述像素单元包括像素电路；以及
    第一电源线，被配置为向所述像素电路提供第一电压信号，
    其中，所述第一电源线包括多条第一导线、多条第二导线和多条第三导线，所述第一导线从所述第二显示区域延伸至所述第一显示区域，所述多条第二导线位于所述第一显示区域，并且位于相邻第一导线之间，所述第二导线沿第一方向延伸，所述第三导线沿第二方向延伸，所述第一方向与所述第二方向相交，所述第三导线从所述第二显示区域延伸至所述第一显示区域，并且
    相邻第二导线沿所述第一方向彼此间隔，所述第二导线通过所述第三导线与所述第一导线相连。
  2. 根据权利要求1所述的显示面板，其中，所述多条第二导线沿所述第一方向依次排列。
  3. 根据权利要求1或2所述的显示面板，其中，所述相邻第二导线不直接相连。
  4. 根据权利要求1-3任一项所述的显示面板，其中，所述第一导线的位于所述第一显示区域的部分在所述第一方向上的长度大于所述第二导线在所述第一方向上的长度。
  5. 根据权利要求1-4任一项所述的显示面板，其中，所述第一导线包括位于不同层的部分，所述位于不同层的部分通过贯穿绝缘层的过孔相连。
  6. 根据权利要求1-5任一项所述的显示面板，其中，所述第一电源线还包括第四导线，所述第四导线沿所述第二方向延伸，所述第二导线通过所述第四导线连接至所述第一导线，所述第四导线在所述第二方向上的长度小于或等于所述第三导线在所述第二方向上的长度。
  7. 根据权利要求1-6任一项所述的显示面板，其中，包括多条第四导线，所述多条第四导线位于相邻第三导线之间，所述多条第四导线沿所述第二方向依次排列，相邻第四导线在所述第二方向上彼此间隔。
  8. 根据权利要求6或7所述的显示面板，其中，所述第一导线的一部分与所述第三导线位于同一层，所述第四导线与所述第三导线位于同一层。
  9. 根据权利要求1-8任一项所述的显示面板，其中，位于所述第一显示区域的像素单元构成多个像素岛，所述像素岛至少包括位于相邻两行的两个像素单元，所述第一导线和所述第二导线分别与位于所述相邻两行的两个像素单元交叠。
  10. 根据权利要求9所述的显示面板，其中，所述像素单元还包括发光元件，所述像素电路包括第一晶体管和第二晶体管，所述第一晶体管与所述第二晶体管相连，所述第二晶体管与所述发光元件相连，所述第一晶体管包括第一沟道和第二沟道，所述第一沟道和所述第二沟道通过导电部相连，所述第二导线还包括连接臂，所述连接臂与所述像素岛中的与所述第二导线交叠的一个像素单元的所述导电部在第三方向上彼此间隔，且在所述第三方向上部分重叠，所述第三方向垂直于所述第一方向，并且垂直于所述第二方向。
  11. 根据权利要求10所述的显示面板，其中，所述连接臂的形状包括C型。
  12. 根据权利要求10或11所述的显示面板，其中，所述第一导线具有分支，所述分支与所述像素岛中的与所述第一导线交叠的一个像素单元的所述导电部在所述第三方向上彼此间隔，且在所述第三方向上部分重叠。
  13. 根据权利要求1-12任一项所述的显示面板，其中，所述第一方向垂直于所述第二方向。
  14. 根据权利要求1-13任一项所述的显示面板，其中，所述第一电源线还包括第五导线，所述第五导线沿所述第一方向延伸，所述第五导线位于所述第二显示区域，所述第五导线位于相邻第一导线之间，所述第五导线和与其相邻的第二导线沿所述第一方向彼此间隔。
  15. 根据权利要求9所述的显示面板，还包括初始化信号线，所述初始化信号线被配置为向所述像素电路提供初始化信号，其中，所述第二导线被所述初始化信号线的一部分环绕。
  16. 根据权利要求15所述的显示面板，其中，所述第一导线包括第一部分和第二部分，所述第一导线的第一部分与所述第二导线位于同一层，所述第一导线的第二部分不与所述第二导线位于同一层，所述第一导线的所述第一部分被所述初始化信号线的一部分环绕。
  17. 根据权利要求16所述的显示面板，其中，所述第一导线的所述第一部分具有沿所述第一方向延伸的第一子部和沿所述第二方向延伸的第二子部，所述第二子部具有分支，所述分支沿所述第一方向延伸。
  18. 根据权利要求17所述的显示面板，其中，所述分支在所述第一方向上的长度小于所述第一子部在所述第一方向上的长度。
  19. 根据权利要求16-18任一项所述的显示面板，其中，所述像素单元还包括发光元件，所述像素电路包括第一晶体管和第二晶体管，所述第一晶体管与所述第二晶体管相连，所述第二晶体管与所述发光元件相连，所述第一晶体管包括第一沟道和第二沟道，所述第一沟道和所述第二沟道通过导电部相连，所述分支与所述像素岛中的与所述第一导线交叠的一个像素单元的所述导电部在所述第三方向上彼此间隔，且在所述第三方向上部分重叠，所述第三方向垂直于所述第一方向，并且垂直于所述第二方向。
  20. 根据权利要求19所述的显示面板，其中，所述第二导线还包括连接臂，所述连接臂与所述像素岛中的与所述第二导线交叠的一个像素单元的所述导电部在第三方向上彼此间隔，且在所述第三方向上部分重叠。
  21. 根据权利要求9所述的显示面板，还包括衬底基板和数据线，其中，所述数据线被配置为向所述像素电路提供数据信号，所述数据线包括第一数据线，其中，所述第一数据线从所述第一显示区域延伸至所述第二显示区域，所述第一数据线与所述第三导线在所述衬底基板上的正投影部分交叠。
  22. 根据权利要求21所述的显示面板，其中，所述第一数据线包括第一部分和第二部分，所述第一数据线的所述第一部分与所述第三导线部分交叠，所述第一数据线的所述第二部分与所述第三导线不交叠，所述第一数据线的所述第一部分和所述第一数据线的所述第二部分分别位于不同的层。
  23. 根据权利要求22所述的显示面板，其中，相邻像素岛之间具有透光区域，所述第一数据线的所述第一部分位于相邻像素岛之间。
  24. 根据权利要求21-23任一项所述的显示面板，其中，提供两条第一数据线，所述两条第一数据线分别与相邻两列像素单元相连，所述两条第一数据线与同一条第三导线在所述衬底基板上的正投 影部分交叠。
  25. 根据权利要求21-24任一项所述的显示面板，还包括栅线，其中，所述栅线被配置为向一行像素单元提供扫描信号，所述栅线包括第一栅线，所述第一栅线从所述第二显示区域延伸至所述第一显示区域，所述透光区域由两条相邻第一栅线以及两条相邻第一数据线围设而成。
  26. 一种显示装置，包括权利要求1-25任一项所述的显示面板。
PCT/CN2021/094383 2020-06-04 2021-05-18 显示面板和显示装置 WO2021244279A1 (zh)

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