WO2021238711A1 - 发光二极管及其驱动方法、光源装置及电子设备 - Google Patents

发光二极管及其驱动方法、光源装置及电子设备 Download PDF

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WO2021238711A1
WO2021238711A1 PCT/CN2021/094199 CN2021094199W WO2021238711A1 WO 2021238711 A1 WO2021238711 A1 WO 2021238711A1 CN 2021094199 W CN2021094199 W CN 2021094199W WO 2021238711 A1 WO2021238711 A1 WO 2021238711A1
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layer
electrode
type semiconductor
light
reflective
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PCT/CN2021/094199
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English (en)
French (fr)
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解潇
刘洋
陈华斌
李兴亮
高英强
王琳琳
王瑞瑞
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京东方科技集团股份有限公司
北京京东方显示技术有限公司
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Priority to US17/762,654 priority Critical patent/US20220344537A1/en
Publication of WO2021238711A1 publication Critical patent/WO2021238711A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0756—Stacked arrangements of devices
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
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    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

Definitions

  • the present disclosure relates to the field of semiconductor technology, and in particular to a light emitting diode and a driving method thereof, a light source device and electronic equipment.
  • LED Light Emitting Diode
  • LED is a commonly used light emitting device that can emit energy through the recombination of electrons and holes to emit light. It is widely used in many fields such as lighting, display, and medical treatment. Light-emitting diodes can efficiently convert electrical energy into light energy and have a wide range of uses in modern society.
  • the present disclosure provides a light emitting diode and a driving method thereof, a light source device and electronic equipment.
  • the present disclosure discloses a light emitting diode, including:
  • a reflective light-emitting layer, the reflective light-emitting layer is disposed on the substrate;
  • a first electrode, a second electrode and a first insulating layer, the first electrode, the second electrode and the first insulating layer are separately arranged on the reflective light-emitting layer;
  • a saturable absorber layer, the saturable absorber layer is disposed on the first insulating layer;
  • the third electrode, the fourth electrode and the reflective composite layer, the third electrode, the fourth electrode and the reflective composite layer are separately arranged on the saturable absorber layer, and the reflectivity of the reflective light-emitting layer is greater than The reflectivity of the reflective composite layer;
  • the orthographic projection of the saturable absorber layer, the third electrode, the fourth electrode, and the reflective composite layer on the reflective light-emitting layer is the same as that of the first electrode and the second electrode. None overlap.
  • the saturable absorber layer includes:
  • a first P-type semiconductor layer, the first P-type semiconductor layer is disposed on the first insulating layer, and the third electrode is disposed on the first P-type semiconductor layer;
  • the first quantum well layer, the first quantum well layer is disposed on the first P-type semiconductor layer, the orthographic projection of the first quantum well layer on the first P-type semiconductor layer and the third The electrodes do not overlap;
  • a first N-type semiconductor layer, the first N-type semiconductor layer is disposed on the first quantum well layer, and the orthographic projection of the first N-type semiconductor layer on the first P-type semiconductor layer and the The third electrode does not overlap, and the fourth electrode is disposed on the first N-type semiconductor layer.
  • the reflective light-emitting layer includes:
  • a P-type semiconductor reflective composite layer, the P-type semiconductor reflective composite layer is arranged on the substrate, and the first electrode is arranged on the P-type semiconductor reflective composite layer;
  • the second quantum well layer is arranged on the P-type semiconductor reflective composite layer, and the orthographic projection of the second quantum well layer on the P-type semiconductor reflective composite layer is the same as that of the first The electrodes do not overlap;
  • a second N-type semiconductor layer, the second N-type semiconductor layer is disposed on the second quantum well layer, and the orthographic projection of the second N-type semiconductor layer on the P-type semiconductor reflective composite layer is consistent with the The first electrode does not overlap, and the second electrode is disposed on the second N-type semiconductor layer.
  • the P-type semiconductor reflective composite layer has a mirror structure
  • the P-type semiconductor reflective composite layer includes a stacked second P-type semiconductor layer and a first mirror layer, wherein the first mirror layer is disposed close to the substrate.
  • the light emitting diode further includes:
  • optical amplifier layer the optical amplifier layer is arranged on the reflective composite layer
  • a fifth electrode and a sixth electrode, the fifth electrode and the sixth electrode are separately arranged on the optical amplifier layer;
  • the orthographic projections of the optical amplifier layer, the fifth electrode and the sixth electrode on the reflective light-emitting layer respectively do not overlap with the first electrode and the second electrode; the optical amplifier The orthographic projections of the layer, the fifth electrode and the sixth electrode on the saturable absorber layer respectively do not overlap with the third electrode and the fourth electrode.
  • the optical amplifier layer includes:
  • a third P-type semiconductor layer, the third P-type semiconductor layer is disposed on the reflective composite layer, and the fifth electrode is disposed on the third P-type semiconductor layer;
  • the third quantum well layer, the third quantum well layer is disposed on the third P-type semiconductor layer, and the orthographic projection of the third quantum well layer on the third P-type semiconductor layer is the same as that of the fifth The electrodes do not overlap;
  • the third N-type semiconductor layer, the third N-type semiconductor layer is disposed on the third quantum well layer, and the orthographic projection of the third N-type semiconductor layer on the third P-type semiconductor layer is the same as the The fifth electrode does not overlap, and the sixth electrode is disposed on the third N-type semiconductor layer.
  • the fifth electrode and the sixth electrode are the anode and the cathode of the optical amplifier layer, respectively.
  • the reflective composite layer has a mirror structure and is made of insulating material; or,
  • the reflective composite layer includes a second insulating layer and a second mirror layer that are stacked.
  • the first electrode and the second electrode are respectively an anode and a cathode of the reflective light-emitting layer
  • the third electrode and the fourth electrode are respectively a cathode and a cathode of the saturable absorber layer. anode.
  • the present disclosure also discloses a driving method for driving the above-mentioned light emitting diode, and the method includes:
  • a first positive voltage is input to the first electrode, and a first negative voltage is input to the second electrode.
  • the method further includes:
  • the second negative voltage is input to the third electrode, and the second positive voltage is input to the fourth electrode.
  • the light emitting diode further includes an optical amplifier layer, a fifth electrode and a sixth electrode, and the method further includes:
  • a third positive voltage is input to the fifth electrode, and a third negative voltage is input to the sixth electrode.
  • the present disclosure also discloses a computing processing device, which includes:
  • a memory in which computer-readable codes are stored
  • One or more processors when the computer-readable code is executed by the one or more processors, the computing processing device executes the aforementioned driving method.
  • the present disclosure also discloses a computer program, including computer-readable code, which when the computer-readable code runs on a computing processing device, causes the computing processing device to execute the above-mentioned driving method.
  • the present disclosure also discloses a computer-readable medium in which the above-mentioned computer program is stored.
  • the present disclosure also discloses a light source device, which includes the above-mentioned light-emitting diode.
  • the present disclosure also discloses an electronic device, including the above-mentioned light source device.
  • Fig. 1 shows a schematic cross-sectional view of a light emitting diode according to an embodiment of the present disclosure
  • FIG. 2 shows a schematic diagram of spectral changes before and after the light emitted by a reflective light-emitting layer passes through a saturable absorber layer according to an embodiment of the present disclosure
  • Fig. 3 shows a schematic cross-sectional view of another light emitting diode according to an embodiment of the present disclosure
  • FIG. 4 shows a schematic cross-sectional view of another light-emitting diode according to an embodiment of the present disclosure
  • FIG. 5 shows a schematic diagram of spectrum changes before and after light emitted by a reflective light-emitting layer of an embodiment of the present disclosure sequentially passes through a saturable absorber layer and an optical amplifier layer;
  • FIG. 6 shows a schematic cross-sectional view of still another light-emitting diode according to an embodiment of the present disclosure
  • FIG. 7 shows a top view of an epitaxial wafer with three quantum well structures grown according to an embodiment of the present disclosure
  • FIG. 8 shows a schematic diagram of a photoresist covering area 01 and a light-emitting area 00 according to an embodiment of the present disclosure
  • FIG. 9 shows a schematic diagram of a photoresist covering area 01, area 02, and light-emitting area 00 according to an embodiment of the present disclosure
  • FIG. 10 shows a schematic diagram of a photoresist covering area 01, area 02, area 03, and light-emitting area 00 according to an embodiment of the present disclosure
  • FIG. 11 shows a schematic diagram of a photoresist covering area 01, area 02, area 03, area 04, and light-emitting area 00 according to an embodiment of the present disclosure
  • FIG. 12 shows a schematic diagram of a photoresist covering area 01, area 02, area 03, area 04, area 05, and light-emitting area 00 according to an embodiment of the present disclosure
  • FIG. 13 shows a top view of a light-emitting diode with electrodes provided in an embodiment of the present disclosure
  • FIG. 14 schematically shows a block diagram of a computing processing device for executing the method according to the present disclosure.
  • Fig. 15 schematically shows a storage unit for holding or carrying program codes for implementing the method according to the present disclosure.
  • FIG. 1 shows a schematic cross-sectional view of a light-emitting diode according to an embodiment of the present disclosure.
  • the light-emitting diode includes:
  • the reflective light-emitting layer 20 is disposed on the substrate 10;
  • the first electrode A, the second electrode B and the first insulating layer 30 are separately arranged on the reflective light-emitting layer 20;
  • the saturable absorber layer 40 is disposed on the first insulating layer 30;
  • the third electrode C, the fourth electrode D and the reflective composite layer 50 are separately arranged on the saturable absorber layer 40, and the reflectivity of the reflective light-emitting layer 20 is greater than the reflectivity of the reflective composite layer 50;
  • the reflective light-emitting layer 20 has the functions of reflecting light and emitting light.
  • the first electrode A and the second electrode B may serve as an anode and a cathode of the reflective light-emitting layer 20.
  • the third electrode C and the fourth electrode D may serve as a cathode and an anode of the saturable absorber layer 40.
  • the reflective composite layer 50 has the function of reflecting light.
  • the first electrode A, the second electrode B, the third electrode C, and the fourth electrode D all need to be exposed on the uppermost layer for wiring connection to receive the voltage signal used to control the corresponding layer, saturable absorption is required
  • the orthographic projections of the bulk layer 40, the third electrode C, the fourth electrode D, and the reflective composite layer 50 on the reflective light-emitting layer 20 do not overlap with the first electrode A and the second electrode B, so that the first electrode A and None of the second electrodes B will be blocked by the upper structure.
  • the embodiment of the present disclosure adds a saturable absorber layer 40.
  • a saturable absorber is a substance with non-linear absorption properties. The absorption coefficient of light is a function of light intensity. When the light intensity is small, its light absorption coefficient is very large, and it is basically opaque. When increasing to a certain value, its light absorption coefficient will suddenly decrease, appearing to be almost transparent. Therefore, in the embodiment of the present disclosure, a saturable absorber layer 40 is added to the related light emitting diode structure, that is, a saturable absorber is added to the light emitting layer of the related light emitting diode structure.
  • FIG. 2 shows a schematic diagram of the spectral changes before and after the light emitted by the reflective light-emitting layer passes through the saturable absorber layer according to an embodiment of the present disclosure.
  • FIG. 2 when the light emitted by the reflective light-emitting layer 20 passes through the saturable absorber layer 40, , Low-energy light absorbs more, and high-energy light absorbs less. Therefore, the half-height width FHWM of the light-emitting diode spectrum is reduced, thereby improving the color purity of the light-emitting diode.
  • the saturable absorber can be arranged between the two mirror structures, so that the reflected light can be emitted.
  • the light emitted by the layer 20 can be reflected multiple times between the two mirror structures, so that the light can be absorbed by the saturable absorber multiple times.
  • the reflective light-emitting layer 20 has the function of reflecting light and can be used as a mirror structure
  • the reflective composite layer 50 also has the function of reflecting light, and can be used as another mirror structure.
  • the saturable absorber layer 40 is located in Between the reflective light-emitting layer 20 and the reflective composite layer 50, the light emitted by the reflective light-emitting layer 20 can be absorbed multiple times, so that the function of the saturable absorber can be fully exerted, which is beneficial to reducing the half-width of the light-emitting diode spectrum.
  • the reflectivity of the reflective light-emitting layer 20 is greater than that of the reflective composite layer 50, so that the light emitted by the reflective light-emitting layer 20 can be absorbed and reflected by the saturable absorber layer 40 and the reflective composite layer 50 for multiple times.
  • the side away from the substrate 10 emits light.
  • the mirror structure can specifically be a distributed Bragg reflection (DBR) mirror structure.
  • the DBR mirror structure is a periodic structure composed of two materials with different refractive indexes alternately arranged in an ABAB manner. , The optical thickness of each layer of material is 1/4 of the central reflection wavelength.
  • the quantum well material can exhibit the characteristics of a saturable absorber when no voltage is applied or a reverse bias is applied. Therefore, the embodiments of the present disclosure can add a layer of non-toxicity to the related art light-emitting diode structure.
  • a quantum well structure with voltage or reverse bias applied adds a saturable absorber.
  • the saturable absorber layer 40 includes:
  • the first P-type semiconductor layer 41 is disposed on the first insulating layer 30, and the third electrode C is disposed on the first P-type semiconductor layer 41;
  • the first quantum well layer 42 is disposed on the first P-type semiconductor layer 41, and the orthographic projection of the first quantum well layer 42 on the first P-type semiconductor layer 41 is different from the third electrode C overlapping;
  • the first N-type semiconductor layer 43 is disposed on the first quantum well layer 42, and the orthographic projection of the first N-type semiconductor layer 43 on the first P-type semiconductor layer 41 and the third electrode C Without overlapping, the fourth electrode D is disposed on the first N-type semiconductor layer 43.
  • the first insulating layer 30 functions as an insulation between the reflective light-emitting layer 20 and the saturable absorber layer 40.
  • the third electrode C is connected to the first P-type semiconductor layer 41 to realize the control voltage input to the saturable absorber layer 40 through the first P-type semiconductor layer 41.
  • the fourth electrode D is connected to the first N-type semiconductor layer 43 to realize the control voltage input to the saturable absorber layer 40 through the first N-type semiconductor layer 43.
  • the orthographic projections of the first quantum well layer 42 and the first N-type semiconductor layer 43 respectively on the first P-type semiconductor layer 41 do not overlap with the third electrode C, so that the third electrode C is not blocked by the upper structure, and the movement is realized. ⁇ Wire connection.
  • a common quantum well structure usually applies a positive voltage to the P-type semiconductor layer and a negative voltage to the N-type semiconductor layer.
  • a negative voltage can be applied to the first P-type semiconductor layer 41 of the saturable absorber layer 40, and a positive voltage can be applied to the first N-type semiconductor layer 43, that is, a negative voltage can be input to the third electrode C, and a negative voltage can be applied to the third electrode C.
  • the forward voltage is input to the four electrodes D, so that the reverse bias voltage is applied to the saturable absorber layer 40.
  • the reflective light-emitting layer 20 includes:
  • the P-type semiconductor reflective composite layer 21 is provided on the substrate 10, and the first electrode A is provided on the P-type semiconductor reflective composite layer 21;
  • the second quantum well layer 22 is arranged on the P-type semiconductor reflective composite layer 21, and the orthographic projection of the second quantum well layer 22 on the P-type semiconductor reflective composite layer 21 is different from the first electrode A. overlapping;
  • the second N-type semiconductor layer 23 is disposed on the second quantum well layer 22.
  • the first electrode A is connected to the P-type semiconductor reflective composite layer 21 to realize the control voltage input to the reflective light-emitting layer 20 through the P-type semiconductor reflective composite layer 21.
  • the second electrode B is connected to the second N-type semiconductor layer 23 to realize the control voltage input to the reflective light-emitting layer 20 through the second N-type semiconductor layer 23.
  • the orthographic projections of the second quantum well layer 22 and the second N-type semiconductor layer 23 respectively on the P-type semiconductor reflective composite layer 21 do not overlap with the first electrode A, so that the first electrode A is not blocked by the upper layer structure, so as to realize walking ⁇ Wire connection.
  • the P-type semiconductor reflective composite layer 21 has a mirror structure; or, referring to FIG. 3, a schematic cross-sectional view of another light-emitting diode according to an embodiment of the present disclosure is shown, and the P-type semiconductor reflective composite layer 21 It includes a second P-type semiconductor layer 21 a and a first mirror layer 21 b that are arranged in a stack, wherein the first mirror layer 21 b is arranged close to the substrate 10.
  • the first electrode A is disposed on the second P-type semiconductor layer 21a, which can realize electrical connection with the second P-type semiconductor layer 21a.
  • the first mirror layer 21b may specifically be a DBR mirror layer.
  • the P-type semiconductor reflective composite layer 21 can have both a P-type semiconductor function and a mirror function, so that the thickness of the light emitting diode can be reduced.
  • the P-type semiconductor reflective composite layer 21 may also be a superposition of a mirror structure and a P-type semiconductor layer, which is not specifically limited in the embodiment of the present disclosure.
  • FIG. 4 a cross-sectional schematic diagram of another light-emitting diode according to an embodiment of the present disclosure is shown, and the light-emitting diode may further include:
  • the optical amplifier layer 60 is arranged on the reflective composite layer 50;
  • the fifth electrode E and the sixth electrode F are separately arranged on the optical amplifier layer 60;
  • the orthographic projections of the optical amplifier layer 60, the fifth electrode E, and the sixth electrode F on the reflective light-emitting layer 20 are different from those of the first electrode A and the second electrode B. Overlapping; the optical amplifier layer 60, the fifth electrode E and the sixth electrode F respectively on the orthographic projection of the saturable absorber layer 40 and the third electrode C and the fourth electrode D None overlap.
  • the optical amplifier layer 60 has the function of amplifying the optical output power.
  • the fifth electrode E and the sixth electrode F may serve as the anode and the cathode of the optical amplifier layer 60.
  • an optical amplifier layer 60 that is, a semiconductor optical amplifier, may be added to the upper layer of the saturable absorber layer 40 to increase the light output power of the light emitting diode.
  • the optical amplifier layer 60 includes:
  • the third P-type semiconductor layer 61 is disposed on the reflective composite layer 50, and the fifth electrode E is disposed on the third P-type semiconductor layer 61;
  • the third quantum well layer 62 is disposed on the third P-type semiconductor layer 61, and the orthographic projection of the third quantum well layer 62 on the third P-type semiconductor layer 61 is different from the fifth electrode E overlapping;
  • the third N-type semiconductor layer 63 is disposed on the third quantum well layer 62.
  • the fifth electrode E is connected to the third P-type semiconductor layer 61, so as to realize the control voltage input to the optical amplifier layer 60 through the third P-type semiconductor layer 61.
  • the sixth electrode F is connected to the third N-type semiconductor layer 63 to realize the control voltage input to the optical amplifier layer 60 through the third N-type semiconductor layer 63.
  • the orthographic projections of the third quantum well layer 62 and the third N-type semiconductor layer 63 respectively on the third P-type semiconductor layer 61 do not overlap with the fifth electrode E, so that the fifth electrode E is not blocked by the upper layer structure, and the movement is realized. ⁇ Wire connection.
  • the two electrodes B do not overlap. Therefore, the second electrode B will not be blocked by the upper structure, and the wiring connection can be realized.
  • the orthographic projections of the optical amplifier layer 60, the fifth electrode E, and the sixth electrode F respectively on the saturable absorber layer 40 do not overlap with the fourth electrode D. Therefore, the fourth electrode D will not be blocked by the upper structure, which can be realized Wire connection.
  • the sixth electrode F is arranged on the uppermost layer of all the structures, so it will not be blocked, and the wiring connection can be realized.
  • the structure of the semiconductor optical amplifier is also a quantum well structure, but the working principles of the semiconductor optical amplifier and the quantum well light-emitting layer are different.
  • the quantum well light-emitting layer uses energy level transitions to cause population inversion, and then high-energy particles transition to low energy levels to achieve spontaneous luminescence.
  • the semiconductor optical amplifier will perform stimulated radiation, and the wavelength of the light emitted by it will be the same as that of the semiconductor optical amplifier.
  • the incident light has the same wavelength, so it does not broaden the spectrum.
  • the first quantum well structure (P-type semiconductor + quantum well + N-type semiconductor in the reflective light-emitting layer 20) close to the substrate 10 can be used as the light-emitting layer
  • the second one above The quantum well structure (P-type semiconductor + quantum well + N-type semiconductor in the saturable absorber layer 40) can be used as a saturable absorber
  • the third quantum well structure above (the P-type semiconductor in the optical amplifier layer 60 + Quantum well + N-type semiconductor) can be used as a semiconductor optical amplifier.
  • a forward bias can be applied to the first quantum well structure and the third quantum well structure, and a negative bias or no voltage can be applied to the second quantum well structure, so that the light-emitting diode can be achieved. drive.
  • FIG. 5 shows a schematic diagram of the spectral changes before and after the light emitted by a reflective light-emitting layer of an embodiment of the present disclosure passes through the saturable absorber layer and the optical amplifier layer.
  • the light emitted from the saturable absorber layer passes through the light After the amplifier layer, the half-maximum width FHWM of the spectrum is basically unchanged, but the output light energy increases (the amount of light energy can be reflected by the height of the spectrum), that is, the light output power of the light-emitting diode increases.
  • the reflective composite layer 50 may have a mirror structure.
  • the reflective composite layer 50 when the light emitting diode includes the optical amplifier layer 60, optionally, the reflective composite layer 50 has a mirror structure and uses an insulating material; or, referring to FIG. 6, it shows In another schematic cross-sectional view of a light emitting diode according to an embodiment of the present disclosure, the reflective composite layer 50 includes a second insulating layer 50a and a second mirror layer 50b that are stacked. Wherein, the second insulating layer 50a or the second mirror layer 50b may be disposed close to the substrate 10, which is not specifically limited in the embodiment of the present disclosure. In practical applications, the second mirror layer 50b may specifically be a DBR mirror layer.
  • the manufacturing method of the light-emitting diode provided by the embodiments of the present disclosure is mainly different from the manufacturing method of the related light-emitting diode in terms of the growth of the epitaxial wafer and the preparation of the electrode.
  • substrate thinning, preparation of isolation trenches, filling of isolation trenches, and fixation of the lower surface of the chip reference may be made to related technologies. The following will take the light-emitting diode structure shown in Figure 1 as an example, focusing on the process flow of epitaxial wafer growth and electrode preparation:
  • the epitaxial wafer can be cleaned with deionized water, ethanol, acetone, ethanol, and deionized water in sequence, and then the epitaxial wafer can be soaked in concentrated sulfuric acid (H 2 SO 4 ) to remove oxides on the surface of the epitaxial wafer.
  • the epitaxial wafer can be selected from intrinsic semiconductor materials, such as AlGaInP.
  • the structure or film layer in the light emitting diode other than the electrode can be an AlGaInP-based structure or film layer.
  • the substrate can be an AlGaInP layer
  • each P-type semiconductor layer in the light emitting diode can be The boron-doped AlGaInP layer
  • each N-type semiconductor layer in the light emitting diode may be a phosphorus-doped AlGaInP layer.
  • the epitaxial wafer can be grown by the MOCVD (Metal-organic Chemical Vapor Deposition) method. Different from the conventional light-emitting diode structure, the embodiments of the present disclosure need to grow three quantum well structures, which are used as light-emitting layers, saturable absorbers and optical amplifiers respectively, and an intrinsic semiconductor material layer can be grown between each quantum well structure for insulation , As shown in Figure 7.
  • MOCVD Metal-organic Chemical Vapor Deposition
  • the setting area of the fifth electrode E Referring to FIG. 8, the area 01 for setting the sixth electrode F and the light-emitting area 00 are covered by photoresist, and then ICP (inductively coupled plasma, inductively coupled plasma) can be used.
  • ICP inductively coupled plasma, inductively coupled plasma
  • the upper layers of the third P-type semiconductor layer 61 in the area 02, the area 03, the area 04, the area 05, and the area 06 are dry-etched away. Among them, any one of the area 02, the area 03, the area 04, the area 05, and the area 06 obtained after this etching can be used as the setting area of the fifth electrode E.
  • Forming the setting area of the fourth electrode D Taking the area 02 as the setting area of the fifth electrode E as an example, referring to FIG. 9, the area 01 for setting the sixth electrode F and the fifth electrode E are covered by photoresist. In the area 02 and the light-emitting area 00, the upper structures of the first N-type semiconductor layer 43 in the area 03, the area 04, the area 05 and the area 06 can be etched away by the ICP dry method. Among them, any one of the region 03, the region 04, the region 05, and the region 06 obtained after this etching can be used as the setting region of the fourth electrode D.
  • Forming the setting area of the third electrode C Taking the area 03 as the setting area of the fourth electrode D as an example, referring to FIG. In the area 02, the area 03 of the fourth electrode D, and the light-emitting area 00, the upper structures of the first P-type semiconductor layer 41 in the area 04, the area 05 and the area 06 can be etched away by the ICP dry method. Among them, any one of the region 04, the region 05, and the region 06 obtained after this etching can be used as the setting region of the third electrode C.
  • Forming the setting area of the second electrode B Taking the area 04 as the setting area of the third electrode C as an example, referring to FIG. 11, the area 01 for setting the sixth electrode F and the fifth electrode E are covered by photoresist Area 02, area 03 of the fourth electrode D, area 04 of the third electrode C, and light-emitting area 00, and then the upper structure of the second N-type semiconductor layer 23 in the area 05 and the area 06 can be etched away by the ICP dry method . Among them, any one of the region 05 and the region 06 obtained after this etching can be used as the setting region of the second electrode B.
  • Electrodes technologies such as tape stripping + evaporation, or evaporation + photolithography can be used to fabricate the first electrode A in area 06, the second electrode B in area 05, and the second electrode in area 04. Three electrodes C, a fourth electrode D in area 03, a fifth electrode E in area 02, and a sixth electrode F in area 01, as shown in FIG. 13.
  • the method for manufacturing the light-emitting diode may also include other conventional process flows, and the description of the embodiment of the present disclosure will not be repeated here.
  • the light-emitting diode includes a substrate, a reflective light-emitting layer disposed on the substrate, a first electrode, a second electrode, and a first insulating layer separately disposed on the reflective light-emitting layer, and the first insulating layer is disposed on the first insulating layer.
  • the saturable absorber layer on the upper surface, and the third electrode, the fourth electrode and the reflective composite layer separately arranged on the saturable absorber layer.
  • the reflectivity of the reflective light-emitting layer is greater than the reflectivity of the reflective composite layer to ensure that the light exits from the side away from the substrate.
  • the orthographic projections of the saturable absorber layer, the third electrode, the fourth electrode and the reflective composite layer on the reflective light-emitting layer respectively do not overlap with the first electrode and the second electrode, so that the first electrode, the second electrode, Neither the third electrode nor the fourth electrode will be blocked by the upper structure, so that the wiring connection can be realized.
  • the light with low energy is absorbed more, and the light with high energy is absorbed less, so The half-height width of the light-emitting diode spectrum is reduced, thereby improving the color purity of the light-emitting diode.
  • the embodiment of the present disclosure also discloses a driving method, which can be used to drive the above-mentioned light emitting diode, and the driving method includes:
  • a first positive voltage is input to the first electrode A, and a first negative voltage is input to the second electrode B.
  • the first electrode A can be used as an anode for controlling the reflective light-emitting layer 20
  • the second electrode B can be used as a cathode for controlling the reflective light-emitting layer 20. Press to drive the reflective light-emitting layer 20 to emit light.
  • the method further includes:
  • a second negative voltage is input to the third electrode C, and a second positive voltage is input to the fourth electrode D.
  • the third electrode C can be used as a cathode for controlling the saturable absorber layer 40
  • the fourth electrode D can be used as an anode for controlling the saturable absorber layer 40.
  • the layer 40 receives a reverse bias voltage, thereby driving the saturable absorber layer 40.
  • no voltage may be input to the third electrode C and the fourth electrode D, that is, no voltage may be applied to the saturable absorber layer 40, and the saturable absorber layer 40 may not be
  • the function of the saturable absorber can be realized under both the voltage application and the reverse bias voltage application, which is not specifically limited in the embodiment of the present disclosure. Among them, applying a reverse bias can make the saturable absorption capacity of the saturable absorber layer 40 better.
  • the light emitting diode further includes an optical amplifier layer 60, a fifth electrode E and a sixth electrode F, and the method further includes:
  • a third positive voltage is input to the fifth electrode E, and a third negative voltage is input to the sixth electrode F.
  • the fifth electrode E can be used as the anode of the optical amplifier layer 60
  • the sixth electrode F can be used as the cathode of the optical amplifier layer 60. That is, in the embodiment of the present disclosure, a forward bias voltage can be input to the optical amplifier layer 60. Thus, the optical amplifier layer 60 is driven to amplify the optical power.
  • the first positive voltage can be input to the first electrode of the light emitting diode
  • the first negative voltage can be input to the second electrode
  • the second negative voltage can be input to the third electrode
  • the fourth electrode can be input.
  • the reverse bias voltage and the forward bias voltage applied to the optical amplifier layer can drive the light-emitting diode to emit light, improve the color purity of the light-emitting diode, and increase the light output power of the light-emitting diode.
  • the embodiment of the present disclosure also discloses a light source device including the above-mentioned light-emitting diode.
  • the light source device may specifically be a backlight module, and the embodiment of the present disclosure does not specifically limit the light source device.
  • the light-emitting diode in the light source device includes a substrate, a reflective light-emitting layer provided on the substrate, a first electrode, a second electrode, and a first insulating layer separately provided on the reflective light-emitting layer, and A saturable absorber layer on the first insulating layer, and a third electrode, a fourth electrode, and a reflective composite layer separately arranged on the saturable absorber layer.
  • the reflectivity of the reflective light-emitting layer is greater than the reflectivity of the reflective composite layer to ensure that the light exits from the side away from the substrate.
  • the orthographic projections of the saturable absorber layer, the third electrode, the fourth electrode and the reflective composite layer on the reflective light-emitting layer respectively do not overlap with the first electrode and the second electrode, so that the first electrode, the second electrode, Neither the third electrode nor the fourth electrode will be blocked by the upper structure, so that the wiring connection can be realized.
  • the light with low energy is absorbed more, and the light with high energy is absorbed less, so The half-height width of the light-emitting diode spectrum is reduced, thereby improving the color purity of the light-emitting diode.
  • the embodiment of the present disclosure also discloses an electronic device including the above-mentioned light source device.
  • the electronic device may specifically be a display device, and the embodiment of the present disclosure does not specifically limit the electronic device.
  • the light-emitting diode in the electronic device includes a substrate, a reflective light-emitting layer disposed on the substrate, a first electrode, a second electrode, and a first insulating layer separately disposed on the reflective light-emitting layer, and A saturable absorber layer on the first insulating layer, and a third electrode, a fourth electrode, and a reflective composite layer separately arranged on the saturable absorber layer.
  • the reflectivity of the reflective light-emitting layer is greater than the reflectivity of the reflective composite layer to ensure that the light exits from the side away from the substrate.
  • the orthographic projections of the saturable absorber layer, the third electrode, the fourth electrode and the reflective composite layer on the reflective light-emitting layer respectively do not overlap with the first electrode and the second electrode, so that the first electrode, the second electrode, Neither the third electrode nor the fourth electrode will be blocked by the upper structure, so that the wiring connection can be realized.
  • the light with low energy is absorbed more, and the light with high energy is absorbed less, so The half-height width of the light-emitting diode spectrum is reduced, thereby improving the color purity of the light-emitting diode.
  • the device embodiments described above are merely illustrative, where the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in One place, or it can be distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the objectives of the solutions of the embodiments. Those of ordinary skill in the art can understand and implement without creative work.
  • the various component embodiments of the present disclosure may be implemented by hardware, or by software modules running on one or more processors, or by a combination of them.
  • a microprocessor or a digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the computing processing device according to the embodiments of the present disclosure.
  • DSP digital signal processor
  • the present disclosure can also be implemented as a device or device program (for example, a computer program and a computer program product) for executing part or all of the methods described herein.
  • Such a program for realizing the present disclosure may be stored on a computer-readable medium, or may have the form of one or more signals.
  • Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.
  • FIG. 14 shows a computing processing device that can implement the method according to the present disclosure.
  • the computing processing device traditionally includes a processor 1010 and a computer program product in the form of a memory 1020 or a computer readable medium.
  • the memory 1020 may be an electronic memory such as flash memory, EEPROM (Electrically Erasable Programmable Read Only Memory), EPROM, hard disk, or ROM.
  • the memory 1020 has a storage space 1030 for executing program codes 1031 of any method steps in the above methods.
  • the storage space 1030 for program codes may include various program codes 1031 respectively used to implement various steps in the above method. These program codes can be read from or written into one or more computer program products.
  • These computer program products include program code carriers such as hard disks, compact disks (CDs), memory cards or floppy disks.
  • Such a computer program product is usually a portable or fixed storage unit as described with reference to FIG. 15.
  • the storage unit may have storage segments, storage spaces, and the like arranged similarly to the memory 1020 in the computing processing device of FIG. 14.
  • the program code can be compressed in a suitable form, for example.
  • the storage unit includes computer-readable codes 1031', that is, codes that can be read by, for example, a processor such as 1010. These codes, when run by a computing processing device, cause the computing processing device to execute the method described above. The various steps.

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Abstract

发光二极管及其驱动方法、光源装置及电子设备，涉及半导体技术领域。其中，发光二极管包括：衬底；反射发光层，设置在衬底上；第一电极、第二电极、第一绝缘层，分立设置在反射发光层上；可饱和吸收体层，设置在第一绝缘层上；第三电极、第四电极、反射复合层，分立设置在可饱和吸收体层上，反射发光层反射率大于反射复合层反射率；其中，可饱和吸收体层、第三电极、第四电极、反射复合层分别在反射发光层上的正投影与第一电极及第二电极均不重叠。

Description

发光二极管及其驱动方法、光源装置及电子设备
相关申请的交叉引用
本公开要求在2020年05月27日提交中国专利局、申请号为202010461152.7、名称为“一种发光二极管及其驱动方法、光源装置及电子设备”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本公开涉及半导体技术领域，特别是涉及一种发光二极管及其驱动方法、光源装置及电子设备。
背景技术
发光二极管(Light Emitting Diode，LED)是一种常用的发光器件，可以通过电子与空穴的复合释放能量发光，它在照明、显示、医疗等诸多领域应用广泛。发光二极管可高效地将电能转化为光能，在现代社会具有广泛的用途。
概述
本公开提供一种发光二极管及其驱动方法、光源装置及电子设备。
本公开公开了一种发光二极管，包括：
衬底；
反射发光层，所述反射发光层设置在所述衬底上；
第一电极、第二电极和第一绝缘层，所述第一电极、所述第二电极和所述第一绝缘层分立设置在所述反射发光层上；
可饱和吸收体层，所述可饱和吸收体层设置在所述第一绝缘层上；
第三电极、第四电极和反射复合层，所述第三电极、所述第四电极和所述反射复合层分立设置在所述可饱和吸收体层上，所述反射发光层的反射率大于所述反射复合层的反射率；
其中，所述可饱和吸收体层、所述第三电极、所述第四电极和所述反射复合层分别在所述反射发光层上的正投影与所述第一电极及所述第二电极均不重叠。
可选地，所述可饱和吸收体层包括：
第一P型半导体层，所述第一P型半导体层设置在所述第一绝缘层上，所述第三电极设置在所述第一P型半导体层上；
第一量子阱层，所述第一量子阱层设置在所述第一P型半导体层上，所述第一量子阱层在所述第一P型半导体层上的正投影与所述第三电极不重叠；以及
第一N型半导体层，所述第一N型半导体层设置在所述第一量子阱层上，所述第一N型半导体层在所述第一P型半导体层上的正投影与所述第三电极不重叠，所述第四电极设置在所述第一N型半导体层上。
可选地，所述反射发光层包括：
P型半导体反射复合层，所述P型半导体反射复合层设置在所述衬底上，所述第一电极设置在所述P型半导体反射复合层上；
第二量子阱层，所述第二量子阱层设置在所述P型半导体反射复合层上，所述第二量子阱层在所述P型半导体反射复合层上的正投影与所述第一电极不重叠；以及
第二N型半导体层，所述第二N型半导体层设置在所述第二量子阱层上，所述第二N型半导体层在所述P型半导体反射复合层上的正投影与所述第一电极不重叠，所述第二电极设置在所述第二N型半导体层上。
可选地，所述P型半导体反射复合层具有反射镜结构；或者，
所述P型半导体反射复合层包括叠层设置的第二P型半导体层和第一反射镜层，其中，所述第一反射镜层靠近所述衬底设置。
可选地，所述发光二极管还包括：
光放大器层，所述光放大器层设置在所述反射复合层上；
第五电极和第六电极，所述第五电极和第六电极分立设置在所述光放大器层上；
其中，所述光放大器层、所述第五电极和所述第六电极分别在所述反射发光层上的正投影与所述第一电极及所述第二电极均不重叠；所述光放大器层、所述第五电极和所述第六电极分别在所述可饱和吸收体层上的正投影与所述第三电极及所述第四电极均不重叠。
可选地，所述光放大器层包括：
第三P型半导体层，所述第三P型半导体层设置在所述反射复合层上，所述第五电极设置在所述第三P型半导体层上；
第三量子阱层，所述第三量子阱层设置在所述第三P型半导体层上，所 述第三量子阱层在所述第三P型半导体层上的正投影与所述第五电极不重叠；
第三N型半导体层，所述第三N型半导体层设置在所述第三量子阱层上，所述第三N型半导体层在所述第三P型半导体层上的正投影与所述第五电极不重叠，所述第六电极设置在所述第三N型半导体层上。
可选地，所述第五电极和所述第六电极分别为所述光放大器层的阳极和阴极。
可选地，所述反射复合层具有反射镜结构，且采用绝缘材料；或者，
所述反射复合层包括叠层设置的第二绝缘层和第二反射镜层。
可选地，所述第一电极和所述第二电极分别为所述反射发光层的阳极和阴极，所述第三电极和所述第四电极分别为所述可饱和吸收体层的阴极和阳极。
本公开还公开了一种驱动方法，用于驱动上述发光二极管，所述方法包括：
向第一电极输入第一正向电压，以及向第二电极输入第一负向电压。
可选地，所述方法还包括：
向第三电极输入第二负向电压，以及向第四电极输入第二正向电压。
可选地，所述发光二极管还包括光放大器层、第五电极和第六电极，所述方法还包括：
向所述第五电极输入第三正向电压，以及向所述第六电极输入第三负向电压。
本公开还公开了一种计算处理设备，其中，包括：
存储器，其中存储有计算机可读代码；以及
一个或多个处理器，当所述计算机可读代码被所述一个或多个处理器执行时，所述计算处理设备执行上述的驱动方法。
本公开还公开了一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行上述的驱动方法。
本公开还公开了一种计算机可读介质，其中存储了上述的计算机程序。
本公开还公开了一种光源装置，包括上述发光二极管。
本公开还公开了一种电子设备，包括上述光源装置。
上述说明仅是本公开技术方案的概述，为了能够更清楚了解本公开的技术手段，而可依照说明书的内容予以实施，并且为了让本公开的上述和其它 目的、特征和优点能够更明显易懂，以下特举本公开的具体实施方式。
附图简述
为了更清楚地说明本公开实施例或相关技术中的技术方案，下面将对实施例或相关技术描述中所需要使用的附图作一简单地介绍，显而易见地，下面描述中的附图是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1示出了本公开实施例的一种发光二极管的截面示意图；
图2示出了本公开实施例的一种反射发光层发出的光经过可饱和吸收体层前后的光谱变化示意图；
图3示出了本公开实施例的另一种发光二极管的截面示意图；
图4示出了本公开实施例的又一种发光二极管的截面示意图；
图5示出了本公开实施例的一种反射发光层发出的光依次经过可饱和吸收体层和光放大器层前后的光谱变化示意图；
图6示出了本公开实施例的再一种发光二极管的截面示意图；
图7示出了本公开实施例的一种生长有三个量子阱结构的外延片的俯视图；
图8示出了本公开实施例的一种光刻胶覆盖区域01及发光区00的示意图；
图9示出了本公开实施例的一种光刻胶覆盖区域01、区域02及发光区00的示意图；
图10示出了本公开实施例的一种光刻胶覆盖区域01、区域02、区域03及发光区00的示意图；
图11示出了本公开实施例的一种光刻胶覆盖区域01、区域02、区域03、区域04及发光区00的示意图；
图12示出了本公开实施例的一种光刻胶覆盖区域01、区域02、区域03、区域04、区域05及发光区00的示意图；
图13示出了本公开实施例的设置电极后的发光二极管的俯视图；
图14示意性地示出了用于执行根据本公开的方法的计算处理设备的框图；并且
图15示意性地示出了用于保持或者携带实现根据本公开的方法的程序代码的存储单元。
详细描述
为使本公开的上述目的、特征和优点能够更加明显易懂，下面结合附图和具体实施方式对本公开作进一步详细的说明。显然，所描述的实施例是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
图1示出了本公开实施例的一种发光二极管的截面示意图，参照图1，该发光二极管包括：
衬底10；
反射发光层20，设置在所述衬底10上；
第一电极A、第二电极B和第一绝缘层30，分立设置在所述反射发光层20上；
可饱和吸收体层40，设置在所述第一绝缘层30上；
第三电极C、第四电极D和反射复合层50，分立设置在所述可饱和吸收体层40上，所述反射发光层20的反射率大于所述反射复合层50的反射率；
其中，所述可饱和吸收体层40、所述第三电极C、所述第四电极D和所述反射复合层50分别在所述反射发光层20上的正投影与所述第一电极A及所述第二电极B均不重叠。
在本公开实施例中，反射发光层20具有反射光线以及发光的作用。第一电极A和第二电极B可以作为反射发光层20的阳极和阴极。第三电极C和第四电极D可以作为可饱和吸收体层40的阴极和阳极。反射复合层50具有反射光线的作用。其中，由于第一电极A、第二电极B、第三电极C和第四电极D均需要暴露在最上层进行走线连接，以接收用于控制相应层的电压信号，因此，需要可饱和吸收体层40、第三电极C、第四电极D和反射复合层50分别在反射发光层20上的正投影与第一电极A及第二电极B均不重叠，从而可以使第一电极A及第二电极B均不会被上层结构遮挡。
其中，相比于相关的发光二极管结构，本公开实施例增加了可饱和吸收体层40。可饱和吸收体是一种非线性吸收性质的物质，对光的吸收系数是光强的函数，在光强较小时，它的光吸收系数很大，表现为基本不透光，而当光强增大到某一个值时，它的光吸收系数会突然减小，表现为几乎透明。因此，本公开实施例在相关发光二极管结构上，增加了一层可饱和吸收体层40， 也即是在相关发光二极管结构的发光层上层增加了一个可饱和吸收体。
图2示出了本公开实施例的一种反射发光层发出的光经过可饱和吸收体层前后的光谱变化示意图，参照图2，当反射发光层20发出的光经过可饱和吸收体层40之后，能量低的光吸收的多，能量高的光吸收的少，因此，发光二极管光谱的半高宽FHWM降低，从而提高了发光二极管的色光颜色纯度。
另外，由于可饱和吸收体对光的吸收能力有限，因此，在具体应用时，可以配合两个反射镜结构，其中，可饱和吸收体可以设置在两个反射镜结构之间，从而使得反射发光层20发出的光可以在两个反射镜结构之间多次反射，进而使光线可以多次经过可饱和吸收体进行吸收。在本公开实施例中，反射发光层20具有反射光线的作用，可以作为一个反射镜结构，反射复合层50也具有反射光线的作用，可以作为另一个反射镜结构，可饱和吸收体层40位于反射发光层20与反射复合层50之间，从而可以多次吸收反射发光层20发出的光，使得可饱和吸收体的作用充分发挥，有利于降低发光二极管光谱的半高宽。
其中，反射发光层20的反射率大于反射复合层50的反射率，可以使反射发光层20发出的光经过可饱和吸收体层40和反射复合层50的多次吸收和反射之后，从发光二极管远离衬底10的一侧出射。
在实际应用中，反射镜结构具体可以是分布式布拉格反射(distributed Bragg reflection，DBR)镜结构，DBR反射镜结构是由两种不同折射率的材料以ABAB的方式交替排列组成的周期结构，其中，每层材料的光学厚度为中心反射波长的1/4。
经研究发现，量子阱材料在不施加电压或施加反向偏压时，可以表现出可饱和吸收体的特性，因此，本公开实施例可以在相关技术的发光二极管结构上，增加了一层不施加电压或施加反向偏压的量子阱结构，即增加了一个可饱和吸收体。
可选地，参照图1，所述可饱和吸收体层40包括：
第一P型半导体层41，设置在所述第一绝缘层30上，所述第三电极C设置在所述第一P型半导体层41上；
第一量子阱层42，设置在所述第一P型半导体层41上，所述第一量子阱层42在所述第一P型半导体层41上的正投影与所述第三电极C不重叠；
第一N型半导体层43，设置在所述第一量子阱层42上，所述第一N型半导体层43在所述第一P型半导体层41上的正投影与所述第三电极C不重 叠，所述第四电极D设置在所述第一N型半导体层43上。
其中，第一绝缘层30在反射发光层20与可饱和吸收体层40之间起绝缘作用。第三电极C与第一P型半导体层41连接，以通过第一P型半导体层41实现对可饱和吸收体层40的控制电压输入。第四电极D与第一N型半导体层43连接，以通过第一N型半导体层43实现对可饱和吸收体层40的控制电压输入。第一量子阱层42和第一N型半导体层43分别在第一P型半导体层41上的正投影与第三电极C不重叠，从而可使第三电极C不被上层结构遮挡，实现走线连接。
另外，由于量子阱结构在不施加电压或施加反向偏压时，才可表现出可饱和吸收体的特性，因此，在实际应用中，可以对可饱和吸收体层40不施加电压或施加反向偏压。以对可饱和吸收体层40施加反向偏压为例，常见的量子阱结构通常是向P型半导体层施加正向电压，向N型半导体层施加负向电压，而在本公开实施例中，可以向可饱和吸收体层40的第一P型半导体层41施加负向电压，向第一N型半导体层43施加正向电压，也即是向第三电极C输入负向电压，向第四电极D输入正向电压，从而实现了对可饱和吸收体层40施加反向偏压。
可选地，参照图1，所述反射发光层20包括：
P型半导体反射复合层21，设置在所述衬底10上，所述第一电极A设置在所述P型半导体反射复合层21上；
第二量子阱层22，设置在所述P型半导体反射复合层21上，所述第二量子阱层22在所述P型半导体反射复合层21上的正投影与所述第一电极A不重叠；
第二N型半导体层23，设置在所述第二量子阱层22上，所述第二N型半导体层23在所述P型半导体反射复合层21上的正投影与所述第一电极A不重叠，所述第二电极B设置在所述第二N型半导体层23上。
其中，第一电极A与P型半导体反射复合层21连接，以通过P型半导体反射复合层21实现对反射发光层20的控制电压输入。第二电极B与第二N型半导体层23连接，以通过第二N型半导体层23实现对反射发光层20的控制电压输入。第二量子阱层22和第二N型半导体层23分别在P型半导体反射复合层21上的正投影与第一电极A不重叠，从而可使第一电极A不被上层结构遮挡，实现走线连接。
可选地，所述P型半导体反射复合层21具有反射镜结构；或者，参照图 3，示出了本公开实施例的另一种发光二极管的截面示意图，所述P型半导体反射复合层21包括叠层设置的第二P型半导体层21a和第一反射镜层21b，其中，所述第一反射镜层21b靠近所述衬底10设置。第一电极A设置在第二P型半导体层21a上，即可实现与第二P型半导体层21a的电连接。在实际应用中，第一反射镜层21b具体可以是DBR反射镜层。
也即是在本公开实施例中，P型半导体反射复合层21可以同时具有P型半导体作用以及反射镜作用，从而可以减小发光二极管的厚度。当然，P型半导体反射复合层21也可以是一层反射镜结构与一层P型半导体层的叠加，本公开实施例对此不作具体限定。
在本公开实施例中，可选地，参照图4，示出了本公开实施例的又一种发光二极管的截面示意图，所述发光二极管还可以包括：
光放大器层60，设置在所述反射复合层50上；
第五电极E和第六电极F，分立设置在所述光放大器层60上；
其中，所述光放大器层60、所述第五电极E和所述第六电极F分别在所述反射发光层20上的正投影与所述第一电极A及所述第二电极B均不重叠；所述光放大器层60、所述第五电极E和所述第六电极F分别在所述可饱和吸收体层40上的正投影与所述第三电极C及所述第四电极D均不重叠。
在本公开实施例中，光放大器层60具有放大光输出功率的作用。第五电极E和第六电极F可以作为光放大器层60的阳极和阴极。
参照图2可知，由于反射发光层20发出的光经过了可饱和吸收体层40之后，光的能量会降低，因此，发光二极管的光输出功率较低。所以在本公开实施例中，可以在可饱和吸收体层40的上层增加一个光放大器层60，也即半导体光放大器，以提高发光二极管的光输出功率。
可选地，参照图4，所述光放大器层60包括：
第三P型半导体层61，设置在所述反射复合层50上，所述第五电极E设置在所述第三P型半导体层61上；
第三量子阱层62，设置在所述第三P型半导体层61上，所述第三量子阱层62在所述第三P型半导体层61上的正投影与所述第五电极E不重叠；
第三N型半导体层63，设置在所述第三量子阱层62上，所述第三N型半导体层63在所述第三P型半导体层61上的正投影与所述第五电极E不重叠，所述第六电极F设置在所述第三N型半导体层63上。
其中，第五电极E与第三P型半导体层61连接，以通过第三P型半导体 层61实现对光放大器层60的控制电压输入。第六电极F与第三N型半导体层63连接，以通过第三N型半导体层63实现对光放大器层60的控制电压输入。第三量子阱层62和第三N型半导体层63分别在第三P型半导体层61上的正投影与第五电极E不重叠，从而可使第五电极E不被上层结构遮挡，实现走线连接。
另外，可饱和吸收体层40、第三电极C、第四电极D、反射复合层50、光放大器层60、第五电极E和第六电极F分别在反射发光层20上的正投影与第二电极B不重叠，因此，第二电极B也不会被上层结构遮挡，可以实现走线连接。光放大器层60、第五电极E和第六电极F分别在可饱和吸收体层40上的正投影与第四电极D不重叠，因此，第四电极D也不会被上层结构遮挡，可以实现走线连接。第六电极F设置在所有结构的最上层，因此也不会被遮挡，可以实现走线连接。
在本公开实施例中，半导体光放大器的结构也是一个量子阱结构，但是半导体光放大器与量子阱发光层的工作原理不同。量子阱发光层利用能级跃迁出现粒子数反转，之后高能粒子向低能级跃迁，实现自发辐射发光。但半导体光放大器出现粒子数反转后，由于反射发光层20发出的光经过可饱和吸收体后会照射到半导体光放大器中，因此，半导体光放大器会进行受激辐射，其发出的光波长与入射光波长相同，所以不会将光谱展宽。
在本公开实施例提供的发光二极管中，靠近衬底10的第一个量子阱结构(反射发光层20中的P型半导体+量子阱+N型半导体)可以作为发光层，上方的第二个量子阱结构(可饱和吸收体层40中的P型半导体+量子阱+N型半导体)可以作为可饱和吸收体，再上方的第三个量子阱结构(光放大器层60中的P型半导体+量子阱+N型半导体)可以作为半导体光放大器。发光二极管工作时，可以向第一个量子阱结构和第三个量子阱结构施加正向偏压，向第二个量子阱结构施加负向偏压或不施加电压，从而可以实现该发光二极管的驱动。
图5示出了本公开实施例的一种反射发光层发出的光依次经过可饱和吸收体层和光放大器层前后的光谱变化示意图，参照图5，从可饱和吸收体层出射的光在经过光放大器层之后，光谱的半高宽FHWM基本不变，但输出的光能量增加(光能量的大小可通过光谱高度体现)，也即是发光二极管的光输出功率增大。
此外，在发光二极管不包括光放大器层60的情况下，反射复合层50具 有反射镜结构即可。但是，在发光二极管包括光放大器层60的情况下，反射复合层50还需要与光放大器层60进行绝缘。因此，在本公开实施例中，在发光二极管包括光放大器层60的情况下，可选地，所述反射复合层50具有反射镜结构，且采用绝缘材料；或者，参照图6，示出了本公开实施例的再一种发光二极管的截面示意图，所述反射复合层50包括叠层设置的第二绝缘层50a和第二反射镜层50b。其中，第二绝缘层50a或第二反射镜层50b靠近衬底10设置均可，本公开实施例对此不作具体限定。在实际应用中，第二反射镜层50b具体可以是DBR反射镜层。
进一步地，本公开实施例提供的发光二极管的制备方法，主要是在外延片的生长以及电极的制备方面与相关发光二极管的制备方法有所不同，其他工艺流程，例如外延片清洗、外延片正面保护、衬底减薄、隔离沟道的制备、隔离沟道的填充、芯片下表面的固定等方面可以参考相关技术。以下将以图1所示的发光二极管结构为例，重点介绍外延片生长、电极制备等工艺流程：
1)清洗外延片：可以依次通过去离子水、乙醇、丙酮、乙醇、去离子水清洗外延片，之后通过浓硫酸(H 2SO 4)浸泡外延片，去除外延片表面的氧化物。其中，外延片可以选用本征半导体材料，例如AlGaInP等。以AlGaInP外延片为例，则发光二极管中除电极之外的结构或膜层均可以是AlGaInP基的结构或膜层，例如衬底可以是AlGaInP层，发光二极管中的各个P型半导体层可以是硼掺杂AlGaInP层，发光二极管中的各个N型半导体层可以是磷掺杂AlGaInP层。
2)外延片生长：可以通过MOCVD(Metal-organic Chemical Vapor Deposition，金属有机化学气相沉积)法进行外延片的生长。与常规发光二极管结构不同，本公开实施例需要生长三个量子阱结构，分别作为发光层，可饱和吸收体和光放大器，并可以在每一个量子阱结构之间生长本征半导体材料层用于绝缘，如图7所示。
3)形成第五电极E的设置区域：参照图8，通过光刻胶覆盖用于设置第六电极F的区域01，以及发光区00，然后可采用ICP(inductively coupled plasma，感应耦合等离子体)干法刻蚀掉区域02、区域03、区域04、区域05及区域06中第三P型半导体层61的上层各结构。其中，本次刻蚀后得到的区域02、区域03、区域04、区域05及区域06中的任一区域，均可作为第五电极E的设置区域。
4)形成第四电极D的设置区域：以区域02为第五电极E的设置区域为 例，参照图9，通过光刻胶覆盖用于设置第六电极F的区域01、第五电极E的区域02，以及发光区00，然后可采用ICP干法刻蚀掉区域03、区域04、区域05及区域06中第一N型半导体层43的上层各结构。其中，本次刻蚀后得到的区域03、区域04、区域05及区域06中的任一区域，均可作为第四电极D的设置区域。
5)形成第三电极C的设置区域：以区域03为第四电极D的设置区域为例，参照图10，通过光刻胶覆盖用于设置第六电极F的区域01、第五电极E的区域02、第四电极D的区域03，以及发光区00，然后可采用ICP干法刻蚀掉区域04、区域05及区域06中第一P型半导体层41的上层各结构。其中，本次刻蚀后得到的区域04、区域05及区域06中的任一区域，均可作为第三电极C的设置区域。
6)形成第二电极B的设置区域：以区域04为第三电极C的设置区域为例，参照图11，通过光刻胶覆盖用于设置第六电极F的区域01、第五电极E的区域02、第四电极D的区域03、第三电极C的区域04，以及发光区00，然后可采用ICP干法刻蚀掉区域05及区域06中第二N型半导体层23的上层各结构。其中，本次刻蚀后得到的区域05及区域06中的任一区域，均可作为第二电极B的设置区域。
7)形成第一电极A的设置区域：以区域05为第二电极B的设置区域为例，参照图12，通过光刻胶覆盖用于设置第六电极F的区域01、第五电极E的区域02、第四电极D的区域03、第三电极C的区域04、第二电极B的区域05，以及发光区00，然后可采用ICP干法刻蚀掉区域06中P型半导体反射复合层21的上层各结构。其中，本次刻蚀后得到的区域06，可作为第一电极A的设置区域。
8)制作电极：可以采用带胶剥离+蒸镀，或蒸镀+光刻等技术，分别在区域06制作出第一电极A、在区域05制作出第二电极B、在区域04制作出第三电极C、在区域03制作出第四电极D、在区域02制作出第五电极E，以及在区域01制作出第六电极F，如图13所示。
当然，本公开实施例提供的发光二极管制备方法还可以包括其他常规的工艺流程，本公开实施例在此不再赘述。
另外，上述各图示中的区域01、区域02、区域03、区域04、区域05及区域06的划分方式仅为一种示例，并不对本公开构成限定。在实际应用中，只需第一电极A、第二电极B、第三电极C、第四电极D、第五电极E及第六 电极F露出最上层，能够实现走线连接即可，本公开实施例对此不作具体限定。
在本公开实施例中，发光二极管包括衬底，设置在衬底上的反射发光层，分立设置在反射发光层上的第一电极、第二电极和第一绝缘层，设置在第一绝缘层上的可饱和吸收体层，以及分立设置在可饱和吸收体层上的第三电极、第四电极和反射复合层。其中，反射发光层的反射率大于反射复合层的反射率，以保证光从远离衬底的一侧出射。另外，可饱和吸收体层、第三电极、第四电极和反射复合层分别在反射发光层上的正投影与第一电极及第二电极均不重叠，以使第一电极、第二电极、第三电极和第四电极均不会被上层结构遮挡，从而可实现走线连接。在本公开实施例中，通过增加可饱和吸收体层，可使反射发光层发出的光经过可饱和吸收体层后，能量低的光被吸收较多，能量高的光被吸收较少，从而降低了发光二极管光谱的半高宽，进而提高了发光二极管的色光颜色纯度。
本公开实施例还公开了一种驱动方法，该驱动方法可用于驱动上述发光二极管，该驱动方法包括：
向第一电极A输入第一正向电压，以及向第二电极B输入第一负向电压。
其中，第一电极A可以作为控制反射发光层20的阳极，第二电极B可以作为控制反射发光层20的阴极，也即是在本公开实施例中，可以向反射发光层20输入正向偏压，从而驱动反射发光层20发光。
可选地，所述方法还包括：
向第三电极C输入第二负向电压，以及向第四电极D输入第二正向电压。
其中，第三电极C可以作为控制可饱和吸收体层40的阴极，第四电极D可以作为控制可饱和吸收体层40的阳极，也即是在本公开实施例中，可以向可饱和吸收体层40输入反向偏压，从而驱动可饱和吸收体层40。
另外，在实际应用中，可选地，还可以不向第三电极C和第四电极D输入电压，也即是可以不向可饱和吸收体层40施加电压，可饱和吸收体层40在不施加电压以及施加反向偏压的情况下，均可以实现可饱和吸收体的作用，本公开实施例对此不作具体限定。其中，施加反向偏压可使可饱和吸收体层40的可饱和吸收能力更佳。
可选地，所述发光二极管还包括光放大器层60、第五电极E和第六电极F，所述方法还包括：
向所述第五电极E输入第三正向电压，以及向所述第六电极F输入第三 负向电压。
其中，第五电极E可以作为光放大器层60的阳极，第六电极F可以作为光放大器层60的阴极，也即是在本公开实施例中，可以向光放大器层60输入正向偏压，从而驱动光放大器层60进行光功率放大。
在本公开实施例中，可以向发光二极管的第一电极输入第一正向电压，以及向第二电极输入第一负向电压，向第三电极输入第二负向电压，以及向第四电极输入第二正向电压，向第五电极输入第三正向电压，以及向第六电极输入第三负向电压，也即是向反射发光层施加正向偏压，向可饱和吸收体层施加反向偏压，以及向光放大器层施加正向偏压，从而可以在驱动发光二极管发光的同时，提高发光二极管的色光颜色纯度，以及提高发光二极管的光输出功率。
本公开实施例还公开了一种光源装置，包括上述发光二极管。
其中，在显示领域，光源装置具体可以是背光模组，本公开实施例对于光源装置不作具体限定。
在本公开实施例中，光源装置中的发光二极管包括衬底，设置在衬底上的反射发光层，分立设置在反射发光层上的第一电极、第二电极和第一绝缘层，设置在第一绝缘层上的可饱和吸收体层，以及分立设置在可饱和吸收体层上的第三电极、第四电极和反射复合层。其中，反射发光层的反射率大于反射复合层的反射率，以保证光从远离衬底的一侧出射。另外，可饱和吸收体层、第三电极、第四电极和反射复合层分别在反射发光层上的正投影与第一电极及第二电极均不重叠，以使第一电极、第二电极、第三电极和第四电极均不会被上层结构遮挡，从而可实现走线连接。在本公开实施例中，通过增加可饱和吸收体层，可使反射发光层发出的光经过可饱和吸收体层后，能量低的光被吸收较多，能量高的光被吸收较少，从而降低了发光二极管光谱的半高宽，进而提高了发光二极管的色光颜色纯度。
本公开实施例还公开了一种电子设备，包括上述光源装置。
其中，在显示领域，电子设备具体可以是显示设备，本公开实施例对于电子设备不作具体限定。
在本公开实施例中，电子设备中的发光二极管包括衬底，设置在衬底上的反射发光层，分立设置在反射发光层上的第一电极、第二电极和第一绝缘层，设置在第一绝缘层上的可饱和吸收体层，以及分立设置在可饱和吸收体层上的第三电极、第四电极和反射复合层。其中，反射发光层的反射率大于 反射复合层的反射率，以保证光从远离衬底的一侧出射。另外，可饱和吸收体层、第三电极、第四电极和反射复合层分别在反射发光层上的正投影与第一电极及第二电极均不重叠，以使第一电极、第二电极、第三电极和第四电极均不会被上层结构遮挡，从而可实现走线连接。在本公开实施例中，通过增加可饱和吸收体层，可使反射发光层发出的光经过可饱和吸收体层后，能量低的光被吸收较多，能量高的光被吸收较少，从而降低了发光二极管光谱的半高宽，进而提高了发光二极管的色光颜色纯度。
对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本公开并不受所描述的动作顺序的限制，因为依据本公开，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本公开所必须的。
以上所描述的装置实施例仅仅是示意性的，其中所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部模块来实现本实施例方案的目的。本领域普通技术人员在不付出创造性的劳动的情况下，即可以理解并实施。
本公开的各个部件实施例可以以硬件实现，或者以在一个或者多个处理器上运行的软件模块实现，或者以它们的组合实现。本领域的技术人员应当理解，可以在实践中使用微处理器或者数字信号处理器(DSP)来实现根据本公开实施例的计算处理设备中的一些或者全部部件的一些或者全部功能。本公开还可以实现为用于执行这里所描述的方法的一部分或者全部的设备或者装置程序(例如，计算机程序和计算机程序产品)。这样的实现本公开的程序可以存储在计算机可读介质上，或者可以具有一个或者多个信号的形式。这样的信号可以从因特网网站上下载得到，或者在载体信号上提供，或者以任何其他形式提供。
例如，图14示出了可以实现根据本公开的方法的计算处理设备。该计算处理设备传统上包括处理器1010和以存储器1020形式的计算机程序产品或者计算机可读介质。存储器1020可以是诸如闪存、EEPROM(电可擦除可编程只读存储器)、EPROM、硬盘或者ROM之类的电子存储器。存储器1020具有用于执行上述方法中的任何方法步骤的程序代码1031的存储空间1030。 例如，用于程序代码的存储空间1030可以包括分别用于实现上面的方法中的各种步骤的各个程序代码1031。这些程序代码可以从一个或者多个计算机程序产品中读出或者写入到这一个或者多个计算机程序产品中。这些计算机程序产品包括诸如硬盘，紧致盘(CD)、存储卡或者软盘之类的程序代码载体。这样的计算机程序产品通常为如参考图15所述的便携式或者固定存储单元。该存储单元可以具有与图14的计算处理设备中的存储器1020类似布置的存储段、存储空间等。程序代码可以例如以适当形式进行压缩。通常，存储单元包括计算机可读代码1031’，即可以由例如诸如1010之类的处理器读取的代码，这些代码当由计算处理设备运行时，导致该计算处理设备执行上面所描述的方法中的各个步骤。
本说明书中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、商品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、商品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、商品或者设备中还存在另外的相同要素。
以上对本公开所提供的一种发光二极管及其驱动方法、光源装置及电子设备，进行了详细介绍，本文中应用了具体个例对本公开的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本公开的方法及其核心思想；同时，对于本领域的一般技术人员，依据本公开的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本公开的限制。

Claims (17)

  1. 一种发光二极管，其中，包括：
    衬底；
    反射发光层，所述反射发光层设置在所述衬底上；
    第一电极、第二电极和第一绝缘层，所述第一电极、所述第二电极和所述第一绝缘层分立设置在所述反射发光层上；
    可饱和吸收体层，所述可饱和吸收体层设置在所述第一绝缘层上；
    第三电极、第四电极和反射复合层，所述第三电极、所述第四电极和所述反射复合层分立设置在所述可饱和吸收体层上，所述反射发光层的反射率大于所述反射复合层的反射率；
    其中，所述可饱和吸收体层、所述第三电极、所述第四电极和所述反射复合层分别在所述反射发光层上的正投影与所述第一电极及所述第二电极均不重叠。
  2. 根据权利要求1所述的发光二极管，其中，所述可饱和吸收体层包括：
    第一P型半导体层，所述第一P型半导体层设置在所述第一绝缘层上，所述第三电极设置在所述第一P型半导体层上；
    第一量子阱层，所述第一量子阱层设置在所述第一P型半导体层上，所述第一量子阱层在所述第一P型半导体层上的正投影与所述第三电极不重叠；以及
    第一N型半导体层，所述第一N型半导体层设置在所述第一量子阱层上，所述第一N型半导体层在所述第一P型半导体层上的正投影与所述第三电极不重叠，所述第四电极设置在所述第一N型半导体层上。
  3. 根据权利要求1所述的发光二极管，其中，所述反射发光层包括：
    P型半导体反射复合层，所述P型半导体反射复合层设置在所述衬底上，所述第一电极设置在所述P型半导体反射复合层上；
    第二量子阱层，所述第二量子阱层设置在所述P型半导体反射复合层上，所述第二量子阱层在所述P型半导体反射复合层上的正投影与所述第一电极不重叠；以及
    第二N型半导体层，所述第二N型半导体层设置在所述第二量子阱层上，所述第二N型半导体层在所述P型半导体反射复合层上的正投影与所述第一 电极不重叠，所述第二电极设置在所述第二N型半导体层上。
  4. 根据权利要求3所述的发光二极管，其中，所述P型半导体反射复合层具有反射镜结构；或者，
    所述P型半导体反射复合层包括叠层设置的第二P型半导体层和第一反射镜层，其中，所述第一反射镜层靠近所述衬底设置。
  5. 根据权利要求1-4任一项所述的发光二极管，其中，所述发光二极管还包括：
    光放大器层，所述光放大器层设置在所述反射复合层上；
    第五电极和第六电极，所述第五电极和第六电极分立设置在所述光放大器层上；
    其中，所述光放大器层、所述第五电极和所述第六电极分别在所述反射发光层上的正投影与所述第一电极及所述第二电极均不重叠；所述光放大器层、所述第五电极和所述第六电极分别在所述可饱和吸收体层上的正投影与所述第三电极及所述第四电极均不重叠。
  6. 根据权利要求5所述的发光二极管，其中，所述光放大器层包括：
    第三P型半导体层，所述第三P型半导体层设置在所述反射复合层上，所述第五电极设置在所述第三P型半导体层上；
    第三量子阱层，所述第三量子阱层设置在所述第三P型半导体层上，所述第三量子阱层在所述第三P型半导体层上的正投影与所述第五电极不重叠；以及
    第三N型半导体层，所述第三N型半导体层设置在所述第三量子阱层上，所述第三N型半导体层在所述第三P型半导体层上的正投影与所述第五电极不重叠，所述第六电极设置在所述第三N型半导体层上。
  7. 根据权利要求5所述的发光二极管，其中，所述第五电极和所述第六电极分别为所述光放大器层的阳极和阴极。
  8. 根据权利要求5所述的发光二极管，其中，所述反射复合层具有反射镜结构，且采用绝缘材料；或者，
    所述反射复合层包括叠层设置的第二绝缘层和第二反射镜层。
  9. 根据权利要求1-8任一项所述的发光二极管，其中，所述第一电极和所述第二电极分别为所述反射发光层的阳极和阴极，所述第三电极和所述第 四电极分别为所述可饱和吸收体层的阴极和阳极。
  10. 一种驱动方法，其中，用于驱动权利要求1-9任一项所述的发光二极管，所述方法包括：
    向第一电极输入第一正向电压，以及向第二电极输入第一负向电压。
  11. 根据权利要求10所述的方法，其中，所述方法还包括：
    向第三电极输入第二负向电压，以及向第四电极输入第二正向电压。
  12. 根据权利要求8-11任一项所述的方法，其中，所述发光二极管还包括光放大器层、第五电极和第六电极，所述方法还包括：
    向所述第五电极输入第三正向电压，以及向所述第六电极输入第三负向电压。
  13. 一种计算处理设备，其中，包括：
    存储器，其中存储有计算机可读代码；以及
    一个或多个处理器，当所述计算机可读代码被所述一个或多个处理器执行时，所述计算处理设备执行如权利要求10-12中任一项所述的驱动方法。
  14. 一种计算机程序，包括计算机可读代码，当所述计算机可读代码在计算处理设备上运行时，导致所述计算处理设备执行根据权利要求10-12中任一项所述的驱动方法。
  15. 一种计算机可读介质，其中存储了如权利要求14所述的计算机程序。
  16. 一种光源装置，其中，包括权利要求1-9任一项所述的发光二极管。
  17. 一种电子设备，其中，包括权利要求16所述的光源装置。
PCT/CN2021/094199 2020-05-27 2021-05-17 发光二极管及其驱动方法、光源装置及电子设备 WO2021238711A1 (zh)

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