WO2021233333A1 - 半导体封装结构及其封装方法 - Google Patents

半导体封装结构及其封装方法 Download PDF

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Publication number
WO2021233333A1
WO2021233333A1 PCT/CN2021/094600 CN2021094600W WO2021233333A1 WO 2021233333 A1 WO2021233333 A1 WO 2021233333A1 CN 2021094600 W CN2021094600 W CN 2021094600W WO 2021233333 A1 WO2021233333 A1 WO 2021233333A1
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Prior art keywords
bonding pad
lead
chip
silver
liquid
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PCT/CN2021/094600
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English (en)
French (fr)
Inventor
杨志强
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东莞链芯半导体科技有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Definitions

  • the invention relates to the field of semiconductors, in particular to a semiconductor packaging structure and a packaging method thereof.
  • a semiconductor package structure which includes chips, solder pads, leads, etc. wrapped in the package body, and solder balls are arranged at the bottom of the package body corresponding to the solder pads.
  • the solder balls can facilitate the semiconductor package structure and the circuit board.
  • the electrical connection can be realized, and the structure formed after soldering can also be used to make the part of the semiconductor package structure wrapped in the package body and the circuit board have a certain distance; through the above gap, the semiconductor package structure and the circuit board can be improved
  • the problem of heat dissipation between the semiconductor package structure and the circuit board can be avoided due to the inconsistency of the thermal expansion rate during the operation of the semiconductor package structure.
  • this semiconductor package structure has the above advantages, due to the low melting point of the solder ball, it is between the circuit board and the semiconductor package structure. During reflow soldering, it is easy to cause the solder ball to melt and spread to the surroundings, and then it is easy to short-circuit with the adjacent solder ball, and it is difficult to keep the semiconductor package structure and the circuit board between the semiconductor package structure and the circuit board after the solder ball is melted. Set the distance gap.
  • the present invention aims to solve at least one of the technical problems existing in the prior art. For this reason, the present invention proposes a semiconductor package structure, which can maintain a sufficient preset distance gap with the circuit board, and can avoid the problem of diffusion and shorting during soldering.
  • the invention also provides a semiconductor packaging method.
  • a semiconductor package structure includes: a chip, a silver solder pad, a lead, and a package body; the silver solder pad includes a lead solder pad; one end of the lead is connected to the lead solder pad, and the other end is connected The chip; the package body covers the chip and the lead, and the lead bonding pad protrudes from the lower surface of the package body.
  • the semiconductor package structure according to the embodiment of the first aspect of the present invention has at least the following beneficial effects: since the lead pads protrude from the lower surface of the package body, when connecting with the circuit board, only a small amount of the lower surface of the lead pads needs to be smeared.
  • the solder paste is then reflowed to complete the connection between the semiconductor package structure and the circuit board; with the support of the wire bonding pad, a sufficient preset distance gap can be maintained between the semiconductor package structure and the circuit board, and due to the wire soldering
  • the pad is a silver soldering pad. Silver has a high melting point. During reflow soldering, it can maintain its inherent shape and will not diffuse to the surrounding due to melting. Therefore, it can avoid short diffusion when soldering to the circuit board. The problem.
  • the silver bonding pad includes a chip bonding pad, the chip is disposed on the chip bonding pad, and the chip bonding pad protrudes from the lower surface of the package body.
  • the semiconductor package structure includes a DAF film, the DAF film protrudes from the lower surface of the package body, and one side of the DAF film is bonded to the chip.
  • the height of the silver solder pad is between 10-100 microns.
  • both ends of the lead are connected to the chip or the lead pad by welding.
  • the semiconductor packaging method includes the following steps: setting a liquid storage tank at the position of the metal plate corresponding to the lead bonding pad; injecting liquid silver material into the liquid storage tank; making the liquid silver The material is solidified into silver solder pads in the liquid tank; the two ends of the lead are respectively connected to the chip and the lead solder pads obtained by curing; encapsulation, and the package body covers the chip and the lead from the metal plate; removes the metal Board; cut to form independent packaged chips.
  • the lead frame according to the embodiment of the second aspect of the present invention has at least the following beneficial effects: the semiconductor package structure manufactured by the above method has lead pads protruding from the lower surface of the package body, and only needs to be connected to the circuit board when the lead frame is connected to the circuit board. Apply a little tin paste on the lower surface of the soldering pads, and then perform reflow soldering to complete the connection between the semiconductor package structure and the circuit board; with the support of the lead soldering pads, it is possible to maintain sufficient preheating between the semiconductor package and the circuit board. Set a distance gap, and because the lead pad is a silver pad, silver has a high melting point. During reflow soldering, it can maintain its original shape well without spreading to the surrounding due to melting, so it can be avoided There is a problem of diffusion and shorting during welding.
  • the liquid silver material is any one of low-temperature sintered silver paste or light-cured silver paste.
  • the liquid silver material is solidified into a silver solder pad in the liquid tank by baking, light curing or laser sintering.
  • an anti-oxidation protection layer is preset on the upper surface of the metal plate.
  • a protective gas is used to prevent oxidation of the metal plate.
  • the liquid silver material is injected into the liquid storage tank by 3D printing.
  • the liquid storage tank is opened on the metal plate by means of laser cutting or chemical etching.
  • the liquid storage tank is also opened on the metal plate at a position corresponding to the chip bonding pad.
  • FIG. 1 is a semiconductor package structure according to an embodiment of the present invention
  • FIG. 2 is a schematic diagram of a packaging process of a semiconductor packaging method according to an embodiment of the present invention.
  • first, second, third, etc. may be used in the embodiments to describe various structures, systems, and data, these structures, systems, and data should not be limited to these terms. These terms are only used to distinguish the same type of structure, system, and data from each other.
  • first data may also be referred to as second data
  • second data may also be referred to as first data.
  • the use of any and all examples or exemplary language (“such as”, “such as”, etc.) provided herein is only intended to better illustrate the embodiments of the present invention, and unless otherwise required, will not impose limitations on the scope of the present invention .
  • the semiconductor package structure 100 of the embodiment of the present invention includes: a chip 30, a silver pad, a lead 40, and a package body 50; the silver pad includes a lead pad 210; one end of the lead 40 is connected to the wire bond The other end of the pad 210 is connected to the chip 30; the package body 50 covers the chip 30 and the lead 40, and the lead bonding pad 210 protrudes from the lower surface of the package body 50.
  • the lead pad 210 protrudes from the lower surface of the package body 50, when connecting with the circuit board, only a little solder paste is applied on the lower surface of the lead pad 210, and then reflow soldering is performed to complete the semiconductor package structure 100 Connection with the circuit board; with the support of the lead pad 210, a sufficient preset distance gap can be maintained between the semiconductor package structure 100 and the circuit board, and since the lead pad 210 is a silver pad, silver has a high The melting point can well maintain its inherent shape during reflow soldering, and will not spread to the surrounding due to melting, so it can avoid the problem of diffusion and shorting during soldering.
  • the silver bonding pad includes a chip bonding pad 220, the chip 30 is disposed on the chip bonding pad 220, and the chip bonding pad 220 protrudes under the package body 50 surface. Therefore, when connecting with the circuit board, the position of the chip 30 of the semiconductor packaging structure 100 is supported by the chip bonding pad 220, which can be more safe and reliable.
  • the semiconductor package structure 100 may also include a DAF film, which is protrudingly disposed under the package body 50. On the surface, one side of the DAF film is bonded to the chip 30, so that the position of the chip 30 of the semiconductor package structure 100 is supported by the DAF film.
  • the height of the silver pad is between 10-100 microns, for example, it can be 10 microns, 30 microns, 70 microns, 100 microns, etc.
  • the height of the silver solder pad is mainly determined by the predetermined distance between the semiconductor package structure 100 and the circuit board. The larger the predetermined distance between the semiconductor package structure 100 and the circuit board, the higher the height of the silver solder pad.
  • the two ends of the lead are connected to the chip 30 or the lead bonding pad 210 by welding; specifically, in order to ensure higher conductivity, the lead selects silver bonding wire, Gold bonding wires, or gold-silver alloy bonding wires, etc., are soldered to the chip 30 and the lead bonding pad 210 through solder paste.
  • the semiconductor packaging method includes the following steps: setting a liquid storage tank 110 at the position of the metal plate 10 corresponding to the lead bonding pad 210; injecting liquid into the liquid storage tank 110 Silver material; solidify the liquid silver material into a silver solder pad in the liquid tank 110; connect both ends of the lead 40 to the chip 30 and the solidified lead solder pad 210; package, and make the package body 50 covers the chip 30 and the leads 40 from the top of the metal plate 10; removes the metal plate 10; and cuts to form an independent packaged chip 30.
  • the silver solder pad is formed by solidifying the liquid silver material in the liquid storage tank 110, the edge of the solder pad can be prevented from being uneven, and the thickness of the silver solder pad can be effectively ensured to be in the preset range; at the same time, it is made by the above method
  • the lead bonding pad 210 protrudes from the lower surface of the package body 50. When connecting with the circuit board, only a small amount of solder paste is applied to the lower surface of the lead bonding pad 210, and then reflow soldering is performed.
  • the metal plate 10 is made of metal copper, which has good electrical conductivity and is also easy to process; of course, according to actual conditions, in some other embodiments of the present invention, the metal plate The member 10 can also be made of other metal materials such as metal aluminum or metal iron.
  • the copper material removed after mechanical peeling or chemical etching can be reused by melting or chemical extraction.
  • the metal plates in the manufacturing process such as copper plates
  • the lead frame part is formed
  • the copper plate will be encapsulated inside the package body to participate in the formation of part of the structure in the QFN package semiconductor. Therefore, using the traditional QFN semiconductor packaging structure and packaging method, the consumption of copper material will be much greater than the semiconductor packaging structure and packaging method provided by the embodiments of the present invention.
  • the liquid silver material is a low-temperature sintered silver paste
  • the low-temperature sintered silver paste can be cured by low-temperature baking; when curing by baking, if the baking temperature is too high, it will cause the metal plate
  • the surface of the piece 10 is oxidized.
  • the metal plate 10 is made of copper
  • the surface of the metal plate 10 will be black and green, and the use of low-temperature sintered silver paste can be baked and solidified at a lower temperature, thereby avoiding the metal
  • the surface of the board 10 is oxidized; and low-temperature sintered silver paste is used to solidify to form a silver solder pad. Since only low-temperature baking is required, it is also more energy-saving and environmentally friendly.
  • a low-temperature sintered silver paste with a curing temperature below 300°C is selected, and when the liquid silver material is cured by baking, the baking temperature is 250°C- Between 300°C.
  • liquid silver materials of other properties such as light-cured silver paste can also be selected; light-cured silver paste can be cured by UV light, which can also avoid causes The problem of surface oxidation of the metal plate 10 caused by excessively high temperature during curing.
  • the form of laser sintering can also be selected; taking the liquid silver material using low-temperature sintering silver paste as an example ,
  • the low-temperature sintered silver paste in the liquid storage tank 110 can be irradiated at a fixed point by the laser equipment, so that the low-temperature sintered silver paste can be quickly heated to above the curing temperature, so as to quickly solidify into a silver solder pad; and with the help of the high precision and high controllability of the laser
  • the temperature of the metal plate 10 can basically remain unchanged, so the problem of high-temperature oxidation of the metal plate 10 can also be effectively avoided.
  • the shielding gas is used to further prevent the metal plate 10 from being oxidized.
  • Baking and curing can be carried out in an oven. Before baking, pass a protective gas such as nitrogen or helium into the oven, and then make the metal plate 10 to be baked in an atmosphere full of protective gas to prevent the metal plate 10 from being It reacts with oxygen during baking.
  • an anti-oxidation protection layer is preset on the part of the metal plate 10 except for the liquid storage tank 110.
  • the anti-oxidation protective layer is coated on the metal plate 10 by a chemical coating method, and avoids the position of the liquid storage tank 110 during the coating. Through the anti-oxidation protective layer, even at high temperatures and no protective gas atmosphere The metal plate 10 can also be prevented from oxidation; specifically, the thickness of the anti-oxidation protection layer is between 1-5 microns; of course, according to actual conditions, in some other embodiments of the present invention, the method of electroplating can also be selected Set up an anti-oxidation protective layer.
  • the liquid silver material is injected into the liquid storage tank 110 by 3D printing. And because the silver solder pad is formed by solidification after 3D printing of liquid silver material, the entire silver solder pad formation process does not involve an electroplating process, so it will be more green and environmentally friendly.
  • the liquid storage tank 110 is opened on the metal plate 10 by means of laser cutting, which has high processing accuracy, high speed, and is more environmentally friendly.
  • the liquid storage tank 110 may also be formed on the metal plate by etching.
  • the depth of the liquid storage tank 110 is set between 10-120 micrometers, the depth of the liquid storage tank 110 mainly depends on the thickness of the solder pad, and the width of the liquid storage tank 110 is set between 200-300 micrometers, The thickness of the groove 110 mainly depends on the accuracy of the wire bonding equipment during wire bonding.
  • a liquid reservoir is also provided on the metal plate 10 corresponding to the position of the chip bonding pad 220. ⁇ 110.
  • the following describes the semiconductor packaging structure 100 of the first aspect of the present invention and the semiconductor packaging method of the second aspect in the form of a specific embodiment with reference to FIGS. 1 and 2.
  • the semiconductor package structure 100 includes: a chip 30, a silver pad, a lead 40 and a package body 50; the silver pad includes a wire pad 210 and a chip pad 220; the chip 30 is arranged on the chip pad 220 One end of the lead 40 is connected to the lead bonding pad 210, and the other end is connected to the chip 30; the package body 50 covers the chip 30 and the lead 40, and the lead bonding pad 210 and the chip bonding pad 220 protrude from the The lower surface of the package body 50, and the height of the lead pad 210 and the chip pad 220 are both 50 microns; specifically, the lead 40 is a silver wire, and both ends are soldered to the chip 30 and the lead pad 210 by solder paste.
  • the above-mentioned semiconductor packaging structure 100 is manufactured by the following semiconductor packaging method.
  • the semiconductor packaging method includes the following steps: cutting out the liquid storage tank 110 at the positions corresponding to the lead bonding pad 210 and the chip bonding pad 220 on the metal plate 10 by laser processing equipment; the depth of the liquid storage tank 110 is 10-120 The width of the liquid storage tank 110 is between 200-300 micrometers, and specifically is 250 micrometers; the metal plate 10 except for the liquid storage tank 110 is formed by chemical coating Anti-oxidation protection layer, the thickness of the anti-oxidation protection layer is between 1-5 microns, specifically 2 microns; 3D printing is used to inject low-temperature sintered silver paste into the liquid storage tank 110 through 3D printing equipment; a period of time is passed into the oven Nitrogen, and the original air in the oven is exhausted; the metal plate 10 with low-temperature sintering silver paste is placed in the oven, and then the oven is kept at 250°C-300°C for baking under a nitrogen atmosphere, specifically 270°C, And solidify the liquid silver material into the silver solder pad in the liquid storage tank 110; solder the two ends

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Abstract

本发明提出了一种半导体封装结构及其封装方法，半导体封装结构包括：芯片、银焊垫、引线和封装体；银焊垫包括有引线焊垫；引线一端连接引线焊垫，另一端连接芯片；封装体包覆芯片和引线，且引线焊垫凸出于封装体下表面。本发明由于引线焊垫凸出于封装体下表面，在与电路板连接时，只需在引线焊垫下表面抹上少些锡膏，然后进行回流焊，即可完成半导体封装结构与电路板的连接；借助引线焊垫的支撑作用，可以使得半导体封装件与电路板之间保持足够的预设距离间隙，由于引线焊垫为银焊垫，具有很高的熔点，在回流焊时，不会出现因融化而向四周扩散的问题，因此可以避免出现焊接时扩散短接的问题。

Description

半导体封装结构及其封装方法 技术领域
本发明涉及半导体领域，特别涉及一种半导体封装结构及其封装方法。
背景技术
目前，有一种半导体封装结构，其包括有包裹在封装体内的芯片、焊垫、引线等，并且封装体底部对应焊垫的位置还设置有锡球，通过锡球可以便于半导体封装结构与电路板实现电连接，并且还可以借助锡球焊接后形成的结构，使得半导体封装结构中包裹在封装体中的部分与电路板之间具有一定的距离间隔；通过上述间隔可以改善半导体封装结构与电路板之间的散热问题，并且可以避免半导体封装结构和电路板工作时因热膨胀率不一致而导致的脱焊问题；这种半导体封装结构虽然具有上述优点，但是由于锡球熔点低，在与电路板之间进行回流焊时容易出现锡球融化向四周扩散的问题，进而容易出现与相邻锡球出现短接的问题，并且锡球融化后也难以使半导体封装结构与电路板之间保持足够的预设距离间隙。
发明内容
本发明旨在至少解决现有技术中存在的技术问题之一。为此，本发明提出了一种半导体封装结构，其能够与电路板之间保持足够的预设距离间隙，并且可以避免出现焊接时扩散短接的问题。
本发明还提出一种半导体封装方法。
根据本发明的第一方面实施例的半导体封装结构，包括：芯片、银焊垫、引线和封装体；所述银焊垫包括有引线焊垫；引线一端连接所述引线焊垫，另一端连接所述芯片；封装体包覆所述芯片和引线，且所述引线焊垫凸出于所述 封装体下表面。
根据本发明第一方面实施例的半导体封装结构，至少具有如下有益效果：由于引线焊垫凸出于封装体下表面，在与电路板连接时，只需在引线焊垫下表面抹上少些锡膏，然后进行回流焊，即可完成半导体封装结构与电路板的连接；借助引线焊垫的支撑作用，可以使得半导体封装结构与电路板之间保持足够的预设距离间隙，并且由于引线焊垫为银焊垫，银具有很高的熔点，在回流焊时，可以很好地保持固有的形状，不会出现因融化而向四周扩散的问题，因此与电路板焊接时可以避免出现扩散短接的问题。
根据本发明的一些实施例，所述银焊垫包括有芯片焊垫，所述芯片设置在所述芯片焊垫上，所述芯片焊垫凸出于所述封装体下表面。
根据本发明的一些实施例，半导体封装结构包括有DAF膜，所述DAF膜凸出于所述封装体下表面，且所述DAF膜一侧与所述芯片粘接。
根据本发明的一些实施例，所述银焊垫的高度在10-100微米之间。
根据本发明的一些实施例，所述引线的两端通过焊接的方式连接在所述芯片或引线焊垫上。
根据本发明的第二方面实施例的半导体封装方法，包括以下步骤：在金属板件对应引线焊垫的位置设置贮液槽；在所述贮液槽内注入液态银材料；使所述液态银材料在所述贮液槽内固化成银焊垫；将引线的两端分别连接至芯片及固化得到的引线焊垫上；封装，并使封装体从金属板件上方包覆芯片及引线；去除金属板件；切割形成独立封装芯片。
根据本发明第二方面实施例的引线框架，至少具有如下有益效果：通过上述方法制作的半导体封装结构，其引线焊垫凸出于封装体下表面，在与电路板连接时，只需在引线焊垫下表面抹上少些锡膏，然后进行回流焊，即可完成半导体封装结构与电路板的连接；借助引线焊垫的支撑作用，可以使得半导体封装件与电路板之间保持足够的预设距离间隙，并且由于引线焊垫为银焊垫，银具有很高的熔点，在回流焊时，可以很好地保持固有的形状，不会出现因融化 而向四周扩散的问题，因此可以避免出现焊接时扩散短接的问题。
根据本发明的一些实施例，所述液态银材料为低温烧结银浆或光固化银浆中的任一一种。
根据本发明的一些实施例，通过烘烤或光固化或激光烧结的方式使所述液态银材料在所述贮液槽内固化成银焊垫。
根据本发明的一些实施例，通过烘烤固化所述液态银材料前，在所述金属板件上表面预设抗氧化保护层。
根据本发明的一些实施例，通过烘烤固化所述液态银材料时，通过保护气体避免所述金属板件氧化。
根据本发明的一些实施例，所述液态银材料通过3D打印的方式注入所述贮液槽内。
根据本发明的一些实施例，所述贮液槽通过激光切割或者化学蚀刻的方式开设在所述金属板件上。
根据本发明的一些实施例，在所述金属板件上对应芯片焊垫的位置同样开设所述贮液槽。
本发明的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本发明的实践了解到。
附图说明
图1为本发明实施例的半导体封装结构；
图2为本发明实施例的半导体封装方法的封装过程示意图。
附图标记：
半导体封装结构100、金属板件10、贮液槽110、引线焊垫210、芯片焊垫220、芯片30、引线40、封装体50。
具体实施方式
以下将结合实施例和附图对本发明的构思、具体系统、方法及产生的技术效果进行清楚、完整地描述，以充分地理解本发明的目的、特征和效果。显然，所描述的实施例只是本发明的一部分实施例，而不是全部实施例，基于本发明的实施例，本领域的技术人员在不付出创造性劳动的前提下所获得的其他实施例，均属于本发明保护的范围。
需要说明的是，如无特殊说明，在实施例中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。此外，除非另有定义，本文所使用的所有的技术和科学术语与本技术领域的技术人员通常理解的含义相同。本文说明书中所使用的术语只是为了描述具体的实施例，而不是为了限制本发明。本文所使用的术语“和/或”包括一个或多个相关的所列项目的任意的组合。
应当理解，尽管在实施例可能采用术语第一、第二、第三等来描述各种结构、系统、数据，但这些结构、系统、数据不应限于这些术语。这些术语仅用来将同一类型的结构、系统、数据彼此区分开。例如，在不脱离实施例范围的情况下，第一数据也可以被称为第二数据，类似地，第二数据也可以被称为第一数据。本文所提供的任何以及所有实例或示例性语言(“例如”、“如”等)的使用仅意图更好地说明本发明的实施例，并且除非另外要求，否则不会对本发明的范围施加限制。
参照图1，本发明实施例的半导体封装结构100，包括：芯片30、银焊垫、引线40和封装体50；所述银焊垫包括有引线焊垫210；引线40一端连接所述引线焊垫210，另一端连接所述芯片30；封装体50包覆所述芯片30和引线40，且所述引线焊垫210凸出于所述封装体50下表面。
由于引线焊垫210凸出于封装体50的下表面，在与电路板连接时，只需在引线焊垫210下表面抹上少些锡膏，然后进行回流焊，即可完成半导体封装结构100与电路板的连接；借助引线焊垫210的支撑作用，可以使得半导体封装结构100与电路板之间保持足够的预设距离间隙，并且由于引线焊垫210为银 焊垫，银具有很高的熔点，在回流焊时，可以很好地保持固有的形状，不会出现因融化而向四周扩散的问题，因此可以避免出现焊接时扩散短接的问题。
由于引线焊垫210设置于芯片30的四周，当半导体封装结构100仅通过引线焊垫210连接电路板时，半导体封装结构100对应芯片30的位置将处于悬空的状态，由于芯片30较为脆弱，因此在本发明的一些实施例中，所述银焊垫包括有芯片焊垫220，所述芯片30设置在所述芯片焊垫220上，所述芯片焊垫220凸出于所述封装体50下表面。从而在与电路板连接时，借助芯片焊垫220对半导体封装结构100的芯片30位置进行支撑，可以更加安全可靠。
当然根据实际情况，除了可以选择采用芯片焊垫220的结构之外，在其他一些实施例中，半导体封装结构100也可包括DAF膜，所述DAF膜凸出设置于所述封装体50的下表面，且所述DAF膜一侧与所述芯片30粘接，从而借助DAF膜对半导体封装结构100的芯片30位置进行支撑。
根据本发明的一些实施例，所述银焊垫的高度在10-100微米之间，例如可以为10微米、30微米、70微米、100微米等。银焊垫的高度主要由半导体封装结构100与电路板之间的预设间距决定，当半导体封装结构100与电路板之间的预设间距越大，银焊垫的高度就越高。
在本发明的其他一些实施例中，所述引线的两端通过焊接的方式连接在所述芯片30或引线焊垫210上；具体地，为了保证较高的导电率，引线选用银焊线、金焊线、或者金银合金焊线等，并通过锡膏与芯片30及引线焊垫210焊接。
参照图2，根据本发明的第二方面实施例的半导体封装方法，包括以下步骤：在金属板件10对应引线焊垫210的位置设置贮液槽110；在所述贮液槽110内注入液态银材料；使所述液态银材料在所述贮液槽110内固化成银焊垫；将引线40的两端分别连接至芯片30及固化得到的引线焊垫210上；封装，并使封装体50从金属板件10上方包覆芯片30及引线40；去除金属板件10；切割形成独立封装芯片30。
由于银焊垫是通过液态银材料在贮液槽110内固化形成的，进而可以避免 焊垫的边缘不平整，并有效保证银焊垫的厚度处于预设的范围；同时，通过上述方法制作的半导体封装结构100，其引线焊垫210凸出于封装体50下表面，在与电路板连接时，只需在引线焊垫210下表面抹上少些锡膏，然后进行回流焊，即可完成半导体封装结构100与电路板的连接；借助引线焊垫210的支撑作用，可以使得半导体封装件与电路板之间保持足够的预设距离间隙，并且由于引线焊垫210为银焊垫，银具有很高的熔点，在回流焊时，可以很好地保持固有的形状，不会出现因融化而向四周扩散的问题，因此可以避免出现焊接时扩散短接的问题。
在本发明的一些实施例中，金属板件10采用金属铜制成，金属铜具有较好的导电性，同时也便于加工；当然根据实际情况，在本发明的其他一些实施例中，金属板件10也可选择采用金属铝或者金属铁等其他金属材料制成。
去除金属板件10，可以选择采用机械剥离的方式或者采用化学蚀刻的方式，以金属铜为例，机械剥离后或者化学蚀刻去除的铜材，可以通过熔融或者化学提取的方式对铜材再次利用，提高铜材料的利用率，更加环保；并且，传统的QFN封装半导体结构，其制作过程中的金属板件，如铜板材，将参与构成引线框架结构，并且在封装时，构成引线框架部分的铜板材，将被封装在封装体内部，参与形成QFN封装半导体中的部分结构。因此，采用传统的QFN半导体封装结构及封装方法，铜材料的消耗量将远大于本发明实施例所提供的半导体封装结构及封装方法。
在本发明的一些实施例中，液态银材料为低温烧结银浆，低温烧结银浆可以通过低温烘烤的形式实现固化；在通过烘烤方式固化时，如果烘烤温度过高会导致金属板件10表面发生氧化，如金属板件10为铜材时，将会使金属板件10表面发黑发绿，而采用低温烧结银浆可以在较低的温度下进行烘烤固化，从而避免金属板件10表面发生氧化；并且采用低温烧结银浆固化形成银焊垫，由于只需要采用低温烘烤，因此也更加节能环保。在本发明的一些实施例中，为了进一步避免金属板件10表面出现氧化，选择固化温度在300℃以下的低温 烧结银浆，并且通过烘烤固化液态银材料时，烘烤温度在250℃-300℃之间。
当然根据实际情况，在本发明的其他一些实施例中，也可选择采用光固化银浆等其他性质的液态银材料；光固化银浆可以通过UV光线照射的形式实现光固化，同样可以避免因固化时温度过高导致的金属板件10表面氧化的问题。
当然根据实际情况，在本发明的其他一些实施例中，除了低温烘烤和光固化的形式固化液态银材料之外，也可以选择采用激光烧结的形式；以液态银材料采用低温烧结银浆为例，可通过激光设备定点照射贮液槽110内的低温烧结银浆，使低温烧结银浆快速升温至固化温度之上，从而迅速固化成银焊垫；并且借助激光的高精度和高度可控性，定点照射低温烧结银浆，虽然低温烧结银浆的温度将快速上升，但是金属板件10的温度却可以基本保持不变，因此也可以有效避免金属板件10出现高温氧化的问题。
在本发明的一些实施例中，通过烘烤固化液态银材料时，通过保护气体进一步避免金属板件10氧化。烘烤固化可以在烤箱内进行，在烘烤前先将烤箱内通入氮气或者氦气等保护气体，然后使得金属板件10在充满保护气体的氛围下进行烘烤，避免金属板件10在烘烤时与氧气发生氧化反应。
在本发明的一些实施例中，通过烘烤固化液态银材料前，在金属板件10除贮液槽110之外的部分预设抗氧化保护层。抗氧化保护层采用化学涂覆的方式涂覆在金属板件10上，并在涂覆时避开贮液槽110的位置，通过抗氧化保护层，即使是在高温下并且没有保护气体的氛围下也能够避免金属板件10发生氧化；具体地，抗氧化保护层的厚度在1-5微米之间；当然根据实际情况，在本发明的其他一些实施例中，也可以选择采用电镀的方式设置抗氧化保护层。
在本发明的一些实施例中，所述液态银材料通过3D打印的方式注入所述贮液槽110内。并且由于银焊垫是通过液态银材料3D打印后固化所形成的，整个银焊垫的形成过程都不涉及电镀工艺，因此也将更加绿色环保。
在本发明的一些实施例中，贮液槽110通过激光切割的方式开设在金属板件10上，激光切割的方式加工精度高，速度快，并且更加环保。当然根据实际 情况，在本发明的其他一些实施例中，也可以选择采用蚀刻的方式在金属板上形成贮液槽110。并且，具体地，贮液槽110的深度设置在10-120微米之间，贮液槽110的深度主要取决于焊垫的厚度，而贮液槽110的宽度设置在200-300微米，贮液槽110的厚度主要取决于焊线时焊线设备的精度。
由于部分半导体封装结构100存在芯片焊垫220，在本发明的一些实施例中，对于半导体封装结构100存在芯片焊垫220的，在金属板件10上对应芯片焊垫220的位置同样开设贮液槽110。
下面结合附图1、图2，以一个具体实施例的形式描述本发明第一方面的半导体封装结构100和第二方面的半导体封装方法。
半导体封装结构100包括：芯片30、银焊垫、引线40和封装体50；所述银焊垫包括有引线焊垫210和芯片焊垫220；所述芯片30设置在所述芯片焊垫220上；引线40一端连接所述引线焊垫210，另一端连接所述芯片30；封装体50包覆所述芯片30和引线40，所述引线焊垫210和芯片焊垫220均凸出于所述封装体50下表面，且引线焊垫210和芯片焊垫220的高度均为50微米；具体地，引线40为银焊线，并且两端通过锡膏与芯片30及引线焊垫210焊接。
上述半导体封装结构100采用以下半导体封装方法制成。
半导体封装方法包括有以下步骤：通过激光加工设备在金属板件10上对应引线焊垫210和芯片焊垫220的位置，均切割出贮液槽110；贮液槽110的深度度在10-120微米之间，且具体为50微米；贮液槽110的宽度在200-300微米之间，且具体为250微米；金属板件10除贮液槽110之外的部分通过化学涂覆的方式形成抗氧化保护层，抗氧化保护层的厚度在1-5微米之间，具体为2微米；通过3D打印设备在贮液槽110内3D打印注入低温烧结银浆；往烤箱内通入一段时间的氮气，并使得烤箱内的原有空气排出；将带有低温烧结银浆的金属板件10置于烤箱内，然后在氮气氛围下使烤箱保持250℃-300℃烘烤，具体为270℃，并使液态银材料在贮液槽110内固化成银焊垫；将引线40的两端分别焊接到芯片30及固化得到的引线焊垫210上；封装，并使封装体50 从金属板件10上方包覆芯片30及引线40；通过机械剥离的方式，去除金属板件10，此时得到的引线焊垫210及芯片焊垫220将凸出于封装体50的下表面；最后通过切割，得到独立封装芯片30。
以上所述，只是本发明的较佳实施例而已，本发明并不局限于上述实施方式，只要其以相同的手段达到本发明的技术效果，凡在本发明的精神和原则之内，所做的任何修改、等同替换、改进等，均应包含在本发明保护的范围之内。在本发明的保护范围内其技术方案和/或实施方式可以有各种不同的修改和变化。

Claims (10)

  1. 半导体封装结构，其特征在于，包括：
    芯片；
    银焊垫，所述银焊垫包括有引线焊垫；
    引线，一端连接所述引线焊垫，另一端连接所述芯片；
    封装体，包覆所述芯片和引线，且所述引线焊垫凸出于所述封装体下表面。
  2. 根据权利要求1所述的半导体封装结构，其特征在于，所述银焊垫包括有芯片焊垫，所述芯片设置在所述芯片焊垫上，所述芯片焊垫凸出于所述封装体下表面。
  3. 根据权利要求1所述的半导体封装结构，包括有DAF膜，所述DAF膜凸出于所述封装体下表面，且所述DAF膜一侧与所述芯片粘接。
  4. 半导体封装方法，其特征在于，包括以下步骤：
    在金属板件对应引线焊垫的位置设置贮液槽；
    在所述贮液槽内注入液态银材料；
    使所述液态银材料在所述贮液槽内固化成银焊垫；
    将引线的两端分别连接至芯片及固化得到的引线焊垫上；
    封装，并使封装体从金属板件上方包覆芯片及引线；
    去除金属板件；
    切割形成独立封装芯片。
  5. 根据权利要求4所述的半导体封装方法，其特征在于，所述液态银材料为低温烧结银浆或光固化银浆中的任一一种。
  6. 根据权利要求1所述的半导体封装方法，其特征在于，通过烘烤或光固化或激光烧结的方式使所述液态银材料在所述贮液槽内固化成银焊垫。
  7. 根据权利要求6所述的半导体封装方法，其特征在于，通过烘烤固化所述液态银材料前，在所述金属板件上表面预设抗氧化保护层；或者通过烘烤固 化所述液态银材料时，通过保护气体避免所述金属板件氧化。
  8. 根据权利要求4所述的半导体封装方法，其特征在于，所述液态银材料通过3D打印的方式注入所述贮液槽内。
  9. 根据权利要求4所述的半导体封装方法，其特征在于，所述贮液槽通过激光切割或者化学蚀刻的方式开设在所述金属板件上。
  10. 根据权利要求4-9任一项所述的半导体封装方法，其特征在于，在所述金属板件上对应芯片焊垫的位置同样开设所述贮液槽。
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CN111540691A (zh) * 2020-05-22 2020-08-14 东莞链芯半导体科技有限公司 半导体封装结构及其封装方法
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050218499A1 (en) * 2004-03-31 2005-10-06 Advanced Semiconductor Engineering, Inc. Method for manufacturing leadless semiconductor packages
CN101393900A (zh) * 2007-09-20 2009-03-25 株式会社瑞萨科技 半导体器件及其制造方法
CN101834166A (zh) * 2009-03-09 2010-09-15 Asat有限公司 具有支架触点以及管芯附垫的无引脚集成电路封装
CN106409785A (zh) * 2016-11-30 2017-02-15 天水华天科技股份有限公司 一种薄型阵列塑料封装件及其生产方法
CN111540691A (zh) * 2020-05-22 2020-08-14 东莞链芯半导体科技有限公司 半导体封装结构及其封装方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6072239A (en) * 1995-11-08 2000-06-06 Fujitsu Limited Device having resin package with projections
KR20020031881A (ko) * 2000-10-24 2002-05-03 최종언 반도체 패키지 및 그 제조방법
CN212062388U (zh) * 2020-05-22 2020-12-01 东莞链芯半导体科技有限公司 半导体封装结构

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050218499A1 (en) * 2004-03-31 2005-10-06 Advanced Semiconductor Engineering, Inc. Method for manufacturing leadless semiconductor packages
CN101393900A (zh) * 2007-09-20 2009-03-25 株式会社瑞萨科技 半导体器件及其制造方法
CN101834166A (zh) * 2009-03-09 2010-09-15 Asat有限公司 具有支架触点以及管芯附垫的无引脚集成电路封装
CN106409785A (zh) * 2016-11-30 2017-02-15 天水华天科技股份有限公司 一种薄型阵列塑料封装件及其生产方法
CN111540691A (zh) * 2020-05-22 2020-08-14 东莞链芯半导体科技有限公司 半导体封装结构及其封装方法

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