WO2021226743A1 - 显示面板及其制作方法和显示装置 - Google Patents

显示面板及其制作方法和显示装置 Download PDF

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Publication number
WO2021226743A1
WO2021226743A1 PCT/CN2020/089361 CN2020089361W WO2021226743A1 WO 2021226743 A1 WO2021226743 A1 WO 2021226743A1 CN 2020089361 W CN2020089361 W CN 2020089361W WO 2021226743 A1 WO2021226743 A1 WO 2021226743A1
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WIPO (PCT)
Prior art keywords
area
alignment mark
flat
display panel
metal layer
Prior art date
Application number
PCT/CN2020/089361
Other languages
English (en)
French (fr)
Inventor
杨慧娟
刘庭良
尚庭华
周洋
于鹏飞
张毅
王俊喜
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN202080000685.3A priority Critical patent/CN113924652A/zh
Priority to US17/280,130 priority patent/US11957033B2/en
Priority to EP20922490.6A priority patent/EP4148798A4/en
Priority to PCT/CN2020/089361 priority patent/WO2021226743A1/zh
Publication of WO2021226743A1 publication Critical patent/WO2021226743A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/88—Dummy elements, i.e. elements having non-functional features
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/133374—Constructional arrangements; Manufacturing methods for displaying permanent signs or marks
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1345—Conductors connecting electrodes to cell terminals
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/1613—Constructional details or arrangements for portable computers
    • G06F1/1633—Constructional details or arrangements of portable computers not specific to the type of enclosures covered by groups G06F1/1615 - G06F1/1626
    • G06F1/1637—Details related to the display arrangement, including those related to the mounting of the display in the housing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/16—Constructional details or arrangements
    • G06F1/20—Cooling means
    • G06F1/203—Cooling means for portable computers, e.g. for laptops
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/191—Deposition of organic active material characterised by provisions for the orientation or alignment of the layer to be deposited
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/20—Changing the shape of the active layer in the devices, e.g. patterning

Definitions

  • the present disclosure relates to the field of display technology, and in particular, to a display panel, a manufacturing method thereof, and a display device.
  • Pad bending (circuit board bending) technology can be used on the upper or lower frame of the display panel, and the circuit board is bent.
  • the folding technology is to bend part of the circuit board included in the display device (the circuit board may be a flexible circuit board) to the back of the display panel, and attach a heat dissipation film to the surface of the circuit board that is bent to the back of the display panel to reduce The heat generated when a small circuit is working.
  • the alignment needs to be realized by recognizing the alignment marks in the display panel. In the related art, it is impossible to provide a technical solution that can accurately perform alignment marks in a four-sided curved display panel without adding a frame.
  • the main purpose of the present disclosure is to provide a display panel, a manufacturing method thereof, and a display device.
  • an embodiment of the present disclosure provides a display panel including an alignment mark area provided in a flat area of a peripheral area of the display panel;
  • the peripheral area is an area other than an effective display area included in the display panel
  • An alignment mark pattern is arranged in the alignment mark area; and/or, in the alignment mark area, at least one film layer is hollowed out.
  • the film layer includes a metal layer.
  • the surface of the display panel is flat.
  • the display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface, and a fourth side surface;
  • the first side surface, the second side surface, the third side surface, and the fourth side surface are all curved side surfaces
  • the first plane is parallel to the lower surface.
  • the edge of the orthographic projection of the alignment mark area on the substrate is polygonal, L-shaped, or T-shaped, and the orthographic projection of the alignment mark pattern on the substrate is L-shaped, T-shaped, or Polygon.
  • the flat area includes a flat fan-out area; the alignment mark area is included in the flat fan-out area;
  • the display panel includes a first metal layer disposed on a substrate;
  • the first metal layer is hollowed out
  • the first metal layer includes a first metal pattern, and the first metal pattern is arranged around the alignment mark area.
  • the first metal pattern includes a connection line between the data line and the source driver.
  • the first metal pattern includes a DC voltage signal line.
  • the display panel further includes a semiconductor layer disposed between the substrate and the first metal layer;
  • the semiconductor layer is hollowed out
  • the semiconductor layer includes an alignment mark pattern.
  • the display panel further includes an anode layer disposed on a side of the first metal layer away from the substrate;
  • the anode layer is not provided with an opening
  • the anode layer is provided with a plurality of openings arranged at intervals.
  • the flat area includes a flat signal line area; the alignment mark area is included in the flat signal line area;
  • the display panel includes a semiconductor layer disposed on a substrate;
  • the semiconductor layer includes an alignment mark pattern.
  • the flat area includes a flat signal line area; the alignment mark area is included in the flat signal line area;
  • the display panel includes a second metal layer disposed on the substrate;
  • the second metal layer is hollowed out.
  • the second metal layer includes a signal line.
  • an embodiment of the present disclosure also provides a method for manufacturing a display panel, including: setting an alignment mark area in a flat area of a peripheral area of the display panel;
  • An alignment mark pattern is arranged in the alignment mark area; and/or, in the alignment mark area, at least one film layer is hollowed out;
  • the peripheral area is an area other than an effective display area included in the display panel.
  • the film layer includes a metal layer.
  • the surface of the display panel is flat.
  • the display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface, and a fourth side surface;
  • the first side surface, the second side surface, the third side surface, and the fourth side surface are all curved side surfaces
  • the first plane is parallel to the lower surface.
  • the flat area includes a flat fan-out area; the alignment mark area is included in the flat fan-out area;
  • the step of setting the alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat fan-out area,
  • the first metal pattern is arranged around the alignment mark area.
  • the flat area includes a flat fan-out area; the alignment mark area is included in the flat fan-out area;
  • the step of setting the alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat fan-out area,
  • a first metal layer is provided on the side of the semiconductor layer away from the substrate, and a patterning process is performed on the first metal layer to form a first metal pattern, so that in the alignment mark area, the first metal Layer is hollowed out;
  • the first metal pattern is arranged around the alignment mark area.
  • the flat area includes a flat signal line area; the alignment mark area is included in the flat signal line area;
  • the step of setting an alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat signal line area,
  • a semiconductor layer is fabricated on the substrate, and a patterning process is performed on the semiconductor layer to form an alignment mark pattern; the alignment mark pattern is disposed in the alignment mark area.
  • the flat area includes a flat signal line area; the alignment mark area is included in the flat signal line area;
  • the step of setting an alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat signal line area,
  • a second metal layer is provided on one side of the substrate, and the second metal layer is hollowed out in the alignment mark area.
  • the manufacturing method of the display panel described in at least one embodiment of the present disclosure further includes: performing a patterning process on the second metal layer to form a signal line.
  • the present disclosure also provides a display device including the above-mentioned display panel.
  • 1A, 1B, and 1C are top views of the four sides of the four-sided curved display panel before bending after the circuit board is bent;
  • FIG. 1D is a schematic diagram when the alignment mark area 70 is set at the lower left of the four-sided bent display panel
  • FIG. 2 is a plan view of the four-sided curved display panel before the circuit board is bent;
  • FIG. 3 is a schematic diagram of the area division of the lower left corner of the display panel in FIG. 1B;
  • 4A, 4B, 4C, and 4D are top views of the semiconductor layer, the first gate metal layer, the second gate metal layer, and the anode layer sequentially disposed on the substrate in at least part of the area included in the flat fan-out region ;
  • 5A, 5B, and 5C are top views of semiconductor layers, source/drain metal layers, and anode layers sequentially disposed on a substrate in at least part of the area included in the flat signal line area;
  • Fig. 6A is a schematic diagram of Fig. 5A and Fig. 5B after being superimposed;
  • FIG. 6B is a schematic diagram of FIG. 5B and FIG. 5C after being superimposed
  • 6C is a schematic diagram of at least a part of source and drain metal patterns included in the source and drain metal layers disposed in the flat signal line region;
  • FIG. 7 is a schematic diagram of a part of the area included in the driving circuit area and a part of the area included in the fan-out area 30;
  • FIG. 8A is a top view of an embodiment of an active pattern 81 included in a semiconductor layer disposed on a substrate in a flat virtual driving circuit area;
  • FIG. 8B is a top view of an embodiment of the first gate metal pattern 82 included in the first gate metal layer disposed above the semiconductor layer in the flat dummy driving circuit region;
  • FIG. 8C is a schematic diagram after superimposing FIG. 8A and FIG. 8B in the flat virtual driving circuit area;
  • Fig. 8D is a schematic diagram of a second gate metal pattern 83 included in the second gate metal layer added to the flat dummy driving circuit region on the basis of Fig. 8C;
  • FIG. 8E is a schematic diagram of a plurality of via holes H0 after the semiconductor layer, the first gate metal layer and the second gate metal layer are sequentially arranged in the flat dummy driving circuit area;
  • FIG. 8F is a schematic diagram of a source-drain metal layer S0 after a plurality of via holes H0 are provided in the flat virtual driving circuit area;
  • FIG. 8G is a schematic diagram of an anode layer 90 disposed on the source and drain metal layers in the flat dummy driving circuit area.
  • Pad bending (circuit board bending) technology can be used on the upper or lower frame of the display panel, and the circuit board is bent.
  • the folding technology is to bend part of the circuit board included in the display device (the circuit board may be a flexible circuit board) to the back of the display panel, and attach a heat dissipation film to the surface of the circuit board that is bent to the back of the display panel to reduce The heat generated when a small circuit is working.
  • the alignment needs to be realized by recognizing the alignment marks in the display panel.
  • the alignment mark may include a circuit board bending alignment mark and/or a heat dissipation film bonding alignment mark, and the position can be locked by recognizing the alignment mark by an alignment camera. Since the sharpness of the pattern recognized by the alignment camera is related to the consistency of the object distance, the alignment mark needs to be set in a flat area where the surface of the display panel is flat.
  • the display panel is a four-sided curved display panel
  • the upper surface of the display panel and the lower surface of the display panel are flat
  • the upper side of the display panel, the lower side of the display panel, the left side of the display panel, and the right side of the display panel The surfaces are curved sides, so the area of the flat area is small.
  • 1A and 1B are top views of the four sides of the four-sided curved display panel before bending after the circuit board is bent.
  • the label 201 is the outer edge of the display panel, and the label 202 is the effective display area boundary. Inside the effective display area boundary 202 is the AA area (Active Area) of the display panel. Area);
  • the peripheral area of the display panel is an area except for the effective display area included in the display panel
  • 201 is the outer edge of the display panel
  • 203-1 is the left curved area of the display panel
  • 203-2 is the lower curved area of the display panel
  • the 203-3 is the upper curved area of the display panel
  • the 203-4 is the right curved area of the display panel;
  • the first dotted line labeled L1 is the first dotted line, and the area on the left side of the display panel enclosed by the first dotted line L1 and the outer edge of the display panel is the left curved surface area 203-1 of the display panel;
  • the second dashed line labeled L2 is the second dashed line, and the area on the lower side of the display panel enclosed by the second dashed line L2 and the outer edge of the display panel is the lower curved area 203-2 of the display panel;
  • the third dotted line labeled L3 is the third dotted line, and the area on the upper side of the display panel enclosed by the third dotted line L3 and the outer edge of the display panel is the upper curved area 203-3 of the display panel;
  • the fourth dotted line labeled L4 is the fourth dotted line, and the area on the right side of the display panel enclosed by the fourth dotted line L4 and the outer edge of the display panel is the right curved surface area 203-4 of the display panel;
  • the flat area in the peripheral area of the display panel may be the left curved area 203-1, the lower curved area 203-2, and the upper curved area 203 in the peripheral area of the display panel. -3 and the area covered by the right curved area 203-4;
  • the numbered 11 is the first flat area included in the flat area of the display panel
  • the numbered 12 is the second flat area included in the flat area of the display panel
  • the numbered 13 is the flat area of the display panel including
  • the third flat area, numbered 14 is the fourth flat area included in the flat area of the display panel, that is, in the four-sided curved display panel, the flat area is located on the upper left side, lower left side, upper right side and Lower right side.
  • the first flat area 11 is a flat area located on the lower left side of the display panel
  • the second flat area 12 is a flat area located on the lower right side of the display panel
  • the third flat area 13 is located on the upper left side of the display panel.
  • the fourth flat area 14 is a flat area located on the upper right side of the display panel;
  • the first flat area 11 is close to the lower left rounded corner of the effective display area boundary 202
  • the second flat area 12 is close to the lower right rounded corner of the effective display area boundary 202
  • the third flat area 13 is close to the upper left rounded corner of the effective display area boundary 202.
  • the fourth flat area 14 is close to the upper right rounded corner of the effective display area boundary 202.
  • the orthographic projection of the left side surface of the display panel on the first plane and the orthographic projection of the left curved surface area 203-1 on the first plane may overlap, and the display panel
  • the orthographic projection of the lower side of the display panel on the first plane and the orthographic projection of the lower curved area 203-2 on the first plane may overlap, and the orthographic projection of the upper side of the display panel on the first plane is the same as the orthographic projection of the upper side of the display panel on the first plane.
  • the orthographic projection of the upper curved area 203-3 on the first plane may overlap, and the orthographic projection of the right side surface of the display panel on the first plane is the same as that of the right curved area 203-4 on the first plane.
  • Orthographic projections can overlap;
  • the first plane is a plane parallel to the lower surface of the display panel.
  • the lower left rounded corner of the effective display area boundary 202 may be the portion between the first intersection point P1 and the second intersection point P2 included in the effective display area boundary 202; wherein, the first intersection point P1 Is the intersection of the first dashed line L1 and the lower left portion of the effective display area boundary 202, and the second intersection P2 is the intersection of the second dashed line L2 and the lower left portion of the effective display area boundary 202.
  • the lower right rounded corner of the effective display area boundary 202 may be the portion between the third intersection point P3 and the fourth intersection point P4 included in the effective display area boundary 202; wherein, the third intersection point P3 is the intersection of the second dashed line L2 and the lower right part of the effective display area boundary 202, and the fourth intersection P2 is the intersection of the fourth dashed line L4 and the lower left part of the effective display area boundary 202.
  • the upper left rounded corner of the effective display area boundary 202 may be the portion between the fifth intersection point P5 and the sixth intersection point P6 included in the effective display area boundary 202; wherein, the fifth intersection point P5 Is the intersection of the first dashed line L1 and the upper left part of the effective display area boundary 202, and the sixth intersection P6 is the intersection of the third dashed line L3 and the upper left part of the effective display area boundary 202.
  • the upper right rounded corner of the effective display area boundary 202 may be the portion between the seventh intersection point P7 and the eighth intersection point P8 included in the effective display area boundary 202; wherein, the seventh intersection point P7 Is the intersection of the third dashed line L3 and the upper right part of the effective display area boundary 202, and the eighth intersection P8 is the intersection of the fourth dashed line L4 and the upper left portion of the effective display area boundary 202.
  • Figure 2 is a top view of the four-sided curved display panel before the circuit board is bent.
  • the circuit board marked 20 is a circuit board.
  • the circuit board 20 can be a flexible circuit board. When the four-sided curved display panel is manufactured, it is required The circuit board 20 is bent to the back of the display panel.
  • a heat dissipation film may be attached to the back of the display panel and the four sides of the display panel.
  • the circuit board 20 when the circuit board 20 is disposed on the lower side of the display panel, the circuit board 20 needs to be bent to the back of the display panel.
  • the area 11 and/or the second flat area 12 are provided with alignment marks for bending alignment and alignment for attaching the heat dissipation film; and, when the circuit board 20 is set on the lower side of the display panel , Since the upper side of the display panel also needs to be laminated with a heat dissipation film, alignment marks may also be provided in the third flat area 13 and/or the fourth flat area 14 to perform alignment marks for bonding the heat dissipation film;
  • a bending alignment mark may also be provided on the circuit board, by setting the bending alignment mark on the circuit board, and, The alignment marks provided on the first flat area 11 and/or the second flat area 12 are combined to perform bending alignment.
  • the circuit board 20 when the circuit board 20 is disposed on the upper side of the display panel, the circuit board 20 needs to be bent to the back of the display panel.
  • the area 13 and/or the fourth flat area 14 are provided with alignment marks for bending alignment and alignment for attaching the heat dissipation film; and, when the circuit board 20 is set on the upper side of the display panel , Since the lower side of the display panel also needs to be laminated with a heat dissipation film, alignment marks may also be provided in the first flat area 11 and/or the second flat area 12 to perform alignment marks for bonding the heat dissipation film;
  • a bending alignment mark may also be provided on the circuit board, by setting the bending alignment mark on the circuit board, and, The alignment marks provided on the third flat area 13 and/or the fourth flat area 14 are combined to perform bending alignment.
  • a Fanout area In the peripheral area of the display panel, along a direction away from the effective display area, a Fanout area, a driving circuit area, and a signal line area may be sequentially provided;
  • the fan-out area is an area where the connection line between the data line and the source driver in the effective display area is located, and a DC voltage signal line may be provided in the fan-out area;
  • the DC voltage signal line may include a high voltage signal line and/or a low voltage signal line; the high voltage signal line is used to provide a high voltage signal VDD, and the low voltage signal line is used to provide a low voltage signal VSS;
  • connection line between the gate line and the gate driver may also be provided;
  • a signal line may be provided in the signal line area
  • the signal line may include a DC voltage signal line; when the signal line includes a DC voltage signal line, the signal line may include a high voltage signal line and/or a low voltage signal line; the low voltage signal line is used to provide A low voltage signal VSS, and the high voltage signal line is used to provide a high voltage signal VDD;
  • the driving circuit area may include a driving circuit area and a virtual driving circuit area
  • a driving circuit including a multi-stage shift register unit is provided.
  • the driving circuit may include a gate driving circuit, and the gate driving circuit is used to separately provide multiple rows of pixel circuits in the AA area. Provide gate drive signal;
  • the driving circuit may also include a light-emitting control circuit, and the light-emitting control circuit is used to provide light-emitting control signals for multiple rows of pixel circuits in the AA area;
  • a virtual drive circuit In the virtual drive circuit area, a virtual drive circuit is provided.
  • the virtual drive circuit may include at least one stage of virtual shift register unit, and the virtual shift register unit is not coupled to the pixel circuit in the AA area, It is reserved only to maintain the uniformity of etching and the rationality of the layout.
  • the signal line in the virtual shift register unit can be connected to a fixed voltage signal to reduce the influence of signal jump on the drive circuit in the drive circuit area .
  • a first metal layer and an anode layer may be sequentially disposed on the substrate, and the connection line between the data line and the source driver may be disposed in the first On the metal layer; and, in the area other than the alignment mark area included in the fan-out area, the anode layer may also be provided with a plurality of openings, and the openings are used to deflate the organic film layer.
  • the first metal layer may include a gate metal layer and/or a source/drain metal layer
  • the gate metal layer may include a first gate metal layer and a second gate metal layer, but is not limited thereto;
  • connection line between the data line and the source driver may be disposed on the first gate metal layer and/or the second gate metal layer, between the data line and the source driver
  • the connection line of can also be arranged on the source and drain metal layer;
  • connection line between the gate line and the gate driver may be disposed on the first gate metal layer and/or the second gate metal layer, between the gate line and the gate driver
  • the connection line of can also be arranged on the source and drain metal layer
  • the DC voltage signal line may be disposed on the first gate metal layer and/or the second gate metal layer, and the DC voltage signal line may also be disposed on the source and drain metal layer.
  • a semiconductor layer, a second metal layer, and an anode layer may be sequentially arranged on the substrate;
  • the purpose of providing an anode layer on the second metal layer is to connect the cathode of the light-emitting element in the effective display area to the low voltage signal line (covering the second metal layer)
  • the area of the anode layer is determined by the overlap between the low-voltage signal line and the cathode).
  • the second metal layer may include a source and drain metal layer and/or a gate metal layer, but it is not limited thereto.
  • the second metal layer may include a signal line.
  • the signal line may be a DC voltage signal line; when the signal line includes a DC voltage signal line, the signal line may include a high voltage signal line and/or a low voltage signal line; the low voltage signal line is used to provide A low voltage signal VSS, and the high voltage signal line is used to provide a high voltage signal VDD.
  • a plurality of openings may be provided on the anode layer to vent the organic film layer.
  • FIG. 3 is a schematic diagram of the area division of the lower left corner of the display panel in FIG. 1B.
  • the area marked 30 is the AA area
  • the area marked 31 is the fan-out area
  • the area marked 32 is the drive circuit area
  • the area marked 33 is the signal line area
  • the area marked 201 is the display panel.
  • the outer edge of 202 is the effective display area boundary.
  • the flat area may include a partial area of the fan-out area, and/or the flat area may include a partial area of the signal line area;
  • the partial area of the fan-out area is a flat fan-out area
  • the partial area of the signal line area is a flat signal line area.
  • a signal line may be provided in the flat signal line area; the signal line may be a signal line with a certain width, a direct current voltage signal may be added to the signal line, and the direct current voltage signal may be a high voltage
  • the signal can also be a low-voltage signal;
  • the flat area may further include at least a part of the dummy driving circuit area, and when the flat area includes at least a part of the dummy driving circuit area, the dummy At least a part of the driving circuit area is a flat dummy driving circuit area.
  • the display panel includes an alignment mark area provided in a flat area of a peripheral area of the display panel;
  • the peripheral area is an area other than an effective display area included in the display panel
  • An alignment mark pattern is arranged in the alignment mark area; and/or, in the alignment mark area, at least one film layer is hollowed out.
  • the display panel according to at least one embodiment of the present disclosure includes an alignment mark area.
  • the alignment mark pattern can be set in the alignment mark area, or at least one film layer can be hollowed out in the alignment mark area. If at least one film layer is hollowed out in the area, the light transmittance of the alignment mark area is higher than that of the surrounding area, so that the alignment mark can be accurately performed.
  • the surrounding area may be an area included in the surrounding area that is closer to the alignment mark area.
  • the film layer may be a metal layer, but it is not limited to this.
  • the surface of the display panel is flat.
  • the display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface, and a fourth side surface;
  • the first side surface, the second side surface, the third side surface, and the fourth side surface are all curved side surfaces
  • the first plane is parallel to the lower surface.
  • the display panel may be a four-sided curved display panel
  • FIG. 1B shows a top view of the four-sided curved display panel
  • the first side surface may be the left side in FIG. 1B.
  • the two side surfaces may be the lower side surface in FIG. 1B
  • the third side surface may be the upper side surface in FIG. 1B
  • the fourth side surface may be the right side surface in FIG. 1B, but is not limited to this.
  • the first side surface may be a left side surface
  • the second side surface may be a lower side surface
  • the third side surface may be an upper side surface
  • the fourth side surface may be a right side surface
  • the display panel may further include a circuit board arranged on the lower surface, and the circuit board is arranged on the lower side of the display panel;
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than a predetermined distance, And/or, the longest between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane The distance is less than the predetermined distance.
  • the predetermined distance can be selected according to actual conditions; for example, the predetermined distance can be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited to this.
  • the alignment mark area when the circuit board is arranged on the lower side of the display panel, can be arranged at the lower left round corner close to the boundary of the effective display area, and/or near the boundary of the effective display area.
  • the lower right corner is rounded.
  • the alignment mark area 70 when the alignment mark area 70 is close to the lower left rounded corner of the effective display area boundary 202, the orthographic projection of the alignment mark area 70 on the first plane and the lower left circle of the effective display area boundary 202 The longest distance between the corners is: the longest between any point on the boundary line of the orthographic projection of the alignment mark 70 on the first plane and any point on the lower left rounded corner of the effective display area boundary 202 Long distance.
  • the alignment mark area 70 is L-shaped, but not limited to this.
  • the orthographic projection of the alignment mark area on the first plane is consistent with the effective display of the display panel
  • the longest distance between the lower right rounded corners of the orthographic projection of the area boundary on the first plane may refer to: any point on the boundary line of the orthographic projection of the alignment mark area on the first plane and The longest distance between any point on the lower right rounded corner of the boundary of the effective display area.
  • the first side surface may be a left side surface
  • the second side surface may be a lower side surface
  • the third side surface may be an upper side surface
  • the fourth side surface may be a right side surface
  • the display panel may further include a circuit board arranged on the lower surface, and the circuit board is arranged on the upper side of the display panel;
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper-left rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than a predetermined distance, And/or, the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane Less than the predetermined distance.
  • the orthographic projection of the alignment mark area on the first plane and the effective display area of the display panel refers to: any point on the boundary line of the orthographic projection of the alignment mark area on the first plane and the effective The longest distance between any point on the upper left rounded corner of the display area boundary.
  • the orthographic projection of the alignment mark area on the first plane and the effective display area of the display panel refers to any point on the boundary line of the orthographic projection of the alignment mark area on the first plane and the effective The longest distance between any point on the upper right rounded corner of the display area boundary.
  • the predetermined distance can be selected according to actual conditions; for example, the predetermined distance can be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited to this.
  • the alignment mark area when the circuit board is arranged on the upper side of the display panel, can be arranged at the upper left rounded corner close to the boundary of the effective display area, and/or near the boundary of the effective display area.
  • the upper right corner is rounded.
  • the first side surface may be a left side surface
  • the second side surface may be a lower side surface
  • the third side surface may be an upper side surface
  • the fourth side surface may be a right side surface
  • the display panel also includes a circuit board arranged on the lower surface, and the circuit board is arranged on the lower side of the display panel;
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper-left rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than a predetermined distance, And/or, the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane Less than the predetermined distance.
  • the predetermined distance can be selected according to actual conditions; for example, the predetermined distance can be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited to this.
  • the alignment mark area when the circuit board is arranged on the lower side of the display panel, the alignment mark area may be arranged at the upper left rounded corner close to the boundary of the effective display area, and/or near the boundary of the effective display area.
  • the upper right corner is rounded.
  • the first side surface may be a left side surface
  • the second side surface may be a lower side surface
  • the third side surface may be an upper side surface
  • the fourth side surface may be a right side surface
  • the display panel also includes a circuit board arranged on the lower surface, and the circuit board is arranged on the upper side of the display panel;
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than a predetermined distance, And/or, the longest between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane The distance is less than the predetermined distance.
  • the predetermined distance can be selected according to actual conditions; for example, the predetermined distance can be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited to this.
  • the alignment mark area when the circuit board is arranged on the upper side of the display panel, the alignment mark area may be arranged at the lower left rounded corner close to the boundary of the effective display area, and/or near the boundary of the effective display area.
  • the lower right corner is rounded.
  • the flat area may include a flat fan-out area; the alignment mark area is included in the flat fan-out area;
  • the display panel includes a first metal layer disposed on a substrate;
  • the first metal layer is hollowed out
  • the first metal layer includes a first metal pattern, and the first metal pattern is disposed around the alignment mark area.
  • the first metal layer in the flat fan-out region, may include a plurality of metal connection lines arranged in parallel, and the metal connection lines may be used to connect the data line and the source driver, or, The metal connection line can be used to connect the gate line and the gate driver;
  • the first metal layer may also include a DC voltage signal line with a certain width, and the DC voltage signal line may be a high voltage signal line or a low voltage signal line;
  • the reason why the DC voltage signal line has a certain width is to reduce the resistance of the DC voltage signal line to reduce the voltage drop of the DC voltage signal on the DC voltage signal line.
  • the first metal layer may include a gate metal layer and/or a source/drain metal layer
  • the gate metal layer may include a first gate metal layer and a second gate metal layer, but it is not limited thereto.
  • the alignment mark area may be included in the flat fan-out area.
  • the first metal layer is hollowed out to form a fan-out opening, and the first metal layer includes The first metal pattern is arranged around the alignment mark area, so that the flat fan-out area except for the alignment mark area has a lower light transmittance, and the alignment mark area has a higher light transmittance, forming a bright
  • the contrast between the dark field and the field makes it easy to identify the alignment marks, and there is no need for a separate space to place the alignment marks, which can reduce the frame of the display panel and achieve precise alignment of the process.
  • the first metal pattern may include a connection line between a data line and a source driver
  • the first metal pattern may include a connection line between the gate line and the gate driver
  • the first metal pattern may include a DC voltage signal line, and the DC voltage signal line may include a high voltage signal line and/or a low voltage signal line.
  • the first metal layer may include a gate metal layer
  • the gate metal layer may include a first gate metal layer and a second gate metal layer sequentially disposed on the substrate. Area, the first gate metal layer and the second gate metal layer are both hollowed out.
  • a first insulating layer may be provided between the first gate metal layer and the second gate metal layer. Since the first insulating layer is relatively light-transmissive, in the alignment mark area, the first gate The insulating layer may not be hollowed out.
  • the fan-out area is densely routed, when the alignment mark area is included in the flat fan-out area, the contrast between the alignment mark area and the surrounding area is high, bright field and dark field Strong contrast, easy to identify.
  • the display panel further includes a semiconductor layer disposed between the substrate and the first metal layer;
  • the semiconductor layer is hollowed out
  • the semiconductor layer includes an alignment mark pattern.
  • the semiconductor layer may not be provided in the flat fan-out area.
  • the semiconductor layer may be provided between the substrate and the first metal layer in the flat fan-out area, and
  • the flat fan-out area includes an area other than the alignment mark area, in which the semiconductor layer is hollowed out; in the alignment mark area, the semiconductor layer is not hollowed out, so that the semiconductor layer includes the alignment mark area.
  • the alignment mark pattern enables the alignment camera to capture the alignment mark pattern included in the semiconductor layer for accurate alignment.
  • the display panel in the alignment mark area, further includes an anode layer disposed on a side of the first metal layer away from the substrate;
  • the anode layer is not provided with an opening
  • the anode layer is provided with a plurality of openings arranged at intervals.
  • the anode layer in an area of the display panel other than the alignment mark area, is provided with a plurality of openings (there is a certain distance between two adjacent openings) , In order to exhaust the organic film layer, in the alignment mark area, fill up the openings on the anode layer, so that the alignment camera can identify the alignment mark area.
  • the edge of the orthographic projection of the alignment mark area on the substrate is polygonal, L-shaped or T-shaped, but not limited to this.
  • FIGS. 4A, 4B, 4C, and 4D are top views of the semiconductor layer, the first gate metal layer, the second gate metal layer, and the anode layer sequentially disposed on the substrate in at least part of the area included in the flat fan-out region ;
  • the area where the hexagon marked 40 is located is the alignment mark area;
  • the first metal layer includes a gate metal layer
  • the gate metal layer includes a first gate metal layer and a second gate metal layer
  • the semiconductor layer is hollowed out so that the semiconductor layer includes the alignment mark area. ⁇ Alignment mark graphic 43;
  • the first gate metal pattern 41 included in the first gate metal layer is arranged around the alignment mark area 40; in the alignment mark area 40, the first gate metal layer is hollowed out;
  • the second gate metal pattern 42 included in the second gate metal layer is arranged around the alignment mark area 40; in the alignment mark area 40, the second gate metal layer is hollowed out;
  • the anode layer in the alignment mark area 40, is not provided with an opening so that the alignment camera can recognize the alignment mark area 40; except for all areas included in the flat fan-out area
  • the anode layer is provided with a plurality of openings 4d1 (there is a certain distance between two adjacent openings 4d1), and the openings 4d1 are formed by hollowing out the anode layer. 4d1 is used to release the gas of the organic film layer.
  • the shape of the edge of the orthographic projection of the alignment mark area 40 on the substrate can be set according to actual needs, and the shape of the edge can be polygonal, L-shaped or T-shaped.
  • a second insulating layer may be provided between the semiconductor layer and the first gate metal layer, and a second insulating layer may be provided between the first gate metal layer and the second gate metal layer.
  • a first insulating layer may be arranged between the second gate metal layer and the anode layer, and a third insulating layer may be arranged between the second gate metal layer and the anode layer.
  • the light transmittance of the third insulating layer and the third insulating layer are relatively high, so in the alignment mark area, the first insulating layer, the second insulating layer, and the third insulating layer may not be hollowed out.
  • the first insulating layer, the second insulating layer, and the third insulating layer may be made of silicon oxide or silicon nitride, but not limited to this.
  • the flat area may include a flat signal line area; the alignment mark area is included in the flat signal line area;
  • the display panel includes a semiconductor layer disposed on a substrate;
  • the semiconductor layer includes an alignment mark pattern.
  • the flat area may include a flat signal line area
  • an alignment mark pattern may be provided in an alignment mark area included in the flat signal line area
  • the display panel may include a semiconductor layer disposed on the substrate, and the semiconductor layer includes an alignment mark pattern.
  • the orthographic projection of the alignment mark pattern on the substrate is L-shaped, T-shaped or polygonal.
  • the display panel when the alignment mark area is included in the flat signal line area and in the alignment mark area, the display panel includes a semiconductor layer disposed on a substrate, and the semiconductor layer includes an alignment mark pattern
  • the display panel may further include a source-drain metal layer disposed on a side of the semiconductor layer away from the substrate, the source-drain metal layer may include a low-voltage signal line;
  • the display panel may further include an anode layer disposed on the side of the source/drain metal layer away from the semiconductor layer, and the purpose of covering the anode layer above the source/drain metal layer is to protect
  • the cathode of the light-emitting element in the effective display area is connected to the low-voltage signal line (the area of the anode layer covered above the source-drain metal layer is determined by the connection between the low-voltage signal line and the cathode).
  • the semiconductor layer set below is provided with alignment mark graphics to facilitate the alignment camera to accurately capture the alignment mark graphics from the back of the display panel. This solution does not increase the frame or affect the wiring of other backplane circuits. Make the alignment camera accurately capture the contrast mark graphics for alignment.
  • 5A, 5B, and 5C are top views of semiconductor layers, source/drain metal layers, and anode layers sequentially disposed on a substrate in at least part of the area included in the flat signal line area;
  • the semiconductor layer includes an alignment mark pattern 50;
  • 52 is an anode layer disposed on the source/drain metal layer in at least a part of the area included in the flat signal line area.
  • FIG. 6A is a schematic diagram of FIG. 5A and FIG. 5B after being superimposed
  • FIG. 6B is a schematic diagram of FIG. 5B and FIG. 5C after being superimposed.
  • the flat area may include a flat signal line area; the alignment mark area is included in the flat signal line area;
  • the display panel includes a second metal layer disposed on the substrate;
  • the second metal layer is hollowed out.
  • the alignment mark area may be included in a flat signal line area.
  • the display panel includes a second metal layer.
  • the second metal In the alignment mark area, the second metal The layer is hollowed out to form a light-permeable alignment mark, and the light transmittance of the alignment mark area is higher than that of the surrounding area, so that the alignment mark can be accurately performed.
  • the second metal layer may include a source and drain metal layer and/or a gate metal layer, but it is not limited thereto.
  • the second metal layer may include a signal line, and the signal line may include a DC voltage signal line; when the signal line includes a DC voltage signal line, the signal line may include a low voltage signal line and / Or high-voltage signal lines, but not limited to this.
  • the display panel may further include The anode layer disposed on the side of the source/drain metal layer away from the substrate, covering the anode layer above the source/drain metal layer is to connect the cathode of the light-emitting element in the effective display area to the low-voltage signal line On (the area of the anode layer covering the source and drain metal layer is determined by the overlap of the low voltage signal line and the cathode).
  • the shape of the edge of the orthographic projection of the alignment mark area on the substrate may be L-shaped, T-shaped or polygonal.
  • the flat signal line area includes an alignment mark area 70.
  • the source and drain metal layers are hollowed out to form an alignment mark that can transmit light.
  • the light transmittance of the alignment mark area 70 is higher than that of the surrounding area, so that the alignment can be accurately performed mark.
  • the shape of the edge of the orthographic projection of the alignment mark area 70 on the substrate is L-shaped, but it is not limited to this.
  • the flat area may include a flat dummy driving circuit area; the alignment mark area is included in the flat dummy driving circuit area;
  • the display panel includes a semiconductor layer, a third metal layer, and a fourth metal layer sequentially disposed on a substrate;
  • both the third metal layer and the fourth metal layer are hollowed out.
  • the semiconductor layer is also hollowed out.
  • the third metal layer may include a gate metal layer
  • the fourth metal layer may include a source and drain metal layer, but it is not limited thereto.
  • the alignment mark area may be included in a flat dummy drive circuit area; in addition to the alignment mark area, in the peripheral area closer to the alignment mark area, the circuit traces are dense, because The trace is opaque to visible light. Under certain backlight conditions, the alignment camera will appear black in the field of view, but there is no trace arrangement in the alignment mark area, and the backlight can almost completely pass through the alignment The marking area enters the alignment camera and forms a strong contrast with the surrounding area, and the alignment camera can recognize the alignment mark area.
  • the display panel in the alignment mark area, further includes an anode layer disposed on a side of the fourth metal layer away from the second metal layer;
  • the anode layer is not provided with an opening, so that the alignment camera can identify the alignment mark area;
  • the anode layer may be provided with a plurality of openings arranged at intervals.
  • the edge of the orthographic projection of the alignment mark area on the substrate is polygonal, L-shaped or T-shaped.
  • the third metal layer may include a gate metal layer
  • the gate metal layer may include a first gate metal layer and a second gate metal layer sequentially disposed on the side of the semiconductor layer away from the substrate. Gate metal layer.
  • FIG. 7 shows a partial area included in the driving circuit area, a partial area included in the fan-out area 31, and a partial area included in the signal line area 33.
  • the flat area includes a flat dummy driving circuit area 71; the alignment mark area 70 is included in the flat dummy driving circuit area 71; the flat dummy driving circuit area 71 may be included in the driving circuit area, so In addition to the flat dummy driving circuit area 71, the driving circuit area may also include a first driving circuit area 721 and a second driving circuit area 722.
  • the flat dummy driving circuit area 71 includes an alignment mark area 70;
  • the display panel includes a semiconductor layer, a first gate metal layer, a second gate metal layer, a source/drain metal layer, and an anode layer sequentially disposed on a substrate;
  • At least one level of dummy shift register unit is provided in the flat dummy driving circuit area 71 except for the alignment mark area 70; in the first driving circuit area 721 and the second driving circuit area 722.
  • a drive circuit including a multi-stage shift register unit is provided;
  • the semiconductor layer, the gate metal layer, and the source and drain metal layers are all hollowed out, so that the light transmittance of the alignment mark area 70 is much higher than that included in the driving circuit area.
  • the light transmittance of the area adjacent to the alignment mark area 70 enables the alignment camera to accurately identify the alignment mark area; and there is no need for a separate space to place the alignment mark, which can reduce the frame of the display panel and achieve Precise alignment of craftsmanship;
  • the alignment mark area 70 there is no opening on the anode layer, so that the alignment camera can identify the alignment mark area 70;
  • a plurality of openings may be provided on the anode layer for venting the organic film layer.
  • the third metal layer includes a gate metal layer, and the gate metal layer includes a first gate metal layer and a second gate metal layer; the fourth metal layer
  • the layers include source and drain metal layers.
  • the shape of the edge of the orthographic projection of the alignment mark area 70 on the substrate is L-shaped, but not limited to this. In specific implementation, the shape of the edge of the orthographic projection of the alignment mark area 70 on the substrate may also be other shapes.
  • FIG. 8A is a top view of an embodiment of an active pattern 81 included in a semiconductor layer disposed on a substrate in a flat virtual driving circuit area;
  • FIG. 8B is a top view of an embodiment of the first gate metal pattern 82 included in the first gate metal layer disposed above the semiconductor layer in the flat dummy driving circuit region;
  • FIG. 8C is a schematic diagram after superimposing FIG. 8A and FIG. 8B in the flat virtual driving circuit area;
  • FIG. 8D is a schematic diagram of a second gate metal pattern 83 included in the second gate metal layer added on the basis of FIG. 8C in the flat virtual driving circuit area;
  • FIG. 8E is a schematic diagram of a plurality of via holes H0 after the semiconductor layer, the first gate metal layer and the second gate metal layer are sequentially arranged in the flat dummy driving circuit area;
  • FIG. 8F is a schematic diagram of a source-drain metal layer S0 after a plurality of via holes H0 are provided in the flat virtual driving circuit area;
  • the first gate metal layer, the second gate metal layer, the semiconductor layer, and the source/drain metal layer are all hollowed out.
  • 8G is a schematic diagram of the anode layer 90 being provided on the source and drain metal layers in the flat virtual driving circuit area.
  • the anode layer 90 is not provided with openings so that the alignment camera can recognize the alignment.
  • the anode layer 90 is provided with a plurality of openings 9g1.
  • the area enclosed by the dotted line is the alignment mark area 70, and the shape of the edge of the orthographic projection of the alignment mark area 70 on the substrate is L-shaped, but not limited to this.
  • a second insulating layer may be provided between the semiconductor layer and the first gate metal layer, and a second insulating layer may be provided between the first gate metal layer and the second gate metal layer.
  • a first insulating layer may be provided therebetween, a fourth insulating layer may be provided between the second gate metal layer and the source-drain metal layer, and a fourth insulating layer may be provided between the source-drain metal layer and the anode layer.
  • a fifth insulating layer is provided.
  • the In the alignment mark area, the first insulating layer, the second insulating layer, the fourth insulating layer, and the fifth insulating layer may not be hollowed out.
  • the first insulating layer, the second insulating layer, the fourth insulating layer, and the fifth insulating layer may be made of silicon oxide or silicon nitride, but not This is limited.
  • the manufacturing method of the display panel according to at least one embodiment of the present disclosure includes: setting an alignment mark area in a flat area of the peripheral area of the display panel;
  • An alignment mark pattern is arranged in the alignment mark area; and/or, in the alignment mark area, at least one film layer is hollowed out;
  • the peripheral area is an area other than an effective display area included in the display panel.
  • the alignment mark area is provided in the flat area of the peripheral area of the display panel, and the alignment mark pattern may be set in the alignment mark area, or the alignment mark At least one film layer is hollowed out in the marking area. Since at least one film layer is hollowed out in the alignment mark area, the light transmittance of the alignment mark area is higher than the light transmittance of the surrounding area, enabling accurate alignment. Bit mark.
  • the surrounding area may be an area included in the surrounding area that is closer to the alignment mark area.
  • the film layer may include a metal layer; that is, in the alignment mark area, at least one metal layer may be hollowed out.
  • the surface of the display panel is flat.
  • the display panel includes an upper surface, a lower surface, a first side surface, a second side surface, a third side surface, and a fourth side surface;
  • the first side surface, the second side surface, the third side surface, and the fourth side surface are all curved side surfaces
  • the first plane is parallel to the lower surface.
  • the first side surface may be a left side surface
  • the second side surface may be a lower side surface
  • the third side surface may be an upper side surface
  • the fourth side surface may be a right side surface
  • the display panel may also include a circuit board arranged on the lower surface, and the circuit board is arranged on the lower side of the display panel;
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than a predetermined distance
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the bottom right rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than the Predetermined distance.
  • the predetermined distance can be selected according to actual conditions; for example, the predetermined distance can be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited to this.
  • the alignment mark area when the circuit board is arranged on the lower side of the display panel, can be arranged at the lower left round corner close to the boundary of the effective display area, and/or near the boundary of the effective display area.
  • the lower right corner is rounded.
  • the first side surface may be a left side surface
  • the second side surface may be a lower side surface
  • the third side surface may be an upper side surface
  • the fourth side surface may be a right side surface
  • the display panel may also include a circuit board arranged on the lower surface, and the circuit board is arranged on the upper side of the display panel;
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper-left rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than a predetermined distance, The longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than the predetermined distance.
  • the predetermined distance can be selected according to actual conditions; for example, the predetermined distance can be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited to this.
  • the alignment mark area when the circuit board is arranged on the upper side of the display panel, can be arranged at the upper left rounded corner close to the boundary of the effective display area, and/or near the boundary of the effective display area.
  • the upper right corner is rounded.
  • the first side surface may be a left side surface
  • the second side surface may be a lower side surface
  • the third side surface may be an upper side surface
  • the fourth side surface may be a right side surface
  • the display panel also includes a circuit board arranged on the lower surface, and the circuit board is arranged on the lower side of the display panel;
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper-left rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than a predetermined distance, And/or, the longest distance between the orthographic projection of the alignment mark area on the first plane and the upper right rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane Less than the predetermined distance.
  • the predetermined distance can be selected according to actual conditions; for example, the predetermined distance can be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited to this.
  • the alignment mark area when the circuit board is arranged on the lower side of the display panel, the alignment mark area may be arranged at the upper left rounded corner close to the boundary of the effective display area, and/or near the boundary of the effective display area.
  • the upper right corner is rounded.
  • the first side surface may be a left side surface
  • the second side surface may be a lower side surface
  • the third side surface may be an upper side surface
  • the fourth side surface may be a right side surface
  • the display panel also includes a circuit board arranged on the lower surface, and the circuit board is arranged on the upper side of the display panel;
  • the longest distance between the orthographic projection of the alignment mark area on the first plane and the lower left rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane is less than a predetermined distance, And/or, the longest between the orthographic projection of the alignment mark area on the first plane and the lower right rounded corner of the orthographic projection of the effective display area boundary of the display panel on the first plane The distance is less than the predetermined distance.
  • the predetermined distance can be selected according to actual conditions; for example, the predetermined distance can be greater than or equal to 300 microns and less than or equal to 1100 microns, but is not limited to this.
  • the alignment mark area when the circuit board is arranged on the upper side of the display panel, the alignment mark area may be arranged at the lower left rounded corner close to the boundary of the effective display area, and/or near the boundary of the effective display area.
  • the lower right corner is rounded.
  • the flat area includes a flat fan-out area; the alignment mark area is included in the flat fan-out area;
  • the step of setting the alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat fan-out area,
  • the first metal layer pattern is arranged around the alignment mark area.
  • the alignment mark area may be included in the flat fan-out area.
  • the first metal layer is hollowed out to form a fan-out opening, so that the flat fan-out area includes
  • the light transmittance of the alignment mark area is relatively high, forming a bright field and dark field contrast, which makes the identification of the alignment mark convenient and does not require a separate space to place the alignment Marking can not only reduce the frame of the display panel, but also realize the precise alignment of the craft.
  • the first metal layer may include a gate metal layer and/or a source/drain metal layer
  • the gate metal layer may include a first gate metal layer and a second gate metal layer, but it is not limited thereto.
  • the flat area includes a flat fan-out area; the alignment mark area is included in the flat fan-out area;
  • the step of setting the alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat fan-out area,
  • a first metal layer is provided on the side of the semiconductor layer away from the substrate, and a patterning process is performed on the first metal layer to form a first metal pattern, so that in the alignment mark area, the first metal Layer is hollowed out;
  • the first metal layer pattern is arranged around the alignment mark area.
  • the semiconductor layer may not be provided in the flat fan-out area.
  • the semiconductor layer may be provided between the substrate and the first metal layer in the flat fan-out area, and
  • the flat fan-out area includes an area other than the alignment mark area, in which the semiconductor layer is hollowed out; in the alignment mark area, the semiconductor layer is not hollowed out, so that the semiconductor layer includes the alignment mark area.
  • the alignment mark pattern enables the alignment camera to capture the alignment mark pattern included in the semiconductor layer for accurate alignment.
  • the flat area includes a flat signal line area; the alignment mark area is included in the flat signal line area;
  • the step of setting an alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat signal line area,
  • a semiconductor layer is fabricated on the substrate, and a patterning process is performed on the semiconductor layer to form an alignment mark pattern; the alignment mark pattern is disposed in the alignment mark area.
  • the flat area may include a flat signal line area
  • an alignment mark pattern may be provided in an alignment mark area included in the flat signal line area
  • the display panel may include a semiconductor layer disposed on the substrate, and the semiconductor layer includes an alignment mark pattern.
  • the flat area may include a flat signal line area; the alignment mark area may be included in the flat signal line area;
  • the step of setting an alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat signal line area,
  • a second metal layer is provided on one side of the substrate, and the second metal layer is hollowed out in the alignment mark area.
  • the flat area may include a flat signal line area
  • the alignment mark area may be included in the flat signal line area
  • the second metal layer is hollowed out in the alignment mark area
  • the second metal layer may include a source and drain metal layer and/or a gate metal layer, but it is not limited thereto.
  • the manufacturing method of the display panel described in at least one embodiment of the present disclosure may further include: performing a patterning process on the second metal layer to form a signal line.
  • the signal line may include a DC voltage signal line; when the signal line includes a DC voltage signal line, the signal line may include a low voltage signal line and/or a high voltage signal line.
  • the flat area includes a flat dummy driving circuit area; the alignment mark area is included in the flat dummy driving circuit area;
  • the step of setting an alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat dummy drive circuit area,
  • a third metal layer is provided on the side of the semiconductor layer away from the substrate, and a patterning process is performed on the third metal layer to form a third metal pattern, so that in the alignment mark area, the third metal Layer is hollowed out;
  • a fourth metal layer is provided on the side of the third metal layer away from the semiconductor layer, and a patterning process is performed on the fourth metal layer to form a fourth metal pattern, so that in the alignment mark area, the The fourth metal layer is hollowed out.
  • the third metal layer may include a gate metal layer
  • the fourth metal layer may include a source and drain metal layer, but it is not limited thereto.
  • the flat area includes a flat dummy driving circuit area; the alignment mark area is included in the flat dummy driving circuit area;
  • the step of setting an alignment mark area in the flat area of the peripheral area of the display panel includes: in the flat dummy drive circuit area,
  • a third metal layer is provided on the side of the semiconductor layer away from the substrate, and a patterning process is performed on the third metal layer to form a third metal pattern, so that in the alignment mark area, the first metal Layer is hollowed out;
  • a fourth metal layer is provided on the side of the third metal layer away from the semiconductor layer, and a patterning process is performed on the fourth metal layer to form a fourth metal pattern, so that in the alignment mark area, the The fourth metal layer is hollowed out.
  • the third metal layer may include a gate metal layer
  • the fourth metal layer may include a source and drain metal layer, but it is not limited thereto.
  • the alignment mark area may be included in a flat dummy drive circuit area; in addition to the alignment mark area, in the peripheral area closer to the alignment mark area, the circuit traces are dense, because The trace is opaque to visible light. Under certain backlight conditions, the alignment camera will appear black in the field of view, but there is no trace arrangement in the alignment mark area, and the backlight can almost completely pass through the alignment The marking area enters the alignment camera and forms a strong contrast with the surrounding area, and the alignment camera can recognize the alignment mark area.
  • the display device described in at least one embodiment of the present disclosure may include the display panel described in the embodiment of the present disclosure.
  • the display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

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Abstract

本公开提供一种显示面板及其制作方法和显示装置。显示面板包括设置于显示面板的周边区域的平坦区的对位标记区域；所述周边区域为所述显示面板包括的除了有效显示区域之外的区域；在所述对位标记区域中设置有对位标记图形；和/或，在所述对位标记区域内，至少一层膜层被挖空。

Description

显示面板及其制作方法和显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示面板及其制作方法和显示装置。
背景技术
随着对显示设备的需求日益增多，显示面板内的电路和布线的数量也越来越多，则可以在显示面板的上边框或下边框采用pad bending(电路板弯折)技术，电路板弯折技术就是将显示装置包括的部分电路板(所述电路板可以为柔性电路板)弯折到显示面板的背面，并会在弯折至显示面板的背面的电路板表面贴合散热膜以减小电路工作时产生的热量。为了提高弯折对位及散热膜贴合的精度，需要通过识别显示面板中的对位标记来实现对位。在相关技术中，不能提供一种在四面弯曲显示面板中能够在准确的进行对位标记的同时，不增加边框的技术方案。
发明内容
本公开的主要目的在于提供一种显示面板及其制作方法和显示装置。
在一个方面中，本公开实施例提供一种显示面板，包括设置于显示面板的周边区域的平坦区的对位标记区域；
所述周边区域为所述显示面板包括的除了有效显示区域之外的区域；
在所述对位标记区域中设置有对位标记图形；和/或，在所述对位标记区域内，至少一层膜层被挖空。
可选的，所述膜层包括金属层。
可选的，在所述平坦区，所述显示面板的表面是平面。
可选的，所述显示面板包括上表面、下表面、第一侧面，第二侧面、第三侧面和第四侧面；
所述第一侧面、所述第二侧面、所述第三侧面和所述第四侧面都为弯曲的侧面；
所述第一侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第二侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第三侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第四侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第一平面与所述下表面平行。
可选的，所述对位标记区域在所述基底上的正投影的边缘为多边形、L形或T字形，所述对位标记图形在所述基底上的正投影为L形、T字形或多边形。
可选的，所述平坦区包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
在所述平坦扇出区，所述显示面板包括设置于基底上的第一金属层；
在所述对位标记区域，所述第一金属层被挖空；
在所述平坦扇出区，所述第一金属层包括第一金属图形，所述第一金属图形围绕着所述对位标记区域设置。
可选的，所述第一金属图形包括数据线与源极驱动器之间的连接线。
可选的，所述第一金属图形包括直流电压信号线。
可选的，在所述平坦扇出区，所述显示面板还包括设置于所述基底与所述第一金属层之间的半导体层；
在所述平坦扇出区包括的除了对位标记区域之外的区域，所述半导体层被挖空；
在所述对位标记区域，所述半导体层包括对位标记图形。
可选的，在所述对位标记区域，所述显示面板还包括设置于所述第一金属层远离所述基底的一面的阳极层；
在所述对位标记区域，所述阳极层不设有开口；
在除了所述对位标记区域之外的区域，所述阳极层设有多个间隔设置的 开口。
可选的，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
在所述对位标记区域，所述显示面板包括设置于基底上的半导体层；
所述半导体层包括对位标记图形。
可选的，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
在所述平坦信号线区域，所述显示面板包括设置于所述基底上的第二金属层；
在所述对位标记区域，所述第二金属层被挖空。
可选的，所述第二金属层包括信号线。
在第二个方面中，本公开实施例还提供了一种显示面板的制作方法，包括：在显示面板的周边区域的平坦区设置对位标记区域；
在所述对位标记区域中设置有对位标记图形；和/或，在所述对位标记区域内，至少一层膜层被挖空；
所述周边区域为所述显示面板包括的除了有效显示区域之外的区域。
可选的，所述膜层包括金属层。
可选的，在所述平坦区，所述显示面板的表面是平面。
可选的，所述显示面板包括上表面、下表面、第一侧面，第二侧面、第三侧面和第四侧面；
所述第一侧面、所述第二侧面、所述第三侧面和所述第四侧面都为弯曲的侧面；
所述第一侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第二侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第三侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第四侧面在第一平面上的正投影与所述平坦区在所述第一平面上的 正投影不交叠；
所述第一平面与所述下表面平行。
可选的，所述平坦区包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦扇出区，
在所述基底的一面设置第一金属层，对所述第一金属层进行构图工艺，以形成第一金属图形，并使得在所述对位标记区域，所述第一金属层被挖空；
所述第一金属图形围绕着所述对位标记区域设置。
可选的，所述平坦区包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦扇出区，
在基底上设置半导体层，对所述半导体层进行构图工艺，使得在所述平坦扇出区包括的除了对位标记区域之外的区域，所述半导体层被挖空；
在所述半导体层远离所述基底的一面设置第一金属层，对所述第一金属层进行构图工艺，以形成第一金属图形，并使得在所述对位标记区域，所述第一金属层被挖空；
所述第一金属图形围绕着所述对位标记区域设置。
可选的，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦信号线区域，
在所述基底上制作半导体层，对所述半导体层进行构图工艺，以形成对位标记图形；所述对位标记图形设置于所述对位标记区域。
可选的，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦信号线区域，
在所述基底的一面设置第二金属层，并使得在所述对位标记区域，所述第二金属层被挖空。
可选的，本公开至少一实施例所述的显示面板的制作方法还包括：对所述第二金属层进行构图工艺，以形成信号线。
在第三个方面中，本公开还提供了一种显示装置，包括上述的显示面板。
附图说明
图1A、图1B和图1C是进行电路板弯折后，四面弯曲显示面板的四个侧面未弯折之前的俯视图；
图1D是当对位标记区域70设置于四面弯折显示面板的左下方时的示意图；
图2是进行电路板弯折前的四面弯曲显示面板的俯视图；
图3是图1B中的显示面板的左下圆角的区域划分示意图；
图4A、图4B、图4C和图4D是在所述平坦扇出区包括的至少部分区域，依次设置于基底上的半导体层、第一栅金属层、第二栅金属层和阳极层的俯视图；
图5A、图5B和图5C是在所述平坦信号线区域包括的至少部分区域，依次设置于基底上的半导体层、源漏金属层和阳极层的俯视图；
图6A是图5A和图5B叠加后的示意图；
图6B是图5B和图5C叠加后的示意图；
图6C是设置于所述平坦信号线区域的源漏金属层包括的至少一部分源漏金属图形的示意图；
图7是驱动电路区包括的部分区域和扇出区30包括的部分区域的示意图；
图8A是在平坦虚拟驱动电路区域，设置于基底上的半导体层包括的有源图形81的一种实施例的俯视图；
图8B是在平坦虚拟驱动电路区域，设置于所述半导体层上方的第一栅金属层包括的第一栅金属图形82的一种实施例的俯视图；
图8C是在平坦虚拟驱动电路区域，图8A和图8B叠加后的示意图；
图8D是在平坦虚拟驱动电路区域，在图8C的基础上增加了第二栅金属 层包括的第二栅金属图形83的示意图；
图8E是在平坦虚拟驱动电路区域，依次设置了半导体层、第一栅金属层和第二栅金属层之后，设置多个过孔H0的示意图；
图8F是在平坦虚拟驱动电路区域，在设置了多个过孔H0后，再设置源漏金属层S0的示意图；
图8G是在平坦虚拟驱动电路区域，在源漏金属层上设置了阳极层90的示意图。
具体实施方式
下面将结合本公开实施例中的附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本公开保护的范围。
随着对显示设备的需求日益增多，显示面板内的电路和布线的数量也越来越多，则可以在显示面板的上边框或下边框采用pad bending(电路板弯折)技术，电路板弯折技术就是将显示装置包括的部分电路板(所述电路板可以为柔性电路板)弯折到显示面板的背面，并会在弯折至显示面板的背面的电路板表面贴合散热膜以减小电路工作时产生的热量。为了提高弯折对位及散热膜贴合的精度，需要通过识别显示面板中的对位标记来实现对位。在具体实施时，所述对位标记可以包括电路板弯折对位标记和/或散热膜贴合对位标记，可以通过对位相机识别所述对位标记来锁定位置。由于对位相机对焦识别到的图案清晰度与物距的一致性相关，因此所述对位标记需要设置在平坦区，在所述平坦区，所述显示面板的表面是平面。
当所述显示面板为四面弯曲显示面板时，显示面板的上表面和显示面板的下表面为平面，显示面板的上侧面、显示面板的下侧面、显示面板的左侧面和显示面板的右侧面都为弯曲的侧面，因此平坦区的面积较小。
图1A和图1B是进行电路板弯折后，四面弯曲显示面板的四个侧面未弯折之前的俯视图。
在图1A中，标号为201的为当所述显示面板的外边缘，标号为202的 为有效显示区边界，在所述有效显示区边界202里面是显示面板的AA区(Active Area，有效显示区)；
显示面板的周边区域为所述显示面板包括的除了有效显示区域之外的区域；
在图1B中，标号为201的为当所述显示面板的外边缘，标号为203-1的为显示面板的左侧曲面区，标号为203-2的为显示面板的下侧曲面区，标号为203-3的为显示面板的上侧曲面区，标号为203-4的为显示面板的右侧曲面区；
在图1B中，标号为L1的为第一虚线，所述第一虚线L1与显示面板的外边缘围起来的显示面板左侧的区域为显示面板的左侧曲面区203-1；
标号为L2的为第二虚线，所述第二虚线L2与显示面板的外边缘围起来的显示面板下侧的区域为显示面板的下侧曲面区203-2；
标号为L3的为第三虚线，所述第三虚线L3与显示面板的外边缘围起来的显示面板上侧的区域为显示面板的上侧曲面区203-3；
标号为L4的为第四虚线，所述第四虚线L4与显示面板的外边缘围起来的显示面板右侧的区域为显示面板的右侧曲面区203-4；
所述显示面板的周边区域中的平坦区可以为所述显示面板的周边区域中未被所述左侧曲面区203-1、所述下侧曲面区203-2、所述上侧曲面区203-3和所述右侧曲面区203-4覆盖的区域；
在图1B中，标号为11的为显示面板的平坦区包括的第一平坦区域，标号为12的为显示面板的平坦区包括的第二平坦区域，标号为13的为显示面板的平坦区包括的第三平坦区域，标号为14的为显示面板的平坦区包括的第四平坦区域，也即，在四面弯曲显示面板中，平坦区位于临近有效显示区的左上侧、左下侧、右上侧和右下侧。
在图1B中，第一平坦区域11是位于显示面板的左下侧的平坦区域，第二平坦区域12是位于显示面板的右下侧的平坦区域，第三平坦区域13是位于显示面板的左上侧的平坦区域，第四平坦区域14是位于显示面板的右上侧的平坦区域；
所述第一平坦区域11靠近有效显示区边界202左下圆角，所述第二平坦 区域12靠近有效显示区边界202右下圆角，第三平坦区域13靠近有效显示区边界202左上圆角，第四平坦区域14靠近有效显示区边界202右上圆角。
在本公开至少一实施例中，所述显示面板的左侧面在第一平面上的正投影与所述左侧曲面区203-1在第一平面上的正投影可以重叠，所述显示面板的下侧面在第一平面上的正投影与所述下侧曲面区203-2在第一平面上的正投影可以重叠，所述显示面板的上侧面在第一平面上的正投影与所述上侧曲面区203-3在第一平面上的正投影可以重叠，所述显示面板的右侧面在第一平面上的正投影与所述右侧曲面区203-4在第一平面上的正投影可以重叠；
所述第一平面为与所述显示面板的下表面平行的平面。
如图1C所示，所述有效显示区边界202的左下圆角可以为所述有效显示区边界202包括的第一交点P1和第二交点P2之间的部分；其中，所述第一交点P1为所述第一虚线L1与所述有效显示区边界202的左下部分相交的交点，所述第二交点P2为第二虚线L2与所述有效显示区边界202的左下部分相交的交点。
如图1C所示，所述有效显示区边界202的右下圆角可以为所述有效显示区边界202包括的第三交点P3和第四交点P4之间的部分；其中，所述第三交点P3为所述第二虚线L2与所述有效显示区边界202的右下部分相交的交点，所述第四交点P2为第四虚线L4与所述有效显示区边界202的左下部分相交的交点。
如图1C所示，所述有效显示区边界202的左上圆角可以为所述有效显示区边界202包括的第五交点P5和第六交点P6之间的部分；其中，所述第五交点P5为所述第一虚线L1与所述有效显示区边界202的左上部分相交的交点，所述第六交点P6为第三虚线L3与所述有效显示区边界202的左上部分相交的交点。
如图1C所示，所述有效显示区边界202的右上圆角可以为所述有效显示区边界202包括的第七交点P7和第八交点P8之间的部分；其中，所述第七交点P7为所述第三虚线L3与所述有效显示区边界202的右上部分相交的交点，所述第八交点P8为第四虚线L4与所述有效显示区边界202的左上部分相交的交点。
图2是进行电路板弯折前的四面弯曲显示面板的俯视图，在图2中，标号为20的为电路板，电路板20可以为柔性电路板，在制作所述四面弯曲显示面板时，需要将所述电路板20弯折至所述显示面板的背面。
在本公开至少一实施例中，在将电路板20弯折至显示面板的背面，为了散热，可以在显示面板的背面和显示面板的四个侧面都贴合散热膜。
在本公开至少一实施例中，当所述电路板20设置于显示面板的下侧边的时候，需要将所述电路板20弯折至所述显示面板的背面，可以在所述第一平坦区域11和/或第二平坦区域12设置对位标记，以进行弯折对位以及用于贴合散热膜的对位；并且，当所述电路板20设置于显示面板的下侧边的时候，由于显示面板的上侧面也需要贴合散热膜，则也可以在第三平坦区域13和/或第四平坦区域14设置对位标记，以为贴合散热膜进行对位标记；
在具体实施时，当所述电路板20设置于显示面板的下侧边时，在电路板上也可以设置弯折对位标记，通过将电路板上设置的弯折对位标记，以及，在所述第一平坦区域11和/或第二平坦区域12设置的对位标记相结合，可以进行弯折对位。
在本公开至少一实施例中，当所述电路板20设置于显示面板的上侧边的时候，需要将所述电路板20弯折至所述显示面板的背面，可以在所述第三平坦区域13和/或第四平坦区域14设置对位标记，以进行弯折对位以及用于贴合散热膜的对位；并且，当所述电路板20设置于显示面板的上侧边的时候，由于显示面板的下侧面也需要贴合散热膜，则也可以在第一平坦区域11和/或第二平坦区域12设置对位标记，以为贴合散热膜进行对位标记；
在具体实施时，当所述电路板20设置于显示面板的上侧边时，在电路板上也可以设置弯折对位标记，通过将电路板上设置的弯折对位标记，以及，在所述第三平坦区域13和/或第四平坦区域14设置的对位标记相结合，可以进行弯折对位。
在所述显示面板的周边区域，沿着远离所述有效显示区域的方向，可以依次设置有Fanout(扇出)区，驱动电路区和信号线区域；
所述扇出区是有效显示区中的数据线与源极驱动器之间的连接线所在的区域，并且在所述扇出区中可以设置有直流电压信号线；
所述直流电压信号线可以包括高电压信号线和/或低电压信号线；所述高电压信号线用于提供高电压信号VDD，所述低电压信号线用于提供低电压信号VSS；
在所述扇出区，还可以设置有栅线与栅极驱动器之间的连接线；
在所述信号线区域可以设置有信号线；
所述信号线可以包括直流电压信号线；当所述信号线包括直流电压信号线时，所述信号线可以包括高电压信号线和/或低电压信号线；所述低电压信号线用于提供低电压信号VSS，所述高电压信号线用于提供高电压信号VDD；
所述驱动电路区可以包括驱动电路区域和虚拟驱动电路区域；
在所述驱动电路区域内，设置有包括多级移位寄存器单元的驱动电路，所述驱动电路可以包括栅极驱动电路，所述栅极驱动电路用于为AA区中的多行像素电路分别提供栅极驱动信号；
可选的，所述驱动电路也可以包括发光控制电路，所述发光控制电路用于为AA区中的多行像素电路分别提供发光控制信号；
在所述虚拟驱动电路区域中，设置有虚拟驱动电路，所述虚拟驱动电路可以包括至少一级虚拟移位寄存器单元，所述虚拟移位寄存器单元并不与AA区中的像素电路耦接，仅是为了保持刻蚀均一性及布局的合理性而保留，所述虚拟移位寄存器单元中的信号线可以接入固定电压信号以减少信号跳变对所述驱动电路区域中的驱动电路的影响。
在本公开至少一实施例中，在所述扇出区，在所述基底上可以依次设置第一金属层和阳极层，数据线与源极驱动器之间的连接线可以设置于所述第一金属层上；并且，在所述扇出区包括的除了对位标记区域之外的区域，所述阳极层上也可以设有多个开口，所述开口用于为有机膜层放气。
在具体实施时，所述第一金属层可以包括栅金属层和/或源漏金属层，所述栅金属层可以包括第一栅金属层和第二栅金属层，但不以此为限；
在所述扇出区，所述数据线与源极驱动器之间的连接线可以设置于所述第一栅金属层和/或第二栅金属层上，所述数据线与源极驱动器之间的连接线也可以设置于源漏金属层上；
在所述扇出区，所述栅线与栅极驱动器之间的连接线可以设置于所述第 一栅金属层和/或第二栅金属层上，所述栅线与栅极驱动器之间的连接线也可以设置于源漏金属层上；
在所述扇出区，所述直流电压信号线可以设置于所述第一栅金属层和/或第二栅金属层上，所述直流电压信号线也可以设置于源漏金属层上。
在本公开至少一实施例中，在所述信号线区域，可以在基底上依次设置半导体层、第二金属层和阳极层；
在所述信号线区域，在所述第二金属层上设置阳极层的目的是为了将有效显示区中的发光元件的阴极搭接到所述低电压信号线上(在第二金属层上方覆盖的阳极层的面积有低电压信号线与阴极搭接情况决定)。
可选的，所述第二金属层可以包括源漏金属层和/或栅金属层，但不以此为限。
在具体实施时，所述第二金属层可以包括信号线。所述信号线可以为直流电压信号线；当所述信号线包括直流电压信号线时，所述信号线可以包括高电压信号线和/或低电压信号线；所述低电压信号线用于提供低电压信号VSS，所述高电压信号线用于提供高电压信号VDD。
并且，在所述信号线区域包括的除了对位标记区域之外的区域，所述阳极层上可以设有多个开口，以为有机膜层放气。
图3是图1B中的显示面板的左下圆角的区域划分示意图。在图3中，标号为30的为AA区，标号为31的为扇出区，标号为32的为驱动电路区，标号为33的为信号线区域，标号为201的为当所述显示面板的外边缘，标号为202的为有效显示区边界。
在本公开至少一实施例中，所述平坦区可以包括所述扇出区的部分区域，和/或，所述平坦区可以包括所述信号线区域的部分区域；
当所述平坦区包括扇出区的部分区域时，所述扇出区的部分区域为平坦扇出区；
当所述平坦区包括所述信号线区域的部分区域时，所述信号线区域的部分区域为平坦信号线区域。
在具体实施时，在平坦信号线区域可以设置有信号线；所述信号线可以是具有一定宽度的信号线，所述信号线上可以加有直流电压信号，所述直流 电压信号可以为高电压信号，也可以为低电压信号；
所述信号线具有一定宽度的原因是降低所述信号线的电阻，以降低所述信号线上的直流电压信号的压降。可选的，在本公开至少一实施例中，所述平坦区还可以包括所述虚拟驱动电路区域的至少部分区域，当所述平坦区包括虚拟驱动电路区域的至少部分区域时，所述虚拟驱动电路区域的至少部分区域为平坦虚拟驱动电路区域。
本公开至少一实施例所述的显示面板包括设置于显示面板的周边区域的平坦区的对位标记区域；
所述周边区域为所述显示面板包括的除了有效显示区域之外的区域；
在所述对位标记区域中设置有对位标记图形；和/或，在所述对位标记区域内，至少一层膜层被挖空。
本公开至少一实施例所述的显示面板包括对位标记区域，可以在对位标记区域中设置对位标记图形，也可以在对位标记区域中挖空至少一膜层，由于在对位标记区域，至少一层膜层被挖空，则对位标记区域的透光率高于周围区域的透光率，使得能够准确的进行对位标记。
在本公开至少一实施例中，所述周围区域可以为所述周边区域包括的距离所述对位标记区域较近的区域。
在本公开至少一实施例中，所述膜层可以金属层，但不以此为限。
在具体实施时，在所述平坦区，所述显示面板的表面是平面。
可选的，所述显示面板包括上表面、下表面、第一侧面，第二侧面、第三侧面和第四侧面；
所述第一侧面、所述第二侧面、所述第三侧面和所述第四侧面都为弯曲的侧面；
所述第一侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第二侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第三侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第四侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第一平面与所述下表面平行。
在本公开至少一实施例中，所述显示面板可以为四面弯曲显示面板，图1B示出了四面弯曲显示面板的俯视图，所述第一侧面可以为图1B中的左侧面，所述第二侧面可以为图1B中的下侧面，所述第三侧面可以为图1B中的上侧面，所述第四侧面可以为图1B中的右侧面，但不以此为限。
根据一种具体实施方式，所述第一侧面可以为左侧面，所述第二侧面可以为下侧面，所述第三侧面可以为上侧面，所述第四侧面可以为右侧面；所述显示面板还可以包括设置于所述下表面的电路板，并所述电路板设置于所述显示面板的下侧边；
所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左下圆角之间的最长距离小于预定距离，和/或，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右下圆角之间的最长距离小于所述预定距离。
在具体实施时，所述预定距离可以根据实际情况选定；例如，所述预定距离可以为大于或等于300微米而小于或等于1100微米，但不以此为限。
在本公开至少一实施例中，当电路板设置于显示面板的下侧边时，则对位标记区域可以设置于靠近有效显示区边界的左下圆角，和/或，靠近有效显示区边界的右下圆角。
如图1D所示，当对位标记区域70靠近有效显示区边界202的左下圆角时，所述对位标记区域70在第一平面上的正投影与所述有效显示区边界202的左下圆角之间的最长距离为：所述对位标记70在第一平面上的正投影的边界线上的任一点与所述有效显示区边界202的左下圆角上的任一点之间的最长距离。在图1D中，所述对位标记区域70为L形，但不以此为限。
在本公开至少一实施例中，当对位标记区域靠近有效显示区边界的右下圆角时，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右下圆角之间的最长距离指的可 以是：所述对位标记区域在第一平面上的正投影的边界线上的任一点与所述有效显示区边界的右下圆角上的任一点之间的最长距离。
根据另一种具体实施方式，所述第一侧面可以为左侧面，所述第二侧面可以为下侧面，所述第三侧面可以为上侧面，所述第四侧面可以为右侧面；所述显示面板还可以包括设置于所述下表面的电路板，并所述电路板设置于所述显示面板的上侧边；
所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左上圆角之间的最长距离小于预定距离，和/或，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右上圆角之间的最长距离小于所述预定距离。
在本公开至少一实施例中，当对位标记区域靠近有效显示区边界的左上圆角时，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左上圆角之间的最长距离指的是：所述对位标记区域在第一平面上的正投影的边界线上的任一点与所述有效显示区边界的左上圆角上的任一点之间的最长距离。
在本公开至少一实施例中，当对位标记区域靠近有效显示区边界的右上圆角时，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右上圆角之间的最长距离指的是：所述对位标记区域在第一平面上的正投影的边界线上的任一点与所述有效显示区边界的右上圆角上的任一点之间的最长距离。
在具体实施时，所述预定距离可以根据实际情况选定；例如，所述预定距离可以为大于或等于300微米而小于或等于1100微米，但不以此为限。
在本公开至少一实施例中，当电路板设置于显示面板的上侧边时，则对位标记区域可以设置于靠近有效显示区边界的左上圆角，和/或，靠近有效显示区边界的右上圆角。
在本公开至少一实施例中，所述第一侧面可以为左侧面，所述第二侧面可以为下侧面，所述第三侧面可以为上侧面，所述第四侧面可以为右侧面；所述显示面板还包括设置于所述下表面的电路板，并所述电路板设置于所述 显示面板的下侧边；
所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左上圆角之间的最长距离小于预定距离，和/或，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右上圆角之间的最长距离小于所述预定距离。
在具体实施时，所述预定距离可以根据实际情况选定；例如，所述预定距离可以为大于或等于300微米而小于或等于1100微米，但不以此为限。
在本公开至少一实施例中，当电路板设置于显示面板的下侧边时，则对位标记区域可以设置于靠近有效显示区边界的左上圆角，和/或，靠近有效显示区边界的右上圆角。
在本公开至少一实施例中，所述第一侧面可以为左侧面，所述第二侧面可以为下侧面，所述第三侧面可以为上侧面，所述第四侧面可以为右侧面；所述显示面板还包括设置于所述下表面的电路板，并所述电路板设置于所述显示面板的上侧边；
所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左下圆角之间的最长距离小于预定距离，和/或，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右下圆角之间的最长距离小于所述预定距离。
在具体实施时，所述预定距离可以根据实际情况选定；例如，所述预定距离可以为大于或等于300微米而小于或等于1100微米，但不以此为限。
在本公开至少一实施例中，当电路板设置于显示面板的上侧边时，则对位标记区域可以设置于靠近有效显示区边界的左下圆角，和/或，靠近有效显示区边界的右下圆角。根据一种具体实施方式，所述平坦区可以包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
在所述平坦扇出区，所述显示面板包括设置于基底上的第一金属层；
在所述对位标记区域，所述第一金属层被挖空；
在所述平坦扇出区，所述第一金属层包括第一金属图形，所述第一金属 图形围绕着所述对位标记区域设置。
在本公开至少一实施例中，在所述平坦扇出区中，第一金属层可以包括多条并列设置金属连接线，所述金属连接线可以用于连接数据线和源极驱动器，或者，所述金属连接线可以用于连接栅线和栅极驱动器；
在所述平坦扇出区中，所述第一金属层也可以包括具有一定宽度的直流电压信号线，所述直流电压信号线可以为高电压信号线，也可以为低电压信号线；
所述直流电压信号线具有一定宽度的原因是降低所述直流电压信号线的电阻，以降低所述直流电压信号线上的直流电压信号的压降。
可选的，所述第一金属层可以包括栅金属层和/或源漏金属层，所述栅金属层可以包括第一栅金属层和第二栅金属层，但不以此为限。
在具体实施时，所述对位标记区域可以包含于所述平坦扇出区，在所述对位标记区域，第一金属层被挖空，以形成扇出开口，并第一金属层包括的第一金属图形围绕着所述对位标记区域设置，使得平坦扇出区包括的除了所述对位标记区域的透光率较低，所述对位标记区域的透光率较高，形成明场暗场反差，使得对位标记识别方便，而且不需要单独的空间放置对位标记，既能缩减显示面板的边框，又能实现工艺的精准对位。
在本公开至少一实施例中，所述第一金属图形可以包括数据线与源极驱动器之间的连接线；
所述第一金属图形可以包括栅线与栅极驱动器之间的连接线；
所述第一金属图形可以包括直流电压信号线，所述直流电压信号线可以包括高电压信号线和/或低电压信号线。
在具体实施时，所述第一金属层可以包括栅金属层，所述栅金属层可以包括依次设置于所述基底上的第一栅金属层和第二栅金属层，在所述对位标记区域，所述第一栅金属层和所述第二栅金属层都被挖空。所述第一栅金属层和所述第二栅金属层之间可以设置有第一绝缘层，由于所述第一绝缘层较透光，因此在所述对位标记区域，所述第一栅绝缘层可以不被挖空。
在对位相机识别范围内，由于扇出区走线密集，当所述对位标记区域包含于所述平坦扇出区时，因此对位标记区域与周围区域的对比度很高，明场 暗场反差强，识别方便。
可选的，在所述平坦扇出区，所述显示面板还包括设置于所述基底与所述第一金属层之间的半导体层；
在所述平坦扇出区包括的除了对位标记区域之外的区域，所述半导体层被挖空；
在所述对位标记区域，所述半导体层包括对位标记图形。
在相关技术中，在平坦扇出区可以不设置半导体层，然而在本公开至少一实施例中，在所述平坦扇出区，可以在基底与第一金属层之间设置半导体层，在所述平坦扇出区包括的除了对位标记区域之外的区域，所述半导体层被挖空；在所述对位标记区域，所述半导体层未被挖空，以使得所述半导体层包括对位标记图形，使得对位相机能够捕捉所述半导体层包括的对位标记图形而准确对位。
在具体实施时，在所述对位标记区域，所述显示面板还包括设置于所述第一金属层远离所述基底的一面的阳极层；
在所述对位标记区域，所述阳极层不设有开口；
在除了所述对位标记区域之外的区域，所述阳极层设有多个间隔设置的开口。
在本公开至少一实施例中，在所述显示面板的除了所述对位标记区域之外的区域，所述阳极层设置有多个开口(相邻的两个该开口之间存在一定距离)，以用于有机膜层排气，在所述对位标记区域，将所述阳极层上的开口补齐，以便对位相机可以识别所述对位标记区域。
可选的，所述对位标记区域在所述基底上的正投影的边缘为多边形、L形或T字形，但不以此为限。
图4A、图4B、图4C和图4D是在所述平坦扇出区包括的至少部分区域，依次设置于基底上的半导体层、第一栅金属层、第二栅金属层和阳极层的俯视图；在图4A、图4B、图4C和图4D中，标号为40的六边形所在区域为对位标记区域；
在图4A、图4B、图4C和图4D对应的实施例中，所述第一金属层包括栅金属层，所述栅金属层包括第一栅金属层和第二栅金属层；
如图4A所示，在所述平坦扇出区包括的除了所述对位标记区域40之外的区域，所述半导体层被挖空，以使得所述半导体层包括设置于对位标记区域中的对位标记图形43；
如图4B所示，第一栅金属层包括的第一栅金属图形41围绕着所述对位标记区域40设置；在所述对位标记区域40，所述第一栅金属层被挖空；
如图4C所示，第二栅金属层包括的第二栅金属图形42围绕着所述对位标记区域40设置；在所述对位标记区域40，所述第二栅金属层被挖空；
如图4D所示，在所述对位标记区域40，所述阳极层上不设有开口，以便对位相机可以识别所述对位标记区域40；在所述平坦扇出区包括的除了所述对位标记区域40的其他区域，所述阳极层上设有多个开口4d1(相邻的两开口4d1之间存在一定距离)，通过在阳极层上挖空以形成开口4d1，所述开口4d1用于释放有机膜层的气体。
在本公开至少一实施例中，所述对位标记区域40在基底上的正投影的边缘的形状可以根据实际需要设定，该边缘的形状可以为多边形、L形或T字形等形状。
在具体实施时，在平坦扇出区，所述半导体层与所述第一栅金属层之间可以设置有第二绝缘层，在所述第一栅金属层与所述第二栅金属层之间可以设置有第一绝缘层，在所述第二栅金属层和所述阳极层之间可以设置有第三绝缘层，由于第一绝缘层的透光率、第二绝缘层的透光率和第三绝缘层的透光率较高，因此在所述对位标记区域，所述第一绝缘层、所述第二绝缘层和所述第三绝缘层可以不被挖空。
在具体实施时，所述第一绝缘层、所述第二绝缘层和所述第三绝缘层可以由氧化硅或氮化硅制成，但不以此为限。
根据另一种具体实施方式，所述平坦区可以包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
在所述对位标记区域，所述显示面板包括设置于基底上的半导体层；
所述半导体层包括对位标记图形。
在本公开至少一实施例中，所述平坦区可以包括平坦信号线区域，可以在平坦信号线区域包括的对位标记区域设置对位标记图形，在所述平坦信号 线区域包括的对位标记区域，显示面板可以包括设置于基底上的半导体层，所述半导体层包括对位标记图形。
可选的，所述对位标记图形在所述基底上的正投影为L形、T字形或多边形。
在具体实施时，当所述对位标记区域包含于平坦信号线区域，并在所述对位标记区域，所述显示面板包括设置于基底上的半导体层，所述半导体层包括对位标记图形时，所述显示面板还可以包括设置于所述半导体层远离所述基底的一面的源漏金属层，所述源漏金属层可以包括低电压信号线；
并且，在所述平坦信号线区域，所述显示面板还可以包括设置于所述源漏金属层远离所述半导体层的一面的阳极层，在源漏金属层上方覆盖阳极层的目的是为了将有效显示区中的发光元件的阴极搭接到所述低电压信号线上(在源漏金属层上方覆盖的阳极层的面积有低电压信号线与阴极搭接情况决定)，在源漏金属层下方设置的半导体层设置对位标记图形，以方便对位相机从显示面板背面准确抓取所述对位标记图形，此方案既不增加边框，也不影响其他背板电路的排线，也能够使得对位相机准确无误的抓取对比标记图形而进行对位。
图5A、图5B和图5C是在所述平坦信号线区域包括的至少部分区域，依次设置于基底上的半导体层、源漏金属层和阳极层的俯视图；
如图5A所示，在所述平坦信号线区域包括的对位标记区域，半导体层包括对位标记图形50；
如图5B所示，标号为51的在所述平坦信号线区域包括的至少部分区域，所述源漏金属层包括的低电压信号线；
如图5C所示，标号为52的为在所述平坦信号线区域包括的至少部分区域，设置于所述源漏金属层之上的阳极层。
图6A是图5A和图5B叠加后的示意图，图6B是图5B和图5C叠加后的示意图。
在具体实施时，所述平坦区可以包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
在所述平坦信号线区域，所述显示面板包括设置于所述基底上的第二金 属层；
在所述对位标记区域，所述第二金属层被挖空。
在本公开至少一实施例中，所述对位标记区域可以包含于平坦信号线区域，在平坦信号线区域，显示面板包括第二金属层，在所述对位标记区域，所述第二金属层被挖空，以形成可以透光的对位标记，对位标记区域的透光率高于周围区域的透光率，使得能够准确的进行对位标记。
可选的，所述第二金属层可以包括源漏金属层和/或栅金属层，但不以此为限。
在具体实施时，所述第二金属层可以包括信号线，所述信号线可以包括直流电压信号线；当所述信号线包括直流电压信号线时，所述信号线可以包括低电压信号线和/或高电压信号线，但不以此为限。
在本公开至少一实施例中，当所述第二金属层包括源漏金属层，所述源漏金属层包括低电压信号线时，在所述平坦信号线区域，所述显示面板还可以包括设置于所述源漏金属层远离所述基底的一面的阳极层，在源漏金属层上方覆盖阳极层的目的是为了将有效显示区中的发光元件的阴极搭接到所述低电压信号线上(在源漏金属层上方覆盖的阳极层的面积有低电压信号线与阴极搭接情况决定)。
可选的，所述对位标记区域在所述基底上的正投影的边缘的形状可以为L形、T字形或多边形。
图6C示出了设置于所述平坦信号线区域的源漏金属层包括的至少一部分源漏金属图形的示意图，如图6C所示，平坦信号线区域包括对位标记区域70，在所述对位标记区域70，所述源漏金属层被挖空，以形成可以透光的对位标记，对位标记区域70的透光率高于周围区域的透光率，使得能够准确的进行对位标记。
在图6C所示的实施例中，所述对位标记区域70在基底上的正投影的边缘的形状为L形，但不以此为限。
根据又一种具体实施方式，所述平坦区可以包括平坦虚拟驱动电路区域；所述对位标记区域包含于所述平坦虚拟驱动电路区域；
在所述对位标记区域，所述显示面板包括依次设置于基底上的半导体层、 第三金属层和第四金属层；
在所述对位标记区域，所述第三金属层和所述第四金属层都被挖空。
在优选情况下，在所述对位标记区域，所述半导体层也被挖空。
可选的，所述第三金属层可以包括栅金属层，所述第四金属层可以包括源漏金属层，但不以此为限。
在具体实施时，所述对位标记区域可以包含于平坦虚拟驱动电路区域；除了所述对位标记区域之外，在距离所述对位标记区域较近的周边区域，电路走线密集，由于走线对可见光是不透明的，在一定的背光源条件下，对位相机视场中会表现为黑色，而在对位标记区域中无走线排布，背光几乎可全部透过所述对位标记区域进入对位相机，与周围区域形成强烈对比，对位相机便可识别所述对位标记区域。
在具体实施时，在所述对位标记区域，所述显示面板还包括设置于所述第四金属层远离所述第二金属层的一面的阳极层；
在所述对位标记区域，所述阳极层不设有开口，以便对位相机可以识别所述对位标记区域；
在除了所述对位标记区域之外的区域，所述阳极层可以设有多个间隔设置的开口。
可选的，所述对位标记区域在所述基底上的正投影的边缘为多边形、L形或T字形。
在本公开至少一实施例中，所述第三金属层可以包括栅金属层，所述栅金属层可以包括依次设置于所述半导体层远离所述基底的一面的第一栅金属层和第二栅金属层。
图7中示出了驱动电路区包括的部分区域、扇出区31包括的部分区域和信号线区域33包括的部分区域。
如图7所示，所述平坦区包括平坦虚拟驱动电路区域71；所述对位标记区域70包含于所述平坦虚拟驱动电路区域71；平坦虚拟驱动电路区域71可以包含于驱动电路区，所述驱动电路区除了包括所述平坦虚拟驱动电路区域71之外，还可以包括第一驱动电路区域721和第二驱动电路区域722，所述平坦虚拟驱动电路区域71包括对位标记区域70；
在所述对位标记区域70，所述显示面板包括依次设置于基底上的半导体层、第一栅金属层、第二栅金属层、源漏金属层和阳极层；
在所述平坦虚拟驱动电路区域71包括的除了所述对位标记区域70之外的区域，设置有至少一级虚拟移位寄存器单元；在所述第一驱动电路区域721和第二驱动电路区域722，设置有包括多级移位寄存器单元的驱动电路；
在所述对位标记区域70，所述半导体层、所述栅金属层和所述源漏金属层都被挖空，以使得对位标记区域70的透光率远高于驱动电路区包括的与对位标记区域70临近的区域的透光率，使得对位相机能够准确识别所述对位标记区域；而且不需要单独的空间放置对位标记，既能缩减显示面板的边框，又能实现工艺的精准对位；
在所述对位标记区域70，所述阳极层上不设有开口，以便对位相机可以识别所述对位标记区域70；
在驱动电路区包括的除了所述对位标记区域70中，所述阳极层上可以设有多个开口，用于为有机膜层放气。
在图7、图8A-图8G所示的实施例中，所述第三金属层包括栅金属层，所述栅金属层包括第一栅金属层和第二栅金属层；所述第四金属层包括源漏金属层。
如图7所示，所述对位标记区域70在所述基底上的正投影的边缘的形状为L形，但不以此为限。在具体实施时，所述对位标记区域70在所述基底上的正投影的边缘的形状也可以为其他形状。
图8A是在平坦虚拟驱动电路区域，设置于基底上的半导体层包括的有源图形81的一种实施例的俯视图；
图8B是在平坦虚拟驱动电路区域，设置于所述半导体层上方的第一栅金属层包括的第一栅金属图形82的一种实施例的俯视图；
图8C是在平坦虚拟驱动电路区域，图8A和图8B叠加后的示意图；
图8D是在平坦虚拟驱动电路区域，在图8C的基础上增加了第二栅金属层包括的第二栅金属图形83的示意图；
图8E是在平坦虚拟驱动电路区域，依次设置了半导体层、第一栅金属层和第二栅金属层之后，设置多个过孔H0的示意图；
图8F是在平坦虚拟驱动电路区域，在设置了多个过孔H0后，再设置源漏金属层S0的示意图；
如图8F所示，在所述对位标记区域70，所述第一栅金属层、所述第二栅金属层、所述半导体层和所述源漏金属层都被挖空。
图8G是在平坦虚拟驱动电路区域，在源漏金属层上设置了阳极层90的示意图，在对位标记区域70，所述阳极层90不设有开口，以便对位相机可以识别所述对位标记区域70；在除了所述对位标记区域70之外的区域，所述阳极层90设有多个开口9g1。
在图8F和图8G中，虚线所围起来的区域为所述对位标记区域70，该对位标记区70在基底上的正投影的边缘的形状为L形，但不以此为限。
在具体实施时，在平坦虚拟驱动电路区域，所述半导体层与所述第一栅金属层之间可以设置有第二绝缘层，在所述第一栅金属层与所述第二栅金属层之间可以设置有第一绝缘层，在所述第二栅金属层和所述源漏金属层之间可以设置有第四绝缘层，在所述源漏金属层和所述阳极层之间可以设置有第五绝缘层，由于第一绝缘层的透光率、第二绝缘层的透光率、第四绝缘层的透光率和所述第五绝缘层的透光率较高，因此在所述对位标记区域，所述第一绝缘层、所述第二绝缘层、所述第四绝缘层和所述第五绝缘层可以不被挖空。
在本公开至少一实施例中，所述第一绝缘层、所述第二绝缘层、所述第四绝缘层和所述第五绝缘层可以由氧化硅或氮化硅制成，但不以此为限。
本公开至少一实施例所述的显示面板的制作方法包括：在显示面板的周边区域的平坦区设置对位标记区域；
在所述对位标记区域中设置有对位标记图形；和/或，在所述对位标记区域内，至少一层膜层被挖空；
所述周边区域为所述显示面板包括的除了有效显示区域之外的区域。
在本公开至少一实施例所述的显示面板的制作方法中，在显示面板的周边区域的平坦区设置对位标记区域，可以在对位标记区域中设置对位标记图形，也可以在对位标记区域中挖空至少一膜层，由于在对位标记区域，至少一层膜层被挖空，则对位标记区域的透光率高于周围区域的透光率，使得能 够准确的进行对位标记。
在本公开至少一实施例中，所述周围区域可以为所述周边区域包括的距离所述对位标记区域较近的区域。
可选的，所述膜层可以包括金属层；也即，在对位标记区域，至少一层金属层可以被挖空。
在具体实施时，在所述平坦区，所述显示面板的表面是平面。
可选的，所述显示面板包括上表面、下表面、第一侧面，第二侧面、第三侧面和第四侧面；
所述第一侧面、所述第二侧面、所述第三侧面和所述第四侧面都为弯曲的侧面；
所述第一侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第二侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第三侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第四侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
所述第一平面与所述下表面平行。
在本公开至少一实施例中，所述第一侧面可以为左侧面，所述第二侧面可以为下侧面，所述第三侧面可以为上侧面，所述第四侧面可以为右侧面；所述显示面板还可以包括设置于所述下表面的电路板，并所述电路板设置于所述显示面板的下侧边；
所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左下圆角之间的最长距离小于预定距离，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右下圆角之间的最长距离小于所述预定距离。
在具体实施时，所述预定距离可以根据实际情况选定；例如，所述预定 距离可以为大于或等于300微米而小于或等于1100微米，但不以此为限。
在本公开至少一实施例中，当电路板设置于显示面板的下侧边时，则对位标记区域可以设置于靠近有效显示区边界的左下圆角，和/或，靠近有效显示区边界的右下圆角。
在本公开至少一实施例中，所述第一侧面可以为左侧面，所述第二侧面可以为下侧面，所述第三侧面可以为上侧面，所述第四侧面可以为右侧面；所述显示面板还可以包括设置于所述下表面的电路板，并所述电路板设置于所述显示面板的上侧边；
所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左上圆角之间的最长距离小于预定距离，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右上圆角之间的最长距离小于所述预定距离。
在具体实施时，所述预定距离可以根据实际情况选定；例如，所述预定距离可以为大于或等于300微米而小于或等于1100微米，但不以此为限。
在本公开至少一实施例中，当电路板设置于显示面板的上侧边时，则对位标记区域可以设置于靠近有效显示区边界的左上圆角，和/或，靠近有效显示区边界的右上圆角。
在本公开至少一实施例中，所述第一侧面可以为左侧面，所述第二侧面可以为下侧面，所述第三侧面可以为上侧面，所述第四侧面可以为右侧面；所述显示面板还包括设置于所述下表面的电路板，并所述电路板设置于所述显示面板的下侧边；
所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左上圆角之间的最长距离小于预定距离，和/或，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右上圆角之间的最长距离小于所述预定距离。
在具体实施时，所述预定距离可以根据实际情况选定；例如，所述预定距离可以为大于或等于300微米而小于或等于1100微米，但不以此为限。
在本公开至少一实施例中，当电路板设置于显示面板的下侧边时，则对位标记区域可以设置于靠近有效显示区边界的左上圆角，和/或，靠近有效显示区边界的右上圆角。
在本公开至少一实施例中，所述第一侧面可以为左侧面，所述第二侧面可以为下侧面，所述第三侧面可以为上侧面，所述第四侧面可以为右侧面；所述显示面板还包括设置于所述下表面的电路板，并所述电路板设置于所述显示面板的上侧边；
所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的左下圆角之间的最长距离小于预定距离，和/或，所述对位标记区域在所述第一平面上的正投影与所述显示面板的有效显示区边界在所述第一平面上的正投影的右下圆角之间的最长距离小于所述预定距离。
在具体实施时，所述预定距离可以根据实际情况选定；例如，所述预定距离可以为大于或等于300微米而小于或等于1100微米，但不以此为限。
在本公开至少一实施例中，当电路板设置于显示面板的上侧边时，则对位标记区域可以设置于靠近有效显示区边界的左下圆角，和/或，靠近有效显示区边界的右下圆角。
根据一种具体实施方式，所述平坦区包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦扇出区，
在所述基底的一面设置第一金属层，对所述第一金属层进行构图工艺，以形成第一金属图形，并使得在所述对位标记区域，所述第一金属层被挖空；
所述第一金属层图形围绕着所述对位标记区域设置。
在具体实施时，所述对位标记区域可以包含于所述平坦扇出区，在所述对位标记区域，第一金属层被挖空，以形成扇出开口，使得平坦扇出区包括的除了所述对位标记区域的透光率较低，所述对位标记区域的透光率较高，形成明场暗场反差，使得对位标记识别方便，而且不需要单独的空间放置对位标记，既能缩减显示面板的边框，又能实现工艺的精准对位。
可选的，所述第一金属层可以包括栅金属层和/或源漏金属层，所述栅金属层可以包括第一栅金属层和第二栅金属层，但不以此为限。
根据另一种具体实施方式，所述平坦区包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦扇出区，
在基底上设置半导体层，对所述半导体层进行构图工艺，使得在所述平坦扇出区包括的除了对位标记区域之外的区域，所述半导体层被挖空；
在所述半导体层远离所述基底的一面设置第一金属层，对所述第一金属层进行构图工艺，以形成第一金属图形，并使得在所述对位标记区域，所述第一金属层被挖空；
所述第一金属层图形围绕着所述对位标记区域设置。
在相关技术中，在平坦扇出区可以不设置半导体层，然而在本公开至少一实施例中，在所述平坦扇出区，可以在基底与第一金属层之间设置半导体层，在所述平坦扇出区包括的除了对位标记区域之外的区域，所述半导体层被挖空；在所述对位标记区域，所述半导体层未被挖空，以使得所述半导体层包括对位标记图形，使得对位相机能够捕捉所述半导体层包括的对位标记图形而准确对位。
根据又一种具体实施方式，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦信号线区域，
在所述基底上制作半导体层，对所述半导体层进行构图工艺，以形成对位标记图形；所述对位标记图形设置于所述对位标记区域。
在本公开至少一实施例中，所述平坦区可以包括平坦信号线区域，可以在平坦信号线区域包括的对位标记区域设置对位标记图形，在所述平坦信号线区域包括的对位标记区域，显示面板可以包括设置于基底上的半导体层，所述半导体层包括对位标记图形。
根据另一种具体实施方式，所述平坦区可以包括平坦信号线区域；所述 对位标记区域可以包含于所述平坦信号线区域；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦信号线区域，
在所述基底的一面设置第二金属层，并使得在所述对位标记区域，所述第二金属层被挖空。
在本公开至少一实施例中，所述平坦区可以包括平坦信号线区域，所述对位标记区域可以包含于所述平坦信号线区域，在对位标记区域，将第二金属层挖空，以形成可以透光的对位标记，对位标记区域的透光率高于周围区域的透光率，使得能够准确的进行对位标记。
可选的，所述第二金属层可以包括源漏金属层和/或栅金属层，但不以此为限。
在具体实施时，本公开至少一实施例所述的显示面板的制作方法还可以包括：对所述第二金属层进行构图工艺，以形成信号线。
可选的，所述信号线可以包括直流电压信号线；当所述信号线包括直流电压信号线时，所述信号线可以包括低电压信号线和/或高电压信号线。
根据再一种具体实施方式，所述平坦区包括平坦虚拟驱动电路区域；所述对位标记区域包含于所述平坦虚拟驱动电路区域；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦虚拟驱动电路区域，
在基底上设置半导体层，对所述半导体层进行构图工艺，形成有源图形；
在所述半导体层远离所述基底的一面设置第三金属层，对所述第三金属层进行构图工艺，以形成第三金属图形，并使得在所述对位标记区域，所述第三金属层被挖空；
在所述第三金属层远离所述半导体层的一面设置第四金属层，对所述第四金属层进行构图工艺，以形成第四金属图形，并使得在所述对位标记区域，所述第四金属层被挖空。
可选的，所述第三金属层可以包括栅金属层，所述第四金属层可以包括源漏金属层，但不以此为限。
根据又一种具体实施方式，所述平坦区包括平坦虚拟驱动电路区域；所 述对位标记区域包含于所述平坦虚拟驱动电路区域；
所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦虚拟驱动电路区域，
在基底上设置半导体层，对所述半导体层进行构图工艺，形成有源图形，并使得在所述对位标记区域，所述半导体层被挖空；
在所述半导体层远离所述基底的一面设置第三金属层，对所述第三金属层进行构图工艺，以形成第三金属图形，并使得在所述对位标记区域，所述第一金属层被挖空；
在所述第三金属层远离所述半导体层的一面设置第四金属层，对所述第四金属层进行构图工艺，以形成第四金属图形，并使得在所述对位标记区域，所述第四金属层被挖空。
可选的，所述第三金属层可以包括栅金属层，所述第四金属层可以包括源漏金属层，但不以此为限。
在具体实施时，所述对位标记区域可以包含于平坦虚拟驱动电路区域；除了所述对位标记区域之外，在距离所述对位标记区域较近的周边区域，电路走线密集，由于走线对可见光是不透明的，在一定的背光源条件下，对位相机视场中会表现为黑色，而在对位标记区域中无走线排布，背光几乎可全部透过所述对位标记区域进入对位相机，与周围区域形成强烈对比，对位相机便可识别所述对位标记区域。
本公开至少一实施例所述的显示装置可以包括本公开实施例所述的显示面板。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物 理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述是本公开的优选实施方式，应当指出，对于本技术领域的普通技术人员来说，在不脱离本公开所述原理的前提下，还可以作出若干改进和润饰，这些改进和润饰也应视为本公开的保护范围。

Claims (23)

  1. 一种显示面板，包括设置于显示面板的周边区域的平坦区的对位标记区域；
    所述周边区域为所述显示面板包括的除了有效显示区域之外的区域；
    在所述对位标记区域中设置有对位标记图形；和/或，在所述对位标记区域内，至少一层膜层被挖空。
  2. 如权利要求1所述的显示面板，其中，所述膜层包括金属层。
  3. 如权利要求1所述的显示面板，其中，在所述平坦区，所述显示面板的表面是平面。
  4. 如权利要求1所述的显示面板，其中，所述显示面板包括上表面、下表面、第一侧面，第二侧面、第三侧面和第四侧面；
    所述第一侧面、所述第二侧面、所述第三侧面和所述第四侧面都为弯曲的侧面；
    所述第一侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
    所述第二侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
    所述第三侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
    所述第四侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
    所述第一平面与所述下表面平行。
  5. 如权利要求1所述的显示面板，其中，所述对位标记区域在所述基底上的正投影的边缘为多边形、L形或T字形，所述对位标记图形在所述基底上的正投影为L形、T字形或多边形。
  6. 如权利要求1至5中任一权利要求所述的显示面板，其中，所述平坦区包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
    在所述平坦扇出区，所述显示面板包括设置于基底上的第一金属层；
    在所述对位标记区域，所述第一金属层被挖空；
    在所述平坦扇出区，所述第一金属层包括第一金属图形，所述第一金属图形围绕着所述对位标记区域设置。
  7. 如权利要求6所述的显示面板，其中，所述第一金属图形包括数据线与源极驱动器之间的连接线。
  8. 如权利要求6所述的显示面板，其中，所述第一金属图形包括直流电压信号线。
  9. 如权利要求6所述的显示面板，其中，
    在所述平坦扇出区，所述显示面板还包括设置于所述基底与所述第一金属层之间的半导体层；
    在所述平坦扇出区包括的除了对位标记区域之外的区域，所述半导体层被挖空；
    在所述对位标记区域，所述半导体层包括对位标记图形。
  10. 如权利要求6所述的显示面板，其中，在所述对位标记区域，所述显示面板还包括设置于所述第一金属层远离所述基底的一面的阳极层；
    在所述对位标记区域，所述阳极层不设有开口；
    在除了所述对位标记区域之外的区域，所述阳极层设有多个间隔设置的开口。
  11. 如权利要求1至5中任一权利要求所述的显示面板，其中，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
    在所述对位标记区域，所述显示面板包括设置于基底上的半导体层；
    所述半导体层包括对位标记图形。
  12. 如权利要求1至5中任一权利要求所述的显示面板，其中，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
    在所述平坦信号线区域，所述显示面板包括设置于所述基底上的第二金属层；
    在所述对位标记区域，所述第二金属层被挖空。
  13. 如权利要求12所述的显示面板，其中，所述第二金属层包括信号线。
  14. 一种显示面板的制作方法，包括：在显示面板的周边区域的平坦区 设置对位标记区域；
    在所述对位标记区域中设置有对位标记图形；和/或，在所述对位标记区域内，至少一层膜层被挖空；
    所述周边区域为所述显示面板包括的除了有效显示区域之外的区域。
  15. 如权利要求14所述的显示面板的制作方法，其中，所述膜层包括金属层。
  16. 如权利要求14所述的显示面板的制作方法，其中，在所述平坦区，所述显示面板的表面是平面。
  17. 如权利要求14所述的显示面板的制作方法，其中，所述显示面板包括上表面、下表面、第一侧面，第二侧面、第三侧面和第四侧面；
    所述第一侧面、所述第二侧面、所述第三侧面和所述第四侧面都为弯曲的侧面；
    所述第一侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
    所述第二侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
    所述第三侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
    所述第四侧面在第一平面上的正投影与所述平坦区在所述第一平面上的正投影不交叠；
    所述第一平面与所述下表面平行。
  18. 如权利要求14至17中任一权利要求所述的显示面板的制作方法，其中，所述平坦区包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
    所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦扇出区，
    在所述基底的一面设置第一金属层，对所述第一金属层进行构图工艺，以形成第一金属图形，并使得在所述对位标记区域，所述第一金属层被挖空；
    所述第一金属图形围绕着所述对位标记区域设置。
  19. 如权利要求14至17中任一权利要求所述的显示面板的制作方法，其中，所述平坦区包括平坦扇出区；所述对位标记区域包含于所述平坦扇出区；
    所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦扇出区，
    在基底上设置半导体层，对所述半导体层进行构图工艺，使得在所述平坦扇出区包括的除了对位标记区域之外的区域，所述半导体层被挖空；
    在所述半导体层远离所述基底的一面设置第一金属层，对所述第一金属层进行构图工艺，以形成第一金属图形，并使得在所述对位标记区域，所述第一金属层被挖空；
    所述第一金属图形围绕着所述对位标记区域设置。
  20. 如权利要求14至17中任一权利要求所述的显示面板的制作方法，其中，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
    所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦信号线区域，
    在所述基底上制作半导体层，对所述半导体层进行构图工艺，以形成对位标记图形；所述对位标记图形设置于所述对位标记区域。
  21. 如权利要求14至17中任一权利要求所述的显示面板的制作方法，其中，所述平坦区包括平坦信号线区域；所述对位标记区域包含于所述平坦信号线区域；
    所述在显示面板的周边区域的平坦区设置对位标记区域步骤包括：在所述平坦信号线区域，
    在所述基底的一面设置第二金属层，并使得在所述对位标记区域，所述第二金属层被挖空。
  22. 如权利要求21所述的显示面板的制作方法，其中，还包括：对所述第二金属层进行构图工艺，以形成信号线。
  23. 一种显示装置，包括如权利要求1至13中任一权利要求所述的显示面板。
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