WO2021220942A1 - Inspection device and inspection method - Google Patents

Inspection device and inspection method Download PDF

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Publication number
WO2021220942A1
WO2021220942A1 PCT/JP2021/016358 JP2021016358W WO2021220942A1 WO 2021220942 A1 WO2021220942 A1 WO 2021220942A1 JP 2021016358 W JP2021016358 W JP 2021016358W WO 2021220942 A1 WO2021220942 A1 WO 2021220942A1
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WO
WIPO (PCT)
Prior art keywords
wiring
capacitance
capacity
correction
substrate
Prior art date
Application number
PCT/JP2021/016358
Other languages
French (fr)
Japanese (ja)
Inventor
範明 高木
慶太 郡司
Original Assignee
日本電産リード株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電産リード株式会社 filed Critical 日本電産リード株式会社
Priority to KR1020227037149A priority Critical patent/KR20230002489A/en
Priority to CN202180031140.3A priority patent/CN115485572A/en
Priority to JP2022517696A priority patent/JPWO2021220942A1/ja
Publication of WO2021220942A1 publication Critical patent/WO2021220942A1/en

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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • G01R27/2605Measuring capacitance
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02General constructional details
    • G01R1/06Measuring leads; Measuring probes
    • G01R1/067Measuring probes
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/26Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2836Fault-finding or characterising
    • G01R31/2837Characterising or performance testing, e.g. of frequency response
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2853Electrical testing of internal connections or -isolation, e.g. latch-up or chip-to-lead connections
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851Testing of integrated circuits [IC]
    • G01R31/2896Testing of IC packages; Test features related to IC packages
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52Testing for short-circuits, leakage current or ground faults
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54Testing for continuity
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
    • G01R35/007Standards or reference devices, e.g. voltage or resistance standards, "golden references"
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits

Definitions

  • the present invention relates to an inspection device for inspecting a substrate and an inspection method.
  • the capacitance of the wiring also changes depending on the facing area of the wiring. Therefore, if the width of the wiring, the thickness of the insulating layer, and the like vary due to variations in the manufacturing of the substrate, the capacitance of the wiring also varies.
  • An object of the present invention is to provide an inspection device and an inspection method that can easily correct variations in capacitance due to variations in substrate manufacturing.
  • the inspection device is an inspection device that inspects a plurality of substrates on which wirings provided as the same wiring in design are formed, and the capacitance of the wiring of each substrate is used as a measurement capacitance.
  • the measurement unit to be measured, the average capacity calculation unit that calculates the average value of the measurement capacity measured from the wiring provided as the same wiring in the design as the average capacity, and one of the plurality of substrates as the target substrate.
  • the correction capacity is calculated by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the capacity.
  • the inspection method is an inspection method for inspecting a plurality of substrates on which wirings provided as the same wiring in design are formed, and measures the capacitance of the wiring of each of the substrates.
  • the measurement step of measuring as the capacity the average capacity calculation step of calculating the average value of the measured capacities measured from the wiring provided as the same wiring in the design as the average capacity, and one of the plurality of substrates.
  • the capacity correction step includes a capacity correction step of calculating a correction capacity which is a correction value of the measured capacity of the target wiring to be inspected on the target board, and the capacity correction step is performed on the wiring of the target board.
  • the correction capacity is calculated by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the measurement capacity.
  • the inspection device and inspection method having such a configuration can easily correct the variation in capacitance due to the variation in manufacturing of the substrate.
  • the substrate inspection device 1 shown in FIG. 1 is an apparatus for inspecting the wiring of the substrates A1 to A25 formed on the panel 100.
  • the substrate inspection device 1 corresponds to an example of the inspection device.
  • the substrate inspection device 1 shown in FIG. 1 has a housing 11.
  • the board fixing device 12, the inspection unit 3, the control unit 2, and the inspection unit moving mechanism 15 for appropriately moving the inspection unit 3 in the housing 11 are mainly provided in the internal space of the housing 11. ing.
  • the board fixing device 12 is configured to fix the panel 100 to be inspected at a predetermined position.
  • the inspection unit 3 is located above the panel 100 fixed to the substrate fixing device 12.
  • An inspection jig 4 for inspecting the substrate A formed on the panel 100 is attached to the inspection unit 3.
  • a plurality of probes Pr are attached to the inspection jig 4.
  • the panel 100 shown in FIG. 2 includes substrates A1 to A25.
  • the substrates A1 to A25 are collectively referred to as a substrate A, and when individual substrates are indicated, a substrate number n is added to the reference numeral A and the substrate is referred to as a substrate An.
  • the panel 100 is, for example, a panel for PLP (Panel Level Packaging).
  • the substrate A is, for example, a package substrate or film carrier for a semiconductor package, a printed wiring board, a glass epoxy substrate, a flexible substrate, a ceramic multilayer wiring board, an electrode plate for a display such as a liquid crystal display or an EL (Electro-Luminescence) display, and a touch panel. It may be various substrates such as a transparent conductive plate for use, a semiconductor wafer, a semiconductor chip, a semiconductor substrate such as a CSP (Chip size package), and the like. Inspection points such as wiring patterns, pads, lands, solder bumps, vias, and terminals are formed on the substrate A.
  • the same wiring pattern is formed on the boards A1 to A25 by design.
  • the number of substrates A included in the panel 100 is not limited to 25.
  • the substrate A is, for example, a substrate after the RDL is formed on the carrier and before the chip die is mounted on the RDL when a fan-out package, which is a kind of semiconductor chip package, is manufactured in the RDL (Redistribution Layer) first process. Is.
  • the substrate An is, for example, a multilayer substrate including a plurality of wiring layers of the first layer L1, the second layer L2, and the third layer L3.
  • the board An has wirings P (n, 1) to P (n, 5) having wiring numbers 1 to 5 and reference wirings B (n, 1) to B (n, 3) having wiring numbers 1 to 3. It is formed.
  • the wiring of the wiring number j on the substrate Ai of the substrate number i is referred to as wiring P (i, j)
  • reference wiring of the wiring number j on the substrate Ai of the substrate number i is referred to as reference wiring B (i, j). do.
  • Wiring P (n, 1) to P (n, 5) and reference wiring B (n, 1) to B (n, 3) correspond to an example of wiring.
  • the wirings P (n, 1) to P (n, 5) are collectively referred to as wiring Pn
  • the wirings P (1,1) to P (25, 5) are collectively referred to as wiring P, which is a reference wiring.
  • B (n, 1) to B (n, 3) are collectively referred to as reference wiring Bn
  • reference wiring B (1,1) to B (25,3) are collectively referred to as reference wiring B.
  • the wiring P and the reference wiring B each include an end portion e and g, and a main body f connecting the end portion e and the end portion g, respectively.
  • the ends e and g are, for example, vias and pads.
  • the main body f extends in a strip shape and constitutes a main part of each wiring.
  • the end portion e of the wiring P and the reference wiring B is formed in the first layer L1.
  • the end portion g of the wiring P and the reference wiring B is formed in the third layer L3.
  • the main body f of the wiring P (n, 1) and the reference wiring B (n, 1) is formed in the first layer L1.
  • the main body f of the wiring P (n, 2), P (n, 3), and the reference wiring B (n, 2) is formed in the second layer L2.
  • the main body f of the wiring P (n, 4), P (n, 5), and the reference wiring B (n, 3) is formed in the third layer L3.
  • the portion formed in the first layer L1 is indicated by a solid line
  • the portion formed in the second layer L2 is indicated by a broken line
  • the portion formed in the third layer L3 is indicated by a alternate long and short dash line.
  • the second layer L2 of the substrate An has a planar pattern G (n, 1) formed so as to face the reference wiring B (n, 1) and spread in a planar manner.
  • a planar pattern G (n, 3) is formed so as to be arranged so as to face the reference wiring B (n, 3) and spread in a planar manner.
  • a planar pattern G (n, 2) is formed on the first layer L1 of the substrate An so as to be arranged to face the reference wiring B (n, 2) and spread in a planar manner.
  • Vias exposed on the first layer L1 are connected to the planar patterns G (n, 1) and G (n, 3).
  • the probe Pr By bringing the probe Pr into contact with this via, the probe Pr can be conductively connected to the planar patterns G (n, 1) and G (n, 3).
  • the probe Pr comes into contact with the via to enable a conductive connection.
  • the influence of the capacity of the first layer L1 itself can be minimized by forming it small.
  • planar patterns G (n, 1), G (n, 2), and G (n, 3) are referred to as reference wirings B (n, 1), B (n, 2), and B (n, 3). It suffices that they are arranged so as to face each other, and the arranged layers are not limited to the example shown in FIG.
  • the panel 100 is composed of a carrier substrate 102, a release layer 103, and a substrate A laminated in this order.
  • the end portion e of each wiring is formed in the first layer L1
  • the end portion g of each wiring is formed in the third layer L3.
  • the carrier is attached to one surface (third layer L3) of the substrate A, so that the substrate It is not possible to inspect the continuity of the wiring by bringing the probe into contact with both sides of A.
  • the substrate inspection device 1 has an end e, a planar pattern G (n, 2), or a planar pattern G (n, 1) on the exposed side surface (first layer L1) of the substrate A. , G (n, 3) is brought into contact with the probe Pr, and the capacitance of the wiring is measured to inspect the wiring.
  • the probe Pr comes into contact with the via to enable a conductive connection.
  • the influence of the capacity of the first layer L1 itself can be minimized by forming it small.
  • the panel 100 is not limited to the substrate after the substrate A is formed on the carrier and before the chip die is mounted on the substrate A.
  • the inspection unit 3 includes a plurality of probe Prs, a scanner unit 31, an AC power supply 32, and a plurality of ammeters 33.
  • Each probe Pr, one end of the AC power supply 32, one end of each ammeter 33, and the circuit ground are connected to the scanner unit 31.
  • the other end of the AC power supply 32 and the other end of each ammeter 33 are connected to the circuit ground.
  • the scanner unit 31 is a switching circuit configured by using a switching element such as a transistor or a relay switch.
  • the scanner unit 31 connects the AC power supply 32 and each ammeter 33 to an arbitrary probe Pr in response to the control signal from the control unit 2.
  • the AC power supply 32 is an AC power supply circuit that outputs an AC voltage V having a preset frequency f to the probe Pr via the scanner unit 31.
  • the ammeter 33 is an AC ammeter configured by using, for example, a shunt resistor, a Hall element, an analog-digital converter, or the like. The ammeter 33 measures the current I flowing from the probe Pr connected via the scanner unit 31 to the circuit ground, and transmits a signal indicating the current I to the control unit 2.
  • the voltage V and the current I may be effective values or peak values.
  • control unit 2 stores, for example, a CPU (Central Processing Unit) that executes a predetermined logical operation, a RAM (Random Access Memory) that temporarily stores data, a predetermined control program, and the like in advance. It is configured by using a non-volatile storage device and a microcomputer equipped with peripheral circuits thereof and the like.
  • CPU Central Processing Unit
  • RAM Random Access Memory
  • the control unit 2 functions as an inspection control unit 21, a measurement unit 22, an average capacity calculation unit 23, a capacity correction unit 24, a reference value calculation unit 25, and a determination unit 26, for example, by executing the above-mentioned control program.
  • the inspection control unit 21 appropriately moves the inspection unit 3 to bring each probe Pr into contact with each inspection point such as an end e on the substrate A fixed to the substrate fixing device 12.
  • the measuring unit 22 measures the capacitance of the wiring of each substrate A as the measuring capacitance. Specifically, the measuring unit 22 measures the capacitance between the reference wiring B (n, 1) and the planar pattern G (n, 1) as the measurement capacitance of the reference wiring B (n, 1). , The capacitance between the reference wiring B (n, 2) and the planar pattern G (n, 2) is measured as the measured capacitance of the reference wiring B (n, 2), and the reference wiring B (n, 3) is measured. The capacitance between the surface pattern G (n, 3) and the planar pattern G (n, 3) is measured as the measurement capacitance of the reference wiring B (n, 3).
  • the capacitance measured by bringing the probe Pr into contact with the reference wiring B (n, 1) and the planar pattern G (n, 1) includes the capacitance around the reference wiring B (n, 1). It also includes the capacitance generated between the material and the material.
  • the capacitance measured by bringing the probe Pr into contact with the reference wiring B (n, 2) and the planar pattern G (n, 2) includes the material around the reference wiring B (n, 2).
  • the capacitance generated between the two is also included, and the capacitance measured by bringing the probe Pr into contact with the reference wiring B (n, 3) and the planar pattern G (n, 3) includes the reference wiring B.
  • the capacitance generated between the material around (n, 3) is also included.
  • the capacitance is inversely proportional to the distance and proportional to the area. Therefore, if the reference wiring B (n, 1), B (n, 2), B (n, 3) and the wiring around it are separated from each other, the reference wiring B (n, 1) having a large area has a large area. Capacitance between the surface pattern G (n, 1) and the reference wiring B (n, 2), and the capacitance between the reference wiring B (n, 2) and the surface pattern G (n, 2), and the reference wiring B (n, n). , 3) and the planar pattern G (n, 3) dominate.
  • the capacitance measured by bringing a pair of probes Pr into contact with the reference wiring B (n, 1) and the planar pattern G (n, 1) is the capacitance of the reference wiring B (n, 1).
  • the capacitance measured by bringing a pair of probes Pr into contact with the reference wiring B (n, 2) and the planar pattern G (n, 2) can be approximated as the reference wiring B (n, 2).
  • the capacitance of the wiring Pn may be the capacitance between the wiring Pn and all other wirings and patterns, and the wiring Pn and one or more other presets. It may be the capacitance between the wiring or the pattern.
  • the capacitance of the wiring Pn may be the capacitance between the wiring Pn and the carrier substrate 102.
  • the measuring unit 22 may use the capacitance measured between the wiring Pn and the pair of probes Pr in contact with the arbitrarily set wiring or pattern as the measurement capacitance of the wiring Pn.
  • the measuring unit 22 connects the ammeter 33 to the probe Pr that comes into contact with the reference wiring Bn or the wiring Pn to be measured by the scanner unit 31. Further, the measuring unit 22 connects the AC power supply 32 to the probe Pr paired with the probe Pr by the scanner unit 31.
  • the voltage V of the frequency f output from the AC power supply 32 causes a current I to flow through the capacitance of the reference wiring Bn or the wiring Pn to be measured, and the current I is measured by the current meter 33.
  • Capacitance X I / (V ⁇ 2 ⁇ f) ⁇ ⁇ ⁇ (1)
  • the capacitance X can be known if the current I is obtained. Therefore, the measuring unit 22 can measure the capacitance X as the measuring capacitance C.
  • the measuring unit 22 measures the capacitance X using the scanner unit 31, the AC power supply 32, and the ammeter 33, and the measuring unit 22 simply measures the capacitance X, that is, the measuring capacity C. , And so on.
  • the average capacity calculation unit 23 calculates the average value of the measurement capacity C measured from the wirings corresponding to each other as the average capacity Cav.
  • the wiring corresponding to each other is a wiring created as the same wiring in the design for each substrate A.
  • the reference wirings B (1,1), B (2,1), B (3,1), ... B (2,2), B (3,2), ... Are wirings corresponding to each other, and reference wirings B (1,3), B (2,3), B (3,3), ... -Is the wiring corresponding to each other.
  • the capacitance correction unit 24 determines the ratio of the average capacitance Cav to the measured capacitance Ci of the wiring of the target substrate Ai of the target substrate Ai. By multiplying the measurement capacity C of the target wiring to be inspected, the correction capacity Cc, which is the correction value of the measurement capacity C of the target wiring, is calculated.
  • the capacitance correction unit 24 calculates the correction capacitance Cc for the target wiring of each substrate A by sequentially using each substrate A as the target substrate.
  • the reference value calculation unit 25 calculates the average value of the correction capacitance Cc for the target wiring of each substrate A as the determination reference value Clef.
  • the determination unit 26 determines the correction capacity Cc based on the determination reference value Clef.
  • the measurement capacity of the reference wiring B (i, j) is C (B (i, j))
  • the measurement capacity of the wiring P (i, j) is C (P (i, j))
  • the wiring P is described as Cc (P (i, j)).
  • the measuring unit 22 initializes the board number i to 1 (step S1).
  • each probe Pr brings each probe Pr into contact with the first layer L1 of the substrate Ai.
  • each probe Pr is provided with reference wiring B (i, 1) to B (i, 3), wiring P (i, 1) to P (i, 5), and planar pattern G (i, 1). -G (i, 3) and wiring P (i, 1)-P (i, 5) are brought into contact with any wiring or the like paired with each other (step S2).
  • the measuring unit 22 has a measuring capacity C (B (i, 1)), a C (B (i, 2), a C (B (i, 3), and a measuring capacity C (P (i, 1))). , C (P (i, 2)), C (P (i, 3)), C (P (i, 4)), C (P (i, 5)) (step S2: measurement step) ..
  • the measuring unit 22 compares the substrate number i with 25 (step S3), and if the substrate number i is not 25 (NO in step S3), 1 is added to the substrate number i to measure the new substrate A. Addition (step S4), and steps S2 and S3 are repeated again. On the other hand, if the substrate number i is 25 (YES in step S3), the measurement capacitance C has been measured for all the wirings, so the process proceeds to step S5.
  • the average capacity calculation unit 23 measures the average value of the measurement capacities C (B (1,1)) to C (B (25,1)) as the average capacity Cav (L1) of the first layer L1.
  • the average value of the capacities C (B (1,2)) to C (B (25,2)) is defined as the average capacity Cav (L2) of the second layer L2, and the measurement capacities C (B (1,3)) to Let the average value of C (B (25,3)) be the average capacity Cav (L3) of the third layer L3 (step S5: average capacity calculation step).
  • the measurement capacities C (B (1,1)) to C (B (25,1)) are reference wirings B having wiring numbers 1 corresponding to each other, and are from the reference wiring B formed in the first layer L1.
  • the measurement capacities C (B (1,2)) to C (B (25,2)) are reference wirings B having wiring numbers 2 corresponding to each other, and are from the reference wiring B formed in the second layer L2.
  • the measurement capacities C (B (1,3)) to C (B (25,3)) are reference wirings B having wiring numbers 3 corresponding to each other, and are from the reference wiring B formed in the third layer L3.
  • the average capacities Cav (L1), Cav (L2), and Cav (L3) may be calculated by averaging the measurement capacities C of the plurality of reference wirings B for each substrate for each of the plurality of substrates and for each layer.
  • the capacitance correction unit 24 initializes the board number i to 1 (step S6).
  • the capacitance correction unit 24 calculates the correction capacitance Cc (P (i, 1)) of the wiring P (i, 1) of the first layer L1 based on the following equation (1) (step S7: Capacity correction process).
  • Correction capacity Cc (P (i, 1)) C (P (i, 1)) x Cav (L1) / C (B (i, 1)) ... (1)
  • step S7 the board Ai corresponds to the target board
  • the wiring P (i, 1) corresponds to the target wiring of the first layer L1
  • the reference wiring B (i, 1) corresponds to the wiring of the target board Ai.
  • Cav (L1) / C (B (i, 1)) corresponds to the ratio of the average capacity Cav (L1) to the measured capacity C (B (i, 1)) of the wiring of the target substrate Ai.
  • the capacitance correction unit 24 uses the correction capacitances Cc (P (i, 2)) and Cc (P (i, 3)) of the wirings P (i, 2) and P (i, 3) of the second layer L2. Is calculated based on the following equations (2) and (3) (step S8: capacity correction step).
  • Correction capacity Cc (P (i, 2)) C (P (i, 2)) ⁇ Cav (L2) / C (B (i, 2)) ⁇ ⁇ ⁇ (2)
  • Correction capacity Cc (P (i, 3)) C (P (i, 3)) x Cav (L2) / C (B (i, 2)) ... (3)
  • step S8 the board Ai corresponds to the target board
  • the wirings P (i, 2) and P (i, 3) correspond to the target wiring of the second layer L2
  • the reference wiring B (i, 2) corresponds to the target board.
  • Corresponds to the wiring of Ai, and Cav (L2) / C (B (i, 2)) corresponds to the ratio of the average capacitance Cav (L2) to the measured capacitance C (B (i, 2)) of the wiring of the target substrate Ai. do.
  • the capacitance correction unit 24 uses the correction capacitances Cc (P (i, 4)) and Cc (P (i, 5)) of the wirings P (i, 4) and P (i, 5) of the third layer L3. Is calculated based on the following equations (4) and (5) (step S9: capacity correction step).
  • Correction capacity Cc (P (i, 4)) C (P (i, 4)) x Cav (L3) / C (B (i, 3)) ...
  • Correction capacity Cc (P (i, 5)) C (P (i, 5)) x Cav (L3) / C (B (i, 3)) ... (5)
  • step S9 the board Ai corresponds to the target board
  • the wirings P (i, 4) and P (i, 5) correspond to the target wiring of the third layer L3
  • the reference wiring B (i, 3) corresponds to the target board.
  • Corresponds to the wiring of Ai, and Cav (L3) / C (B (i, 3)) corresponds to the ratio of the average capacity Cav (L3) to the measured capacity C (B (i, 3)) of the wiring of the target substrate Ai. do.
  • the capacitance correction unit 24 compares the substrate number i with 25 (step S10), and if the substrate number i is not 25 (NO in step S10), the capacitance correction unit 24 sets the substrate number i to 1 in order to correct the new substrate A. Is added (step S11), and steps S7 to 10 are repeated again. On the other hand, if the substrate number i is 25 (YES in step S10), it means that all the measurement capacities C have been corrected, so the process proceeds to step S21.
  • the measurement capacity C varies from substrate A to substrate A.
  • the measurement capacity C decreases when the wiring P is broken, and increases when the wiring P is short-circuited with other wiring or the like. If there is no variation in the substrate, it is possible to determine whether the wiring P is broken or short-circuited by increasing or decreasing the measurement capacity C.
  • the measurement capacity C (P (2,2)) when the wiring P (2,2) is broken is a solid line
  • the wiring P ( The measured capacity C (P (2,2)) when 2 and 2) are normal is shown by a broken line.
  • the measurement capacity C (P (2, 2)) when the wiring P (2, 2) is broken is the measurement capacity C (P (P (2)) of the normal wiring P (1, 2). It is smaller than 1,2)) and larger than the measurement capacity C (P (25,2)) of the normal wiring P (25,2). Therefore, it is difficult to determine that the wiring P (2, 2) is defective based on the measurement capacity C (P (2, 2)).
  • the correction capacitances Cc (P (1,1)) to Cc (P (25,5)) corrected in steps S7 to S9 have the same wiring number if the wiring P is normal. In the wirings P corresponding to each other, the influence of the variation of the substrate is reduced, and the capacitance becomes substantially the same. As described above, according to steps S1 to S11, it becomes easy to correct the variation in the capacitance X due to the manufacturing variation in the substrate A.
  • step S2 the measurement capacities C (B (1,1)) to C (B (25,3)) are obtained from the reference wirings B (n, 1) to B (n, 3) provided in each layer. Be measured.
  • step S5 the average capacities Cav (L1), Cav (L2), and Cav (L3) are calculated for each layer.
  • steps S7 to S9 the measurement capacities C (P (1,1)) to C (P (25,5)) are corrected for each layer, and the correction capacities Cc (P (1,1)) to Cc (P (P (P)). 25,5)) is calculated.
  • correction capacities Cc (P (1,1)) to Cc (P (25,5)) can be calculated so as to reduce the difference in the variation for each layer.
  • the reference value calculation unit 25 uses the average value of the correction capacitances Cc (P (1,1)) to C (P (25,1)) as the determination reference for the wiring P (n, 1).
  • the value Clef (1) is set, and the average value of the correction capacities Cc (P (1,2)) to Cc (P (25,2)) is set as the judgment reference value Clef (2) of the wiring P (n, 2).
  • the average value of the correction capacitances Cc (P (1,3)) to Cc (P (25,3)) is set as the judgment reference value Clef (3) of the wiring P (n, 3), and the correction capacitance Cc (P (1)) is used.
  • the determination unit 26 initializes the board number i and the wiring number j to 1 (step S22).
  • the determination unit 26 determines the wiring P. If (i, j) is determined to be good (step S24) and the determination ratio Ref is exceeded (NO in step S23), the wiring P (i, j) is determined to be defective (step S25).
  • the determination unit 26 determines that the wiring P is defective. can do.
  • the determination ratio Ref may be appropriately set according to the required inspection accuracy.
  • the determination unit 26 compares the wiring number j with 5 (step S26), and if the wiring number j is not 5 (NO in step S26), the wiring number j is used to determine another wiring P on the board Ai. 1 is added to (step S27), and steps S23 to S26 are repeated again.
  • step S26 if the wiring number j is 5 (YES in step S26), the board number i is compared with 25 (step S28), and if the board number i is not 25 (NO in step S28), the new board A is In order to determine, 1 is added to the board number i, the wiring number j is initialized to 1 (step S29), and steps S23 to 28 are repeated again.
  • step S28 if the board number i is 25 (YES in step S28), it means that the quality of all wiring P has been determined, so the process proceeds to step S30.
  • step S30 the determination unit 26 confirms whether or not there is a wiring P determined to be defective in step S25 (step S30). If there is no wiring P determined to be defective (NO in step S30), the process ends.
  • step S30 if there is even one wiring P determined to be defective (YES in step S30), the process proceeds to step S41.
  • step S30 If there is even one wiring P determined to be defective (YES in step S30), the average value calculated in step S21 including the correction capacity Cc of the defective wiring P is used as the determination reference value Clef. Therefore, the quality judgment accuracy of the wiring P based on the judgment reference value Clef is lowered.
  • step S41 the reference value calculation unit 25 corrects the remainder by removing the correction capacity of the wiring determined to be defective from the correction capacities Cc (P (1,1)) to C (P (25,1)). Let the average value of the capacitance be the new judgment reference value Clef (1) of the wiring P (n, 1).
  • the reference value calculation unit 25 averages the remaining correction capacities excluding the correction capacities of the wiring determined to be defective from the correction capacities Cc (P (1,2)) to C (P (25,2)). Let the value be the new determination reference value Clef (2) of the wiring P (n, 2) (step S41).
  • the reference value calculation unit 25 calculates the average value of the residual correction capacity obtained by excluding the correction capacity of the wiring determined to be defective from the correction capacities Cc (P (1,3)) to C (P (25,3)). Set the new determination reference value Clef (3) of the wiring P (n, 3) (step S41).
  • the reference value calculation unit 25 calculates the average value of the residual correction capacity obtained by excluding the correction capacity of the wiring determined to be defective from the correction capacities Cc (P (1,4)) to C (P (25,4)).
  • the new determination reference value Clef (4) of the wiring P (n, 4) is set (step S41).
  • the reference value calculation unit 25 calculates the average value of the residual correction capacity obtained by excluding the correction capacity of the wiring determined to be defective from the correction capacities Cc (P (1,5)) to C (P (25,5)). Set the new determination reference value Clef (5) of the wiring P (n, 5) (step S41).
  • step S41 when there is a defective wiring, a new determination reference value Clef can be obtained based on the residual correction capacitance excluding the correction capacitance of the defective wiring. Therefore, the accuracy of the determination reference value Clef can be determined. Can be improved.
  • the determination unit 26 initializes the board number i and the wiring number j to 1 (step S42).
  • step S43 the determination unit 26 confirms in step S25 whether or not the wiring P (i, j) is defective (step S43). If the wiring P (i, j) is not defective (NO in step S43), the determination unit 26 shifts the process to step S51. If the wiring P (i, j) is defective (YES in step S43), the determination unit 26 shifts the process to step S54.
  • step S51 the determination unit 26 determines that the absolute value of ⁇ Cc (P (i, j))-Clef (j) ⁇ / Clef (j) is equal to or less than the determination ratio Ref based on the new determination reference value Clef. If there is (YES in step S51), the wiring P (i, j) is determined to be good (step S52), and if the determination ratio Ref is exceeded (NO in step S51), the wiring P (i, j) is defective. (Step S53).
  • the determination unit 26 compares the wiring number j with 5 (step S54), and if the wiring number j is not 5 (NO in step S54), the determination unit 26 determines the other wiring P on the board Ai. 1 is added to (step S55), and steps S51 to 54 are repeated again.
  • step S54 if the wiring number j is 5 (YES in step S54), the board number i is compared with 25 (step S56), and if the board number i is not 25 (NO in step S56), the new board A is In order to determine, 1 is added to the board number i, the wiring number j is initialized to 1 (step S57), and steps S51 to 56 are repeated again.
  • step S56 if the board number i is 25 (YES in step S56), it means that all the wirings P that were not defective last time have been judged to be good or bad based on the new judgment reference value Clef, so that step S58 Move the process to.
  • step S58 the determination unit 26 confirms whether or not there is a wiring P newly determined to be defective in step S53 (step S58). If there is no wiring P newly determined to be defective (NO in step S58), the process ends.
  • steps S41 to S58 are repeated again.
  • step S28 It is not always necessary to execute steps S30 to S53, and if YES in step S28, the process may be terminated.
  • the reference wiring B is not limited to the example of being provided for each layer of the substrate A.
  • the reference wiring B (n, 2) is provided as the reference wiring, and in steps S7 and S9, Cav (L1) / C (B (i, 1)) and Cav (L3) / C (B (i, 3)) are provided. )) May be used instead of Cav (L2) / C (B (i, 2)).
  • the example is not limited to the case where the reference wiring B is provided separately from the wiring P to be inspected.
  • the reference wiring B may not be provided, and any of the wirings P may be used instead of the reference wiring B.
  • the wirings P (n, 2) and P (n, 4) may be used instead of the reference wirings B (n, 2) and B (n, 3).
  • step S5 the average value of the measurement capacities C (P (1,2)) to C (P (25,2)) is set as the average capacitance Cav (L2) of the second layer L2, and the measurement capacitance C ( The average value of P (1,4)) to C (P (25,4)) can be defined as the average capacity Cav (L3) of the third layer L3.
  • step S8 the measurement capacity C (P (i, 2)) is used instead of the measurement capacity C (B (i, 2)), and in step S9, the measurement capacity C (B (i, 3)) is replaced.
  • the measurement capacity C (P (i, 4)) can be used.
  • the wirings P (n, 2) and P (n, 4) cannot be inspected in steps S23 to S25 and steps S51 to S53, the wirings P (n, 3) and P (n, 5) cannot be inspected. Can be inspected.
  • the wiring P (n, 2), P (n, 4) instead of the reference wiring B (n, 2), B (n, 3), the wiring P (n, 3), P ( n, 5) may be used.
  • the reference wiring B it is not necessary to provide the reference wiring B separately from the wiring P.
  • the wiring P that is routed to form the circuit tends to be routed in a complicated manner, tends to have a complicated shape, and the capacitance X tends to become unstable.
  • the reference wiring B for calculating the average capacitance should be shaped and arranged so that the capacitance is easy to stabilize, regardless of the necessity in the circuit. Is easy.
  • the substrate inspection apparatus and inspection method according to the present invention need only be able to easily correct the variation in capacitance due to the variation in manufacturing of the substrate, and YES in step S10 without executing steps S21 to S58. In the case of, the process may be terminated.
  • step S43 the wiring P once determined to be defective in step S43 is not determined again in steps S51 to S53, the wiring P may be shifted from step S42 to step S51 without executing step S43.
  • the inspection device is an inspection device that inspects a plurality of substrates on which wirings provided as the same wiring in design are formed, and measures the capacitance of the wiring of each of the substrates.
  • a measurement unit that measures as a capacity an average capacity calculation unit that calculates the average value of the measurement capacity measured from the wiring provided as the same wiring in the design as an average capacity, and one of the plurality of substrates.
  • the target board is provided with a capacitance correction unit that calculates a correction capacity which is a correction value of the measurement capacity of the target wiring to be inspected, and the capacitance correction unit is a wiring of the target board.
  • the correction capacity is calculated by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the measurement capacity.
  • the inspection method is an inspection method for inspecting a plurality of substrates on which wirings provided as the same wiring in design are formed, and measures the capacitance of the wiring of each of the substrates.
  • the measurement step of measuring as the capacity the average capacity calculation step of calculating the average value of the measured capacities measured from the wiring provided as the same wiring in the design as the average capacity, and one of the plurality of substrates.
  • the capacity correction step includes a capacity correction step of calculating a correction capacity which is a correction value of the measured capacity of the target wiring to be inspected on the target board, and the capacity correction step is performed on the wiring of the target board.
  • the correction capacity is calculated by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the measurement capacity.
  • the capacitance of the wiring of each board is measured as the measurement capacity, and the average value of the measurement capacities measured from the wirings corresponding to each other provided as the same wiring in the design is calculated as the average capacity.
  • the ratio of the average capacity to the measured capacity of the wiring of the target board, which is one of the plurality of boards, is multiplied by the measured capacity of the target wiring to be inspected on the target board to calculate the correction capacity of the target wiring.
  • the variation in the correction capacitance between the substrates is reduced, so that it becomes easy to correct the variation in the capacitance due to the manufacturing variation of the substrate.
  • the capacitance correction unit calculates the correction capacitance of the target wiring of each target substrate using the plurality of substrates as the target substrates, and the inspection device sets the average value of the correction capacitances as a determination reference value. It is preferable to further include a reference value calculation unit for calculating as, and a determination unit for determining each correction capacity based on the determination reference value.
  • the determination reference value can be automatically calculated based on the correction capacity of the target wiring of each target board, so that each correction capacity can be easily determined.
  • the reference value calculation unit calculates the average value of the residual correction capacity excluding the correction capacity determined to be defective by the determination unit as a new determination reference value, and the determination unit calculates the new determination. It is preferable to determine at least the residual correction capacity based on the reference value.
  • the correction capacity of the defective wiring is excluded from the data that is the source of the judgment reference value, and a new judgment reference value is calculated, so that the judgment accuracy based on the new judgment reference value is improved.
  • the wiring includes a reference wiring that is not an inspection target and is provided as the same wiring in design between the plurality of substrates, and the measuring unit uses the capacitance of the reference wiring as the reference wiring. It is preferable that the measurement is performed as the measurement capacity, and the average capacity calculation unit calculates the average value of the measurement capacities of the reference wiring on each substrate as the average capacity.
  • the average capacity is calculated based on the measured capacity measured from the reference wiring different from the wiring to be inspected.
  • the wiring to be inspected that is routed to form a circuit tends to be routed in a complicated manner, tends to have a complicated shape, and the capacitance tends to be unstable.
  • the reference wiring for calculating the average capacitance should be shaped and arranged so that the capacitance is easy to stabilize, regardless of the necessity in the circuit. Is easy.
  • the substrate is a multilayer substrate and the reference wiring is provided for each layer of the substrate.
  • wiring and reference wiring are formed for each layer, so even within the same substrate, the variation may differ for each layer. Therefore, by providing the reference wiring for each layer of the substrate, it becomes easy to calculate the correction capacitance so as to reduce the difference in the variation for each layer.
  • a probe for contacting the wiring is provided, and the measuring unit measures the capacitance via the probe.
  • the capacitance of the wiring can be measured by bringing the probe into contact with the wiring.

Abstract

Provided is an inspection device and an inspection method that can easily correct variations in electrostatic capacitance due to variations in manufacture of substrates. A substrate inspection device 1 for inspecting a plurality of substrates A each having a wiring P and a reference wiring B formed thereon comprises: a measurement unit 22 that measures electrostatic capacitance of the wiring P and the reference wiring B of each substrate A as measurement capacitances C; an average capacitance calculation unit 23 that calculates, as an average capacitance Cav, an average value of the measurement capacitances C obtained from the reference wirings B provided as the same wiring in terms of design; and a capacitance correction unit 24 that calculates a corrected capacitance Cc, which is a corrected value of the measurement capacitance C of a target wiring P being inspected on a target substrate Ai, which is one of the plurality of substrates A, wherein the capacitance correction unit 24 calculates the corrected capacitance Cc by multiplying the ratio of the average capacitance Cav to the measurement capacitance C of the wiring of the target substrate Ai by the measurement capacitance C of the target wiring P.

Description

検査装置、及び検査方法Inspection equipment and inspection method
 本発明は、基板を検査する検査装置、及び検査方法に関する。 The present invention relates to an inspection device for inspecting a substrate and an inspection method.
 従来より、測定対象の回路基板における複数の導体パターンと基準電極との間の対電極間静電容量を測定し、その測定した対電極間静電容量に基づいて回路基板を検査する回路基板検査方法が知られている(例えば、特許文献1参照。)。 Conventionally, a circuit board inspection that measures the capacitance between a plurality of conductor patterns and a reference electrode in a circuit board to be measured and inspects the circuit board based on the measured capacitance between the counter electrodes. A method is known (see, for example, Patent Document 1).
特開2003-14807号公報Japanese Unexamined Patent Publication No. 2003-14807
 ところで、配線の静電容量は配線の対向面積等によっても変化する。そのため、基板の製造ばらつきによって、配線の幅や絶縁層の厚み等がばらつくと、配線の静電容量もまた、ばらつくことになる。 By the way, the capacitance of the wiring also changes depending on the facing area of the wiring. Therefore, if the width of the wiring, the thickness of the insulating layer, and the like vary due to variations in the manufacturing of the substrate, the capacitance of the wiring also varies.
 本発明の目的は、基板の製造ばらつきによる静電容量のばらつきを補正することが容易な検査装置、及び検査方法を提供することである。 An object of the present invention is to provide an inspection device and an inspection method that can easily correct variations in capacitance due to variations in substrate manufacturing.
 本発明の一例に係る検査装置は、設計上同一の配線として設けられた配線がそれぞれ形成された複数の基板を検査する検査装置であって、前記各基板の配線の静電容量を測定容量として測定する測定部と、前記設計上同一の配線として設けられた配線から測定された測定容量の平均値を、平均容量として算出する平均容量算出部と、前記複数の基板のうち一つを目的基板とした場合に、前記目的基板の検査対象となる目的配線の前記測定容量の補正値である補正容量を算出する容量補正部とを備え、前記容量補正部は、前記目的基板の配線の前記測定容量に対する前記平均容量の比率を、前記目的配線の前記測定容量に乗じることによって、前記補正容量を算出する。 The inspection device according to an example of the present invention is an inspection device that inspects a plurality of substrates on which wirings provided as the same wiring in design are formed, and the capacitance of the wiring of each substrate is used as a measurement capacitance. The measurement unit to be measured, the average capacity calculation unit that calculates the average value of the measurement capacity measured from the wiring provided as the same wiring in the design as the average capacity, and one of the plurality of substrates as the target substrate. In the case of The correction capacity is calculated by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the capacity.
 また、本発明の一例に係る検査方法は、設計上同一の配線として設けられた配線がそれぞれ形成された複数の基板を検査する検査方法であって、前記各基板の配線の静電容量を測定容量として測定する測定工程と、前記設計上同一の配線として設けられた配線から測定された測定容量の平均値を、平均容量として算出する平均容量算出工程と、前記複数の基板のうち一つを目的基板とした場合に、前記目的基板の検査対象となる目的配線の前記測定容量の補正値である補正容量を算出する容量補正工程とを含み、前記容量補正工程は、前記目的基板の配線の前記測定容量に対する前記平均容量の比率を、前記目的配線の前記測定容量に乗じることによって、前記補正容量を算出する。 Further, the inspection method according to an example of the present invention is an inspection method for inspecting a plurality of substrates on which wirings provided as the same wiring in design are formed, and measures the capacitance of the wiring of each of the substrates. The measurement step of measuring as the capacity, the average capacity calculation step of calculating the average value of the measured capacities measured from the wiring provided as the same wiring in the design as the average capacity, and one of the plurality of substrates. When the target board is used, the capacity correction step includes a capacity correction step of calculating a correction capacity which is a correction value of the measured capacity of the target wiring to be inspected on the target board, and the capacity correction step is performed on the wiring of the target board. The correction capacity is calculated by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the measurement capacity.
 このような構成の検査装置、及び検査方法は、基板の製造ばらつきによる静電容量のばらつきを補正することが容易である。 The inspection device and inspection method having such a configuration can easily correct the variation in capacitance due to the variation in manufacturing of the substrate.
本発明の一実施形態に係る検査方法を用いる基板検査装置の構成を概略的に示す概念図である。It is a conceptual diagram which shows schematic structure of the substrate inspection apparatus which uses the inspection method which concerns on one Embodiment of this invention. パネル100の一例を示す説明図である。It is explanatory drawing which shows an example of a panel 100. 基板Aの一例を示す上面図である。It is a top view which shows an example of the substrate A. 基板Anの一例、及び検査部3の電気的構成の一例を示す説明図である。It is explanatory drawing which shows an example of the substrate An and the example of the electric structure of the inspection part 3. ステップS1~S11を示すフローチャートである。It is a flowchart which shows steps S1 to S11. ステップS21~S30を示すフローチャートである。It is a flowchart which shows steps S21 to S30. ステップS41~S43を示すフローチャートである。It is a flowchart which shows the step S41-S43. ステップS51~S58を示すフローチャートである。It is a flowchart which shows the step S51-S58. 測定容量C(P(1,1))~C(P(25,5))の一例を示すグラフである。It is a graph which shows an example of the measuring capacity C (P (1,1)) to C (P (25,5)). 補正容量Cc(P(1,1))~Cc(P(25,5))の一例を示すグラフである。It is a graph which shows an example of the correction capacitance Cc (P (1,1)) to Cc (P (25,5)).
 以下、本発明に係る実施形態を図面に基づいて説明する。なお、各図において同一の符号を付した構成は、同一の構成であることを示し、その説明を省略する。図1に示す基板検査装置1は、パネル100に形成された基板A1~A25の配線を検査するための装置である。基板検査装置1は、検査装置の一例に相当する。 Hereinafter, embodiments according to the present invention will be described with reference to the drawings. It should be noted that the configurations with the same reference numerals in the respective figures indicate that they are the same configurations, and the description thereof will be omitted. The substrate inspection device 1 shown in FIG. 1 is an apparatus for inspecting the wiring of the substrates A1 to A25 formed on the panel 100. The substrate inspection device 1 corresponds to an example of the inspection device.
 図1に示す基板検査装置1は、筐体11を有している。筐体11の内部空間には、基板固定装置12と、検査部3と、制御部2と、検査部3を筐体11内で適宜移動するための検査部移動機構15とが主に設けられている。基板固定装置12は、検査対象となるパネル100を所定の位置に固定するように構成されている。 The substrate inspection device 1 shown in FIG. 1 has a housing 11. The board fixing device 12, the inspection unit 3, the control unit 2, and the inspection unit moving mechanism 15 for appropriately moving the inspection unit 3 in the housing 11 are mainly provided in the internal space of the housing 11. ing. The board fixing device 12 is configured to fix the panel 100 to be inspected at a predetermined position.
 検査部3は、基板固定装置12に固定されたパネル100の上方に位置する。検査部3には、パネル100に形成された基板Aを検査するための検査治具4が取り付けられている。検査治具4には、複数のプローブPrが取り付けられている。 The inspection unit 3 is located above the panel 100 fixed to the substrate fixing device 12. An inspection jig 4 for inspecting the substrate A formed on the panel 100 is attached to the inspection unit 3. A plurality of probes Pr are attached to the inspection jig 4.
 図2に示すパネル100は、基板A1~A25を含んでいる。以下、基板A1~A25を総称して基板Aと称し、個別の基板を示すときは、符号Aに基板番号nを付して、基板Anのように称する。パネル100は、例えばPLP(Panel Level Packaging)用のパネルである。 The panel 100 shown in FIG. 2 includes substrates A1 to A25. Hereinafter, the substrates A1 to A25 are collectively referred to as a substrate A, and when individual substrates are indicated, a substrate number n is added to the reference numeral A and the substrate is referred to as a substrate An. The panel 100 is, for example, a panel for PLP (Panel Level Packaging).
 基板Aは、例えば半導体パッケージ用のパッケージ基板やフィルムキャリア、プリント配線基板、ガラスエポキシ基板、フレキシブル基板、セラミック多層配線基板、液晶ディスプレイやEL(Electro-Luminescence)ディスプレイ等のディスプレイ用の電極板、タッチパネル用等の透明導電板、半導体ウェハや半導体チップやCSP(Chip size package)等の半導体基板等々種々の基板であってもよい。基板Aには、配線パターン、パッド、ランド、半田バンプ、ビア、及び端子等の検査点が形成されている。 The substrate A is, for example, a package substrate or film carrier for a semiconductor package, a printed wiring board, a glass epoxy substrate, a flexible substrate, a ceramic multilayer wiring board, an electrode plate for a display such as a liquid crystal display or an EL (Electro-Luminescence) display, and a touch panel. It may be various substrates such as a transparent conductive plate for use, a semiconductor wafer, a semiconductor chip, a semiconductor substrate such as a CSP (Chip size package), and the like. Inspection points such as wiring patterns, pads, lands, solder bumps, vias, and terminals are formed on the substrate A.
 基板A1~A25には、設計上、同じ配線パターンが形成されている。パネル100に含まれる基板Aの個数は25個に限らない。基板Aは、例えば、半導体チップのパッケージの一種であるファンアウトパッケージをRDL(Redistribution Layer)ファースト工程で製造する際の、キャリアにRDLが形成された後、チップダイがRDLに実装される前の基板である。 The same wiring pattern is formed on the boards A1 to A25 by design. The number of substrates A included in the panel 100 is not limited to 25. The substrate A is, for example, a substrate after the RDL is formed on the carrier and before the chip die is mounted on the RDL when a fan-out package, which is a kind of semiconductor chip package, is manufactured in the RDL (Redistribution Layer) first process. Is.
 図3、図4を参照して、基板Anは、例えば第一層L1、第二層L2、及び第三層L3の複数の配線層を備えた多層基板となっている。基板Anには、配線番号1~5の配線P(n,1)~P(n,5)と、配線番号1~3の基準配線B(n,1)~B(n,3)とが形成されている。以下、基板番号iの基板Aiにおける配線番号jの配線を配線P(i,j)と表記し、基板番号iの基板Aiにおける配線番号jの基準配線を基準配線B(i,j)と表記する。 With reference to FIGS. 3 and 4, the substrate An is, for example, a multilayer substrate including a plurality of wiring layers of the first layer L1, the second layer L2, and the third layer L3. The board An has wirings P (n, 1) to P (n, 5) having wiring numbers 1 to 5 and reference wirings B (n, 1) to B (n, 3) having wiring numbers 1 to 3. It is formed. Hereinafter, the wiring of the wiring number j on the substrate Ai of the substrate number i is referred to as wiring P (i, j), and the reference wiring of the wiring number j on the substrate Ai of the substrate number i is referred to as reference wiring B (i, j). do.
 配線P(n,1)~P(n,5)、及び基準配線B(n,1)~B(n,3)は、配線の一例に相当している。以下、配線P(n,1)~P(n,5)を総称して配線Pnと称し、配線P(1,1)~P(25,5)を総称して配線Pと称し、基準配線B(n,1)~B(n,3)を総称して基準配線Bnと称し、基準配線B(1,1)~B(25,3)を総称して基準配線Bと称する。 Wiring P (n, 1) to P (n, 5) and reference wiring B (n, 1) to B (n, 3) correspond to an example of wiring. Hereinafter, the wirings P (n, 1) to P (n, 5) are collectively referred to as wiring Pn, and the wirings P (1,1) to P (25, 5) are collectively referred to as wiring P, which is a reference wiring. B (n, 1) to B (n, 3) are collectively referred to as reference wiring Bn, and reference wiring B (1,1) to B (25,3) are collectively referred to as reference wiring B.
 配線P、及び基準配線Bは、それぞれ端部e,gと、端部eと端部gとの間を結ぶ本体fとを備えている。端部e,gは、例えばビアやパッド等である。本体fは、帯状に延び、各配線の主要部分を構成している。 The wiring P and the reference wiring B each include an end portion e and g, and a main body f connecting the end portion e and the end portion g, respectively. The ends e and g are, for example, vias and pads. The main body f extends in a strip shape and constitutes a main part of each wiring.
 配線P及び基準配線Bの端部eは、第一層L1に形成されている。配線P及び基準配線Bの端部gは、第三層L3に形成されている。配線P(n,1)、及び基準配線B(n,1)の本体fは、第一層L1に形成されている。配線P(n,2),P(n,3)、及び基準配線B(n,2)の本体fは、第二層L2に形成されている。配線P(n,4),P(n,5)、及び基準配線B(n,3)の本体fは、第三層L3に形成されている。 The end portion e of the wiring P and the reference wiring B is formed in the first layer L1. The end portion g of the wiring P and the reference wiring B is formed in the third layer L3. The main body f of the wiring P (n, 1) and the reference wiring B (n, 1) is formed in the first layer L1. The main body f of the wiring P (n, 2), P (n, 3), and the reference wiring B (n, 2) is formed in the second layer L2. The main body f of the wiring P (n, 4), P (n, 5), and the reference wiring B (n, 3) is formed in the third layer L3.
 図3では、第一層L1に形成されている部分を実線で、第二層L2に形成されている部分を破線で、第三層L3に形成されている部分を一点鎖線で示している。 In FIG. 3, the portion formed in the first layer L1 is indicated by a solid line, the portion formed in the second layer L2 is indicated by a broken line, and the portion formed in the third layer L3 is indicated by a alternate long and short dash line.
 図4に示すように、基板Anの第二層L2には、基準配線B(n,1)と対向配置されて面状に拡がるように形成された面状パターンG(n,1)と、基準配線B(n,3)と対向配置されて面状に拡がるように形成された面状パターンG(n,3)とが形成されている。基板Anの第一層L1には、基準配線B(n,2)と対向配置されて面状に拡がるように形成された面状パターンG(n,2)が形成されている。 As shown in FIG. 4, the second layer L2 of the substrate An has a planar pattern G (n, 1) formed so as to face the reference wiring B (n, 1) and spread in a planar manner. A planar pattern G (n, 3) is formed so as to be arranged so as to face the reference wiring B (n, 3) and spread in a planar manner. A planar pattern G (n, 2) is formed on the first layer L1 of the substrate An so as to be arranged to face the reference wiring B (n, 2) and spread in a planar manner.
 面状パターンG(n,1),G(n,3)には、第一層L1に露出するビアが接続されている。このビアにプローブPrを接触させることによって、プローブPrを面状パターンG(n,1),G(n,3)に導通接続可能とされている。実際には、ビアに接続された第一層L1がビアの上に必ず配置されるため、これにプローブPrが接触することで導通接続が可能になる。第一層L1自身の容量はこれを小さく形成することでその影響を極小にすることができる。 Vias exposed on the first layer L1 are connected to the planar patterns G (n, 1) and G (n, 3). By bringing the probe Pr into contact with this via, the probe Pr can be conductively connected to the planar patterns G (n, 1) and G (n, 3). In reality, since the first layer L1 connected to the via is always arranged on the via, the probe Pr comes into contact with the via to enable a conductive connection. The influence of the capacity of the first layer L1 itself can be minimized by forming it small.
 なお、面状パターンG(n,1),G(n,2),G(n,3)は、基準配線B(n,1),B(n,2),B(n,3)とそれぞれ対向配置されていればよく、配置されている層は図4に示す例に限らない。 The planar patterns G (n, 1), G (n, 2), and G (n, 3) are referred to as reference wirings B (n, 1), B (n, 2), and B (n, 3). It suffices that they are arranged so as to face each other, and the arranged layers are not limited to the example shown in FIG.
 パネル100は、キャリア基板102と剥離層103と基板Aとが、この順に積層されて構成されている。各配線の端部eは第一層L1に形成され、各配線の端部gは第三層L3に形成されている。しかしながら、キャリア基板102に基板Aが形成された後、チップダイが基板Aに実装される前のパネル100は、基板Aの一方の面(第三層L3)にキャリアが取り付けられているので、基板Aの両面にプローブを接触させて配線の導通を検査することができない。 The panel 100 is composed of a carrier substrate 102, a release layer 103, and a substrate A laminated in this order. The end portion e of each wiring is formed in the first layer L1, and the end portion g of each wiring is formed in the third layer L3. However, in the panel 100 after the substrate A is formed on the carrier substrate 102 and before the chip die is mounted on the substrate A, the carrier is attached to one surface (third layer L3) of the substrate A, so that the substrate It is not possible to inspect the continuity of the wiring by bringing the probe into contact with both sides of A.
 そこで、基板検査装置1は、基板Aの露出している側の面(第一層L1)の、端部eや面状パターンG(n,2)、又は面状パターンG(n,1),G(n,3)に連なるビアにプローブPrを接触させて、配線の静電容量を測定することによって、配線の検査を行う。実際には、ビアに接続された第一層L1がビアの上に必ず配置されるため、これにプローブPrが接触することで導通接続が可能になる。第一層L1自身の容量はこれを小さく形成することでその影響を極小にすることができる。 Therefore, the substrate inspection device 1 has an end e, a planar pattern G (n, 2), or a planar pattern G (n, 1) on the exposed side surface (first layer L1) of the substrate A. , G (n, 3) is brought into contact with the probe Pr, and the capacitance of the wiring is measured to inspect the wiring. In reality, since the first layer L1 connected to the via is always arranged on the via, the probe Pr comes into contact with the via to enable a conductive connection. The influence of the capacity of the first layer L1 itself can be minimized by forming it small.
 なお、パネル100は、キャリアに基板Aが形成された後、チップダイが基板Aに実装される前の基板に限らない。 The panel 100 is not limited to the substrate after the substrate A is formed on the carrier and before the chip die is mounted on the substrate A.
 図4を参照して、検査部3は、複数のプローブPrと、スキャナ部31と、交流電源32と、複数の電流計33とを備えている。スキャナ部31には、各プローブPrと、交流電源32の一端と、各電流計33の一端と、回路グラウンドとが接続されている。交流電源32の他端と、各電流計33の他端とは、回路グラウンドに接続されている。 With reference to FIG. 4, the inspection unit 3 includes a plurality of probe Prs, a scanner unit 31, an AC power supply 32, and a plurality of ammeters 33. Each probe Pr, one end of the AC power supply 32, one end of each ammeter 33, and the circuit ground are connected to the scanner unit 31. The other end of the AC power supply 32 and the other end of each ammeter 33 are connected to the circuit ground.
 スキャナ部31は、例えばトランジスタやリレースイッチ等のスイッチング素子を用いて構成された切り替え回路である。スキャナ部31は、制御部2からの制御信号に応じて、交流電源32と各電流計33とを、任意のプローブPrに接続する。 The scanner unit 31 is a switching circuit configured by using a switching element such as a transistor or a relay switch. The scanner unit 31 connects the AC power supply 32 and each ammeter 33 to an arbitrary probe Pr in response to the control signal from the control unit 2.
 交流電源32は、予め設定された周波数fの交流の電圧Vを、スキャナ部31を介してプローブPrへ出力する交流電源回路である。電流計33は、例えばシャント抵抗、ホール素子、アナログデジタルコンバータ等を用いて構成された交流電流計である。電流計33は、スキャナ部31を介して接続されたプローブPrから回路グラウンドへ流れる電流Iを測定し、電流Iを示す信号を制御部2へ送信する。電圧V及び電流Iは、実効値であってもよく、ピーク値であってもよい。 The AC power supply 32 is an AC power supply circuit that outputs an AC voltage V having a preset frequency f to the probe Pr via the scanner unit 31. The ammeter 33 is an AC ammeter configured by using, for example, a shunt resistor, a Hall element, an analog-digital converter, or the like. The ammeter 33 measures the current I flowing from the probe Pr connected via the scanner unit 31 to the circuit ground, and transmits a signal indicating the current I to the control unit 2. The voltage V and the current I may be effective values or peak values.
 図1を参照して、制御部2は、例えば、所定の論理演算を実行するCPU(Central Processing Unit)、データを一時的に記憶するRAM(Random Access Memory)、所定の制御プログラム等を予め記憶する不揮発性の記憶装置、及びこれらの周辺回路等を備えたマイクロコンピュータを用いて構成されている。 With reference to FIG. 1, the control unit 2 stores, for example, a CPU (Central Processing Unit) that executes a predetermined logical operation, a RAM (Random Access Memory) that temporarily stores data, a predetermined control program, and the like in advance. It is configured by using a non-volatile storage device and a microcomputer equipped with peripheral circuits thereof and the like.
 制御部2は、例えば上述の制御プログラムを実行することによって、検査制御部21、測定部22、平均容量算出部23、容量補正部24、基準値算出部25、及び判定部26として機能する。 The control unit 2 functions as an inspection control unit 21, a measurement unit 22, an average capacity calculation unit 23, a capacity correction unit 24, a reference value calculation unit 25, and a determination unit 26, for example, by executing the above-mentioned control program.
 検査制御部21は、検査部3を適宜移動させ、基板固定装置12に固定された基板Aにおける端部e等の各検査点に各プローブPrを接触させる。 The inspection control unit 21 appropriately moves the inspection unit 3 to bring each probe Pr into contact with each inspection point such as an end e on the substrate A fixed to the substrate fixing device 12.
 測定部22は、各基板Aの配線の静電容量を測定容量として測定する。具体的には、測定部22は、基準配線B(n,1)と面状パターンG(n,1)との間の静電容量を基準配線B(n,1)の測定容量として測定し、基準配線B(n,2)と面状パターンG(n,2)との間の静電容量を基準配線B(n,2)の測定容量として測定し、基準配線B(n,3)と面状パターンG(n,3)との間の静電容量を基準配線B(n,3)の測定容量として測定する。 The measuring unit 22 measures the capacitance of the wiring of each substrate A as the measuring capacitance. Specifically, the measuring unit 22 measures the capacitance between the reference wiring B (n, 1) and the planar pattern G (n, 1) as the measurement capacitance of the reference wiring B (n, 1). , The capacitance between the reference wiring B (n, 2) and the planar pattern G (n, 2) is measured as the measured capacitance of the reference wiring B (n, 2), and the reference wiring B (n, 3) is measured. The capacitance between the surface pattern G (n, 3) and the planar pattern G (n, 3) is measured as the measurement capacitance of the reference wiring B (n, 3).
 厳密には、基準配線B(n,1)と面状パターンG(n,1)とにプローブPrを接触させて測定された静電容量には、基準配線B(n,1)の周囲の材料との間に生じる静電容量も含まれる。同様に、基準配線B(n,2)と面状パターンG(n,2)とにプローブPrを接触させて測定された静電容量には、基準配線B(n,2)の周囲の材料との間に生じる静電容量も含まれ、基準配線B(n,3)と面状パターンG(n,3)とにプローブPrを接触させて測定された静電容量には、基準配線B(n,3)の周囲の材料との間に生じる静電容量も含まれる。 Strictly speaking, the capacitance measured by bringing the probe Pr into contact with the reference wiring B (n, 1) and the planar pattern G (n, 1) includes the capacitance around the reference wiring B (n, 1). It also includes the capacitance generated between the material and the material. Similarly, the capacitance measured by bringing the probe Pr into contact with the reference wiring B (n, 2) and the planar pattern G (n, 2) includes the material around the reference wiring B (n, 2). The capacitance generated between the two is also included, and the capacitance measured by bringing the probe Pr into contact with the reference wiring B (n, 3) and the planar pattern G (n, 3) includes the reference wiring B. The capacitance generated between the material around (n, 3) is also included.
 しかしながら、静電容量は、距離に反比例し、面積に比例する。従って、基準配線B(n,1),B(n,2),B(n,3)とその周囲の配線等との距離が離れていれば、面積が大きい基準配線B(n,1)と面状パターンG(n,1)との間の静電容量、基準配線B(n,2)と面状パターンG(n,2)との間の静電容量、及び基準配線B(n,3)と面状パターンG(n,3)との間の静電容量が支配的となる。 However, the capacitance is inversely proportional to the distance and proportional to the area. Therefore, if the reference wiring B (n, 1), B (n, 2), B (n, 3) and the wiring around it are separated from each other, the reference wiring B (n, 1) having a large area has a large area. Capacitance between the surface pattern G (n, 1) and the reference wiring B (n, 2), and the capacitance between the reference wiring B (n, 2) and the surface pattern G (n, 2), and the reference wiring B (n, n). , 3) and the planar pattern G (n, 3) dominate.
 従って、基準配線B(n,1)と面状パターンG(n,1)とに一対のプローブPrを接触させて測定された静電容量を、基準配線B(n,1)の静電容量として近似することができ、基準配線B(n,2)と面状パターンG(n,2)とに一対のプローブPrを接触させて測定された静電容量を、基準配線B(n,2)の静電容量として近似することができ、基準配線B(n,3)と面状パターンG(n,3)とに一対のプローブPrを接触させて測定された静電容量を、基準配線B(n,3)の静電容量として近似することができる。 Therefore, the capacitance measured by bringing a pair of probes Pr into contact with the reference wiring B (n, 1) and the planar pattern G (n, 1) is the capacitance of the reference wiring B (n, 1). The capacitance measured by bringing a pair of probes Pr into contact with the reference wiring B (n, 2) and the planar pattern G (n, 2) can be approximated as the reference wiring B (n, 2). ) Can be approximated, and the capacitance measured by bringing a pair of probes Pr into contact with the reference wiring B (n, 3) and the planar pattern G (n, 3) is used as the reference wiring. It can be approximated as the capacitance of B (n, 3).
 また、配線Pnの静電容量は、その配線Pnと、他のすべての配線やパターンとの間の静電容量であってもよく、その配線Pnと、その他の予め設定された一又は複数の配線又はパターンとの間の静電容量であってもよい。あるいは、キャリア基板102が導体基板であった場合、配線Pnの静電容量は、その配線Pnと、キャリア基板102との間の静電容量であってもよい。測定部22は、配線Pnと、任意に設定された配線又はパターンとに接触する一対のプローブPr間で測定された静電容量を、その配線Pnの測定容量とすればよい。 Further, the capacitance of the wiring Pn may be the capacitance between the wiring Pn and all other wirings and patterns, and the wiring Pn and one or more other presets. It may be the capacitance between the wiring or the pattern. Alternatively, when the carrier substrate 102 is a conductor substrate, the capacitance of the wiring Pn may be the capacitance between the wiring Pn and the carrier substrate 102. The measuring unit 22 may use the capacitance measured between the wiring Pn and the pair of probes Pr in contact with the arbitrarily set wiring or pattern as the measurement capacitance of the wiring Pn.
 測定部22は、測定対象の基準配線Bn又は配線Pnに接触するプローブPrに、スキャナ部31によって電流計33を接続させる。また、測定部22は、そのプローブPrと対になるプローブPrに、スキャナ部31によって交流電源32を接続させる。 The measuring unit 22 connects the ammeter 33 to the probe Pr that comes into contact with the reference wiring Bn or the wiring Pn to be measured by the scanner unit 31. Further, the measuring unit 22 connects the AC power supply 32 to the probe Pr paired with the probe Pr by the scanner unit 31.
 そうすると、交流電源32から出力された周波数fの電圧Vによって、測定対象の基準配線Bn又は配線Pnの静電容量を介して電流Iが流れ、その電流Iが電流計33によって測定される。 Then, the voltage V of the frequency f output from the AC power supply 32 causes a current I to flow through the capacitance of the reference wiring Bn or the wiring Pn to be measured, and the current I is measured by the current meter 33.
 周波数fの電圧Vが静電容量Xに印加されたときに電流Iが流れた場合、静電容量Xは、下記の式(1)で与えられる。
静電容量X=I/(V×2πf) ・・・(1)
When the current I flows when the voltage V of the frequency f is applied to the capacitance X, the capacitance X is given by the following equation (1).
Capacitance X = I / (V × 2πf) ・ ・ ・ (1)
 この場合、Vおよび2πfは既知であるから、電流Iが得られれば静電容量Xが判る。従って、測定部22は、静電容量Xを測定容量Cとして測定することができる。 In this case, since V and 2πf are known, the capacitance X can be known if the current I is obtained. Therefore, the measuring unit 22 can measure the capacitance X as the measuring capacitance C.
 以下、測定部22が、スキャナ部31、交流電源32、及び電流計33を用いて静電容量Xを測定することを、単に、測定部22が、静電容量Xすなわち測定容量Cを測定する、というように記載する。 Hereinafter, the measuring unit 22 measures the capacitance X using the scanner unit 31, the AC power supply 32, and the ammeter 33, and the measuring unit 22 simply measures the capacitance X, that is, the measuring capacity C. , And so on.
 平均容量算出部23は、互いに対応する配線から測定された測定容量Cの平均値を、平均容量Cavとして算出する。互いに対応する配線、とは、各基板Aに対して、設計上同一の配線として作り込まれた配線である。例えば、配線番号が同じ、基準配線B(1,1),B(2,1),B(3,1),・・・は互いに対応する配線であり、基準配線B(1,2),B(2,2),B(3,2),・・・は互いに対応する配線であり、基準配線B(1,3),B(2,3),B(3,3),・・・は互いに対応する配線である。 The average capacity calculation unit 23 calculates the average value of the measurement capacity C measured from the wirings corresponding to each other as the average capacity Cav. The wiring corresponding to each other is a wiring created as the same wiring in the design for each substrate A. For example, the reference wirings B (1,1), B (2,1), B (3,1), ... B (2,2), B (3,2), ... Are wirings corresponding to each other, and reference wirings B (1,3), B (2,3), B (3,3), ... -Is the wiring corresponding to each other.
 容量補正部24は、複数の基板A1~A25のうち、基板番号iの基板Aiを目的基板とした場合に、目的基板Aiの配線の測定容量Ciに対する平均容量Cavの比率を、目的基板Aiの検査対象となる目的配線の測定容量Cに乗じることによって、目的配線の測定容量Cの補正値である補正容量Ccを算出する。 When the substrate Ai of the substrate number i is used as the target substrate among the plurality of substrates A1 to A25, the capacitance correction unit 24 determines the ratio of the average capacitance Cav to the measured capacitance Ci of the wiring of the target substrate Ai of the target substrate Ai. By multiplying the measurement capacity C of the target wiring to be inspected, the correction capacity Cc, which is the correction value of the measurement capacity C of the target wiring, is calculated.
 さらに容量補正部24は、各基板Aを順次目的基板とすることにより、各基板Aの目的配線に対する補正容量Ccを算出する。 Further, the capacitance correction unit 24 calculates the correction capacitance Cc for the target wiring of each substrate A by sequentially using each substrate A as the target substrate.
 基準値算出部25は、各基板Aの目的配線に対する補正容量Ccの平均値を、判定基準値Crefとして算出する。 The reference value calculation unit 25 calculates the average value of the correction capacitance Cc for the target wiring of each substrate A as the determination reference value Clef.
 判定部26は、判定基準値Crefに基づいて、補正容量Ccを判定する。 The determination unit 26 determines the correction capacity Cc based on the determination reference value Clef.
 次に、本発明の一例に係る検査方法を実行する基板検査装置1の動作の一例について、図5~図8を参照しつつ説明する。以下の説明では、基準配線B(i,j)の測定容量をC(B(i,j))、配線P(i,j)の測定容量をC(P(i,j))、配線P(i,j)の補正容量をCc(P(i,j))と記載する。 Next, an example of the operation of the substrate inspection device 1 that executes the inspection method according to the example of the present invention will be described with reference to FIGS. 5 to 8. In the following description, the measurement capacity of the reference wiring B (i, j) is C (B (i, j)), the measurement capacity of the wiring P (i, j) is C (P (i, j)), and the wiring P. The correction capacitance of (i, j) is described as Cc (P (i, j)).
 まず、測定部22は、基板番号iを1に初期化する(ステップS1)。 First, the measuring unit 22 initializes the board number i to 1 (step S1).
 次に、検査制御部21は、各プローブPrを基板Aiの第一層L1に接触させる。具体的には、各プローブPrを、基準配線B(i,1)~B(i,3)、配線P(i,1)~P(i,5)、面状パターンG(i,1)~G(i,3)、及び配線P(i,1)~P(i,5)と対になる任意の配線等に接触させる(ステップS2)。 Next, the inspection control unit 21 brings each probe Pr into contact with the first layer L1 of the substrate Ai. Specifically, each probe Pr is provided with reference wiring B (i, 1) to B (i, 3), wiring P (i, 1) to P (i, 5), and planar pattern G (i, 1). -G (i, 3) and wiring P (i, 1)-P (i, 5) are brought into contact with any wiring or the like paired with each other (step S2).
 次に、測定部22は、測定容量C(B(i,1)),C(B(i,2),C(B(i,3),及び測定容量C(P(i,1)),C(P(i,2)),C(P(i,3)),C(P(i,4)),C(P(i,5))を測定する(ステップS2:測定工程)。 Next, the measuring unit 22 has a measuring capacity C (B (i, 1)), a C (B (i, 2), a C (B (i, 3), and a measuring capacity C (P (i, 1))). , C (P (i, 2)), C (P (i, 3)), C (P (i, 4)), C (P (i, 5)) (step S2: measurement step) ..
 次に、測定部22は、基板番号iを25と比較し(ステップS3)、基板番号iが25でなければ(ステップS3でNO)、新たな基板Aについて測定するべく基板番号iに1を加算し(ステップS4)、再びステップS2,S3を繰り返す。一方、基板番号iが25であれば(ステップS3でYES)、すべての配線について測定容量Cを測定したことになるから、ステップS5へ処理を移行する。 Next, the measuring unit 22 compares the substrate number i with 25 (step S3), and if the substrate number i is not 25 (NO in step S3), 1 is added to the substrate number i to measure the new substrate A. Addition (step S4), and steps S2 and S3 are repeated again. On the other hand, if the substrate number i is 25 (YES in step S3), the measurement capacitance C has been measured for all the wirings, so the process proceeds to step S5.
 次に、平均容量算出部23は、測定容量C(B(1,1))~C(B(25,1))の平均値を、第一層L1の平均容量Cav(L1)とし、測定容量C(B(1,2))~C(B(25,2))の平均値を、第二層L2の平均容量Cav(L2)とし、測定容量C(B(1,3))~C(B(25,3))の平均値を、第三層L3の平均容量Cav(L3)とする(ステップS5:平均容量算出工程)。 Next, the average capacity calculation unit 23 measures the average value of the measurement capacities C (B (1,1)) to C (B (25,1)) as the average capacity Cav (L1) of the first layer L1. The average value of the capacities C (B (1,2)) to C (B (25,2)) is defined as the average capacity Cav (L2) of the second layer L2, and the measurement capacities C (B (1,3)) to Let the average value of C (B (25,3)) be the average capacity Cav (L3) of the third layer L3 (step S5: average capacity calculation step).
 測定容量C(B(1,1))~C(B(25,1))は、配線番号が1の互いに対応する基準配線Bであって、第一層L1に形成された基準配線Bから測定された測定容量Cである。測定容量C(B(1,2))~C(B(25,2))は、配線番号が2の互いに対応する基準配線Bであって、第二層L2に形成された基準配線Bから測定された測定容量Cである。測定容量C(B(1,3))~C(B(25,3))は、配線番号が3の互いに対応する基準配線Bであって、第三層L3に形成された基準配線Bから測定された測定容量Cである。 The measurement capacities C (B (1,1)) to C (B (25,1)) are reference wirings B having wiring numbers 1 corresponding to each other, and are from the reference wiring B formed in the first layer L1. The measured measurement capacity C. The measurement capacities C (B (1,2)) to C (B (25,2)) are reference wirings B having wiring numbers 2 corresponding to each other, and are from the reference wiring B formed in the second layer L2. The measured measurement capacity C. The measurement capacities C (B (1,3)) to C (B (25,3)) are reference wirings B having wiring numbers 3 corresponding to each other, and are from the reference wiring B formed in the third layer L3. The measured measurement capacity C.
 なお、一つの基板Aにおいて、層毎に基準配線Bを一つ設ける例を示したが、層毎に複数の基準配線Bを備えてもよい。そして、基板毎の複数の基準配線Bの測定容量Cを、複数基板分、層毎に平均して平均容量Cav(L1),Cav(L2),Cav(L3)を算出してもよい。 Although one reference wiring B is provided for each layer on one substrate A, a plurality of reference wirings B may be provided for each layer. Then, the average capacities Cav (L1), Cav (L2), and Cav (L3) may be calculated by averaging the measurement capacities C of the plurality of reference wirings B for each substrate for each of the plurality of substrates and for each layer.
 次に、容量補正部24は、基板番号iを1に初期化する(ステップS6)。 Next, the capacitance correction unit 24 initializes the board number i to 1 (step S6).
 次に、容量補正部24は、第一層L1の配線P(i,1)の補正容量Cc(P(i,1))を、下記の式(1)に基づいて算出する(ステップS7:容量補正工程)。補正容量Cc(P(i,1)) = C(P(i,1))×Cav(L1)/C(B(i,1)) ・・・(1) Next, the capacitance correction unit 24 calculates the correction capacitance Cc (P (i, 1)) of the wiring P (i, 1) of the first layer L1 based on the following equation (1) (step S7: Capacity correction process). Correction capacity Cc (P (i, 1)) = C (P (i, 1)) x Cav (L1) / C (B (i, 1)) ... (1)
 ステップS7において、基板Aiが目的基板に相当し、配線P(i,1)が第一層L1の目的配線に相当し、基準配線B(i,1)が目的基板Aiの配線に相当し、Cav(L1)/C(B(i,1))が目的基板Aiの配線の測定容量C(B(i,1))に対する平均容量Cav(L1)の比率に相当する。 In step S7, the board Ai corresponds to the target board, the wiring P (i, 1) corresponds to the target wiring of the first layer L1, and the reference wiring B (i, 1) corresponds to the wiring of the target board Ai. Cav (L1) / C (B (i, 1)) corresponds to the ratio of the average capacity Cav (L1) to the measured capacity C (B (i, 1)) of the wiring of the target substrate Ai.
 次に、容量補正部24は、第二層L2の配線P(i,2),P(i,3)の補正容量Cc(P(i,2)),Cc(P(i,3))を、下記の式(2),(3)に基づいて算出する(ステップS8:容量補正工程)。
補正容量Cc(P(i,2)) = C(P(i,2))×Cav(L2)/C(B(i,2)) ・・・(2)
補正容量Cc(P(i,3)) = C(P(i,3))×Cav(L2)/C(B(i,2)) ・・・(3)
Next, the capacitance correction unit 24 uses the correction capacitances Cc (P (i, 2)) and Cc (P (i, 3)) of the wirings P (i, 2) and P (i, 3) of the second layer L2. Is calculated based on the following equations (2) and (3) (step S8: capacity correction step).
Correction capacity Cc (P (i, 2)) = C (P (i, 2)) × Cav (L2) / C (B (i, 2)) ・ ・ ・ (2)
Correction capacity Cc (P (i, 3)) = C (P (i, 3)) x Cav (L2) / C (B (i, 2)) ... (3)
 ステップS8において、基板Aiが目的基板に相当し、配線P(i,2),P(i,3)が第二層L2の目的配線に相当し、基準配線B(i,2)が目的基板Aiの配線に相当し、Cav(L2)/C(B(i,2))が目的基板Aiの配線の測定容量C(B(i,2))に対する平均容量Cav(L2)の比率に相当する。 In step S8, the board Ai corresponds to the target board, the wirings P (i, 2) and P (i, 3) correspond to the target wiring of the second layer L2, and the reference wiring B (i, 2) corresponds to the target board. Corresponds to the wiring of Ai, and Cav (L2) / C (B (i, 2)) corresponds to the ratio of the average capacitance Cav (L2) to the measured capacitance C (B (i, 2)) of the wiring of the target substrate Ai. do.
 次に、容量補正部24は、第三層L3の配線P(i,4),P(i,5)の補正容量Cc(P(i,4)),Cc(P(i,5))を、下記の式(4),(5)に基づいて算出する(ステップS9:容量補正工程)。
補正容量Cc(P(i,4)) = C(P(i,4))×Cav(L3)/C(B(i,3)) ・・・(4)
補正容量Cc(P(i,5)) = C(P(i,5))×Cav(L3)/C(B(i,3)) ・・・(5)
Next, the capacitance correction unit 24 uses the correction capacitances Cc (P (i, 4)) and Cc (P (i, 5)) of the wirings P (i, 4) and P (i, 5) of the third layer L3. Is calculated based on the following equations (4) and (5) (step S9: capacity correction step).
Correction capacity Cc (P (i, 4)) = C (P (i, 4)) x Cav (L3) / C (B (i, 3)) ... (4)
Correction capacity Cc (P (i, 5)) = C (P (i, 5)) x Cav (L3) / C (B (i, 3)) ... (5)
 ステップS9において、基板Aiが目的基板に相当し、配線P(i,4),P(i,5)が第三層L3の目的配線に相当し、基準配線B(i,3)が目的基板Aiの配線に相当し、Cav(L3)/C(B(i,3))が目的基板Aiの配線の測定容量C(B(i,3))に対する平均容量Cav(L3)の比率に相当する。 In step S9, the board Ai corresponds to the target board, the wirings P (i, 4) and P (i, 5) correspond to the target wiring of the third layer L3, and the reference wiring B (i, 3) corresponds to the target board. Corresponds to the wiring of Ai, and Cav (L3) / C (B (i, 3)) corresponds to the ratio of the average capacity Cav (L3) to the measured capacity C (B (i, 3)) of the wiring of the target substrate Ai. do.
 次に、容量補正部24は、基板番号iを25と比較し(ステップS10)、基板番号iが25でなければ(ステップS10でNO)、新たな基板Aについて補正するべく基板番号iに1を加算し(ステップS11)、再びステップS7~10を繰り返す。一方、基板番号iが25であれば(ステップS10でYES)、すべての測定容量Cを補正し終えたことになるから、ステップS21へ処理を移行する。 Next, the capacitance correction unit 24 compares the substrate number i with 25 (step S10), and if the substrate number i is not 25 (NO in step S10), the capacitance correction unit 24 sets the substrate number i to 1 in order to correct the new substrate A. Is added (step S11), and steps S7 to 10 are repeated again. On the other hand, if the substrate number i is 25 (YES in step S10), it means that all the measurement capacities C have been corrected, so the process proceeds to step S21.
 図9に示すように、同じ配線番号の配線P同士であっても、基板A毎に、測定容量Cがばらついている。測定容量Cは、配線Pが断線していると減少し、配線Pが他の配線等と短絡すると、増大する。基板のばらつきがなければ、測定容量Cの増減により、配線Pの断線又は短絡を判断することができる。 As shown in FIG. 9, even if the wirings P have the same wiring number, the measurement capacity C varies from substrate A to substrate A. The measurement capacity C decreases when the wiring P is broken, and increases when the wiring P is short-circuited with other wiring or the like. If there is no variation in the substrate, it is possible to determine whether the wiring P is broken or short-circuited by increasing or decreasing the measurement capacity C.
 しかしながら、図9に示すように、基板のばらつきによる測定容量Cのばらつきが大きいと、測定容量Cに基づいて配線Pの断線又は短絡を判断することが容易でない。 However, as shown in FIG. 9, if the variation of the measurement capacity C due to the variation of the substrate is large, it is not easy to determine the disconnection or short circuit of the wiring P based on the measurement capacitance C.
 例えば図9に示す測定容量C(P(2,2))は、配線P(2,2)が断線している場合の測定容量C(P(2,2))を実線で、配線P(2,2)が正常な場合の測定容量C(P(2,2))を破線で示している。図9に示す例では、配線P(2,2)が断線している場合の測定容量C(P(2,2))は、正常な配線P(1,2)の測定容量C(P(1,2))よりも小さく、正常な配線P(25,2)の測定容量C(P(25,2))よりも大きい。そのため、測定容量C(P(2,2))に基づいて配線P(2,2)を不良と判定することが困難である。 For example, in the measurement capacity C (P (2,2)) shown in FIG. 9, the measurement capacity C (P (2,2)) when the wiring P (2,2) is broken is a solid line, and the wiring P ( The measured capacity C (P (2,2)) when 2 and 2) are normal is shown by a broken line. In the example shown in FIG. 9, the measurement capacity C (P (2, 2)) when the wiring P (2, 2) is broken is the measurement capacity C (P (P (2)) of the normal wiring P (1, 2). It is smaller than 1,2)) and larger than the measurement capacity C (P (25,2)) of the normal wiring P (25,2). Therefore, it is difficult to determine that the wiring P (2, 2) is defective based on the measurement capacity C (P (2, 2)).
 図10に示すように、ステップS7~S9で補正された補正容量Cc(P(1,1))~Cc(P(25,5))は、正常な配線Pであれば、配線番号が同じで互いに対応する配線P同士では基板のばらつきによる影響が低減されて、略同程度の静電容量となる。このように、ステップS1~S11によれば、基板Aの製造ばらつきによる静電容量Xのばらつきを補正することが容易となる。 As shown in FIG. 10, the correction capacitances Cc (P (1,1)) to Cc (P (25,5)) corrected in steps S7 to S9 have the same wiring number if the wiring P is normal. In the wirings P corresponding to each other, the influence of the variation of the substrate is reduced, and the capacitance becomes substantially the same. As described above, according to steps S1 to S11, it becomes easy to correct the variation in the capacitance X due to the manufacturing variation in the substrate A.
 また、基板Aの製造プロセスでは、層毎に配線P及び基準配線Bが形成されるため、同じ基板A内であっても、層毎にばらつき方が異なる場合がある。そこで、ステップS2では、各層に設けられた基準配線B(n,1)~B(n,3)から、測定容量C(B(1,1))~C(B(25,3))が測定される。ステップS5では、層毎に平均容量Cav(L1),Cav(L2),Cav(L3)が算出される。ステップS7~S9では、層毎に測定容量C(P(1,1))~C(P(25,5))が補正されて補正容量Cc(P(1,1))~Cc(P(25,5))が算出される。 Further, in the manufacturing process of the substrate A, since the wiring P and the reference wiring B are formed for each layer, the variation may differ for each layer even within the same substrate A. Therefore, in step S2, the measurement capacities C (B (1,1)) to C (B (25,3)) are obtained from the reference wirings B (n, 1) to B (n, 3) provided in each layer. Be measured. In step S5, the average capacities Cav (L1), Cav (L2), and Cav (L3) are calculated for each layer. In steps S7 to S9, the measurement capacities C (P (1,1)) to C (P (25,5)) are corrected for each layer, and the correction capacities Cc (P (1,1)) to Cc (P (P (P)). 25,5)) is calculated.
 これにより、層毎のばらつきの差異を低減させるように、補正容量Cc(P(1,1))~Cc(P(25,5))を算出することができる。 Thereby, the correction capacities Cc (P (1,1)) to Cc (P (25,5)) can be calculated so as to reduce the difference in the variation for each layer.
 次に、ステップS21において、基準値算出部25は、補正容量Cc(P(1,1))~C(P(25,1))の平均値を、配線P(n,1)の判定基準値Cref(1)とし、補正容量Cc(P(1,2))~Cc(P(25,2))の平均値を、配線P(n,2)の判定基準値Cref(2)とし、補正容量Cc(P(1,3))~Cc(P(25,3))の平均値を、配線P(n,3)の判定基準値Cref(3)とし、補正容量Cc(P(1,4))~Cc(P(25,4))の平均値を、配線P(n,4)の判定基準値Cref(4)とし、補正容量Cc(P(1,5))~Cc(P(25,5))の平均値を、配線P(n,5)の判定基準値Cref(5)とする(ステップS21:基準値算出工程)。 Next, in step S21, the reference value calculation unit 25 uses the average value of the correction capacitances Cc (P (1,1)) to C (P (25,1)) as the determination reference for the wiring P (n, 1). The value Clef (1) is set, and the average value of the correction capacities Cc (P (1,2)) to Cc (P (25,2)) is set as the judgment reference value Clef (2) of the wiring P (n, 2). The average value of the correction capacitances Cc (P (1,3)) to Cc (P (25,3)) is set as the judgment reference value Clef (3) of the wiring P (n, 3), and the correction capacitance Cc (P (1)) is used. , 4)) to Cc (P (25,4)) is set as the judgment reference value Clef (4) of the wiring P (n, 4), and the correction capacitances Cc (P (1,5)) to Cc ( Let the average value of P (25,5)) be the determination reference value Clef (5) of the wiring P (n, 5) (step S21: reference value calculation step).
 次に、判定部26は、基板番号i及び配線番号jを1に初期化する(ステップS22)。 Next, the determination unit 26 initializes the board number i and the wiring number j to 1 (step S22).
 次に、判定部26は、{Cc(P(i,j))-Cref(j)}/Cref(j)の絶対値が、判定比率Ref以下であれば(ステップS23でYES)、配線P(i,j)は良好と判定し(ステップS24)、判定比率Refを超えていれば(ステップS23でNO)、配線P(i,j)は不良と判定する(ステップS25)。 Next, if the absolute value of {Cc (P (i, j))-Clef (j)} / Clef (j) is equal to or less than the determination ratio Ref (YES in step S23), the determination unit 26 determines the wiring P. If (i, j) is determined to be good (step S24) and the determination ratio Ref is exceeded (NO in step S23), the wiring P (i, j) is determined to be defective (step S25).
 すなわち判定部26は、判定基準値Crefに対する、各配線Pの補正容量Ccと判定基準値Crefとの差の比率が、予め設定された判定比率Refを超えたとき、その配線Pを不良と判定することができる。判定比率Refは、要求される検査精度に応じて適宜設定すればよい。 That is, when the ratio of the difference between the correction capacitance Cc of each wiring P and the determination reference value Clef with respect to the determination reference value Clef exceeds the preset determination ratio Ref, the determination unit 26 determines that the wiring P is defective. can do. The determination ratio Ref may be appropriately set according to the required inspection accuracy.
 次に、判定部26は、配線番号jを5と比較し(ステップS26)、配線番号jが5でなければ(ステップS26でNO)、基板Aiにおける他の配線Pを判定するべく配線番号jに1を加算し(ステップS27)、再びステップS23~S26を繰り返す。 Next, the determination unit 26 compares the wiring number j with 5 (step S26), and if the wiring number j is not 5 (NO in step S26), the wiring number j is used to determine another wiring P on the board Ai. 1 is added to (step S27), and steps S23 to S26 are repeated again.
 一方、配線番号jが5であれば(ステップS26でYES)、基板番号iを25と比較し(ステップS28)、基板番号iが25でなければ(ステップS28でNO)、新たな基板Aについて判定するべく基板番号iに1を加算、配線番号jを1に初期化し(ステップS29)、再びステップS23~28を繰り返す。 On the other hand, if the wiring number j is 5 (YES in step S26), the board number i is compared with 25 (step S28), and if the board number i is not 25 (NO in step S28), the new board A is In order to determine, 1 is added to the board number i, the wiring number j is initialized to 1 (step S29), and steps S23 to 28 are repeated again.
 一方、基板番号iが25であれば(ステップS28でYES)、すべての配線Pについて良否を判定し終えたことになるから、ステップS30へ処理を移行する。 On the other hand, if the board number i is 25 (YES in step S28), it means that the quality of all wiring P has been determined, so the process proceeds to step S30.
 ステップS30では、判定部26は、ステップS25で不良と判定された配線Pが有ったか否かを確認する(ステップS30)。不良と判定された配線Pが一つもなければ(ステップS30でNO)処理を終了する。 In step S30, the determination unit 26 confirms whether or not there is a wiring P determined to be defective in step S25 (step S30). If there is no wiring P determined to be defective (NO in step S30), the process ends.
 一方、不良と判定された配線Pが一つでもあれば(ステップS30でYES)、ステップS41へ移行する。 On the other hand, if there is even one wiring P determined to be defective (YES in step S30), the process proceeds to step S41.
 不良と判定された配線Pが一つでもあった場合(ステップS30でYES)、その不良配線Pの補正容量Ccも含めてステップS21で算出された平均値が判定基準値Crefとされる。そのため、判定基準値Crefによる配線Pの良否判定精度が低下する。 If there is even one wiring P determined to be defective (YES in step S30), the average value calculated in step S21 including the correction capacity Cc of the defective wiring P is used as the determination reference value Clef. Therefore, the quality judgment accuracy of the wiring P based on the judgment reference value Clef is lowered.
 そこで、ステップS41において、基準値算出部25は、補正容量Cc(P(1,1))~C(P(25,1))から不良と判定された配線の補正容量を除いた残余の補正容量の平均値を、配線P(n,1)の新たな判定基準値Cref(1)とする。 Therefore, in step S41, the reference value calculation unit 25 corrects the remainder by removing the correction capacity of the wiring determined to be defective from the correction capacities Cc (P (1,1)) to C (P (25,1)). Let the average value of the capacitance be the new judgment reference value Clef (1) of the wiring P (n, 1).
 同様に、基準値算出部25は、補正容量Cc(P(1,2))~C(P(25,2))から不良と判定された配線の補正容量を除いた残余の補正容量の平均値を、配線P(n,2)の新たな判定基準値Cref(2)とする(ステップS41)。 Similarly, the reference value calculation unit 25 averages the remaining correction capacities excluding the correction capacities of the wiring determined to be defective from the correction capacities Cc (P (1,2)) to C (P (25,2)). Let the value be the new determination reference value Clef (2) of the wiring P (n, 2) (step S41).
 基準値算出部25は、補正容量Cc(P(1,3))~C(P(25,3))から不良と判定された配線の補正容量を除いた残余の補正容量の平均値を、配線P(n,3)の新たな判定基準値Cref(3)とする(ステップS41)。 The reference value calculation unit 25 calculates the average value of the residual correction capacity obtained by excluding the correction capacity of the wiring determined to be defective from the correction capacities Cc (P (1,3)) to C (P (25,3)). Set the new determination reference value Clef (3) of the wiring P (n, 3) (step S41).
 基準値算出部25は、補正容量Cc(P(1,4))~C(P(25,4))から不良と判定された配線の補正容量を除いた残余の補正容量の平均値を、配線P(n,4)の新たな判定基準値Cref(4)とする(ステップS41)。 The reference value calculation unit 25 calculates the average value of the residual correction capacity obtained by excluding the correction capacity of the wiring determined to be defective from the correction capacities Cc (P (1,4)) to C (P (25,4)). The new determination reference value Clef (4) of the wiring P (n, 4) is set (step S41).
 基準値算出部25は、補正容量Cc(P(1,5))~C(P(25,5))から不良と判定された配線の補正容量を除いた残余の補正容量の平均値を、配線P(n,5)の新たな判定基準値Cref(5)とする(ステップS41)。 The reference value calculation unit 25 calculates the average value of the residual correction capacity obtained by excluding the correction capacity of the wiring determined to be defective from the correction capacities Cc (P (1,5)) to C (P (25,5)). Set the new determination reference value Clef (5) of the wiring P (n, 5) (step S41).
 ステップS41によれば、不良配線があった場合、その不良配線の補正容量を除いた残余の補正容量に基づいて、新たな判定基準値Crefを求めることができるので、判定基準値Crefの精度を向上することができる。 According to step S41, when there is a defective wiring, a new determination reference value Clef can be obtained based on the residual correction capacitance excluding the correction capacitance of the defective wiring. Therefore, the accuracy of the determination reference value Clef can be determined. Can be improved.
 次に、判定部26は、基板番号i及び配線番号jを1に初期化する(ステップS42)。 Next, the determination unit 26 initializes the board number i and the wiring number j to 1 (step S42).
 次に、判定部26は、ステップS25で配線P(i,j)は不良であったか否かを確認する(ステップS43)。配線P(i,j)が不良でなければ(ステップS43でNO)判定部26は、ステップS51へ処理を移行する。配線P(i,j)が不良であれば(ステップS43でYES)、判定部26は、ステップS54へ処理を移行する。 Next, the determination unit 26 confirms in step S25 whether or not the wiring P (i, j) is defective (step S43). If the wiring P (i, j) is not defective (NO in step S43), the determination unit 26 shifts the process to step S51. If the wiring P (i, j) is defective (YES in step S43), the determination unit 26 shifts the process to step S54.
 ステップS51において、判定部26は、新たな判定基準値Crefに基づいて、{Cc(P(i,j))-Cref(j)}/Cref(j)の絶対値が、判定比率Ref以下であれば(ステップS51でYES)、配線P(i,j)は良好と判定し(ステップS52)、判定比率Refを超えていれば(ステップS51でNO)、配線P(i,j)は不良と判定する(ステップS53)。 In step S51, the determination unit 26 determines that the absolute value of {Cc (P (i, j))-Clef (j)} / Clef (j) is equal to or less than the determination ratio Ref based on the new determination reference value Clef. If there is (YES in step S51), the wiring P (i, j) is determined to be good (step S52), and if the determination ratio Ref is exceeded (NO in step S51), the wiring P (i, j) is defective. (Step S53).
 次に、判定部26は、配線番号jを5と比較し(ステップS54)、配線番号jが5でなければ(ステップS54でNO)、基板Aiにおける他の配線Pを判定するべく配線番号jに1を加算し(ステップS55)、再びステップS51~54を繰り返す。 Next, the determination unit 26 compares the wiring number j with 5 (step S54), and if the wiring number j is not 5 (NO in step S54), the determination unit 26 determines the other wiring P on the board Ai. 1 is added to (step S55), and steps S51 to 54 are repeated again.
 一方、配線番号jが5であれば(ステップS54でYES)、基板番号iを25と比較し(ステップS56)、基板番号iが25でなければ(ステップS56でNO)、新たな基板Aについて判定するべく基板番号iに1を加算、配線番号jを1に初期化し(ステップS57)、再びステップS51~56を繰り返す。 On the other hand, if the wiring number j is 5 (YES in step S54), the board number i is compared with 25 (step S56), and if the board number i is not 25 (NO in step S56), the new board A is In order to determine, 1 is added to the board number i, the wiring number j is initialized to 1 (step S57), and steps S51 to 56 are repeated again.
 一方、基板番号iが25であれば(ステップS56でYES)、前回不良でなかったすべての配線Pについて、新たな判定基準値Crefに基づいて良否を判定し終えたことになるから、ステップS58へ処理を移行する。 On the other hand, if the board number i is 25 (YES in step S56), it means that all the wirings P that were not defective last time have been judged to be good or bad based on the new judgment reference value Clef, so that step S58 Move the process to.
 ステップS58では、判定部26は、ステップS53で新たに不良と判定された配線Pが有ったか否かを確認する(ステップS58)。新たに不良と判定された配線Pが一つもなければ(ステップS58でNO)、処理を終了する。 In step S58, the determination unit 26 confirms whether or not there is a wiring P newly determined to be defective in step S53 (step S58). If there is no wiring P newly determined to be defective (NO in step S58), the process ends.
 一方、新たに不良と判定された配線Pが一つでもあれば(ステップS58でYES)、再びステップS41~S58を繰り返す。 On the other hand, if there is at least one wiring P newly determined to be defective (YES in step S58), steps S41 to S58 are repeated again.
 以上、ステップS30,S41~S58の処理によれば、不良と判定された配線Pがあった場合に、不良と判定された配線Pの影響を排除して、新たに判定基準値Crefを算出し、新たに算出された判定基準値Crefに基づいて、良品と判定されていた配線Pの良否判定をやり直すので、配線Pの良否判定精度が向上する。 As described above, according to the processes of steps S30 and S41 to S58, when there is a wiring P determined to be defective, the influence of the wiring P determined to be defective is eliminated, and the determination reference value Clef is newly calculated. Since the quality determination of the wiring P, which has been determined to be a non-defective product, is redone based on the newly calculated determination reference value Clef, the quality determination accuracy of the wiring P is improved.
 なお、必ずしもステップS30~S53を実行する必要はなく、ステップS28でYESの場合、処理を終了してもよい。 It is not always necessary to execute steps S30 to S53, and if YES in step S28, the process may be terminated.
 また、基準配線Bを、基板Aの層毎に設ける例に限らない。例えば、基準配線として基準配線B(n,2)のみを備え、ステップS7,S9において、Cav(L1)/C(B(i,1)),Cav(L3)/C(B(i,3))の代わりにCav(L2)/C(B(i,2))を用いてもよい。 Further, the reference wiring B is not limited to the example of being provided for each layer of the substrate A. For example, only the reference wiring B (n, 2) is provided as the reference wiring, and in steps S7 and S9, Cav (L1) / C (B (i, 1)) and Cav (L3) / C (B (i, 3)) are provided. )) May be used instead of Cav (L2) / C (B (i, 2)).
 また、検査対象となる配線Pとは別に、基準配線Bを備える例に限らない。基準配線Bを備えず、配線Pのいずれかを基準配線Bの代わりに用いてもよい。例えば、基準配線B(n,2),B(n,3)の代わりに、配線P(n,2),P(n,4)を用いてもよい。 Also, the example is not limited to the case where the reference wiring B is provided separately from the wiring P to be inspected. The reference wiring B may not be provided, and any of the wirings P may be used instead of the reference wiring B. For example, the wirings P (n, 2) and P (n, 4) may be used instead of the reference wirings B (n, 2) and B (n, 3).
 この場合、ステップS5において、測定容量C(P(1,2))~C(P(25,2))の平均値を、第二層L2の平均容量Cav(L2)とし、測定容量C(P(1,4))~C(P(25,4))の平均値を、第三層L3の平均容量Cav(L3)とすることができる。また、ステップS8において測定容量C(B(i,2))の代わりに測定容量C(P(i,2))を用い、ステップS9において測定容量C(B(i,3))の代わりに測定容量C(P(i,4))を用いることができる。 In this case, in step S5, the average value of the measurement capacities C (P (1,2)) to C (P (25,2)) is set as the average capacitance Cav (L2) of the second layer L2, and the measurement capacitance C ( The average value of P (1,4)) to C (P (25,4)) can be defined as the average capacity Cav (L3) of the third layer L3. Further, in step S8, the measurement capacity C (P (i, 2)) is used instead of the measurement capacity C (B (i, 2)), and in step S9, the measurement capacity C (B (i, 3)) is replaced. The measurement capacity C (P (i, 4)) can be used.
 これにより、ステップS23~S25、ステップS51~S53において、配線P(n,2),P(n,4)を検査することはできないものの、配線P(n,3),P(n,5)を検査することができる。配線P(n,2),P(n,4)を検査する際には、基準配線B(n,2),B(n,3)の代わりに、配線P(n,3),P(n,5)を用いればよい。 As a result, although the wirings P (n, 2) and P (n, 4) cannot be inspected in steps S23 to S25 and steps S51 to S53, the wirings P (n, 3) and P (n, 5) cannot be inspected. Can be inspected. When inspecting the wiring P (n, 2), P (n, 4), instead of the reference wiring B (n, 2), B (n, 3), the wiring P (n, 3), P ( n, 5) may be used.
 このようにすれば、配線Pとは別に、基準配線Bを備える必要がない。その一方、回路を構成するべく引き回される配線Pは、複雑に引き回され、複雑な形状になりやすく、静電容量Xが不安定になりやすい。しかしながら、配線Pとは別に基準配線Bを備える構成とした場合、回路上の必要性とは無関係に、平均容量算出用の基準配線Bを、静電容量が安定しやすい形状、配置にすることが容易である。 In this way, it is not necessary to provide the reference wiring B separately from the wiring P. On the other hand, the wiring P that is routed to form the circuit tends to be routed in a complicated manner, tends to have a complicated shape, and the capacitance X tends to become unstable. However, when the reference wiring B is provided separately from the wiring P, the reference wiring B for calculating the average capacitance should be shaped and arranged so that the capacitance is easy to stabilize, regardless of the necessity in the circuit. Is easy.
 また、本発明に係る基板検査装置及び検査方法は、少なくとも基板の製造ばらつきによる静電容量のばらつきを補正することが容易であればよく、ステップS21~S58を実行することなく、ステップS10でYESの場合、処理を終了してもよい。 Further, the substrate inspection apparatus and inspection method according to the present invention need only be able to easily correct the variation in capacitance due to the variation in manufacturing of the substrate, and YES in step S10 without executing steps S21 to S58. In the case of, the process may be terminated.
 また、ステップS43において、一度不良と判定された配線Pは、ステップS51~S53で改めて判定しない例を示したが、ステップS43を実行せず、ステップS42からステップS51へ移行してもよい。 Further, although the wiring P once determined to be defective in step S43 is not determined again in steps S51 to S53, the wiring P may be shifted from step S42 to step S51 without executing step S43.
 即ち、本発明の一例に係る検査装置は、設計上同一の配線として設けられた配線がそれぞれ形成された複数の基板を検査する検査装置であって、前記各基板の配線の静電容量を測定容量として測定する測定部と、前記設計上同一の配線として設けられた配線から測定された測定容量の平均値を、平均容量として算出する平均容量算出部と、前記複数の基板のうち一つを目的基板とした場合に、前記目的基板の検査対象となる目的配線の前記測定容量の補正値である補正容量を算出する容量補正部とを備え、前記容量補正部は、前記目的基板の配線の前記測定容量に対する前記平均容量の比率を、前記目的配線の前記測定容量に乗じることによって、前記補正容量を算出する。 That is, the inspection device according to an example of the present invention is an inspection device that inspects a plurality of substrates on which wirings provided as the same wiring in design are formed, and measures the capacitance of the wiring of each of the substrates. A measurement unit that measures as a capacity, an average capacity calculation unit that calculates the average value of the measurement capacity measured from the wiring provided as the same wiring in the design as an average capacity, and one of the plurality of substrates. When the target board is used, the target board is provided with a capacitance correction unit that calculates a correction capacity which is a correction value of the measurement capacity of the target wiring to be inspected, and the capacitance correction unit is a wiring of the target board. The correction capacity is calculated by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the measurement capacity.
 また、本発明の一例に係る検査方法は、設計上同一の配線として設けられた配線がそれぞれ形成された複数の基板を検査する検査方法であって、前記各基板の配線の静電容量を測定容量として測定する測定工程と、前記設計上同一の配線として設けられた配線から測定された測定容量の平均値を、平均容量として算出する平均容量算出工程と、前記複数の基板のうち一つを目的基板とした場合に、前記目的基板の検査対象となる目的配線の前記測定容量の補正値である補正容量を算出する容量補正工程とを含み、前記容量補正工程は、前記目的基板の配線の前記測定容量に対する前記平均容量の比率を、前記目的配線の前記測定容量に乗じることによって、前記補正容量を算出する。 Further, the inspection method according to an example of the present invention is an inspection method for inspecting a plurality of substrates on which wirings provided as the same wiring in design are formed, and measures the capacitance of the wiring of each of the substrates. The measurement step of measuring as the capacity, the average capacity calculation step of calculating the average value of the measured capacities measured from the wiring provided as the same wiring in the design as the average capacity, and one of the plurality of substrates. When the target board is used, the capacity correction step includes a capacity correction step of calculating a correction capacity which is a correction value of the measured capacity of the target wiring to be inspected on the target board, and the capacity correction step is performed on the wiring of the target board. The correction capacity is calculated by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the measurement capacity.
 これらの構成によれば、各基板の配線の静電容量が測定容量として測定され、設計上同一の配線として設けられた互いに対応する配線から測定された測定容量の平均値が平均容量として算出される。そして、複数の基板のうち一つである目的基板の配線の測定容量に対する、平均容量の比率が、目的基板の検査対象となる目的配線の測定容量に乗じられて目的配線の補正容量が算出される。その結果、補正容量における基板相互間のばらつきが低減されるので、基板の製造ばらつきによる静電容量のばらつきを補正することが容易となる。 According to these configurations, the capacitance of the wiring of each board is measured as the measurement capacity, and the average value of the measurement capacities measured from the wirings corresponding to each other provided as the same wiring in the design is calculated as the average capacity. NS. Then, the ratio of the average capacity to the measured capacity of the wiring of the target board, which is one of the plurality of boards, is multiplied by the measured capacity of the target wiring to be inspected on the target board to calculate the correction capacity of the target wiring. NS. As a result, the variation in the correction capacitance between the substrates is reduced, so that it becomes easy to correct the variation in the capacitance due to the manufacturing variation of the substrate.
 また、前記容量補正部は、前記複数の基板をそれぞれ前記目的基板として、前記各目的基板の目的配線の補正容量を算出し、前記検査装置は、前記各補正容量の平均値を、判定基準値として算出する基準値算出部と、前記判定基準値に基づいて、前記各補正容量を判定する判定部とをさらに備えることが好ましい。 Further, the capacitance correction unit calculates the correction capacitance of the target wiring of each target substrate using the plurality of substrates as the target substrates, and the inspection device sets the average value of the correction capacitances as a determination reference value. It is preferable to further include a reference value calculation unit for calculating as, and a determination unit for determining each correction capacity based on the determination reference value.
 この構成によれば、各目的基板の目的配線の補正容量に基づいて、判定基準値を自動的に算出することができるので、各補正容量を判定することが容易となる。 According to this configuration, the determination reference value can be automatically calculated based on the correction capacity of the target wiring of each target board, so that each correction capacity can be easily determined.
 また、前記基準値算出部は、前記判定部によって不良と判定された補正容量を除いた残余の補正容量の平均値を、新たな判定基準値として算出し、前記判定部は、前記新たな判定基準値に基づいて、少なくとも前記残余の補正容量を判定することが好ましい。 Further, the reference value calculation unit calculates the average value of the residual correction capacity excluding the correction capacity determined to be defective by the determination unit as a new determination reference value, and the determination unit calculates the new determination. It is preferable to determine at least the residual correction capacity based on the reference value.
 この構成によれば、不良配線の補正容量が、判定基準値の元となるデータから排除されて新たな判定基準値が算出されるので、新たな判定基準値に基づく判定精度が向上する。 According to this configuration, the correction capacity of the defective wiring is excluded from the data that is the source of the judgment reference value, and a new judgment reference value is calculated, so that the judgment accuracy based on the new judgment reference value is improved.
 また、前記配線には、検査対象でなく、前記複数の基板相互間で設計上同一の配線として設けられる基準配線が含まれ、前記測定部は、前記基準配線の静電容量を前記基準配線の測定容量として測定し、前記平均容量算出部は、前記各基板における前記基準配線の測定容量の平均値を、前記平均容量として算出することが好ましい。 Further, the wiring includes a reference wiring that is not an inspection target and is provided as the same wiring in design between the plurality of substrates, and the measuring unit uses the capacitance of the reference wiring as the reference wiring. It is preferable that the measurement is performed as the measurement capacity, and the average capacity calculation unit calculates the average value of the measurement capacities of the reference wiring on each substrate as the average capacity.
 この構成によれば、検査対象となる配線とは別の基準配線から測定された測定容量に基づいて平均容量が算出される。回路を構成するべく引き回される検査対象の配線は、複雑に引き回され、複雑な形状になりやすく、静電容量が不安定になりやすい。しかしながら、検査対象の配線とは別に基準配線を備える構成とした場合、回路上の必要性とは無関係に、平均容量算出用の基準配線を、静電容量が安定しやすい形状、配置にすることが容易である。 According to this configuration, the average capacity is calculated based on the measured capacity measured from the reference wiring different from the wiring to be inspected. The wiring to be inspected that is routed to form a circuit tends to be routed in a complicated manner, tends to have a complicated shape, and the capacitance tends to be unstable. However, if a reference wiring is provided separately from the wiring to be inspected, the reference wiring for calculating the average capacitance should be shaped and arranged so that the capacitance is easy to stabilize, regardless of the necessity in the circuit. Is easy.
 また、前記基板は多層基板であり、前記基準配線は、前記基板の層毎に設けられていることが好ましい。 Further, it is preferable that the substrate is a multilayer substrate and the reference wiring is provided for each layer of the substrate.
 基板の製造プロセスでは、層毎に配線及び基準配線が形成されるため、同じ基板内であっても、層毎にばらつき方が異なる場合がある。そこで、基準配線を基板の層毎に設けることによって、層毎のばらつきの差異を低減させるように、補正容量を算出することが容易になる。 In the substrate manufacturing process, wiring and reference wiring are formed for each layer, so even within the same substrate, the variation may differ for each layer. Therefore, by providing the reference wiring for each layer of the substrate, it becomes easy to calculate the correction capacitance so as to reduce the difference in the variation for each layer.
 また、前記配線に接触するためのプローブを備え、前記測定部は、前記プローブを介して前記静電容量を測定することが好ましい。 Further, it is preferable that a probe for contacting the wiring is provided, and the measuring unit measures the capacitance via the probe.
 この構成によれば、プローブを配線に接触させることによって、配線の静電容量を測定することができる。 According to this configuration, the capacitance of the wiring can be measured by bringing the probe into contact with the wiring.
1    基板検査装置、2    制御部、3    検査部、4    検査治具、11  筐体、12  基板固定装置、15  検査部移動機構、21  検査制御部、22  測定部、23  平均容量算出部、24  容量補正部、25  基準値算出部、26  判定部、31  スキャナ部、32  交流電源、33  電流計、100      パネル、102      キャリア基板、103      剥離層、A,A1~A25  基板、B    基準配線、C    測定容量、Cav      平均容量、Cc  補正容量、Cref    判定基準値、G    面状パターン、I    電流、L1  第一層、L2  第二層、L3  第三層、P    配線、Pr  プローブ、Ref      判定比率、V    電圧、e,g      端部、f    本体、X    静電容量 1 Board inspection device, 2 Control unit, 3 Inspection unit, 4 Inspection jig, 11 Housing, 12 Board fixing device, 15 Inspection unit movement mechanism, 21 Inspection control unit, 22 Measurement unit, 23 Average capacity calculation unit, 24 Capacity Correction unit, 25 reference value calculation unit, 26 judgment unit, 31 scanner unit, 32 AC power supply, 33 ammeter, 100 panel, 102 carrier board, 103 peeling layer, A, A1 to A25 board, B reference wiring, C measurement capacity , Cav average capacity, Cc correction capacity, Clef judgment reference value, G surface pattern, I current, L1 first layer, L2 second layer, L3 third layer, P wiring, Pr probe, Ref judgment ratio, V e, g, end, f, main body, X, capacitance

Claims (7)

  1.  設計上同一の配線として設けられた配線がそれぞれ形成された複数の基板を検査する検査装置であって、
     前記各基板の配線の静電容量を測定容量として測定する測定部と、
     前記設計上同一の配線として設けられた配線から測定された測定容量の平均値を、平均容量として算出する平均容量算出部と、
     前記複数の基板のうち一つを目的基板とした場合に、前記目的基板の検査対象となる目的配線の前記測定容量の補正値である補正容量を算出する容量補正部とを備え、
     前記容量補正部は、前記目的基板の配線の前記測定容量に対する前記平均容量の比率を、前記目的配線の前記測定容量に乗じることによって、前記補正容量を算出する検査装置。
    It is an inspection device that inspects a plurality of substrates on which wirings provided as the same wiring in design are formed.
    A measuring unit that measures the capacitance of the wiring of each substrate as the measuring capacitance,
    An average capacity calculation unit that calculates the average value of the measured capacities measured from the wiring provided as the same wiring in the design as the average capacity.
    When one of the plurality of substrates is used as the target substrate, a capacitance correction unit for calculating the correction capacitance, which is a correction value of the measurement capacitance of the target wiring to be inspected on the target substrate, is provided.
    The capacity correction unit is an inspection device that calculates the correction capacity by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the measurement capacity of the wiring of the target substrate.
  2.  前記容量補正部は、前記複数の基板をそれぞれ前記目的基板として、前記各目的基板の目的配線の補正容量を算出し、
     前記検査装置は、前記各補正容量の平均値を、判定基準値として算出する基準値算出部と、
     前記判定基準値に基づいて、前記各補正容量を判定する判定部とをさらに備える請求項1に記載の検査装置。
    The capacitance correction unit calculates the correction capacitance of the target wiring of each of the target boards by using the plurality of boards as the target boards.
    The inspection device includes a reference value calculation unit that calculates an average value of each correction capacity as a determination reference value.
    The inspection device according to claim 1, further comprising a determination unit for determining each correction capacity based on the determination reference value.
  3.  前記基準値算出部は、前記判定部によって不良と判定された補正容量を除いた残余の補正容量の平均値を、新たな判定基準値として算出し、
     前記判定部は、前記新たな判定基準値に基づいて、少なくとも前記残余の補正容量を判定する請求項2に記載の検査装置。
    The reference value calculation unit calculates the average value of the residual correction capacity excluding the correction capacity determined to be defective by the determination unit as a new determination reference value.
    The inspection device according to claim 2, wherein the determination unit determines at least the residual correction capacity based on the new determination reference value.
  4.  前記配線には、検査対象でなく、前記複数の基板相互間で設計上同一の配線として設けられる基準配線が含まれ、
     前記測定部は、前記基準配線の静電容量を前記基準配線の測定容量として測定し、
     前記平均容量算出部は、前記各基板における前記基準配線の測定容量の平均値を、前記平均容量として算出する請求項1~3のいずれか1項に記載の検査装置。
    The wiring includes a reference wiring that is not subject to inspection and is provided as the same wiring in design between the plurality of substrates.
    The measuring unit measures the capacitance of the reference wiring as the measurement capacitance of the reference wiring.
    The inspection device according to any one of claims 1 to 3, wherein the average capacity calculation unit calculates an average value of the measured capacities of the reference wiring on each substrate as the average capacity.
  5.  前記基板は多層基板であり、
     前記基準配線は、前記基板の層毎に設けられている請求項4に記載の検査装置。
    The substrate is a multilayer substrate and
    The inspection device according to claim 4, wherein the reference wiring is provided for each layer of the substrate.
  6.  前記配線に接触するためのプローブを備え、
     前記測定部は、前記プローブを介して前記静電容量を測定する請求項1~5のいずれか1項に記載の検査装置。
    Provided with a probe for contacting the wiring
    The inspection device according to any one of claims 1 to 5, wherein the measuring unit measures the capacitance via the probe.
  7.  設計上同一の配線として設けられた配線がそれぞれ形成された複数の基板を検査する検査方法であって、
     前記各基板の配線の静電容量を測定容量として測定する測定工程と、
     前記設計上同一の配線として設けられた配線から測定された測定容量の平均値を、平均容量として算出する平均容量算出工程と、
     前記複数の基板のうち一つを目的基板とした場合に、前記目的基板の検査対象となる目的配線の前記測定容量の補正値である補正容量を算出する容量補正工程とを含み、
     前記容量補正工程は、前記目的基板の配線の前記測定容量に対する前記平均容量の比率を、前記目的配線の前記測定容量に乗じることによって、前記補正容量を算出する検査方法。
    This is an inspection method that inspects a plurality of boards on which wirings provided as the same wiring in design are formed.
    A measurement step of measuring the capacitance of the wiring of each substrate as a measurement capacitance,
    An average capacity calculation step of calculating the average value of the measured capacities measured from the wiring provided as the same wiring in the design as the average capacity, and
    When one of the plurality of substrates is used as the target substrate, a capacitance correction step of calculating a correction capacity which is a correction value of the measured capacitance of the target wiring to be inspected on the target substrate is included.
    The capacity correction step is an inspection method for calculating the correction capacity by multiplying the measurement capacity of the target wiring by the ratio of the average capacity to the measurement capacity of the wiring of the target substrate.
PCT/JP2021/016358 2020-04-28 2021-04-22 Inspection device and inspection method WO2021220942A1 (en)

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