JP2009109445A - Circuit substrate inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit substrate inspection device capable of shortening the inspection time without lowering the inspection precision. <P>SOLUTION: The circuit substrate inspection device comprises: a common electrode plate 2 arranged along the under surface of the circuit substrate 11; a signal impressing part 4 for generating and impressing an inspection signal Sc1 on the common electrode plate 2; inspection probes 5a to 5d capable of contact with wiring patterns 12a to 12d formed on the circuit substrate 11 on a portions exposing on the upper surface of the circuit substrate 11; operational amplifiers 31a to 31d, the noninverting terminals of which are connected with a common reference potential Vr, also the corresponding inspection probes among the inspection probes 5a to 5d are connected with the inverting input terminals; a capacitance detection part 7 for detecting the static capacity of each of wiring patterns 12a to 12d being in contact with each of inspection probes 5a to 5d; and a process part 9 for discriminating qualities of each of wiring patterns 12a to 12d in terms of the detected static capacities. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a circuit board inspection apparatus for inspecting the quality of a wiring pattern formed on a circuit board.

As this type of circuit board inspection apparatus, a circuit board inspection apparatus disclosed in Patent Document 1 below is known. In this circuit board inspection device, when inspecting the quality of a plurality of wiring patterns (connection conductors) formed as independent patterns on one surface of a circuit board (circuit board), each of the wiring patterns faces each other. A common electrode plate (conductive plate) having a capacitance between the circuit board and the other side of the circuit board, and selecting a wiring pattern one by one, between the selected wiring pattern and the common electrode plate When the capacitance is within the reference value range, no short circuit is detected, and when the capacitance exceeds the reference value range, it is determined that there is a short circuit with the adjacent wiring pattern.
Japanese Examined Patent Publication No. 4-17394 (page 7, Fig. 1)

  However, the following problems exist in the conventional circuit board inspection apparatus. That is, in this circuit board inspection apparatus, the wiring pattern is selected one by one, the capacitance is measured, and the quality is determined based on the measured capacitance, so that the time required for the inspection is increased. There are issues to be addressed. As a method for solving this problem, a method in which an inspection probe is simultaneously brought into contact with a plurality of wiring patterns, and a capacitance between each wiring pattern and the common electrode plate can be simultaneously measured. However, in this method, the capacitance detected between each wiring pattern and the common electrode plate is different from each other, so that the signal detected by each inspection probe is a signal having a different phase, In addition, there is a stray capacitance between each inspection probe and a parasitic capacitance between each wiring pattern.Therefore, a phenomenon occurs in which a signal flows between inspection probes via each stray capacitance. The capacitance between the wiring pattern and the common electrode plate cannot be measured accurately. For this reason, this method has a problem that the inspection accuracy of the wiring pattern based on the capacitance decreases.

  The present invention has been made to solve the above-described problems, and has as its main object to provide a circuit board inspection apparatus capable of reducing the time required for inspection without degrading inspection accuracy.

  To achieve the above object, a circuit board inspection apparatus according to claim 1, wherein a common electrode plate disposed along one surface of the circuit board and a signal application for generating an inspection signal and applying the inspection signal to the common electrode plate. And n (n is an integer greater than or equal to 2) inspection probes that can come into contact with a portion exposed on the other surface of the circuit board in the plurality of wiring patterns formed on the circuit board, and the n inspections A corresponding inspection probe among the probes is connected to the inverting input terminal and the non-inverting input terminal has n operational amplifiers connected to a common reference potential, and the n inspection probes are in contact with each other. A capacitance detection unit that detects the capacitances of the n number of wiring patterns, and a processing unit that determines the quality of the n number of wiring patterns based on the detected capacitances.

  The circuit board inspection apparatus according to claim 2 is the circuit board inspection apparatus according to claim 1, wherein the signal applying unit generates two or more types of the inspection signals having different frequencies and simultaneously applies them to the common electrode plate. Apply.

  According to a third aspect of the present invention, there is provided the circuit board inspection apparatus according to the first or second aspect, wherein a moving unit that moves the n inspection probes and the inspection probes in the plurality of wiring patterns are provided. A storage unit in which position information of a contact part is stored, and the processing unit controls the moving unit based on the position information stored in the storage unit so that the inspection probes are connected to the wiring patterns. And move to the contact site.

  In the circuit board inspection apparatus according to claim 1, n inspection probes are connected to the inverting input terminal of the corresponding operational amplifier in the capacitance detection unit, and the non-inverting input terminal of each operational amplifier is connected to a common reference potential. Therefore, all inspection probes connected to the inverting input terminal are at the same potential (reference potential) due to an imaginary short of each operational amplifier. Therefore, according to this circuit board inspection apparatus, it is possible to shorten the inspection time by simultaneously connecting all the inspection probes to the respective wiring patterns formed on the circuit board and simultaneously inspecting these wiring patterns. At this time, each wiring is not affected by the stray capacitance existing between each inspection probe, and based on the capacitance value of the capacitance formed between each wiring pattern and the common electrode plate. The inspection for the pattern can be executed with high accuracy.

  In the circuit board inspection apparatus according to claim 2, the signal applying unit generates two or more kinds of inspection signals having different frequencies and applies them simultaneously to the common electrode plate. Therefore, according to this inspection apparatus, when the capacitance detection unit detects the capacitance of the wiring pattern based on the output signal of the operational amplifier to which the inspection probe that contacts the wiring pattern having a small area is connected, While using a high inspection signal, use a low-frequency inspection signal when detecting capacitance for this wiring pattern based on the output signal of an operational amplifier connected to an inspection probe that contacts a wiring pattern with a large area. Since the capacitance value of the capacitance of each wiring pattern formed between the common electrode plates can be detected more accurately, the accuracy of inspection of each wiring pattern on the circuit board can be further increased. .

  According to the circuit board inspection apparatus according to claim 3, the processing unit controls the moving unit based on the position information of the contact site for each wiring pattern stored in the storage unit, and each inspection probe becomes an inspection target. Since the wiring pattern is moved to and brought into contact with the wiring pattern, a high-speed and high-precision inspection can be automatically performed on a plurality of wiring patterns formed on the circuit board.

  The best mode of a circuit board inspection apparatus according to the present invention will be described below with reference to the accompanying drawings.

  First, a circuit board inspection apparatus 1 (hereinafter also referred to as “inspection apparatus 1”) will be described with reference to the drawings.

  As shown in FIG. 1, the inspection apparatus 1 includes a common electrode plate 2, an insulating plate 3, a signal application unit 4, and n (n is an integer of 2 or more) inspection probes 5 (in this example, inspection probes 5 a, 5b, 5c, and 5d (also referred to as “inspection probe 5” unless otherwise distinguished), a moving unit 6, a capacitance detecting unit 7, a storage unit 8, a processing unit 9, and an output unit 10 are formed on the circuit board 11. The plurality of wiring patterns 12 that have been configured can be inspected. In this example, as an example, as shown in the figure, a circuit board 11 having four wiring patterns 12 formed thereon, specifically, three wiring patterns 12a, 12b, 12c on the upper surface (the other surface in the present invention). The circuit board 11 in which one wiring pattern 12d is formed from the upper surface to the lower surface (one surface in the present invention) will be described as an example.

  As shown in FIG. 1, the common electrode plate 2 and the insulating plate 3 are formed in the same planar shape as an example and are stacked on each other. The insulating plate 3 is formed to have a uniform thickness as a whole. At the time of inspection, the circuit board 11 is arranged so that the lower surface thereof is in close contact with the surface of the insulating plate 3 (upper surface in the figure).

  As shown in FIG. 1, the signal applying unit 4 generates an inspection signal Sc <b> 1 that is an AC signal having a predetermined frequency f <b> 1 and applies it to the common electrode plate 2. The inspection probe 5 is disposed so as to be in contact with a predetermined portion of the wiring pattern 12 exposed on the upper surface of the circuit board 11. The moving unit 6 has the same number of moving arms 21a, 21b, 21c, and 21d as the inspection probes 5 connected to the corresponding inspection probes 5a, 5b, 5c, and 5d (hereinafter referred to as “moving arm 21” unless otherwise specified). ). In addition, the moving unit 6 drives each moving arm 21 under the control of the processing unit 9, so that each inspection probe 5 is an arbitrary wiring pattern 12 among the plurality of wiring patterns 12 formed on the circuit board 11. In contact with the inspection probe (contact part defined in the part exposed on the other surface of the circuit board 11 in the wiring pattern 12).

  As shown in FIGS. 1 and 2, the capacitance detector 7 includes n operational amplifiers (op-amps) 31a, 31b, 31c, 31d (hereinafter referred to as “operational amplifier 31” unless otherwise specified). N feedback circuits 32a, 32b, 32c, 32d (in this example, feedback resistors (hereinafter also referred to as “feedback circuit 32” unless otherwise specified)), n synchronous detection circuits 33a, 33b. , 33c, 33d (hereinafter also referred to as “synchronous detection circuit 33” unless otherwise distinguished), n band-pass filters 34a, 34b, 34c, and 34d (hereinafter also referred to as “filter 34” unless otherwise distinguished), and n phase comparison circuits 35a, 35b, 35c, and 35d (hereinafter also referred to as “phase comparison circuit 35” unless otherwise specified) are provided.

  Specifically, each operational amplifier 31a, 31b, 31c, 31d has a corresponding feedback circuit 32a, 32b, 32c, 32d connected between the inverting input terminal and the output terminal, and a common non-inverting input terminal. Connected to a reference potential Vr (in this example, a ground potential as an example), and corresponding inspection probes 5a, 5b, 5c, and 5d are connected to an inverting input terminal via a cable or the like (not shown) to form an inverting amplifier circuit. It is configured. The synchronous detection circuits 33a, 33b, 33c, and 33d are connected to the corresponding operational amplifiers 31a, 31b, 31c, and 31d, and output signals S2a, S2b, S2c, and S2d of the corresponding operational amplifiers 31a, 31b, 31c, and 31d. (Hereinafter, also referred to as “output signal S2” unless otherwise distinguished) is synchronously detected by the inspection signal Sc1. Each bandpass filter 34a, 34b, 34c, 34d is connected to a corresponding synchronous detection circuit 33a, 33b, 33c, 33d and is included in the output signal of the corresponding synchronous detection circuit 33a, 33b, 33c, 33d. A signal in a predetermined frequency band centered on the frequency f1 of the inspection signal Sc1 is selectively passed. Each phase comparison circuit 35a, 35b, 35c, 35d is connected to the corresponding bandpass filter 34a, 34b, 34c, 34d, and outputs the output signal of the corresponding bandpass filter 34a, 34b, 34c, 34d and the inspection signal Sc1. DC signal S3a, S3b, S3c, S3d (hereinafter, in particular, the level changes according to the phase difference (for example, the level increases / decreases as the phase difference increases / decreases) by detecting the phase difference) When not distinguished, it is also called “DC signal S3”).

  That is, the operational amplifier 31a, the synchronous detection circuit 33a, the band pass filter 34a, and the phase comparison circuit 35a constitute one capacitance detection circuit 7a for outputting one DC signal S3a. Similarly, the operational amplifier 31b, the synchronous detection circuit 33b, the bandpass filter 34b, and the phase comparison circuit 35b constitute another capacitance detection circuit 7b for outputting one DC signal S3b, and the operational amplifier 31c. , The synchronous detection circuit 33c, the band pass filter 34c and the phase comparison circuit 35c constitute another capacitance detection circuit 7c for outputting one DC signal S3c, and the operational amplifier 31d, the synchronous detection circuit 33d, the band The pass filter 34d and the phase comparison circuit 35d constitute another one capacitance detection circuit 7d for outputting one DC signal S3d. In addition, these four capacitance detection circuits 7a to 7d are configured such that each operational amplifier 31, each synchronous detection circuit 33, each band pass filter 34, and each phase comparison circuit 35 are formed in the same configuration. It is configured identically.

  In this case, when the inspection signal Sc1 is applied to the common electrode plate 2, the phase difference of the output signals S2a, S2b, S2c, and S2d output from the operational amplifiers 31a, 31b, 31c, and 31d with respect to the inspection signal Sc1 is In combination with the resistance component between the inspection probe 5 and the capacitance detection unit 7 (mainly the resistance value of the cable for connecting each inspection probe 5 to the capacitance detection unit 7), the corresponding inspection probe 5a, 5b, It changes according to the capacitance value of the capacitance formed between the wiring pattern 12 in contact with 5c and 5d and the common electrode plate 2 (specifically, the smaller the capacitance value, the more the phase difference Will grow). Therefore, the levels of the DC signals S3a, S3b, S3c, and S3d output from the phase comparison circuits 35a, 35b, 35c, and 35d are common to the wiring pattern 12 in contact with the inspection probes 5a, 5b, 5c, and 5d. Since the capacitance value of the capacitance formed between the plate 2 and the plate 2 is indicated, the capacitance detection unit 7 is connected to the wiring pattern 12 in contact with the inspection probes 5a, 5b, 5c, 5d and the common electrode. The capacitance value of the capacitance formed between the plate 2 is substantially detected.

  The storage unit 8 is configured by a semiconductor memory such as a ROM or a RAM, an operation program for defining the operation of the processing unit 9, determination data for the level of the DC signal S3 (for example, an upper limit Du and a lower limit Dl), In addition, position information Dp for a plurality of contact parts defined in the wiring patterns 12a to 12d of the circuit board 11 is stored. The determination data is based on the level of the DC signal S3 for each wiring pattern 12 obtained by inspecting a plurality of non-defective circuit boards 11 in which all the wiring patterns 12 are not disconnected or short-circuited by the inspection apparatus 1. When the circuit board 11 is a non-defective product, the upper limit value of the level of the DC signal S3 for each wiring pattern 12 formed on the circuit board 11 is the upper limit value Du, and the lower limit value is the lower limit value Dl. It is. In this case, in the circuit board 11 as a defective product in which a short circuit occurs between some of the wiring patterns 12, the capacitance of the wiring pattern 12 is increased as compared with the non-defective product. The level of the DC signal S3 measured for the pattern 12 is below the lower limit value Dl. On the other hand, in the circuit board 11 as a defective product in which a part of the wiring pattern 12 is broken, the capacitance of the wiring pattern 12 is smaller than that in the case of a non-defective product. The level of the DC signal S3 measured with respect to exceeds the upper limit Du. Therefore, by comparing the level of the DC signal S3 for each wiring pattern 12 with the determination data, it is possible to inspect whether the wiring pattern 12 of the circuit board 11 is broken or short-circuited. .

  As an example, the processing unit 9 includes n A / D converters and a CPU (none of which are shown). In the processing unit 9, each A / D converter converts the corresponding DC signal S 3 into digital data, and the CPU operates according to the operation program stored in the storage unit 8. An inspection process for the circuit board 11 is executed based on the data. The output unit 10 includes a display device as an example, and outputs (displays) the result of the inspection process executed by the processing unit 9.

  Next, an inspection operation for the circuit board 11 by the inspection apparatus 1 will be described. It is assumed that the circuit board 11 to be inspected is previously arranged on the insulating plate 3 as shown in FIGS. Further, in this state, as shown in FIG. 2, each wiring pattern 12a, 12b, 12c, 12d of the circuit board 11 disposed on the surface of the insulating plate 3 and the common electrode plate 2 have each Capacitances C1, C2, C3, C4 having capacitance values corresponding to the areas and positions (distances from the common electrode plate 2) of the wiring patterns 12a, 12b, 12c, 12d are formed.

  In the operating state of the inspection apparatus 1, the signal application unit 4 generates an inspection signal Sc 1 and applies it to the common electrode plate 2. Further, the capacitance detection unit 7 starts generating the DC signal S3 based on the voltage input to the inverting input terminal of each operational amplifier 31. In this state, the processing unit 9 starts an inspection process for the circuit board 11. In this inspection process, the processing unit 9 first reads out the position information Dp of the contact site for the n (four in this example) wiring patterns 12 to be inspected from the storage unit 8, and uses the read position information Dp as the read position information Dp. Based on this, the moving unit 6 is controlled to drive each moving arm 21 so that the n inspection probes 5 are moved to the contact parts defined on the n wiring patterns 12 to be inspected and brought into contact with each other. As an example, as shown in FIGS. 1 and 2, it is assumed that the inspection probes 5a, 5b, 5c, and 5d are brought into contact with the wiring patterns 12a, 12b, 12c, and 12d, respectively. In this state, a stray capacitance exists between the adjacent inspection probes 5. In this example, in order to facilitate understanding of the invention, as an example, the stray capacitance C5 exists between the adjacent inspection probes 5a and 5b, and the stray capacitance C6 exists between the adjacent inspection probes 5b and 5c. It is assumed that the stray capacitance C7 exists between the inspection probes 5c and 5d.

  When the contact of each inspection probe 5 with the wiring pattern 12 is completed, the inspection signal Sc1 supplied from the signal applying unit 4 to the common electrode plate 2 is transmitted to the wiring pattern 12a via the capacitance C1. Further, it is input to the operational amplifier 31a via the inspection probe 5a. Similarly, the inspection signal Sc1 is input to the operational amplifier 31b via the capacitance C2, the wiring pattern 12b, and the inspection probe 5b, and the operational amplifier 31c via the capacitance C3, the wiring pattern 12c, and the inspection probe 5c. And is input to the operational amplifier 31d through the capacitance C4, the wiring pattern 12d, and the inspection probe 5d. In the capacitance detection unit 7, the four capacitance detection circuits 7a to 7d operate simultaneously to output DC signals S3a to S3d, respectively. In this case, between the adjacent inspection probes 5, as shown in FIG. 2, stray capacitances C5, C6 and C7 exist, and between the wiring patterns 12a to 12d with which the inspection probes 5a to 5d are in contact. Have parasitic capacitances C8, C9, C10, but the non-inverting input terminal of each operational amplifier 31 as an input stage of the capacitance detection unit 7 is connected to a reference potential Vr (ground potential), and each operational amplifier In 31, the so-called “imaginary short” causes the potential difference between the inverting input terminal and the non-inverting input terminal to be almost zero, so that the potential of the non-inverting input terminal also becomes the reference potential Vr. As a result, the potentials of all the inspection probes 5 become the same potential (reference potential Vr). As a result, even in the presence of the stray capacitances C5, C6, C7 and the parasitic capacitances C8, C9, C10, the stray capacitances C5 to C7 and A situation in which an electric signal flows between the inspection probes 5 via the parasitic capacitors C8 to C10 is avoided. Therefore, even in a situation where they are operating simultaneously, the four capacitance detection circuits 7a to 7d are respectively connected to the corresponding wiring patterns 12a, 12b, 12c, and 12d via the capacitances C1, C2, C3, and C4. The inspection signal Sc1 flowing from the common electrode plate 2 is accurately input, and DC signals S3a to S3d having levels according to the phase difference between the input inspection signal Sc and the inspection signal Sc1 directly input from the signal applying unit 4 are obtained. Output.

  Next, the processing unit 9 converts each of the DC signals S3a to S3d input from the capacitance detection unit 7 into digital data, and the determination data (upper limit Du) for the four wiring patterns 12 to be inspected read from the storage unit 8 And the lower limit value Dl). In this case, as described above, the levels of the DC signals S3a to S3d output from the capacitance detection unit 7 are the levels of the wiring pattern 12 and the common electrode plate 2 in contact with the inspection probes 5a, 5b, 5c, and 5d. The capacitance values of the capacitances C1, C2, C3, and C4 formed therebetween are shown. For this reason, when the wiring pattern 12 to be inspected is in an abnormal state where it is short-circuited with another adjacent wiring pattern 12 (when it is defective), the capacitance C formed between the common electrode plate 2 Therefore, the level of the DC signal S3 for the wiring pattern 12 to be inspected is a value less than the lower limit value D1 of the determination data. Further, when the wiring pattern 12 to be inspected is in an abnormal state in which the wiring pattern 12 is disconnected (in a defective state), the capacitance C formed between the common electrode plate 2 and the common electrode plate 2 is in a normal state. Therefore, the level of the DC signal S3 for the wiring pattern 12 to be inspected becomes a value exceeding the upper limit Du of the determination data. On the other hand, when the wiring pattern 12 to be inspected is in a normal state where it is not short-circuited or disconnected (good), the capacitance C formed between the common electrode plate 2 and the common electrode plate 2 is a good circuit board. 11, the level of the DC signal S3 for the wiring pattern 12 to be inspected is equal to or higher than the lower limit value D1 of the determination data. It becomes a value within the range below the upper limit value Du.

  Therefore, when the level of the DC signal S3 for the wiring pattern 12 to be inspected is a value less than the lower limit value Dl of the determination data, the processing unit 9 determines that a short circuit has occurred in the wiring pattern 12, and the determination data When the value exceeds the upper limit value Du, it is determined that the wiring pattern 12 is disconnected. When the value is not less than the lower limit value Dl of the determination data and not more than the upper limit value Du, it is normal. The determination result is stored in the storage unit 8 in correspondence with the identification code of the wiring pattern 12. Finally, the processing unit 9 causes the output unit 10 to output (display) the discrimination results (inspection results) for the wiring patterns 12 a to 12 d stored in the storage unit 8. Thereby, the inspection process for the circuit board 11 by the inspection apparatus 1 is completed.

  Thus, in this inspection apparatus 1, all the inspection probes 5 are connected to the inverting input terminal of the corresponding operational amplifier 31 in the capacitance detection unit 7, and the non-inverting input terminal of the operational amplifier 31 has a common reference potential. Since it is connected to Vr, all the inspection probes 5 connected to the inverting input terminal are at the same potential (the potential of the non-inverting input terminal (reference potential Vr)) due to an imaginary short of each operational amplifier 31. . Therefore, according to the inspection apparatus 1, all inspection probes 5a to 5d are connected to the wiring patterns 12a to 12d formed on the circuit board 11 at the same time, and the inspection for the wiring patterns 12 is executed at the same time. The time can be shortened, and also at this time, the stray capacitances C5 to C7 that exist between the inspection probes 5 and the wiring patterns 12a to 12d that are in contact with the inspection probes 5a to 5d exist. Inspecting each wiring pattern 12 based on the capacitance values of the capacitances C1 to C4 formed between each wiring pattern 12 and the common electrode plate 2 without being affected by the parasitic capacitances C8, C9, and C10. Can be executed with high accuracy.

  Further, in this inspection apparatus 1, the processing unit 9 controls the moving unit 6 based on the position information Dp of the contact site for each wiring pattern 12 stored in the storage unit 8 to inspect each inspection probe 5. The contact part of the wiring pattern 12 to be moved is brought into contact with it. Therefore, high-speed and high-precision inspection can be automatically performed on the plurality of wiring patterns 12 formed on the circuit board 11.

  In addition, this invention is not limited to said structure. For example, in the inspection apparatus 1 described above, a configuration in which one type of inspection signal Sc1 (frequency f1) is supplied from the signal applying unit 4 to the common electrode plate 2 is employed. For example, the common electrode plate 2 and each wiring pattern When the capacitance values of the capacitances C1 to C4 formed between the wiring patterns 12 and 12 are greatly different from each other, the frequency of the inspection signal for the wiring pattern 12 having a small capacitance value is increased and the inspection for the wiring pattern 12 having a large capacitance value is performed. The signal frequency is preferably low. For example, as shown in FIGS. 1 and 2, even if the wiring pattern 12d is formed from the upper surface to the lower surface of the circuit board 11 or the wiring pattern 12 is formed only on the upper surface of the circuit board 11, the wiring pattern A wiring pattern with a large area such as 12b is preferably inspected with a low frequency inspection signal, and a wiring pattern with a small area such as the other wiring patterns 12a and 12c is preferably inspected with a high frequency inspection signal.

  Therefore, as in the inspection apparatus 1A shown in FIGS. 1 and 3, the signal applying unit 4A that simultaneously generates the inspection signal Sc2 having the frequency f2 (> f1) and applies it to the common electrode plate 2 together with the inspection signal Sc1 having the frequency f1. In the capacitance detection circuits 7a and 7c to which the inspection probes 5a and 5c that are in contact with the wiring patterns 12a and 12c having a small area are connected, synchronous detection and phase comparison are performed using the inspection signal Sc1 (frequency f1). The capacitance detection circuits 7b and 7d to which the inspection probes 5b and 5d that are in contact with the large wiring patterns 12b and 12d are connected include a capacitance detection unit 7A that performs synchronous detection and phase comparison using the inspection signal Sc2 (frequency f2). It is also possible to adopt a configuration. In addition, the same code | symbol is attached | subjected to each component of 1 A of inspection apparatuses which have the same function as each corresponding component in the inspection apparatus 1, and the overlapping description is abbreviate | omitted. Further, the filter 34 constituting each capacitance detection circuit 7 uses a filter corresponding to the frequency used in the synchronous detection circuit 33 and the phase comparison circuit 35. According to this inspection apparatus 1A, since an inspection signal having an appropriate frequency can be supplied to each wiring pattern 12 according to the area, the capacitance value of the capacitance of each wiring pattern 12 formed between the common electrode plate 2 Can be generated in the capacitance detection unit 7A, and the accuracy of inspection of each wiring pattern 12 on the circuit board 11 can be further improved based on the DC signal S3. Furthermore, although not shown, for a circuit board in which the capacitance value of each wiring pattern covers a wide range, a signal applying unit capable of generating three or more types of inspection signals having different frequencies is used. A configuration of applying to the common electrode plate 2 can also be adopted.

  In the above example, the inspection probe 5 is simultaneously brought into contact with all the wiring patterns 12 formed on the circuit board 11 and the inspection for all the wiring patterns 12 is simultaneously performed. Of course, the inspection apparatus 1 can also be applied to the circuit board 11 on which the number of the wiring patterns 12 exceeding the number (n) of the probes 5 is formed. In this case, the n number of inspection probes 5 are simultaneously brought into contact with the same number of wiring patterns 12, and inspection of these wiring patterns 12 is performed, and then n wiring patterns 12 among the remaining wiring patterns 12 are applied. The process of moving and inspecting the n inspection probes 5 is repeatedly performed. As a result, even for the circuit board 11 on which the number of wiring patterns 12 exceeding the number (n) of the inspection probes 5 is formed, the inspection time is significantly longer than the configuration in which the wiring patterns 12 are inspected one by one. Inspection accuracy can be sufficiently improved while shortening.

It is a lineblock diagram of inspection device 1 and 1A. FIG. 2 is a cross-sectional view of the circuit board 11 in FIG. It is the WW sectional view taken on the line of the circuit board 11 in FIG. 1, and the block diagram of the capacitance detection part 7A.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1A Inspection apparatus 2 Common electrode plate 4, 4A Signal application part 5 Inspection probe 6 Moving part 7, 7A Capacity | capacitance detection part 8 Memory | storage part 9 Processing part 11 Circuit board 12 Wiring pattern 31 Operational amplifier C1, C2, C3, C4 Static Capacitance Dp Position information Sc1, Sc2 Inspection signal Vr Reference potential

Claims (3)

A common electrode plate disposed along one surface of the circuit board;
A signal applying unit that generates an inspection signal and applies the inspection signal to the common electrode plate;
N (n is an integer of 2 or more) inspection probes that can contact a portion exposed on the other surface of the circuit board in the plurality of wiring patterns formed on the circuit board;
Of the n test probes, the corresponding test probe is connected to the inverting input terminal, and the non-inverting input terminal has n operational amplifiers connected to a common reference potential. A capacitance detector that detects the capacitance of the n wiring patterns in contact with the probe;
A circuit board inspection apparatus comprising: a processing unit that determines whether or not the n wiring patterns are good based on the detected capacitance.   The circuit board inspection apparatus according to claim 1, wherein the signal applying unit generates two or more types of inspection signals having different frequencies and applies them simultaneously to the common electrode plate. A moving unit for moving the n inspection probes;
A storage unit in which position information of a contact part with the inspection probe in the plurality of wiring patterns is stored;
The circuit according to claim 1, wherein the processing unit controls the moving unit based on the position information stored in the storage unit to move the inspection probes to the contact sites in the wiring patterns. Board inspection equipment.

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