WO2021218534A1 - 一种防篡改保护电路 - Google Patents

一种防篡改保护电路 Download PDF

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Publication number
WO2021218534A1
WO2021218534A1 PCT/CN2021/083931 CN2021083931W WO2021218534A1 WO 2021218534 A1 WO2021218534 A1 WO 2021218534A1 CN 2021083931 W CN2021083931 W CN 2021083931W WO 2021218534 A1 WO2021218534 A1 WO 2021218534A1
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WO
WIPO (PCT)
Prior art keywords
mos transistor
electrically connected
power supply
port
supply unit
Prior art date
Application number
PCT/CN2021/083931
Other languages
English (en)
French (fr)
Inventor
朱强
Original Assignee
深圳市时代华影科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN202020714503.6U external-priority patent/CN212695708U/zh
Priority claimed from CN202020718115.5U external-priority patent/CN212033764U/zh
Application filed by 深圳市时代华影科技股份有限公司 filed Critical 深圳市时代华影科技股份有限公司
Priority to EP21797846.9A priority Critical patent/EP4145656A4/en
Publication of WO2021218534A1 publication Critical patent/WO2021218534A1/zh
Priority to US18/049,644 priority patent/US11847255B2/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/86—Secure or tamper-resistant housings
    • G06F21/87—Secure or tamper-resistant housings by means of encapsulation, e.g. for integrated circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/10—Protecting distributed programs or content, e.g. vending or licensing of copyrighted material ; Digital rights management [DRM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/81—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer by operating on the power supply, e.g. enabling or disabling power-on, sleep or resume operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/82—Protecting input, output or interconnection devices
    • G06F21/84—Protecting input, output or interconnection devices output devices, e.g. displays or monitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/02—Details of power systems and of start or stop of display operation
    • G09G2330/027—Arrangements or methods related to powering off a display
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
    • G09G2330/04—Display protection

Definitions

  • the present invention relates to the field of display technology, in particular to an anti-tampering protection circuit.
  • the LED display only has a simple box door detection system to monitor the closed state of the box door to protect the data from being tampered with, and the state of the box door cannot be continuously monitored after the power is off, and the digital copyright cannot be continuously and effectively protected, and it does not meet the information processing standard. Require.
  • the LED display screen needs to design a special anti-tampering protection circuit.
  • the LED display screen When the LED display screen is powered off, it can continue to protect the information security, maintain the digital copyright, and meet the information processing standard requirements.
  • the technical problem to be solved by the present invention is to provide an anti-tampering protection circuit to solve the problem that the information security cannot be continuously protected when the LED display screen is powered off in the prior art.
  • the embodiment of the present invention provides an anti-tampering protection circuit, including: a switch trigger port, a tamper signal transmission port, a power supply unit, a first MOS tube, a second MOS tube, a third MOS tube, and a signal output port.
  • the first input end of the MOS transistor is electrically connected to the first output end of the power supply unit in parallel with the switch trigger port, and the second input end of the first MOS transistor is electrically connected to the first input end of the second MOS transistor.
  • the terminal is electrically connected in parallel to the second output terminal of the power supply unit, and the second input terminal of the second MOS transistor and the first input terminal of the third MOS transistor are electrically connected in parallel to the first input terminal of the power supply unit.
  • Three output terminals, the second input terminal of the third MOS transistor and one end of the signal output port are electrically connected in parallel to the fourth output terminal of the power supply unit, the output terminal of the first MOS transistor, the The output end of the second MOS transistor, the output end of the third MOS transistor, and the other end of the signal output port are electrically connected in parallel to the ground end, and the tampering signal transmission port is connected to the first input of the first MOS transistor. Terminal, the input terminal of the second MOS tube or the input terminal of the third MOS tube is electrically connected.
  • first resistor is provided between them, and the output terminal of the first MOS tube, the output terminal of the second MOS tube, and the output terminal of the third MOS tube are all grounded.
  • the tamper signal transmission port includes: a first signal transmission port and a second signal transmission port;
  • the first signal transmission port is electrically connected to the first input end of the first MOS transistor and the first input end of the second MOS transistor, and the second signal transmission port is electrically connected to the first input end of the third MOS transistor.
  • the input terminal is electrically connected; or
  • the first signal transmission port is electrically connected to the first input terminal of the first MOS transistor or the first input terminal of the second MOS transistor, and the second signal transmission port is electrically connected to the first input terminal of the third MOS transistor. Terminals are electrically connected.
  • the power supply unit includes: a diode and a charging and discharging capacitor.
  • the input terminal of the diode receives a voltage
  • the output terminal of the diode is electrically connected to one end of the charging and discharging capacitor and outputs a power supply voltage.
  • the other end of the charge and discharge capacitor is grounded.
  • the first MOS transistor, the second MOS transistor, and the third MOS transistor are all N-channel MOS transistors.
  • the embodiment of the present invention also provides another anti-tampering protection circuit, including: a switch trigger port, a tampering signal transmission port, a power supply unit, a first MOS tube, a second MOS tube, and a signal output port.
  • the tampering signal transmission port includes The first signal transmission port and the second signal transmission port, the first input end of the first MOS tube, the first signal transmission port, and the switch trigger port are electrically connected in parallel to the first output of the power supply unit Terminal, the second input terminal of the first MOS transistor, the first input terminal of the second MOS transistor, and the second signal transmission port are electrically connected in parallel to the second output terminal of the power supply unit, and the second The second input terminal of the MOS tube and one end of the signal output port are electrically connected in parallel to the third output terminal of the power supply unit, the output terminal of the first MOS tube, the output terminal of the second MOS tube, and The other end of the signal output port is electrically connected in parallel to the ground end.
  • a first resistor is provided between the first input terminal and the output terminal of the first MOS tube and between the first input terminal and the output terminal of the second MOS tube, and the first MOS tube The output terminal of the tube and the output terminal of the second MOS tube are both grounded.
  • the first MOS transistor and the second MOS transistor are both N-channel MOS transistors.
  • the first output terminal of the power supply unit, the second output terminal of the power supply unit, and the third output terminal of the power supply unit are all provided with a second resistor.
  • the power supply unit includes: a diode and a charging and discharging capacitor.
  • the input terminal of the diode receives a voltage
  • the output terminal of the diode is electrically connected to one end of the charging and discharging capacitor and outputs a power supply voltage.
  • the other end of the charge and discharge capacitor is grounded.
  • a power supply unit is set in the anti-tamper protection circuit.
  • the LED display When the LED display is powered off, the internal battery of the digital cinema server will continue to supply power to the digital cinema server to maintain the normal operation of the digital cinema server, and the power supply unit will also be protected against tampering
  • the circuit is powered to ensure the tamper-proof work of the tamper-proof protection circuit, thereby continuously protecting information security, maintaining digital copyright, and meeting the requirements of information processing standards.
  • FIG. 1 is a circuit diagram of a first anti-tampering protection circuit provided by an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a power supply unit provided by an embodiment of the present invention.
  • FIG. 3 is a circuit diagram of a second anti-tampering protection circuit provided by an embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a third anti-tampering protection circuit provided by an embodiment of the present invention.
  • Fig. 5 is a circuit diagram of a fourth anti-tampering protection circuit provided by an embodiment of the present invention.
  • the embodiments of the present invention provide several anti-tampering protection circuits.
  • a switch is set to trigger the port connection switch, the signal output port is connected to the digital movie server, the tamper signal transmission port is used to transmit the tamper signal, and the tamper signal is transmitted to the signal output port through the tamper signal transmission port.
  • the circuit structure and principle of these kinds of anti-tamper protection circuits will be described in detail below, and all the MOS transistors described below are N-channel MOS transistors.
  • the first input terminals of these MOS transistors are gates. Both input ends are drains, and both output ends are sources.
  • FIG. 1 is a circuit diagram of a first anti-tampering protection circuit provided by an embodiment of the present invention
  • FIG. 2 is a circuit diagram of a power supply unit provided by an embodiment of the present invention.
  • an embodiment of the present invention provides an anti-tampering protection circuit, including a switch trigger port (P1/P2), a tamper signal transmission port, a power supply unit, a first MOS transistor Q1, a second MOS transistor Q2, and a second MOS transistor.
  • the three MOS transistor Q3 and the signal output port P7 wherein the first input terminal of the first MOS transistor Q1 and one end of the switch trigger port P1/P2 are electrically connected in parallel to the first output terminal VCC_T of the power supply unit, and the switch trigger port P1/ The other end of P2 is grounded, the second input end of the first MOS transistor Q1 and the first input end of the second MOS transistor Q2 are electrically connected in parallel to the second output end VCC_T of the power supply unit, and the second input of the second MOS transistor Q2
  • the first input terminal of the third MOS transistor Q3 is electrically connected in parallel to the third output terminal VCC_T of the power supply unit, and the second input terminal of the third MOS transistor Q3 and one end of the signal output port P7 are electrically connected in parallel to the power supply unit
  • the signal transmission port is electrically connected to the first input terminal of the first MOS transistor Q1, the input terminal of the second MOS transistor Q2, or the input terminal of the third MOS transistor Q3.
  • the first output terminal VCC_T of the power supply unit, the second output terminal VCC_T of the power supply unit, the third output terminal VCC_T of the power supply unit, and the fourth output terminal VCC_T of the power supply unit are connected to the resistor R1, the resistor R2, and the resistor R3, respectively. And resistor R4, then connect to the circuit.
  • the switch at the switch trigger port when the switch at the switch trigger port is closed, the first MOS transistor Q1 is turned off, the second MOS transistor Q2 is turned on, and the third MOS transistor Q3 is turned off.
  • the signal output port P7 is in a high-impedance state, that is, driving The normally closed port of the digital cinema server is open, and the digital cinema server stops working; when the switch at the switch trigger port is turned off, the first MOS transistor Q1 is turned on, the second MOS transistor Q2 is turned off, and the third MOS transistor Q3 is turned on
  • the signal output port P7 is in the on state, that is, the normally closed port that drives the digital movie server is in the off state, and the digital movie server is working normally.
  • the internal battery of the digital cinema server will continue to supply power to the digital cinema server to maintain the normal operation of the digital cinema server, and the power supply unit will also be protected against tampering.
  • the circuit is powered to ensure the anti-tampering work of the anti-tamper protection circuit.
  • the power supply unit includes a diode D1 and charging and discharging capacitors C1 and C2, where C1 and C2 are connected in parallel, the input terminal of the diode D1 inputs the voltage VCC, and the output terminal of the diode D1 is connected to the charging and discharging capacitors respectively.
  • One end of C1/C2 is electrically connected and outputs the supply voltage VCC_T, and the other ends of the charge and discharge capacitors C1 and C2 are grounded.
  • a resistor R6 is provided between the first input end and the output end of the first MOS transistor Q1
  • a resistor R7 is provided between the first input end and the output end of the second MOS transistor Q2
  • the third MOS transistor Q3 is provided with a resistor R7.
  • a resistor R8 is arranged between an input terminal and an output terminal. The resistance values of R6, R7, and R8 are all about 10M ⁇ , and the output terminal of the first MOS transistor Q1, the output terminal of the second MOS transistor Q2, and the third MOS transistor Q3 The output terminals are all grounded.
  • the tampering signal transmission port includes a first signal transmission port P3/P4 and a second signal transmission port P5/P6, wherein the first signal transmission port P3/P4 is connected to the first signal transmission port of the first MOS transistor Q1 after passing through the resistor R5.
  • An input terminal is electrically connected to the first input terminal of the second MOS transistor Q2 through the resistor R11, and the second signal transmission port P5/P6 is electrically connected to the first input terminal of the third MOS transistor Q3 through the resistor R12.
  • the tamper-proof protection circuit provided in this embodiment is provided with a power supply unit.
  • the battery inside the digital cinema server will continue to supply power to the digital cinema server to maintain the normal operation of the digital cinema server.
  • the power supply unit It will also supply power to the anti-tamper protection circuit to ensure the anti-tamper work of the anti-tamper protection circuit, so as to continuously protect information security, maintain digital copyright, and meet the requirements of information processing standards.
  • FIG. 3 is a circuit diagram of a second anti-tampering protection circuit provided by an embodiment of the present invention.
  • the difference from Embodiment 1 is that the resistor R11 is omitted in this embodiment.
  • the first signal transmission port P3/P4 is only electrically connected to the first input terminal of the first MOS transistor Q1.
  • the two signal transmission ports P5/P6 are electrically connected to the first input terminal of the third MOS transistor Q3.
  • FIG. 4 is a circuit diagram of a third anti-tampering protection circuit provided by an embodiment of the present invention.
  • the difference from Embodiment 1 is that the resistor R5 is omitted in this embodiment.
  • the first signal transmission port P3/P4 is only electrically connected to the first input terminal of the second MOS transistor Q2.
  • the two signal transmission ports P5/P6 are electrically connected to the first input terminal of the third MOS transistor Q3.
  • FIG. 5 is a circuit diagram of a fourth anti-tampering protection circuit provided by an embodiment of the present invention.
  • this embodiment omits the first MOS transistor Q1 and the components associated with the first MOS transistor Q1 (such as resistors R2 and R6).
  • the first signal The transmission port P3/P4 is electrically connected between the switch trigger port (P1/P2) and the power supply unit through the resistor R5, and is electrically connected to the first input terminal of the second MOS transistor Q2 through the resistor R11.
  • one end of the first input terminal of the second MOS transistor Q2, the first signal transmission port P3/P4, and the switch trigger port P1/P2 are electrically connected in parallel to the first output terminal VCC_T of the power supply unit, and the switch trigger port P1/P2 Ground
  • the second input terminal of the second MOS transistor Q2, the second signal transmission port P5/P6 and the first input terminal of the third MOS transistor Q3 are electrically connected in parallel to the third output terminal VCC_T of the power supply unit
  • the second input terminal of Q3 and one end of the signal output port P7 are electrically connected in parallel to the fourth output terminal VCC_T of the power supply unit, the output terminal of the second MOS transistor Q2, the output terminal of the third MOS transistor Q3, and the signal output port P7
  • the other end is electrically connected to the ground terminal GND_T in parallel, and the first output terminal VCC_T of the power supply unit, the third output terminal VCC_T of the power supply unit, and the fourth output terminal VCC_T
  • the switch at the switch trigger port when the switch at the switch trigger port is closed, the second MOS transistor Q2 is turned off, and the third MOS transistor Q3 is turned on.
  • the signal output port P7 is in the on state, that is, the normally closed port of the digital cinema server is driven. In the off state, the digital cinema server works normally; when the switch at the switch trigger port is off, the second MOS transistor Q2 is turned on, and the third MOS transistor Q3 is turned off.
  • the signal output port P7 is in a high-impedance state, that is, driving digital The normally closed port of the movie server is open, and the digital movie server stops working.
  • the tamper-resistant protection circuit provided by any one of Embodiments 1 to 4 is mainly composed of two trigger points (P1/P2) and four transmission points. Point (P3/P4, P5/P6), a signal output point (P7) and charging and discharging capacitors.
  • the trigger points P1 and P2 are connected to the switch.
  • the trigger switch is opened and closed Switch between states, send a signal to P3/P4, and then transmit the signal from P3/P4 to P5/P6.
  • P7 connected to the digital cinema server will trigger the digital cinema server to be normally closed after receiving the signal transmitted via P5/P6
  • the state of the (NC) port changes the digital cinema server will immediately interrupt or resume the output of the film signal source after receiving the signal, and play a role in protecting digital copyright).
  • the tamper-proof protection circuit provided by any one of Embodiments 1 to 4 is provided on the HUB board of each LED box, and the transmission points P3/P4 and P5/P6 are connected in series in adjacent vertical and horizontal directions, respectively.
  • the tamper-proof protection circuit on the HUB board in the LED box When the entire screen of the LED display is working, if the back cover of the individual LED box is opened, causing the micro switch to be triggered, then a signal will be sent to the adjacent LED box, and the signal sent can pass through each LED box Between the horizontal and vertical interfaces (that is, transmission points P3/P4, P5/P6) transmission, and finally to the digital cinema server, the digital cinema server will also immediately interrupt the output of the film signal source after receiving the signal.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Multimedia (AREA)
  • Technology Law (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electronic Switches (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

本发明提供一种防篡改保护电路，包括开关触发端口、篡改信号传输端口、电源供电单元及信号输出端口，其中，开关触发端口连接开关，信号输出端口连接数字电影服务器，篡改信号传输端口用于传输篡改信号，篡改信号会通过篡改信号传输端口传输至信号输出端口。本发明在LED显示屏断电时，数字电影服务器内部的电池会继续为数字电影服务器供电以维持数字电影服务器的正常工作，电源供电单元也会为防篡改保护电路供电以保证防篡改保护电路的防篡改工作，从而能够持续地保护信息安全，维护数字版权，能够达到信息处理标准的要求。

Description

一种防篡改保护电路 技术领域
本发明涉及显示技术领域，尤其涉及一种防篡改保护电路。
 背景技术
目前，LED显示屏只有简单的箱门检测系统来监测箱门闭合状态，保护数据不被篡改，并且断电后不能持续监测箱门状态，无法持续有效的保护数字版权，达不到信息处理标准要求。
因此，LED显示屏需要设计专门的防篡改保护电路，在LED显示屏断电状态下，可以继续保护信息安全，维护数字版权，达到信息处理标准要求。
 技术问题
本发明所要解决的技术问题是：提供一种防篡改保护电路，解决现有技术中在LED显示屏断电状态下，无法持续保护信息安全的问题。
 技术解决方案
为了解决上述技术问题，本发明采用的技术方案为：
本发明实施例提供一种防篡改保护电路，包括：开关触发端口、篡改信号传输端口、电源供电单元、第一MOS管、第二MOS管、第三MOS管以及信号输出端口，所述第一MOS管的第一输入端与所述开关触发端口并联电连接于所述电源供电单元的第一输出端，所述第一MOS管的第二输入端与所述第二MOS管的第一输入端并联电连接于所述电源供电单元的第二输出端，所述第二MOS管的第二输入端与所述第三MOS管的第一输入端并联电连接于所述电源供电单元的第三输出端，所述第三MOS管的第二输入端与所述信号输出端口的一端并联电连接于所述电源供电单元的第四输出端，所述第一MOS管的输出端、所述第二MOS管的输出端、所述第三MOS管的输出端以及所述信号输出端口的另一端并联电连接于接地端，所述篡改信号传输端口与所述第一MOS管的第一输入端、所述第二MOS管的输入端或所述第三MOS管的输入端电连接。
在一些实施例中，所述第一MOS管的第一输入端与输出端之间、第二MOS管的第一输入端与输出端之间以及第三MOS管的第一输入端与输出端之间均设有第一电阻，且所述第一MOS管的输出端、第二MOS管的输出端以及第三MOS管的输出端均接地。
在一些实施例中，所述篡改信号传输端口包括：第一信号传输端口以及第二信号传输端口；
所述第一信号传输端口分别与所述第一MOS管的第一输入端以及所述第二MOS管的第一输入端电连接，所述第二信号传输端口与第三MOS管的第一输入端电连接；或者
所述第一信号传输端口与所述第一MOS管的第一输入端或所述第二MOS管的第一输入端电连接，所述第二信号传输端口与第三MOS管的第一输入端电连接。
在一些实施例中，所述电源供电单元包括：二极管以及充放电电容，所述二极管的输入端输入电压，所述二极管的输出端分别与充放电电容的一端电连接以及输出供电电压，所述充放电电容的另一端接地。
在一些实施例中，所述第一MOS管、所述第二MOS管及所述第三MOS管均为N沟道MOS管。
本发明实施例还提供另一种防篡改保护电路，包括：开关触发端口、篡改信号传输端口、电源供电单元、第一MOS管、第二MOS管以及信号输出端口，所述篡改信号传输端口包括第一信号传输端口及第二信号传输端口，所述第一MOS管的第一输入端、所述第一信号传输端口、所述开关触发端口并联电连接于所述电源供电单元的第一输出端，所述第一MOS管的第二输入端、所述第二MOS管的第一输入端以及第二信号传输端口并联电连接于所述电源供电单元的第二输出端，所述第二MOS管的第二输入端与所述信号输出端口的一端并联电连接于所述电源供电单元的第三输出端，所述第一MOS管的输出端、所述第二MOS管的输出端以及所述信号输出端口的另一端并联电连接于接地端。
在一些实施例中，所述第一MOS管的第一输入端与输出端之间以及第二MOS管的第一输入端与输出端之间均设有第一电阻，且所述第一MOS管的输出端以及第二MOS管的输出端均接地。
在一些实施例中，所述第一MOS管、所述第二MOS管均为N沟道MOS管。
在一些实施例中，所述电源供电单元的第一输出端、所述电源供电单元的第二输出端以及所述电源供电单元的第三输出端均设有第二电阻。
在一些实施例中，所述电源供电单元包括：二极管以及充放电电容，所述二极管的输入端输入电压，所述二极管的输出端分别与充放电电容的一端电连接以及输出供电电压，所述充放电电容的另一端接地。
 有益效果
从上述描述可知，与现有技术相比，本发明的有益效果在于：
在防篡改保护电路中设置电源供电单元，当LED显示屏断电时，数字电影服务器内部的电池会继续为数字电影服务器供电以维持数字电影服务器的正常工作，电源供电单元也会为防篡改保护电路供电以保证防篡改保护电路的防篡改工作，从而能够持续地保护信息安全，维护数字版权，能够达到信息处理标准的要求。
 附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，而不是全部实施例。对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本发明实施例提供的第一种防篡改保护电路的电路图；
图2为本发明实施例提供的电源供电单元的电路图；
图3为本发明实施例提供的第二种防篡改保护电路的电路图；
图4为本发明实施例提供的第三种防篡改保护电路的电路图；
图5为本发明实施例提供的第四种防篡改保护电路的电路图。
 本发明的实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。此外，下面所描述的本发明的各个实施方式中所涉及到的技术特征只要彼此之间未构成冲突就可以相互组合。
区别相关技术中在LED显示屏断电状态下，存在无法持续地保护信息安全的问题。为此，本发明实施例提供了几种防篡改保护电路。在这几种防篡改保护电路中，设置开关触发端口连接开关，信号输出端口连接数字电影服务器，篡改信号传输端口用于传输篡改信号，篡改信号会通过篡改信号传输端口传输至信号输出端口。下面将对这几种防篡改保护电路的电路结构、原理进行详细阐述，且下文所描述的所有MOS管均为N沟道的MOS管，这些MOS管的第一输入端均为栅极，第二输入端均为漏极，输出端均为源极。
实施例1
请参阅图1以及图2，图1为本发明实施例提供的第一种防篡改保护电路的电路图，图2为本发明实施例提供的电源供电单元的电路图。
如图1所示，本发明实施例提供一种防篡改保护电路，包括开关触发端口(P1/P2)、篡改信号传输端口、电源供电单元、第一MOS管Q1、第二MOS管Q2、第三MOS管Q3以及信号输出端口P7，其中，第一MOS管Q1的第一输入端与开关触发端口P1/P2的一端并联电连接于电源供电单元的第一输出端VCC_T，开关触发端口P1/P2的另一端接地，第一MOS管Q1的第二输入端与第二MOS管Q2的第一输入端并联电连接于电源供电单元的第二输出端VCC_T，第二MOS管Q2的第二输入端与第三MOS管Q3的第一输入端并联电连接于电源供电单元的第三输出端VCC_T，第三MOS管Q3的第二输入端与信号输出端口P7的一端并联电连接于电源供电单元的第四输出端VCC_T，第一MOS管Q1的输出端、第二MOS管Q2的输出端、第三MOS管Q3的输出端以及信号输出端口P7的另一端并联电连接于接地端GND_T，篡改信号传输端口与第一MOS管Q1的第一输入端、第二MOS管Q2的输入端或第三MOS管Q3的输入端电连接。电源供电单元的第一输出端VCC_T、电源供电单元的第二输出端VCC_T、电源供电单元的第三输出端VCC_T以及电源供电单元的第四输出端VCC_T分别接入电阻R1、电阻R2、电阻R3以及电阻R4后再接入电路。
在实际应用中，当开关触发端口处的开关闭合时，第一MOS管Q1截止，第二MOS管Q2导通，第三MOS管Q3截止，此时信号输出端口P7处于高阻状态，即驱动数字电影服务器的常闭端口为打开状态，数字电影服务器停止工作；当开关触发端口处的开关断开时，第一MOS管Q1导通，第二MOS管Q2截止，第三MOS管Q3导通，此时信号输出端口P7处于导通状态，即驱动数字电影服务器的常闭端口为关闭状态，数字电影服务器正常工作。基于此，当影院临时断电（也即LED显示屏断电）时，数字电影服务器内部的电池会继续为数字电影服务器供电以维持数字电影服务器的正常工作，电源供电单元也会为防篡改保护电路供电以保证防篡改保护电路的防篡改工作。
具体的，如图2所示，电源供电单元包括二极管D1以及充放电电容C1和C2，其中，C1与C2并联连接，二极管D1的输入端输入电压VCC，二极管D1的输出端分别与充放电电容C1/C2的一端电连接以及输出供电电压VCC_T，充放电电容C1和C2的另一端接地。应当理解，当LED显示屏断电时，充放电电容C1和C2均处于放电状态；当LED显示屏未断电时，充放电电容C1和C2均处于充电状态。
进一步的，第一MOS管Q1的第一输入端与输出端之间设有电阻R6，第二MOS管Q2的第一输入端与输出端之间设有电阻R7，第三MOS管Q3的第一输入端与输出端之间设有电阻R8，R6、R7、R8的阻值均约为10MΩ，且第一MOS管Q1的输出端、第二MOS管Q2的输出端以及第三MOS管Q3的输出端均接地。
更进一步的，篡改信号传输端口包括第一信号传输端口P3/P4以及第二信号传输端口P5/P6，其中，第一信号传输端口P3/P4分别通过电阻R5后与第一MOS管Q1的第一输入端以及通过电阻R11后与第二MOS管Q2的第一输入端电连接，第二信号传输端口P5/P6通过电阻R12后与第三MOS管Q3的第一输入端电连接。
本实施例提供的防篡改保护电路中，设置了电源供电单元，当LED显示屏断电时，数字电影服务器内部的电池会继续为数字电影服务器供电以维持数字电影服务器的正常工作，电源供电单元也会为防篡改保护电路供电以保证防篡改保护电路的防篡改工作，从而能够持续地保护信息安全，维护数字版权，能够达到信息处理标准的要求。
实施例2
请进一步参阅图3，图3为本发明实施例提供的第二种防篡改保护电路的电路图。
如图3所示，与实施例1不同的是，本实施例省去了电阻R11，此时，第一信号传输端口P3/P4只与第一MOS管Q1的第一输入端电连接，第二信号传输端口P5/P6与第三MOS管Q3的第一输入端电连接。
实施例3
请进一步参阅图4，图4为本发明实施例提供的第三种防篡改保护电路的电路图。
如图4所示，与实施例1不同的是，本实施例省去了电阻R5，此时，第一信号传输端口P3/P4只与第二MOS管Q2的第一输入端电连接，第二信号传输端口P5/P6与第三MOS管Q3的第一输入端电连接。
实施例4
请进一步参阅图5，图5为本发明实施例提供的第四种防篡改保护电路的电路图。
如图5所示，与实施例1不同的是，本实施例省去了第一MOS管Q1以及与第一MOS管Q1关联的元器件（如电阻R2、R6），此时，第一信号传输端口P3/P4通过电阻R5后电连接在开关触发端口(P1/P2)与电源供电单元之间，以及通过电阻R11后与第二MOS管Q2的第一输入端电连接。
也即第二MOS管Q2的第一输入端、第一信号传输端口P3/P4以及开关触发端口P1/P2的一端并联电连接于电源供电单元的第一输出端VCC_T，开关触发端口P1/P2接地，第二MOS管Q2的第二输入端、第二信号传输端口P5/P6与第三MOS管Q3的第一输入端并联电连接于电源供电单元的第三输出端VCC_T，第三MOS管Q3的第二输入端与信号输出端口P7的一端并联电连接于电源供电单元的第四输出端VCC_T，第二MOS管Q2的输出端、第三MOS管Q3的输出端以及信号输出端口P7的另一端并联电连接于接地端GND_T，且电源供电单元的第一输出端VCC_T、电源供电单元的第三输出端VCC_T、电源供电单元的第四输出端VCC_T分别接入电阻R1、电阻R3、电阻R4后再接入电路。
在实际应用中，当开关触发端口处的开关闭合时，第二MOS管Q2截止，第三MOS管Q3导通，此时信号输出端口P7处于导通状态，即驱动数字电影服务器的常闭端口为关闭状态，数字电影服务器正常工作；当开关触发端口处的开关断开时，第二MOS管Q2导通，第三MOS管Q3截止，此时信号输出端口P7处于高阻状态，即驱动数字电影服务器的常闭端口为打开状态，数字电影服务器停止工作。
从上文所描述的实施例1至实施例4可以看出，实施例1至实施例4任一实施例所提供的防篡改保护电路主要由两个触发点（P1/P2）、四个传输点（P3/P4、P5/P6）、一个信号输出点（P7）和充放电电容组成，其中，触发点P1、P2连接开关，当LED箱体门打开或关闭时触发开关在断开和闭合状态之间切换，发出信号到P3/P4，再由P3/P4传输信号到P5/P6，连接了数字电影服务器的P7在收到经由P5/P6传输的信号后会触发数字电影服务器的常闭（NC）端口的状态改变（数字电影服务器收到信号后会立即中断或恢复电影信号源的输出，起到保护数字版权的作用）。
实际上，实施例1至实施例4任一实施例所提供的防篡改保护电路设置在每一个LED箱体的HUB板上，传输点P3/P4、P5/P6分别串联相邻垂直和水平方向的LED箱体中的HUB板上的防篡改保护电路。在LED显示屏整屏工作时，如果个别LED箱体的后盖被打开，使得微动开关被触发，那么就会发出信号到相邻的LED箱体，所发出的信号可以通过各LED箱体间的水平和垂直接口（即传输点P3/P4、P5/P6）传输，最终传输到数字电影服务器，数字电影服务器收到信号后同样会立即中断电影信号源的输出。
需要说明的是，本发明内容中的各个实施例均采用递进的方式描述，每个实施例重点说明的都是与其他实施例的不同之处，各个实施例之间相同相似的部分互相参见即可。
还需要说明的是，在本发明内容中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
对所公开的实施例的上述说明，使本领域专业技术人员能够实现或使用本发明内容。对这些实施例的多种修改对本领域的专业技术人员来说将是显而易见的，本发明内容中所定义的一般原理可以在不脱离本发明内容的精神或范围的情况下，在其它实施例中实现。因此，本发明内容将不会被限制于本发明内容所示的这些实施例，而是要符合与本发明内容所公开的原理和新颖特点相一致的最宽的范围。

Claims (10)

  1. 一种防篡改保护电路，其特征在于，包括：开关触发端口、篡改信号传输端口、电源供电单元、第一MOS管、第二MOS管、第三MOS管以及信号输出端口，所述第一MOS管的第一输入端与所述开关触发端口并联电连接于所述电源供电单元的第一输出端，所述第一MOS管的第二输入端与所述第二MOS管的第一输入端并联电连接于所述电源供电单元的第二输出端，所述第二MOS管的第二输入端与所述第三MOS管的第一输入端并联电连接于所述电源供电单元的第三输出端，所述第三MOS管的第二输入端与所述信号输出端口的一端并联电连接于所述电源供电单元的第四输出端，所述第一MOS管的输出端、所述第二MOS管的输出端、所述第三MOS管的输出端以及所述信号输出端口的另一端并联电连接于接地端，所述篡改信号传输端口与所述第一MOS管的第一输入端、所述第二MOS管的输入端或所述第三MOS管的输入端电连接。
  2. 根据权利要求1所述的防篡改保护电路，其特征在于，所述第一MOS管的第一输入端与输出端之间、第二MOS管的第一输入端与输出端之间以及第三MOS管的第一输入端与输出端之间均设有第一电阻，且所述第一MOS管的输出端、第二MOS管的输出端以及第三MOS管的输出端均接地。
  3. 根据权利要求1所述的防篡改保护电路，其特征在于，所述篡改信号传输端口包括：第一信号传输端口以及第二信号传输端口；
    所述第一信号传输端口分别与所述第一MOS管的第一输入端以及所述第二MOS管的第一输入端电连接，所述第二信号传输端口与第三MOS管的第一输入端电连接；或者
    所述第一信号传输端口与所述第一MOS管的第一输入端或所述第二MOS管的第一输入端电连接，所述第二信号传输端口与第三MOS管的第一输入端电连接。
  4. 根据权利要求1所述的防篡改保护电路，其特征在于，所述电源供电单元包括：二极管以及充放电电容，所述二极管的输入端输入电压，所述二极管的输出端分别与充放电电容的一端电连接以及输出供电电压，所述充放电电容的另一端接地。
  5. 根据权利要求1所述的防篡改保护电路，其特征在于，所述第一MOS管、所述第二MOS管及所述第三MOS管均为N沟道MOS管。
  6. 一种防篡改保护电路，其特征在于，包括：开关触发端口、篡改信号传输端口、电源供电单元、第一MOS管、第二MOS管以及信号输出端口，所述篡改信号传输端口包括第一信号传输端口及第二信号传输端口，所述第一MOS管的第一输入端、所述第一信号传输端口、所述开关触发端口并联电连接于所述电源供电单元的第一输出端，所述第一MOS管的第二输入端、所述第二MOS管的第一输入端以及第二信号传输端口并联电连接于所述电源供电单元的第二输出端，所述第二MOS管的第二输入端与所述信号输出端口的一端并联电连接于所述电源供电单元的第三输出端，所述第一MOS管的输出端、所述第二MOS管的输出端以及所述信号输出端口的另一端并联电连接于接地端。
  7. 根据权利要求6所述的防篡改保护电路，其特征在于，所述第一MOS管的第一输入端与输出端之间以及第二MOS管的第一输入端与输出端之间均设有第一电阻，且所述第一MOS管的输出端以及第二MOS管的输出端均接地。
  8. 根据权利要求6所述的防篡改保护电路，其特征在于，所述第一MOS管、所述第二MOS管均为N沟道MOS管。
  9. 根据权利要求6所述的防篡改保护电路，其特征在于，所述电源供电单元的第一输出端、所述电源供电单元的第二输出端以及所述电源供电单元的第三输出端均设有第二电阻。
  10. 根据权利要求6所述的防篡改保护电路，其特征在于，所述电源供电单元包括：二极管以及充放电电容，所述二极管的输入端输入电压，所述二极管的输出端分别与充放电电容的一端电连接以及输出供电电压，所述充放电电容的另一端接地。
PCT/CN2021/083931 2020-04-30 2021-03-30 一种防篡改保护电路 WO2021218534A1 (zh)

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