WO2021218428A1 - 显示面板及其制作方法、显示装置 - Google Patents

显示面板及其制作方法、显示装置 Download PDF

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Publication number
WO2021218428A1
WO2021218428A1 PCT/CN2021/080166 CN2021080166W WO2021218428A1 WO 2021218428 A1 WO2021218428 A1 WO 2021218428A1 CN 2021080166 W CN2021080166 W CN 2021080166W WO 2021218428 A1 WO2021218428 A1 WO 2021218428A1
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WO
WIPO (PCT)
Prior art keywords
layer
touch
substrate
away
electrode
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PCT/CN2021/080166
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English (en)
French (fr)
Inventor
蒲世民
吴建君
汪江胜
张昌
刘奇
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/631,482 priority Critical patent/US11829541B2/en
Publication of WO2021218428A1 publication Critical patent/WO2021218428A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0412—Digitisers structurally integrated in a display
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/0416—Control or interface arrangements specially adapted for digitisers
    • G06F3/04164—Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0445—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04107—Shielding in digitiser, i.e. guard or shielding arrangements, mostly for capacitive touchscreens, e.g. driven shields, driven grounds
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
    • G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
    • G06F2203/04111—Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/40—OLEDs integrated with touch screens

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display panel, a manufacturing method thereof, and a display device.
  • OLED display devices have been widely used.
  • the touch function layer is disposed on the encapsulation layer of the OLED display panel.
  • the embodiments of the present disclosure provide a display panel, a manufacturing method thereof, and a display device.
  • a display panel including:
  • the adhesive force between the organic glue layer is configured to undergo a chemical reaction under preset catalytic conditions to form the transfer layer;
  • a touch structure disposed on a side of the transfer layer away from the substrate, and the touch structure is configured to detect the occurrence of a touch action.
  • the display panel further includes:
  • the insulating spacer layer includes a stack of one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
  • the predetermined catalytic conditions are UV curing conditions or moisture curing conditions.
  • the substrate includes a display area and a peripheral area surrounding the display area, the peripheral area includes a pad area on one side of the display area, and the touch structure includes:
  • One end of the touch signal line located in the peripheral area is connected to the touch electrode pattern, and the other end is connected to the pad.
  • the touch structure further includes a touch insulation layer
  • the touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes
  • the touch driving electrodes and the touch sensing electrodes are arranged to cross each other, the intersection of the touch driving electrodes and the touch sensing electrodes is insulated and spaced apart by the touch insulating layer, and each touch driving electrode is separated from each other by the touch insulating layer.
  • Each of the touch sensing electrodes is correspondingly connected to at least one of the touch signal lines.
  • the touch driving electrodes and the touch sensing electrodes are located in different layers.
  • the touch driving electrode includes: a plurality of driving electrode units arranged along a first direction, and a bridge portion connected between every two adjacent driving electrode units;
  • the touch sensing electrode includes: a plurality of sensing electrode units arranged in a second direction, and a connecting portion connected between every two adjacent sensing electrode units;
  • the first direction crosses the second direction
  • the driving electrode unit, the bridge portion, and the sensing electrode unit are all located on the side of the touch insulating layer away from the substrate and in the same layer It is provided that the connecting portion is located between the touch insulating layer and the packaging layer.
  • the touch structure further includes: a first ground line and a second ground line located in the peripheral area,
  • One end of the first ground wire is connected to a corresponding pad in the pad area, and the other end extends to a side of the display area away from the pad area;
  • One end of the second ground wire is connected to a corresponding pad in the pad area, and the other end extends to a side of the display area away from the pad area;
  • the first ground line and the second ground line form a semi-closed structure surrounding the display area, and each touch signal line is located between the first ground line and the second ground line.
  • the pad connected to the first ground wire and the pad connected to the second ground wire are both configured to load a ground signal.
  • the first ground wire includes a first ground portion
  • the second ground wire includes a second ground portion
  • both the first ground portion and the second ground portion are located far away from the display area.
  • the first grounding portion and the second grounding portion have no contact, and the first grounding portion and the second grounding portion overlap in a first direction, and the first direction is caused by the pad
  • the area points in the direction of the display area.
  • the touch control structure further includes: a first protection line and a second protection line,
  • One end of the first protection line is connected to a corresponding pad in the pad area, and the other end extends to a side of the display area away from the pad area;
  • One end of the second protection line is connected to a corresponding pad in the pad area, and the other end extends to a side of the display area away from the pad area;
  • the first protection line and the second protection line form a semi-closed structure surrounding the display area, and the first protection line is located between the touch signal line closest to the first ground line and the first ground Between the lines, the second protection line is located between the touch signal line closest to the second ground line and the second ground line.
  • the pads connected to the first protection line and the pads connected to the second protection line are both configured to load an alternating current signal.
  • the first protection line includes a first protection part
  • the second protection line includes a second protection part
  • both the first protection part and the second protection part are located far away from the display area.
  • the first protection part and the second protection part have no contact, and the first protection part and the second protection part do not overlap in a first direction, and the first direction is defined by the pad
  • the area points in the direction of the display area.
  • the display panel further includes:
  • the buffer layer is arranged on the substrate
  • the semiconductor layer is arranged on the side of the buffer layer away from the substrate;
  • the first gate insulating layer is arranged on the side of the semiconductor layer away from the substrate;
  • the first gate electrode layer is arranged on the side of the first gate insulating layer away from the substrate;
  • the second gate insulating layer is disposed on the side of the first gate electrode layer away from the substrate;
  • the second gate electrode layer is arranged on the side of the second gate insulating layer away from the substrate;
  • An interlayer insulating layer disposed on the side of the second gate electrode layer away from the substrate;
  • the first source-drain conductive layer is arranged on the side of the interlayer insulating layer away from the substrate;
  • a passivation layer arranged on the side of the first source-drain conductive layer away from the substrate;
  • the first planarization layer is disposed on the side of the passivation layer away from the substrate;
  • the second source-drain conductive layer is disposed on the side of the first planarization layer away from the substrate;
  • the second planarization layer is disposed on the side of the second source-drain conductive layer away from the substrate;
  • each of the plurality of light-emitting elements includes: a first electrode, a light-emitting layer, and a second electrode, the first electrode is located between the second planarization layer and the pixel defining layer, so The light-emitting layer is located on the side of the first electrode away from the substrate, the light-emitting layer is disposed in the corresponding pixel opening, the second electrode is located on the side of the light-emitting layer away from the substrate, and the multiple The second electrodes of the two light-emitting elements are connected as a whole to form a second electrode layer.
  • embodiments of the present disclosure provide a manufacturing method of a display panel, including:
  • a touch structure on the side of the organic glue layer away from the carrier board, the touch structure being configured to detect the occurrence of a touch action
  • Preset catalytic conditions are applied to the organic glue layer, so that the organic glue layer undergoes a chemical reaction to increase its viscosity, thereby forming a transfer layer, and the adhesion force between the transfer layer and the encapsulation layer is greater than that of the organic glue layer The adhesion between the layer and the encapsulation layer.
  • between the step of forming an organic glue layer on the carrier board and the step of forming a touch structure on the side of the organic glue layer away from the carrier board further includes:
  • An insulating spacer layer is formed, the density of the insulating spacer layer is greater than that of the organic glue layer, and a part of the insulating spacer layer exceeds the boundary of the organic glue layer, so that the insulating spacer layer exceeds the density of the organic glue layer.
  • the part of the boundary of the organic glue layer is connected to the carrying board;
  • the method further includes:
  • At least the part of the insulating spacer layer beyond the boundary of the organic glue layer is removed.
  • the step of removing at least a portion of the insulating spacer layer that exceeds the boundary of the organic glue layer includes:
  • the insulating spacer layer and the organic glue layer are cut along a predetermined cutting line, wherein the predetermined cutting line is located on a side of the boundary of the organic glue layer close to the center of the organic glue layer.
  • embodiments of the present disclosure also provide a display device, including the above-mentioned display panel.
  • FIG. 1 is a schematic structural diagram of a display panel provided in some embodiments of the present disclosure.
  • FIG. 2 is a plan view of a display panel provided in some embodiments of the present disclosure.
  • Fig. 3 is a cross-sectional view taken along the line AA' in Fig. 2;
  • Fig. 4 is a plan view of a display panel provided in other embodiments of the present disclosure.
  • Fig. 5 is a cross-sectional view taken along line BB' in Fig. 4;
  • FIG. 6 is a flowchart of a manufacturing method of a display panel provided in some embodiments of the present disclosure.
  • 7A to 7M are process schematic diagrams of a manufacturing method of a display panel provided in some embodiments of the present disclosure.
  • an element or layer when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on the other element or layer. It is directly connected to the other element or layer, or there may be an intermediate element or an intermediate layer. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intervening elements or layers.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • FIG. 1 is a schematic structural diagram of a display panel provided in some embodiments of the present disclosure.
  • the display panel includes a substrate SUB, a light-emitting structure layer 10, an encapsulation layer EPL, a transfer layer 20, and a touch structure 40.
  • the light-emitting structure The layer 10 includes a plurality of light-emitting elements, the plurality of light-emitting elements and the encapsulation layer EPL are disposed on the substrate SUB, and the plurality of light-emitting elements are located between the encapsulation layer EPL and the substrate SUB.
  • the light-emitting element may be an organic light-emitting diode (OLED), and the organic light-emitting diode may emit, for example, red light, green light, blue light, or white light.
  • OLED organic light-emitting diode
  • the encapsulation layer EPL is used to encapsulate the light-emitting element to prevent water vapor and/or oxygen in the external environment from corroding the light-emitting element.
  • the transfer layer 20 is arranged on the side of the encapsulation layer EPL away from the substrate SUB and is bonded to the encapsulation layer EPL.
  • the transfer layer 20 is a film formed by a chemical reaction of the organic glue layer on the encapsulation layer EPL under preset catalytic conditions.
  • the transfer layer 20 is more viscous, and the adhesive force between the transfer layer 20 and the encapsulation layer EPL is greater than the adhesive force between the organic glue layer and the encapsulation layer EPL. That is, the organic glue layer is configured to undergo a chemical reaction under preset catalytic conditions to form the transfer layer 20.
  • the organic glue layer undergoes a chemical reaction to increase its viscosity, thereby As a result, the adhesive force between the organic glue layer (that is, the transfer layer 20 described above) and the encapsulation layer EPL after the chemical reaction is increased.
  • the organic glue layer is an incompletely cured organic composite material film layer. Under a preset catalytic condition, the organic glue layer is further cured to form the transfer layer 20 described above.
  • the touch structure 40 is disposed on a side of the transfer layer 20 away from the substrate SUB, and the touch structure 40 is configured to detect the occurrence of a touch action.
  • the touch structure 40 includes a touch electrode pattern and a touch signal line.
  • the touch electrode pattern receives a touch drive signal and generates a touch sensing signal according to a touch action.
  • the touch structure 40 is configured to detect touch position, touch strength, and so on.
  • the conductive material needs to be etched to form the required pattern.
  • the touch structure 40 is directly formed on the packaging layer EPL, it is easy to cause damage to the packaging layer EPL and the structures between the packaging layer EPL and the substrate SUB during the etching process.
  • transparent conductive materials such as indium tin oxide (ITO) are used to make the touch electrode pattern
  • the indium tin oxide needs to be annealed at a high temperature to reduce the resistance of the touch electrode pattern.
  • indium tin oxide is annealed at a high temperature, it is also easy to cause damage to the packaging layer EPL and the structures between the packaging layer EPL and the substrate SUB.
  • the touch control structure 40 is disposed on the side of the transfer layer 20 away from the substrate SUB, and the transfer layer 20 is formed by a chemical reaction of the organic glue layer on the encapsulation layer EPL under preset catalytic conditions.
  • the adhesive force between the transfer layer 20 and the encapsulation layer EPL is greater than the adhesive force between the organic glue layer and the encapsulation layer EPL.
  • an organic glue layer with less viscosity can be formed on another carrier board, and then the touch structure 40 is formed on the organic glue layer, and then the organic glue layer and the touch structure 40 are transferred On the encapsulation layer EPL, and apply preset catalytic conditions to the organic glue layer, so that the organic glue layer is formed as a transfer layer 20 tightly connected to the encapsulation layer EPL.
  • the touch structure 40 is fabricated, the etching process or the high temperature annealing process of the touch structure 40 will not damage the packaging layer EPL and the film between the packaging layer EPL and the substrate SUB, which is beneficial to Improve the product yield of display panels.
  • the aforementioned predetermined catalytic conditions include light curing (for example, ultraviolet light curing) conditions or moisture curing conditions.
  • the display panel further includes an insulating spacer layer 30.
  • the density of the insulating spacer layer 30 is greater than that of the transfer layer 20.
  • the orthographic projection of the insulating spacer layer 30 on the substrate SUB and the transfer layer The orthographic projections of 20 on the substrate SUB overlap, and the touch structure 40 is disposed on the side of the insulating spacer layer 30 away from the transfer layer 20.
  • a denser insulating spacer layer 30 can be formed again, and a part of the insulating spacer layer 30 exceeds the boundary of the organic glue layer, so that the insulating spacer The part of the layer 30 beyond the boundary of the organic glue layer can be fixedly connected to the carrier board, and then the organic glue layer is fixed on the carrier board.
  • the organic glue layer is transferred to the encapsulation layer, at least the part of the insulating spacer layer 30 beyond the boundary of the organic glue layer is removed, so as to separate the organic glue layer from the carrier board.
  • FIG. 1 simply illustrates the positional relationship of the substrate SUB, the light-emitting structure layer 10 (ie, multiple light-emitting elements), the encapsulation layer EPL, the transfer layer 20, the insulating spacer layer 30, and the touch structure 40, and the substrate SUB It is not in direct contact with the light-emitting element, and other film structures are formed between the two, which will be described in detail below.
  • FIG. 2 is a plan view of a display panel provided in some embodiments of the present disclosure
  • FIG. 3 is a cross-sectional view along line AA' in FIG. 2
  • FIG. 4 is a plan view of a display panel provided in other embodiments of the present disclosure
  • FIG. 5 is A cross-sectional view taken along line BB' in FIG. 4, the display panel in the embodiment of the present disclosure will be introduced below in conjunction with FIG. 2 to FIG. 5.
  • the substrate SUB includes a display area DA and a peripheral area WA surrounding the display area DA.
  • the peripheral area WA includes a pad area BA on one side of the display area DA.
  • the touch structure 40 includes: pad PAD, touch pad Electrode patterns (such as touch driving electrodes TX and touch sensing electrodes RX in FIG. 2 and FIG. 4) and touch signal lines TL.
  • the pad PAD is located in the pad area BA
  • the touch electrode pattern is basically located in the display area DA
  • the touch signal line TL is located in the peripheral area WA.
  • One end of the touch signal line TL is connected to the touch electrode pattern, and the other end is connected to the pad PAD.
  • the pad PAD is not covered by any layer, which facilitates electrical connection to a flexible printed circuit board FPCB (Flexible Print Circuit Board).
  • the flexible printed circuit board FPCB is electrically connected to the touch drive chip, and is configured to transmit signals from the touch drive chip.
  • the touch signal line TL is electrically connected to the pad PAD and the touch electrode pattern, thereby realizing signal transmission between the touch electrode pattern and the flexible printed circuit board FPCB.
  • the touch electrode pattern may adopt a mutual capacitance type structure or a self-capacitance type structure.
  • the embodiments of the present disclosure take a mutual capacitance type structure as an example for description.
  • the touch structure 40 further includes a touch insulating layer TLD, and the material of the touch insulating layer TLD may include, for example, silicon oxide (SiOx), silicon nitride (SiNx) and/or silicon oxynitride ( SiON) is an inorganic material, and can be formed as a multilayer or a single layer.
  • the touch insulating layer TLD can also be made of organic materials.
  • the touch electrode pattern includes a plurality of touch driving electrodes TX and a plurality of touch sensing electrodes RX.
  • the touch driving electrode TX and the touch sensing electrode RX are arranged crosswise. The intersection of the touch driving electrode TX and the touch sensing electrode RX is insulated and separated by the touch insulation layer TLD.
  • Each touch driving electrode TX and each touch sensing The electrode RX is correspondingly connected to at least one touch signal line TL.
  • the cross position of the touch driving electrode TX and the touch sensing electrode RX forms a touch capacitance.
  • the touch driving chip sequentially provides touch driving signals to the pads PAD corresponding to the multiple touch driving electrodes TX.
  • each touch driving electrode TX sequentially loads a touch driving signal
  • the touch sensing electrode RX generates a corresponding sensing signal.
  • the touch driving electrode TX and the touch sensing electrode RX are located in different layers.
  • the touch driving electrodes TX and the touch sensing electrodes RX are both strip-shaped electrodes, and the touch insulating layer at least covers the display area.
  • both touch drive electrodes TX and touch sensing electrodes RX use transparent electrodes; or, both use metal mesh electrodes; or, one of the touch drive electrodes TX and touch sensing electrodes RX uses a transparent electrode, and the other Use metal mesh electrodes.
  • the transparent electrode is an electrode made of a transparent conductive material such as indium tin oxide (ITO), and the metal mesh electrode is a mesh metal made of a metal material such as aluminum or copper.
  • the touch driving electrode TX includes: a plurality of driving electrode units TX1 arranged along a first direction and connected between every two adjacent driving electrode units TX1
  • the bridge part TX2 The touch sensing electrode RX includes a plurality of sensing electrode units RX1 arranged along the second direction, and a connecting portion RX2 connected between every two adjacent sensing electrode units RX1.
  • the first direction crosses the second direction
  • the driving electrode unit TX1 and the touch sensing electrode RX are both located between the touch insulating layer TLD and the packaging layer EPL and arranged in the same layer
  • the bridge portion TX2 is located between the touch insulating layer TLD and the encapsulation layer EPL.
  • the first direction is the left-right direction in FIG. 2, and the second direction is the up-down direction in FIG. 2.
  • the touch driving electrodes TX and the touch sensing electrodes RX shown in FIG. 2 and FIG. 3 are only exemplary descriptions, and do not constitute a limitation of the present disclosure.
  • the connecting portion RX2 may be located on the side of the touch insulation layer TLD away from the substrate SUB, and the bridge portion TX2 may be located on the side of the touch insulation layer TLD close to the substrate SUB.
  • the adjacent drive electrode units TX1 are connected through the connecting portions RX2 provided in different layers, and the adjacent sensing electrode units RX1 are connected through the bridge portions TX2 of the same layer.
  • the driving electrode unit TX1 and the sensing electrode unit RX1 are both transparent electrodes, or the driving electrode unit TX1 and the sensing electrode unit RX1 are both metal mesh electrodes.
  • the bridge portion TX2 is made of the same material as the driving electrode unit TX1, and the connection portion RX2 can be made of metal material.
  • the touch structure 40 further includes: a first ground line GDL1 and a second ground line GDL2 located in the peripheral area WA.
  • One end of the first ground line GDL1 is connected to the corresponding pad PAD in the pad area BA, and the other end extends to a side of the display area DA away from the pad area BA.
  • One end of the second ground line GDL2 is connected to the corresponding pad PAD in the pad area BA, and the other end extends to a side of the display area DA away from the pad area BA.
  • the first ground line GDL1 and the second ground line GDL2 form a semi-closed structure surrounding the display area DA, and each touch signal line TL is located between the first ground line GDL1 and the second ground line GDL2.
  • the pad PAD connected to the first ground line GDL1 and the pad PAD connected to the second ground line GDL2 are both configured to load ground signals.
  • the pad PAD connected to the first ground line GDL1 and the second ground line GDL2 are all connected to the ground terminal on the touch drive chip, so as to prevent the touch electrode pattern and the touch signal line TL from being subjected to external electrostatic interference or other interference.
  • One end of the first ground line GDL1 not connected to the pad PAD and one end of the second ground line GDL2 not connected to the pad PAD are spaced apart.
  • the first ground line GDL1 includes a first ground portion located on the side of the display area DA away from the pad area BA, that is, the first ground portion is the first ground line GDL1 located in the display area DA in FIG.
  • the second ground line GDL2 includes a second ground portion located on the side of the display area DA away from the pad area BA, that is, the second ground portion is the second ground line GDL2 located above the display area DA in FIG. part.
  • the first grounding portion and the second grounding portion have no contact, and the first grounding portion and the second grounding portion overlap in a first direction, and the first direction is the direction from the pad area BA to the display area DA (ie , The direction from bottom to top in Figure 2). That is, a part of the second ground portion is located above the first ground portion.
  • the touch structure 40 further includes: a first guard line Guard1 and a second guard line Guard2.
  • One end of the first guard line Guard1 corresponds to the corresponding one in the pad area BA.
  • the pad PAD is connected, and the other end extends to the side of the display area DA away from the pad area BA.
  • One end of the second guard line Guard2 is connected to the corresponding pad PAD in the pad area BA, and the other end extends to a side of the display area DA away from the pad area BA.
  • the first guard line Guard1 and the second guard line Guard2 form a semi-closed structure surrounding the display area DA.
  • the first guard line Guard1 is located between the touch signal line TL closest to the first ground line GDL1 and the first ground line GDL1.
  • the second guard line Guard2 is located between the touch signal line TL closest to the second ground line GDL2 and the second ground line GDL2.
  • the pad PAD connected to the first guard line Guard1 and the pad PAD connected to the second guard line Guard2 are both configured to load an alternating current signal, which can be set by the touch driving chip according to the touch driving signal, In order to prevent the signal on the touch signal line TL from being interfered.
  • the first guard line Guard1 includes a first guard part located on the side of the display area DA away from the pad area BA, that is, the first guard part is the first guard line Guard1 in FIG. 2 located in the display area DA.
  • the second protection line Guard2 includes a second protection part located on the side of the display area DA away from the pad area BA, that is, the second protection part is the second protection line Guard2 located above the display area DA in FIG. part.
  • the first protection part and the second protection part have no contact, and the first protection part and the second protection part do not overlap in a first direction, and the first direction is defined by the pad area BA Point to the direction of the display area DA (ie, the direction from bottom to top in FIG. 2).
  • the substrate SUB is a flexible substrate SUB, which may be made of a flexible organic material, thereby facilitating the bending of the display panel.
  • the organic materials are resins such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate, and polyethylene naphthalate. Material.
  • the first buffer layer BFL1 is disposed on the substrate SUB to prevent or reduce the diffusion of metal atoms and/or impurities from the substrate SUB into the active layer of the transistor.
  • the first buffer layer BFL1 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and/or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.
  • the semiconductor layer is provided on the first buffer layer BFL1.
  • the material of the semiconductor layer may include, for example, inorganic semiconductor materials (for example, polysilicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials.
  • the semiconductor layer includes the active layer 51 of each transistor 50.
  • the active layer 51 includes a channel portion and a source bridge portion and a drain bridge portion located on both sides of the channel portion.
  • the source bridge portion is connected to the source 53 of the transistor 50.
  • the drain bridge is connected to the drain 54 of the transistor 50.
  • Both the source bridge portion and the drain bridge portion may be doped with impurities having a higher impurity concentration than the channel portion (for example, N-type impurities or P-type impurities).
  • the channel part is directly opposite to the gate 52 of the transistor 50. When the voltage signal loaded by the gate 52 reaches a certain value, a carrier path is formed in the channel part to make the source 53 and the drain 54 of the transistor 50 conductive. .
  • the first gate insulating layer GI1 is disposed on the semiconductor layer, and the material of the first gate insulating layer GI1 may include silicon compound and metal oxide.
  • the material of the first gate insulating layer GI1 includes silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx) , Aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc.
  • the first gate insulating layer GI1 may be a single layer or multiple layers.
  • the first gate electrode layer G1 is disposed on the first gate insulating layer GI1.
  • the first gate electrode layer G1 includes the gate 52 of each transistor 50, the first electrode plate 71 of the capacitor 70, and also includes a scan line (not shown).
  • the material of the first gate electrode layer G1 may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, and the like.
  • the first gate electrode layer G1 may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), nitrogen Tungsten (WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride ( TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), oxide Indium (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc.
  • the first gate electrode layer G1 may have a single layer or multiple
  • the second gate insulating layer GI2 is disposed on the first gate electrode layer G1, and the material of the second gate insulating layer GI2 may include, for example, silicon compound and metal oxide.
  • the material of the second gate insulating layer GI2 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx). ), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc.
  • the second gate insulating layer GI2 may be formed as a single layer or multiple layers.
  • the second gate electrode layer G2 is disposed on the second gate insulating layer GI2.
  • the second gate electrode layer G2 may include the second electrode plate 72 of the capacitor 70.
  • the material of the second gate electrode layer G2 may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, and the like.
  • the gate electrode layer may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride ( WNx), copper (Cu), copper alloys, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloys, titanium (Ti), titanium nitride (TiN x) , Platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide ( InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc.
  • the second gate electrode layer G2 may have
  • the interlayer insulating layer ILD is disposed on the second gate electrode layer G2, and the material of the interlayer insulating layer ILD may include, for example, silicon compound, metal oxide, and the like. Specifically, the silicon compounds and metal oxides listed above can be selected, which will not be repeated here.
  • the first source-drain conductive layer SD1 is disposed on the interlayer insulating layer ILD.
  • the first source-drain conductive layer SD1 may include the source 53 and the drain 54 of each transistor in the display area DA, the source 53 is electrically connected to the source bridge portion, and the drain 54 is electrically connected to the drain bridge portion.
  • the first source-drain conductive layer SD1 may include metal, alloy, metal nitride, conductive metal oxide, transparent conductive material, etc., for example, the first source-drain conductive layer SD1 may be a single layer or multiple layers of metal, such as Mo /Al/Mo or Ti/Al/Ti.
  • the first source-drain conductive layer SD1 may also include a first power line, a second power line, and a data line (not shown).
  • the gate line and the data line divide the display area into a plurality of pixel units.
  • a light-emitting element and a pixel drive circuit are provided.
  • the pixel drive circuit includes a plurality of transistors. The transistor shown in FIGS. 3 and 5 is one of the transistors in the pixel drive circuit.
  • the first power line is used to provide a high-level signal to the pixel circuit, and the second power line is used to provide a low-level signal to the light-emitting element.
  • the passivation layer PVX is disposed on the first source-drain conductive layer SD1, and the material of the passivation layer PVX may include a silicon compound, for example, silicon oxide, silicon nitride, or silicon oxynitride.
  • the first planarization layer PLN1 is disposed on the side of the passivation layer PVX away from the substrate SUB, and the surface of the first planarization layer PLN1 away from the substrate SUB is substantially flat.
  • the first planarization layer PLN1 is made of an organic insulating material, for example, the organic insulating material includes polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, silicon Resin materials such as oxane.
  • the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), and the like.
  • the second source-drain conductive layer SD2 is disposed on the side of the first planarization layer PLN1 away from the substrate SUB.
  • the second source-drain conductive layer SD2 may include the via electrode 60 located in the display area DA.
  • the transfer electrode 60 is electrically connected to the drain 54 through a via hole that penetrates the first planarization layer PLN1 and the passivation layer PVX, and at the same time, the transfer electrode 60 is also connected to the light-emitting element through a via hole that penetrates the second planarization layer PLN2.
  • the first electrode 51 is electrically connected.
  • the via electrode 60 can avoid directly forming via holes with relatively large diameters in the first planarization layer PLN1 and the second planarization layer PLN2, thereby improving the quality of the electrical connection of the vias.
  • the material of the second source-drain conductive layer SD2 may include metal, alloy, metal nitride, conductive metal oxide, or transparent conductive material, etc., for example, the second source-drain conductive layer SD2 may be a single layer or multiple layers of metal, such as It is Mo/Al/Mo or Ti/Al/Ti.
  • the material of the second source-drain conductive layer SD2 may be the same as or different from the material of the first source-drain conductive layer SD1.
  • the second planarization layer PLN2 is disposed on the second source-drain conductive layer SD2, the second planarization layer PLN2 covers the via electrode 60, and the upper surface of the second planarization layer PLN2 is substantially flat.
  • the second planarization layer PLN2 is made of an organic insulating material, for example, the organic insulating material includes polyimide, epoxy, acrylic, polyester, photoresist, polyacrylate, polyamide, silicon Resin materials such as oxane.
  • the organic insulating material includes elastic materials, such as urethane, thermoplastic polyurethane (TPU), and the like.
  • the material of the second planarization layer PLN2 may be the same as or different from the material of the first planarization layer PLN1.
  • the pixel defining layer PDL is disposed on a side of the second planarization layer PLN2 away from the substrate SUB.
  • the pixel defining layer PDL includes pixel openings corresponding to the light-emitting elements one-to-one.
  • the material of the pixel defining layer PDL may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenol resin.
  • the light-emitting element 11 includes a first electrode 11a, a light-emitting layer 11c, and a second electrode 11b.
  • the first electrode 11a is located between the second planarization layer PLN2 and the pixel defining layer.
  • the light-emitting layer 11c is located in the corresponding pixel opening.
  • 11b is located on the side of the light-emitting layer 11c away from the substrate.
  • the second electrodes 11b of all the light-emitting elements 11 in the display area DA are connected to form a second electrode layer.
  • the first electrode 11a is the anode of the light-emitting element
  • the second electrode 11b is the cathode.
  • the first electrode 11 a is electrically connected to the transfer electrode 60 through a via hole penetrating the second planarization layer PLN2, and is further electrically connected to the drain 54 of the transistor 50.
  • the first electrode 51 may be made of materials such as metals, metal alloys, metal nitrides, conductive metal oxides, and transparent conductive materials.
  • the first electrode 51 may have a single-layer or multi-layer structure. A part of the first electrode 51 is exposed by the pixel opening.
  • the light-emitting layer 11c may include small molecular organic materials or polymer molecular organic materials, may be fluorescent light-emitting materials or phosphorescent light-emitting materials, and may emit red light, green light, blue light, or white light.
  • the second electrode 11b is located on the side of the light-emitting layer 11c away from the substrate SUB, and the second electrode 11b can be made of metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, or the like.
  • the light emitting element 11 may adopt a top emission type structure or a bottom emission type structure.
  • the first electrode 11a When a top emission type structure is adopted, the first electrode 11a includes a conductive material with light reflection performance or includes a light reflection film, and the second electrode 11b includes a transparent or semi-transparent conductive material.
  • the second electrode 11b When a bottom emission type structure is adopted, the second electrode 11b is made of a conductive material with light reflective properties or includes a light reflective film, and the first electrode 11a includes a transparent or semi-transparent conductive material.
  • the light-emitting element 11 may also include other film layers.
  • it may also include: a hole injection layer and a hole transport layer located between the first electrode 11a and the light-emitting layer 11c, and a hole-injection layer and a hole transport layer located between the first electrode 11a and the light-emitting layer 11c; An electron transport layer and an electron injection layer between the two electrodes 11b.
  • the encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP.
  • the second inorganic encapsulation layer CVD2 is located on the side of the first inorganic encapsulation layer CVD1 away from the substrate SUB,
  • the organic encapsulation layer IJP is located between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2.
  • Both the first inorganic packaging layer CVD1 and the second inorganic packaging layer CVD2 can be made of highly dense inorganic materials such as silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx) and the like.
  • the organic encapsulation layer IJP can be made of a polymer material containing a desiccant, or a polymer material that can block water vapor.
  • a polymer resin can be used to relieve the stress of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, and it can also include water-absorbing materials such as desiccant to absorb substances such as water and oxygen that have penetrated into the interior.
  • the overcoat layer OC is disposed on the side of the touch structure 40 away from the substrate SUB.
  • the overlying layer OC covers the touch driving electrode TX, the touch sensing electrode RX, the touch signal line TL, the first ground line GDL1 and the second ground line GDL2.
  • the material of the overcoat layer OC may include an inorganic insulating material or an organic insulating material.
  • the flexible substrate SUB of the embodiment of the present disclosure is provided with a first gate insulating layer GI1, a second gate insulating layer GI2, and a buffer layer BFL.
  • a first gate insulating layer GI1 a second gate insulating layer GI2
  • a buffer layer BFL a buffer layer
  • the second planarization layer PNL2 and the transfer electrode 60 may be omitted.
  • the first electrode 11a is directly disposed on the first planarization layer PNL1 and is connected to the via hole on the PNL1.
  • the drain 54 is electrically connected.
  • Embodiments of the present disclosure also provide a manufacturing method of the above-mentioned display panel.
  • FIG. 6 is a flowchart of the manufacturing method of the display panel provided in some embodiments of the present disclosure. As shown in FIG. 6, the manufacturing method includes:
  • a touch structure is formed on the side of the organic glue layer away from the carrier board, and the touch structure is configured to detect the occurrence of a touch action.
  • the touch structure is directly fabricated on the packaging layer. Therefore, the etching process and high temperature annealing process of the touch structure will not cause damage to the packaging layer and the film layer between the packaging layer and the substrate. This is beneficial to improve the product yield of the display panel.
  • step S13 and steps S11 and S12 is not particularly limited, and step S13 can be performed before steps S11 to S12, or can be performed after steps S11 to S12.
  • the predetermined catalytic conditions include light curing (for example, ultraviolet light curing) conditions or moisture curing conditions.
  • the carrying plate is made of a material with higher strength and higher temperature resistance, for example, the carrying plate is a glass substrate.
  • step S13 and step S14 further include: S131, forming an insulating spacer layer, the density of the insulating spacer layer is greater than that of the organic glue layer, and a part of the insulating spacer layer exceeds the boundary of the organic glue layer, The part of the insulating spacer layer beyond the boundary of the organic glue layer is connected to the carrier board, so that the insulating spacer layer and the organic glue layer are stably fixed on the carrier board, so as to form a touch control structure.
  • the insulating spacer layer includes a stack of one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
  • the insulating spacer layer is formed by plasma enhanced chemical vapor deposition (PECVD).
  • Step S14 and step S15 further include: S141, removing at least the part of the insulating spacer layer beyond the boundary of the organic glue layer, so as to separate the organic glue layer from the carrier board.
  • step S141 specifically includes: cutting the insulating spacer layer and the organic glue layer along a predetermined cutting line, where the cutting line is located inside the boundary of the organic glue layer.
  • FIGS. 7A to 7M are process schematic diagrams of the manufacturing method of the display panel provided in some embodiments of the present disclosure. As shown in FIGS. 7A to 7M, the manufacturing method of the display panel includes:
  • a semiconductor layer is formed on the side of the buffer layer BFL away from the substrate SUB.
  • the semiconductor layer includes an active layer 51 of each transistor.
  • the active layer 51 includes a channel portion and a source bridge portion and a drain bridge portion located on both sides of the channel portion.
  • sputtering thermal evaporation, plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), and atmospheric pressure chemical vapor deposition (PECVD) are used.
  • the semiconductor layer is formed by processes such as APCVD or electron cyclotron resonance chemical vapor deposition (ECR-CVD).
  • a first gate insulating layer GI1 is formed on the side of the semiconductor layer away from the substrate SUB; then, a first gate electrode layer G1 is formed on the side of the first gate insulating layer GI1 away from the substrate SUB; After that, a second gate insulating layer GI2 is formed on the side of the first gate electrode layer G1 away from the substrate SUB; then, a second gate electrode layer G2 is formed on the side of the second gate insulating layer GI2 away from the substrate SUB; An interlayer insulating layer ILD is formed on the side of the second gate electrode layer G2 away from the substrate SUB; then, a first source-drain conductive layer SD1 is formed on the side of the interlayer insulating layer ILD away from the substrate SUB.
  • the first gate electrode layer G1 includes the gate 52 of each transistor 50 and the first electrode plate 71 of the capacitor 70.
  • the second gate electrode layer may include the second electrode plate 72 of the capacitor 70.
  • the materials of the first gate insulating layer GI1, the first gate electrode layer G1, the second gate insulating layer GI2, the second gate electrode layer G2, the interlayer insulating layer ILD, and the first source-drain conductive layer SD1 are all referred to above Description, I won’t repeat it here.
  • a physical vapor deposition method such as magnetron sputtering is used to form the first gate electrode layer G1, the second gate electrode layer G2, and the first source-drain conductive layer SD1.
  • PECVD is used to form the first gate insulating layer, the second gate insulating layer GI2, and the interlayer insulating layer ILD.
  • the first source-drain conductive layer SD1 may include the source 53 and the drain 54 of each transistor in the display area.
  • the source 53 passes through the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1.
  • the hole is connected to the source bridge portion of the active layer 51, and the drain 54 is connected to the drain bridge portion of the active layer 51 through the via hole penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1 connect.
  • a passivation layer PVX is formed on the side of the first source-drain conductive layer SD1 away from the substrate SUB, and then a first planarization layer PLN1 is formed.
  • a second source-drain conductive layer SD2 is formed on the side of the first planarization layer PLN1 away from the substrate SUB.
  • the second source-drain conductive layer SD2 includes a transit electrode 60, and the transit electrode 60 is electrically connected to the drain 54 through a via hole penetrating the first planarization layer PLN1 and the passivation layer PVX.
  • the material of the second source-drain conductive layer SD2 refer to the above description, which will not be repeated here.
  • a second planarization layer PLN2 is formed on the side of the second source-drain conductive layer SD2 away from the substrate SUB.
  • the first electrode 11a of each of the plurality of light-emitting elements is formed.
  • the first electrode 11a is connected to the via electrode 60 through a via hole on the second planarization layer PLN2.
  • a pixel defining layer PDL is formed on the side of the second planarization layer PLN2 away from the substrate SUB, and the pixel defining layer PDL includes pixel openings V corresponding to the light emitting elements one-to-one.
  • the first electrode 11a of the light-emitting element is located between the second planarization layer PLN2 and the pixel defining layer PDL, and a part of the first electrode 11a is exposed by the corresponding pixel opening V.
  • the light-emitting layer 11c of each light-emitting element 11 of the plurality of light-emitting elements 11 is formed.
  • the light-emitting layer 11c is located on the side of the first electrode 11a away from the substrate SUB, and the light-emitting layer 11c is located in the corresponding pixel opening. .
  • the light-emitting layer 11c can be formed by vapor deposition.
  • the second electrode 11b of each of the plurality of light-emitting elements 11 is formed, and the second electrodes 11b of the plurality of light-emitting elements 11 are connected as a whole to form a second electrode layer.
  • the steps of forming a plurality of light-emitting elements are steps S21g and S21i.
  • the second source-drain conductive layer SD2, the first electrode 11a, and the second electrode 11b can be formed by a physical vapor deposition method such as magnetron sputtering.
  • the first planarization layer PLN1, the second planarization layer PLN2, and the pixel defining layer PDL may be formed by inkjet printing.
  • an encapsulation layer EPL is formed on the side of the plurality of light-emitting elements 11 away from the substrate SUB.
  • the encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP located between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2.
  • an organic glue layer 21 and an insulating spacer layer 30 are sequentially formed on the carrier board 80.
  • the density of the insulating spacer layer 30 is greater than that of the organic glue layer 21, and a part of the insulating spacer layer 30 exceeds
  • the boundary of the organic glue layer 21 is such that the part of the insulating spacer layer 30 beyond the boundary of the organic glue layer 21 is connected to the carrier board 80.
  • the insulating spacer layer includes a stack of one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.
  • a touch structure 40 is formed on the side of the insulating spacer layer 30 away from the carrier plate 80.
  • the touch structure 40 is shown in FIG. 2 and FIG. 4, and includes a pad PAD, a touch electrode pattern (that is, touch driving electrodes TX and touch sensing electrodes RX), touch signal lines TL, and touch insulation Tier TLD.
  • step S24 includes: forming a pad PAD, a touch electrode pattern, and a touch signal line TL on the side of the insulating spacer layer 30 away from the carrier board 80.
  • the pad PAD is located in the position of the organic glue layer 21 corresponding to the pad area PAD; one end of each touch signal line TL of the plurality of touch signal lines TL is connected to the touch electrode pattern, and the other end is connected to the pad PAD .
  • the touch electrode pattern includes a plurality of touch driving electrodes TX and a plurality of touch sensing electrodes RX, and the touch driving electrodes TX and the touch sensing electrodes RX are intersectedly arranged and spaced apart. Each touch driving electrode TX and each touch sensing electrode RX are correspondingly connected to at least one touch signal line TL.
  • Step S24 further includes: forming the touch insulation layer TLD in FIG. 2 or FIG. 5, and the intersection of the touch driving electrode TX and the touch sensing electrode RX is insulated and separated by the touch insulation layer TLD.
  • the touch driving electrode TX and the touch sensing electrode RX are located in different layers.
  • the touch driving electrode TX includes: a plurality of driving electrode units TX1 arranged in a first direction, and a bridge portion connected between every two adjacent driving electrode units TX1 TX2.
  • the touch sensing electrode RX includes a plurality of sensing electrode units RX1 arranged along the second direction, and a connecting portion RX2 connected between every two adjacent sensing electrode units RX1.
  • the first direction crosses the second direction
  • the driving electrode unit TX1 and the touch sensing electrode RX are both located between the touch insulating layer TLD and the packaging layer EPL
  • the connecting portion RX2 is located between the touch insulating layer TLD and the packaging layer EPL
  • the driving electrode unit TX1 is formed before the bridge portion TX2.
  • step S25 further includes: forming a first ground line and a second ground line, and forming a first ground line and a second ground line.
  • the position and connection relationship of the first ground line and the second ground line are shown in Figures 3 and 5.
  • One end of the first ground line GDL1 is connected to the corresponding pad PAD, and the other end extends to the touch electrode pattern away from the pad.
  • each touch signal line TL is located between the first ground line GDL1 and the second ground line GDL2.
  • step S24 may further include: forming a first protection line Guard1 and a second protection line Guard2.
  • the connection relationship between the first protection line Guard1 and the second protection line Guard2 has been described above, and will not be repeated here.
  • the first protection line Guard1 and the second protection line Guard2 can be made synchronously with the first ground line GDL1 and the second ground line GDL2.
  • this step S25 includes: cutting the insulating spacer layer 30 and the organic glue layer 21 along a predetermined cutting line CL, where the predetermined cutting line CL is located near the boundary of the organic glue layer 21. One side of the center of the organic glue layer.
  • the overcoat layer OC is formed.
  • the overcoat layer OC can also be formed before step S26.
  • An embodiment of the present disclosure also provides a display device, which includes the display panel of any one of the foregoing embodiments.
  • the display device can be any product or component with a display function, such as an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

Abstract

一种显示面板及其制作方法、显示装置，所述显示面板包括：基板（SUB）；设置在所述基板（SUB）上的多个发光元件和封装层（EPL），所述多个发光元件位于所述封装层（EPL）与所述基板（SUB）之间；设置在所述封装层（EPL）远离所述基板（SUB）一侧、且与所述封装层（EPL）粘结的转移层（20），所述转移层（20）与所述封装层（EPL）之间的粘结力大于有机胶层与所述封装层（EPL）之间的粘结力，所述有机胶层被配置为在预设催化条件下发生化学反应而形成为所述转移层（20）；设置在所述转移层（20）远离所述基板（SUB）一侧的触控结构（40），所述触控结构（40）被配置为检测触摸动作的发生。

Description

显示面板及其制作方法、显示装置
本申请要求申请日为2020年4月29日、申请号为“202010359499.0”、发明名称为“显示面板及其制作方法、显示装置”的优先权。
技术领域
本公开涉及显示技术领域，具体涉及一种显示面板及其制作方法、显示装置。
背景技术
随着有机发光二极管(Organic Light Emitting Display，OLED)显示技术的发展，OLED显示装置得到广泛应用。为了满足用户对于产品厚度及触控体验的需求，在一种生产工艺中，将触控功能层设置在OLED显示面板的封装层上。
发明内容
本公开实施例提供一种显示面板及其制作方法和显示装置。
根据本公开的第一方面，提供一种显示面板，包括：
基板；
设置在所述基板上的多个发光元件和封装层，所述多个发光元件位于所述封装层与所述基板之间；
设置在所述封装层远离所述基板一侧、且与所述封装层粘结的转移层，所述转移层与所述封装层之间的粘结力大于有机胶层与所述封装层之间的粘结力，所述有机胶层被配置为在预设催化条件下发生化学反应而形成为所述转移层；
设置在所述转移层远离所述基板一侧的触控结构，所述触控结构被配置为检测触摸动作的发生。
在一些实施例中，所述显示面板还包括：
设置在所述转移层远离所述基板一侧的绝缘间隔层，所述绝缘间隔层的致密度大于所述转移层的致密度，所述绝缘间隔层在所述基板上的正投影与所述转移层在所述基板上的正投影重合，所述触控结构设置在所述绝缘间隔层远离所述转移层的一侧。
在一些实施例中，所述绝缘间隔层包括硅的氮化物层、硅的氧化物层、硅的氮氧化物层中的一者或多者的叠层。
在一些实施例中，所述预设催化条件为紫外光固化条件或湿气固化条件。
在一些实施例中，所述基板包括显示区和环绕所述显示区的外围区，所述外围区包括位于显示区一侧的焊盘区，所述触控结构包括：
位于所述焊盘区的焊盘；
触控电极图形；
位于所述外围区的触控信号线，所述触控信号线的一端连接所述触控电极图形，另一端连接所述焊盘。
在一些实施例中，所述触控结构还包括触控绝缘层，所述触控电极图形包括多个触控驱动电极和多个触控感应电极，
所述触控驱动电极与触控感应电极交叉设置，所述触控驱动电极与所述触控感应电极交叉处被所述触控绝缘层绝缘间隔开，每个所述触控驱动电极和每个所述触控感应电极均对应连接至少一条所述触控信号线。
在一些实施例中，所述触控驱动电极和所述触控感应电极位于不同层中。
在一些实施例中，所述触控驱动电极包括：沿第一方向排列的多个驱动电极单元、以及连接在每相邻两个所述驱动电极单元之间的桥接部；
所述触控感应电极包括：沿第二方向排列的多个感应电极单元、以及连接在每相邻两个所述感应电极单元之间的连接部；
其中，所述第一方向与所述第二方向相交叉，所述驱动电极单元、所述桥接部和所述感应电极单元均位于所述触控绝缘层远离所述基板的一侧且同层设置，所述连接部位于所述触控绝缘层与所述封装层之间。
在一些实施例中，所述触控结构还包括：位于外围区的第一接地线和第二接地线，
所述第一接地线的一端与所述焊盘区中相应的焊盘连接，另一端延伸至所述显示区远离所述焊盘区的一侧；
所述第二接地线的一端与所述焊盘区中相应的焊盘连接，另一端延伸至所述显示区远离所述焊盘区的一侧；
所述第一接地线与所述第二接地线形成环绕所述显示区的半封闭结构，每条所述触控信号线均位于所述第一接地线和所述第二接地线之间。
在一些实施例中，所述第一接地线所连接的焊盘和所述第二接地线所连接的焊盘均被配置为加载接地信号。
在一些实施例中，所述第一接地线包括第一接地部，所述第二接地线包括第二接地部，所述第一接地部和所述第二接地部均位于所述显示区远离所述焊盘区的一侧，
所述第一接地部和所述第二接地部无接触，且所述第一接地部和所述第二接地部在第一方向上存在交叠，所述第一方向为由所述焊盘区指向所述显示区的方向。
在一些实施例中，所述触控结构还包括：第一防护线和第二防护线，
所述第一防护线的一端与所述焊盘区中的相应的焊盘连接，另一端延伸至所述显示区远离所述焊盘区的一侧；
所述第二防护线的一端与所述焊盘区中的相应的焊盘连接，另一端延伸至所述显示区远离所述焊盘区的一侧；
所述第一防护线和所述第二防护线形成环绕所述显示区的半封闭结构，所述第一防护线位于最靠近所述第一接地线的触控信号线与所述第一接地线之间，所述第二防护线位于最靠近所述第二接地线的触控信号线与所述第二接地线之间。
在一些实施例中，所述第一防护线所连接的焊盘和所述第二防护线所连接的焊盘均被配置为加载交流电信号。
在一些实施例中，所述第一防护线包括第一防护部，所述第二防护线包括第二防护部，所述第一防护部和所述第二防护部均位于所述显示区远离所述焊盘区的一侧，
所述第一防护部和所述第二防护部无接触，且所述第一防护部和所述第二防护部在第一方向上无交叠，所述第一方向为由所述焊盘区指向所述显示区的方向。
在一些实施例中，所述显示面板还包括：
缓冲层，设置在所述基板上；
半导体层，设置在所述缓冲层远离所述基板的一侧；
第一栅绝缘层，设置在所述半导体层远离所述基板的一侧；
第一栅电极层，设置在所述第一栅绝缘层远离所述基板的一侧；
第二栅绝缘层，设置在所述第一栅电极层远离所述基板的一侧；
第二栅电极层，设置在所述第二栅绝缘层远离所述基板的一侧；
层间绝缘层，设置在所述第二栅电极层远离所述基板的一侧；
第一源漏导电层，设置在所述层间绝缘层远离所述基板的一侧；
钝化层，设置在所述第一源漏导电层远离所述基板的一侧；
第一平坦化层，设置在所述钝化层远离所述基板的一侧；
第二源漏导电层，设置在所述第一平坦化层远离所述基板的一侧；
第二平坦化层，设置在所述第二源漏导电层远离所述基板的一侧；
像素界定层，设置在所述第二平坦化层远离所述基板的一侧，所述像 素界定层包括与所述发光元件一一对应的像素开口；
其中，所述多个发光元件中的每个发光元件包括：第一电极、发光层和第二电极，所述第一电极位于所述第二平坦化层与所述像素界定层之间，所述发光层位于所述第一电极远离所述基板的一侧，所述发光层设置在相应的像素开口中，所述第二电极位于所述发光层远离所述基板的一侧，所述多个发光元件的第二电极连接为一体，形成第二电极层。
第二方面，本公开实施例提供一种显示面板的制作方法，包括：
在基板上形成多个发光元件；
在所述多个发光元件远离所述基板的一侧形成封装层；
在承载板上形成有机胶层；
在所述有机胶层远离所述承载板的一侧形成触控结构，所述触控结构被配置为检测触摸动作的发生；
将所述有机胶层与所述承载板分离，并将所述有机胶层和所述触控结构转移至所述封装层上；
向所述有机胶层施加预设催化条件，以使所述有机胶层发生化学反应而粘性增强，从而形成为转移层，所述转移层与所述封装层之间的粘结力大于有机胶层与封装层之间的粘结力。
在一些实施例中，所述在承载板上形成有机胶层的步骤与所述在所述有机胶层远离所述承载板的一侧形成触控结构的步骤之间还包括：
形成绝缘间隔层，所述绝缘间隔层的致密度大于所述有机胶层的致密度，且所述绝缘间隔层的一部分超出所述有机胶层的边界，以使所述绝缘间隔层超出所述有机胶层边界的部分与所述承载板连接；
所述在有机胶层远离所述承载板的一侧形成触控结构的步骤与所述将有机胶层与所述承载板分离的步骤之间，还包括：
至少将所述绝缘间隔层超出所述有机胶层边界的部分去除。
在一些实施例中，至少将所述绝缘间隔层超出所述有机胶层边界的部 分去除的步骤包括：
沿预设切割线对所述绝缘间隔层和所述有机胶层切割，其中，所述预设切割线位于所述有机胶层边界的靠近所述有机胶层中心的一侧。
第三方面，本公开实施例还提供一种显示装置，包括上述显示面板。
附图说明
附图是用来提供对本公开的进一步理解，并且构成说明书的一部分，与下面的具体实施方式一起用于解释本公开，但并不构成对本公开的限制。在附图中：
图1为本公开的一些实施例中提供的显示面板的结构示意图。
图2为本公开的一些实施例中提供的显示面板的平面图。
图3为沿图2中AA’线的剖视图。
图4本公开的另一些实施例中提供的显示面板的平面图。
图5为沿图4中BB'线的剖视图。
图6为本公开的一些实施例中提供的显示面板的制作方法流程图。
图7A至图7M为本公开的一些实施例中提供的显示面板的制作方法的过程示意图。
具体实施方式
以下结合附图对本公开的具体实施方式进行详细说明。应当理解的是，此处所描述的具体实施方式仅用于说明和解释本公开，并不用于限制本公开。
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。 基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
这里用于描述本公开的实施例的术语并非旨在限制和/或限定本公开的范围。例如，除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。应该理解的是，本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。除非上下文另外清楚地指出，否则单数形式“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现在“包括”或者“包含”前面的元件或者物件涵盖出现在“包括”或者“包含”后面列举的元件或者物件及其等同，并不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则所述相对位置关系也可能相应地改变。
在下面的描述中，当元件或层被称作“在”另一元件或层“上”或“连接到”另一元件或层时，该元件或层可以直接在所述另一元件或层上、直接连接到所述另一元件或层，或者可以存在中间元件或中间层。然而，当元件或层被称作“直接在”另一元件或层“上”、“直接连接到”另一元件或层时，不存在中间元件或中间层。术语“和/或”包括一个或更多个相关列出项的任意和全部组合。
图1为本公开的一些实施例中提供的显示面板的结构示意图，如图1所示，显示面板包括基板SUB、发光结构层10、封装层EPL、转移层20和触控结构40，发光结构层10包括多个发光元件，多个发光元件和封装层EPL设置在基板SUB上，多个发光元件位于封装层EPL与基板SUB之间。发光元件可以为有机发光二极管(Organic Light-Emitting Diode，OLED)， 有机发光二极管可以发射例如红光、绿光、蓝光或白光。封装层EPL用于对发光元件进行封装，以防止外界环境中的水汽和/或氧气侵蚀发光元件。
转移层20设置在封装层EPL远离基板SUB一侧且与封装层EPL粘结，转移层20为位于封装层EPL上的有机胶层在预设催化条件下发生化学反应而形成的膜层。转移层20的粘性更大，转移层20与封装层EPL之间的粘结力大于有机胶层与封装层EPL之间的粘结力。即，有机胶层被配置为在预设催化条件下发生化学反应而形成为转移层20。在未施加预设催化条件的情况下，有机胶层与封装层EPL之间无粘结力或粘结力较小；在施加预设催化条件后，有机胶层发生化学反应而粘性增强，从而使得发生化学反应后的有机胶层(即上述转移层20)与封装层EPL之间的粘结力增大。例如，有机胶层为未完全固化的有机复合材料膜层，在预设催化条件下，有机胶层进一步固化，形成为上述转移层20。
触控结构40设置在转移层20远离基板SUB的一侧，触控结构40被配置为检测触摸动作的发生。例如，触控结构40包括触控电极图形、触控信号线，触控电极图形接收触控驱动信号，并根据触摸动作产生触控感应信号。例如触控结构40被配置为检测触摸位置、触摸力度等等。
在触控电极图形和触控信号线的形成过程中，需要对导电材料进行刻蚀，以形成所需要的图形。当触控结构40直接形成在封装层EPL上时，刻蚀过程中容易对封装层EPL及其与基板SUB之间的各结构造成损伤。并且，当采用氧化铟锡(ITO)等透明导电材料制作触控电极图形时，需要对氧化铟锡进行高温退火，以降低触控电极图形的电阻。对氧化铟锡进行高温退火时，也很容易对封装层EPL及其与基板SUB之间的各结构造成损伤。
在本公开实施例中，触控结构40设置在转移层20远离基板SUB的一侧，并且，转移层20由位于封装层EPL上的有机胶层在预设催化条件下发生化学反应而形成，转移层20与封装层EPL之间的粘结力大于有机胶层与封装层EPL之间的粘结力。因此，在显示面板的制作过程中，可以先在另 外的承载板上形成粘性较小的有机胶层，再在有机胶层上形成触控结构40，之后将有机胶层和触控结构40转移至封装层EPL上，并向有机胶层施加预设催化条件，以使有机胶层形成为紧密连接在封装层EPL上的转移层20。这种情况下，在制作触控结构40时，触控结构40的刻蚀过程或高温退火过程并不会对封装层EPL及封装层EPL与基板SUB之间的膜层造成损伤，从而有利于提高显示面板的产品良率。
在一些实施例中，上述预设催化条件包括光固化(例如，紫外光照固化)条件或湿气固化条件。
在一些实施例中，如图1所示，显示面板还包括绝缘间隔层30，绝缘间隔层30的致密度大于转移层20的致密度，绝缘间隔层30在基板SUB上的正投影与转移层20在基板SUB上的正投影重合，触控结构40设置在绝缘间隔层30远离转移层20的一侧。在显示面板的制作过程中，在承载板上形成有机胶层后，可以再形成致密度较高的绝缘间隔层30，并使绝缘间隔层30的一部分超出有机胶层的边界，从而使绝缘间隔层30超出有机胶层边界的部分可以与承载板固定连接，进而将有机胶层固定在承载板上。而在将有机胶层转移至封装层上时，至少将绝缘间隔层30超出有机胶层边界的部分去除，以便于将有机胶层与承载板进行分离。
需要说明的是，图1仅简单示意出基板SUB、发光结构层10(即多个发光元件)、封装层EPL、转移层20、绝缘间隔层30和触控结构40的位置关系，而基板SUB与发光元件之间并不是直接接触的，二者之间形成有其他膜层结构，具体将在下文进行描述。
图2为本公开的一些实施例中提供的显示面板的平面图，图3为沿图2中AA’线的剖视图，图4本公开的另一些实施例中提供的显示面板的平面图，图5为沿图4中BB'线的剖视图，下面结合图2至图5对本公开实施例中的显示面板进行介绍。
在一些实施例中，基板SUB包括显示区DA和环绕显示区DA的外围 区WA，外围区WA包括位于显示区DA一侧的焊盘区BA，触控结构40包括：焊盘PAD、触控电极图形(如图2和图4中的触控驱动电极TX和触控感应电极RX)和触控信号线TL。焊盘PAD位于焊盘区BA，触控电极图形基本位于显示区DA，触控信号线TL位于外围区WA。触控信号线TL的一端连接触控电极图形，另一端连接焊盘PAD。
焊盘PAD不被任何层覆盖，这样便于电连接到柔性印刷电路板FPCB(Flexible Print Circuit Board)。柔性印刷电路板FPCB与触控驱动芯片电连接，被配置为传输来自触控驱动芯片的信号。触控信号线TL与焊盘PAD和触控电极图形电连接，从而实现触控电极图形与柔性印刷电路板FPCB之间的信号传输。
其中，触控电极图形可以采用互电容型结构，也可以采用自电容型结构。本公开实施例以互电容型结构为例进行说明。
如图3和图5所示，触控结构40还包括触控绝缘层TLD，触控绝缘层TLD的材料可以包括诸如氧化硅(SiOx)、氮化硅(SiNx)和/或氮氧化硅(SiON)的无机材料，并且可以形成为多层或单层。当然，触控绝缘层TLD也可以采用有机材料制成。
触控电极图形包括多个触控驱动电极TX和多个触控感应电极RX。触控驱动电极TX与触控感应电极RX交叉设置，触控驱动电极TX与触控感应电极RX交叉处被触控绝缘层TLD绝缘间隔开，每个触控驱动电极TX和每个触控感应电极RX对应连接至少一条触控信号线TL。
触控驱动电极TX和触控感应电极RX的交叉位置形成触控电容，在进行触控感应时，触控驱动芯片依次向多个触控驱动电极TX对应的焊盘PAD提供触控驱动信号，从而使各触控驱动电极TX依次加载触控驱动信号，而触控感应电极RX上则产生相应的感应信号。当有触摸发生时，人体或触控笔靠近触控区，使得该区域中的触控电容发生变化，从而使得相应位置的触控感应电极RX的感应信号发生变化，进而使触控驱动芯片根据变化的感 应信号确定触摸位置。
在一些实施例中，如图5所示，触控驱动电极TX和触控感应电极RX位于不同层中。例如，触控驱动电极TX和触控感应电极RX均为条形电极，触控绝缘层至少覆盖显示区。
例如，触控驱动电极TX和触控感应电极RX均采用透明电极；或者，均采用金属网电极；或者，触控驱动电极TX和触控感应电极RX中的一者采用透明电极，另一者采用金属网电极。可选地，透明电极为氧化铟锡(ITO)等透明导电材料制成的电极，金属网电极为采用铝或铜等金属材料制成的网格状金属。
在另一些实施例中，如图2和图3所示，触控驱动电极TX包括：沿第一方向排列的多个驱动电极单元TX1、以及连接在每相邻两个驱动电极单元TX1之间的桥接部TX2。触控感应电极RX包括：沿第二方向排列的多个感应电极单元RX1、以及连接在每相邻两个感应电极单元RX1之间的连接部RX2。其中，第一方向与第二方向相交叉，驱动电极单元TX1和触控感应电极RX均位于触控绝缘层TLD与封装层EPL之间且同层设置，桥接部TX2位于触控绝缘层TLD与封装层EPL之间。例如，第一方向为图2中的左右方向，第二方向为图2中的上下方向。需要说明的是，图2和图3中所示的触控驱动电极TX和触控感应电极RX仅为示例性说明，并不构成对本公开的限制。例如，还可以使连接部RX2位于触控绝缘层TLD远离基板SUB的一侧，桥接部TX2位于触控绝缘层TLD靠近基板SUB的一侧。又例如，将相邻的驱动电极单元TX1通过异层设置的连接部RX2连接，将相邻的感应电极单元RX1利用同层的桥接部TX2连接。
例如，驱动电极单元TX1和感应电极单元RX1均为透明电极，或者，驱动电极单元TX1和感应电极单元RX1均为金属网电极。桥接部TX2采用与驱动电极单元TX1相同的材料制作，连接部RX2可以采用金属材料制作。
在一些实施例中，如图2和图4所示，触控结构40还包括：位于外围区WA的第一接地线GDL1和第二接地线GDL2。第一接地线GDL1的一端与焊盘区BA中相应的焊盘PAD连接，另一端延伸至显示区DA远离焊盘区BA的一侧。第二接地线GDL2的一端与焊盘区BA中相应的焊盘PAD连接，另一端延伸至显示区DA远离焊盘区BA的一侧。第一接地线GDL1与第二接地线GDL2形成环绕显示区DA的半封闭结构，每条触控信号线TL均位于第一接地线GDL1与第二接地线GDL2之间。其中，第一接地线GDL1所连接的焊盘PAD和第二接地线GDL2所连接的焊盘PAD均被配置为加载接地信号，具体地，第一接地线GDL1所连接的焊盘PAD和第二接地线GDL2所连接的焊盘PAD均与触控驱动芯片上的接地端连接，从而防止触控电极图形和触控信号线TL受到外界的静电干扰或其他干扰。第一接地线GDL1未连接焊盘PAD的一端和第二接地线GDL2未连接焊盘PAD的一端相间隔设置。
例如，第一接地线GDL1包括第一接地部，该第一接地部位于显示区DA远离焊盘区BA的一侧，即，第一接地部为图2中第一接地线GDL1位于显示区DA上方的部分。第二接地线GDL2包括第二接地部，该第二接地部位于显示区DA远离焊盘区BA的一侧，即，第二接地部为图2中第二接地线GDL2位于显示区DA上方的部分。第一接地部和第二接地部无接触，且第一接地部和第二接地部在第一方向上存在交叠，所述第一方向为由焊盘区BA指向显示区DA的方向(即，图2中从下向上的方向)。即，第二接地部的一部分位于第一接地部的上方。
在一些实施例中，如图2和图4所示，触控结构40还包括：第一防护线Guard1和第二防护线Guard2，第一防护线Guard1的一端与焊盘区BA中的相应的焊盘PAD连接，另一端延伸至显示区DA远离焊盘区BA的一侧。第二防护线Guard2的一端与焊盘区BA中相应的焊盘PAD连接，另一端延伸至显示区DA远离焊盘区BA的一侧。第一防护线Guard1和第二防 护线Guard2形成环绕显示区DA的半封闭结构，第一防护线Guard1位于最靠近第一接地线GDL1的触控信号线TL与第一接地线GDL1之间，第二防护线Guard2位于最靠近第二接地线GDL2的触控信号线TL与第二接地线GDL2之间。第一防护线Guard1所连接的焊盘PAD和第二防护线Guard2所连接的焊盘PAD均被配置为加载交流电信号，该交流电信号可以由触控驱动芯片根据触控驱动信号进行设置，以防止触控信号线TL上的信号受到干扰。
例如，第一防护线Guard1包括第一防护部，该第一防护部位于显示区DA远离焊盘区BA的一侧，即，第一防护部为图2中第一防护线Guard1位于显示区DA上方的部分。第二防护线Guard2包括第二防护部，该第二防护部位于显示区DA远离焊盘区BA的一侧，即，第二防护部为图2中第二防护线Guard2位于显示区DA上方的部分。所述第一防护部和所述第二防护部无接触，且所述第一防护部和所述第二防护部在第一方向上无交叠，所述第一方向为由焊盘区BA指向显示区DA的方向(即，图2中从下向上的方向)。
在一些实施例中，基板SUB为柔性基板SUB，其可以采用柔性的有机材料制成，从而有利于显示面板的弯折。例如，该有机材料为聚酰亚胺、聚碳酸酯、聚丙烯酸酯、聚醚酰亚胺、聚醚砜、聚对苯二甲酸乙二醇酯和聚萘二甲酸乙二醇酯等树脂类材料。
如图3和图5所示，第一缓冲层BFL1设置在基板SUB上，用于防止或减少金属原子和/或杂质从基板SUB扩散到晶体管的有源层中。例如，第一缓冲层BFL1可以包括诸如氧化硅(SiOx)、氮化硅(SiNx)和/或氮氧化硅(SiON)的无机材料，并且可以形成为多层或单层。
半导体层设置在第一缓冲层BFL1上。半导体层的材料可以包括例如无机半导体材料(例如，多晶硅、非晶硅等)、有机半导体材料、氧化物半导体材料。半导体层包括各晶体管50的有源层51，有源层51包括沟道部和 位于该沟道部两侧的源极桥接部和漏极桥接部，源极桥接部与晶体管50的源极53连接，漏极桥接部与晶体管50的漏极54连接。源极桥接部和漏极桥接部均可以掺杂有比沟道部的杂质浓度高的杂质(例如，N型杂质或P型杂质)。沟道部与晶体管50的栅极52正对，当栅极52加载的电压信号达到一定值时，沟道部中形成载流子通路，形成使晶体管50的源极53和漏极54导通。
第一栅绝缘层GI1设置在半导体层上，第一栅绝缘层GI1的材料可以包括硅化合物、金属氧化物。例如，第一栅绝缘层GI1的材料包括氮氧化硅(SiON)、氧化硅(SiOx)、氮化硅(SiNx)、碳氧化硅(SiOxCy)、氮碳化硅(SiCxNy)、氧化铝(AlOx)、氮化铝(AlNx)、氧化钽(TaOx)、氧化铪(HfOx)、氧化锆(ZrOx)、氧化钛(TiOx)等。另外，第一栅绝缘层GI1可以为单层或多层。
第一栅电极层G1设置在第一栅绝缘层GI1上。其中，第一栅电极层G1包括各晶体管50的栅极52、电容70的第一电极板71，另外还包括扫描线(未示出)。第一栅电极层G1的材料可以包括例如金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等。例如，第一栅电极层G1可以包括金(Au)、金的合金、银(Ag)、银的合金、铝(Al)、铝的合金、氮化铝(AlNx)、钨(W)、氮化钨(WNx)、铜(Cu)、铜的合金、镍(Ni)、铬(Cr)、氮化铬(CrNx)、钼(Mo)、钼的合金、钛(Ti)、氮化钛(TiNx)、铂(Pt)、钽(Ta)、氮化钽(TaNx)、钕(Nd)、钪(Sc)、氧化锶钌(SRO)、氧化锌(ZnOx)、氧化锡(SnOx)、氧化铟(InOx)、氧化镓(GaOx)、氧化铟锡(ITO)、氧化铟锌(IZO)等。第一栅电极层G1可以具有单层或多层。
第二栅绝缘层GI2设置在第一栅电极层G1上，第二栅绝缘层GI2的材料可以包括例如硅化合物、金属氧化物。例如，第二栅绝缘层GI2的材料可以包括氮氧化硅(SiON)、氧化硅(SiOx)、氮化硅(SiNx)、碳氧化硅 (SiOxCy)、氮碳化硅(SiCxNy)、氧化铝(AlOx)、氮化铝(AlNx)、氧化钽(TaOx)、氧化铪(HfOx)、氧化锆(ZrOx)、氧化钛(TiOx)等。第二栅绝缘层GI2可以形成为单层或多层。
第二栅电极层G2设置在第二栅绝缘层GI2上。第二栅电极层G2可以包括电容70的第二电极板72。第二栅电极层G2的材料可以包括例如金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等。例如，栅电极层可以包括金(Au)、金的合金、银(Ag)、银的合金、铝(Al)、铝的合金、氮化铝(AlNx)、钨(W)、氮化钨(WNx)、铜(Cu)、铜的合金、镍(Ni)、铬(Cr)、氮化铬(CrNx)、钼(Mo)、钼的合金、钛(Ti)、氮化钛(TiN x)、铂(Pt)、钽(Ta)、氮化钽(TaNx)、钕(Nd)、钪(Sc)、氧化锶钌(SRO)、氧化锌(ZnOx)、氧化锡(SnOx)、氧化铟(InOx)、氧化镓(GaOx)、氧化铟锡(ITO)、氧化铟锌(IZO)等。第二栅电极层G2可以具有单层或多层。
层间绝缘层ILD设置第二栅电极层G2上，层间绝缘层ILD的材料可以包括例如硅化合物、金属氧化物等。具体可以选择上文所列举的硅化合物和金属氧化物，这里不再赘述。
第一源漏导电层SD1设置在层间绝缘层ILD上。第一源漏导电层SD1可以包括显示区DA中的各晶体管的源极53和漏极54，源极53与源极桥接部电连接，漏极54与漏极桥接部电连接。第一源漏导电层SD1可以包括金属、合金、金属氮化物、导电金属氧化物、透明导电材料等，例如，第一源漏导电层SD1可以为金属构成的单层或多层，例如为Mo/Al/Mo或Ti/Al/Ti。图3和图5所示的晶体管50包括栅极52、源极53、漏极54和有源层51。另外，第一源漏导电层SD1还可以包括第一电源线、第二电源线和数据线(未示出)，栅线和数据线将显示区划分为多个像素单元，每个像素单元中设置有发光元件和像素驱动电路，像素驱动电路包括多个晶体管，图3和图5所示的晶体管为像素驱动电路中的其中一个晶体管。第一电源 线用于向像素电路提供高电平信号，第二电源线用于向发光元件提供低电平信号。
钝化层PVX设置在第一源漏导电层SD1上，钝化层PVX的材料可以包括硅的化合物，例如，氧化硅、氮化硅或氮氧化硅。
第一平坦化层PLN1设置在钝化层PVX远离基板SUB的一侧，第一平坦化层PLN1的远离基板SUB的表面基本平坦。第一平坦化层PLN1采用有机绝缘材料制成，例如，该有机绝缘材料包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。再例如，该有机绝缘材料包括弹性材料，例如、氨基甲酸乙酯、热塑性聚氨酯(TPU)等。
第二源漏导电层SD2设置在第一平坦化层PLN1远离基板SUB的一侧。第二源漏导电层SD2可以包括位于显示区DA内的转接电极60。其中，转接电极60通过贯穿第一平坦化层PLN1和钝化层PVX的过孔与漏极54电连接，同时，转接电极60还通过贯穿第二平坦化层PLN2的过孔与发光元件的第一电极51电连接。转接电极60可以避免直接在第一平坦化层PLN1和第二平坦化层PLN2中形成孔径比较大的过孔，从而改善过孔电连接的质量。第二源漏导电层SD2的材料可以包括金属、合金、金属氮化物、导电金属氧化物或透明导电材料等，例如，第二源漏导电层SD2可以为金属构成的单层或多层，例如为Mo/Al/Mo或Ti/Al/Ti。第二源漏导电层SD2的材料可以与第一源漏导电层SD1的材料相同或不同。
第二平坦化层PLN2设置在第二源漏导电层SD2上，第二平坦化层PLN2覆盖转接电极60，并且第二平坦化层PLN2的上表面基本平坦。第二平坦化层PLN2采用有机绝缘材料制成，例如，该有机绝缘材料包括聚酰亚胺、环氧树脂、压克力、聚酯、光致抗蚀剂、聚丙烯酸酯、聚酰胺、硅氧烷等树脂类材料等。再例如，该有机绝缘材料包括弹性材料，例如、氨基甲酸乙酯、热塑性聚氨酯(TPU)等。第二平坦化层PLN2的材料可以与第 一平坦化层PLN1的材料相同或不同。
像素界定层PDL设置在第二平坦化层PLN2远离基板SUB的一侧。像素界定层PDL包括与发光元件一一对应的像素开口。像素界定层PDL的材料可以包括聚酰亚胺、聚酞亚胺、聚酞胺、丙烯酸树脂、苯并环丁烯或酚醛树脂等有机绝缘材料。
发光元件11包括第一电极11a、发光层11c和第二电极11b，第一电极11a位于第二平坦化层PLN2与像素界定层之间PDL，发光层11c位于相应的像素开口中，第二电极11b位于发光层11c远离基板的一侧。显示区DA中所有发光元件11的第二电极11b连接为一体，形成第二电极层。其中，第一电极11a为发光元件的阳极，第二电极11b为阴极。第一电极11a通过贯穿第二平坦化层PLN2的过孔与转接电极60电连接，进而与晶体管50的漏极54电连接。第一电极51可以采用例如金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等材料制成。第一电极51可以为单层或多层结构。第一电极51的一部分被像素开口暴露出。
发光层11c可以包括小分子有机材料或聚合物分子有机材料，可以为荧光发光材料或磷光发光材料，可以发红光、绿光、蓝光，或可以发白光。第二电极11b位于发光层11c的远离基板SUB的一侧，第二电极11b可以采用金属、金属合金、金属氮化物、导电金属氧化物、透明导电材料等制成。本公开实施例中，发光元件11可以采用顶发射型结构或底发射型结构。当采用顶发射型结构时，第一电极11a包括具有光反射性能的导电材料或者包括光反射膜，第二电极11b包括透明或半透明的导电材料。当采用底发射型结构时，第二电极11b包括光反射性能的导电材料制成或者包括光反射膜，第一电极11a包括透明或半透明的导电材料。
需要说明的是，发光元件11还可以包括其他膜层，例如，还可以包括：位于第一电极11a与发光层11c之间的空穴注入层和空穴传输层，以及位于发光层11c与第二电极11b之间的电子传输层和电子注入层。
在一些实施例中，封装层EPL包括第一无机封装层CVD1、第二无机封装层CVD2和有机封装层IJP，第二无机封装层CVD2位于第一无机封装层CVD1的远离基板SUB的一侧，有机封装层IJP位于第一无机封装层CVD1和第二无机封装层CVD2之间。第一无机封装层CVD1和第二无机封装层CVD2均可以采用氮氧化硅(SiON)、氧化硅(SiOx)、氮化硅(SiNx)等致密性高的无机材料制成。有机封装层IJP可以采用含有干燥剂的高分子材料制成，或采用可阻挡水汽的高分子材料制成。例如，采用高分子树脂，从而可以缓解第一无机封装层CVD1和第二无机封装层CVD2的应力，还可以包括干燥剂等吸水性材料以吸收侵入内部的水、氧等物质。
上覆层OC设置在触控结构40远离基板SUB的一侧。上覆层OC覆盖触控驱动电极TX、触控感应电极RX、触控信号线TL、第一接地线GDL1和第二接地线GDL2。上覆层OC的材料可以包括无机绝缘材料或有机绝缘材料。
本公开实施例的柔性基板SUB上设置有第一栅绝缘层GI1、第二栅绝缘层GI2、缓冲层BFL，然而，可以理解的是，在一些示例中，这些层可以根据实际需要进行删减或增加，本公开对此不作具体限定。
另外，在一些示例中，可以省去第二平坦化层PNL2和转接电极60，这种情况下，第一电极11a直接设置在第一平坦化层PNL1上，并通过PNL1上的过孔与漏极54电连接。
本公开实施例还提供一种上述显示面板的制作方法，图6为本公开的一些实施例中提供的显示面板的制作方法流程图，如图6所示，该制作方法包括：
S11、在基板上形成多个发光元件。
S12、在多个发光元件远离基板的一侧形成封装层。
S13、在承载板上形成有机胶层。
S14、在有机胶层远离承载板的一侧形成触控结构，触控结构被配置为 检测触摸动作的发生。
S15、将有机胶层与承载板分离，并将有机胶层和触控结构转移至封装层上。
S16、向有机胶层施加预设催化条件，以使有机胶层发生化学反应而粘性增强，从而形成为转移层，转移层与封装层之间的粘结力大于有机胶层与封装层之间的粘结力。
在本公开实施例中，触控结构并直接制作在封装层上，因此，触控结构的刻蚀过程和高温退火过程并不会对封装层以及封装层与基板之间的膜层造成损伤，从而有利于提高显示面板的产品良率。
需要说明的是，在本公开实施例中，步骤S13与步骤S11、S12的先后顺序不作特别限定，步骤S13可以在步骤S11～S12之前进行，也可以在步骤S11～S12之后进行。
在一些实施例中，预设催化条件包括光固化(例如，紫外光照固化)条件或湿气固化条件。
在一些实施例中，承载板采用强度大、更耐高温的材料，例如，承载板为玻璃基板。
在一些实施例中，步骤S13和步骤S14之间还包括：S131、形成绝缘间隔层，绝缘间隔层的致密度大于有机胶层的致密度，且绝缘间隔层的一部分超出有机胶层的边界，以使绝缘间隔层超出有机胶层边界的部分与承载板连接，从而使绝缘间隔层和有机胶层稳定地固定在承载板上，以便于形成触控结构。
可选地，绝缘间隔层包括硅的氮化物层、硅的氧化物层、硅的氮氧化物层中的一者或多者的叠层。例如，绝缘间隔层采用等离子体增强化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)形成。
步骤S14与步骤S15之间还包括：S141、至少将绝缘间隔层超出有机胶层边界的部分去除，以便于将有机胶层与承载板进行分离。在一些实施 例中，步骤S141具体包括：沿预设切割线对绝缘间隔层和有机胶层进行切割，其中，切割线位于有机胶层边界的内侧。
图7A至图7M为本公开的一些实施例中提供的显示面板的制作方法的过程示意图，如图7A至图7M所示，显示面板的制作方法包括：
S21a、在基板上形成缓冲层BFL，如图7A所示。
S21b、如图7B所示，在缓冲层BFL远离所述基板SUB的一侧形成半导体层。半导体层包括各晶体管的有源层51，有源层51包括沟道部和位于该沟道部两侧的源极桥接部和漏极桥接部。
可选地，利用溅射、热蒸发、等离子体增强化学气相沉积(plasma enhanced chemical vapor deposition，PECVD)、低压化学气相沉积(low pressure chemical vapor deposition，LPCVD)、大气压化学气相沉积(atmospheric pressure chemical vapor deposition，APCVD)或电子回旋谐振化学气相沉积(electron cyclotron resonance chemical vapor deposition，ECR-CVD)等工艺形成半导体层。
S21c、如图7C所示，然后，在半导体层远离基板SUB的一侧形成第一栅绝缘层GI1；之后，在第一栅绝缘层GI1远离基板SUB的一侧形成第一栅电极层G1；之后，在第一栅电极层G1远离基板SUB的一侧形成第二栅绝缘层GI2；之后，在第二栅绝缘层GI2远离基板SUB的一侧形成第二栅电极层G2；之后，在第二栅电极层G2远离基板SUB的一侧形成层间绝缘层ILD；之后，在层间绝缘层ILD远离基板SUB的一侧形成第一源漏导电层SD1。
其中，第一栅电极层G1包括各晶体管50的栅极52、电容70的第一电极板71。第二栅电极层可以包括电容70的第二电极板72。
其中，第一栅绝缘层GI1、第一栅电极层G1、第二栅绝缘层GI2、第二栅电极层G2、层间绝缘层ILD、第一源漏导电层SD1的材料均参见上文中的描述，这里不再赘述。可选地，利用磁控溅射等物理气相沉积方法形 成第一栅电极层G1、第二栅电极层G2和第一源漏导电层SD1。利用PECVD形成第一栅绝缘层、第二栅绝缘层GI2和层间绝缘层ILD。第一源漏导电层SD1可以包括显示区中的各晶体管的源极53和漏极54，源极53通过贯穿层间绝缘层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1的过孔与有源层51的源极桥接部连接，漏极54通过贯穿层间绝缘层ILD、第二栅绝缘层GI2和第一栅绝缘层GI1的过孔与有源层51的漏极桥接部连接。
S21d、如图7D所示，在第一源漏导电层SD1远离基板SUB的一侧形成钝化层PVX，之后，形成第一平坦化层PLN1。
S21e、如图7E所示，在第一平坦化层PLN1远离基板SUB的一侧形成第二源漏导电层SD2。第二源漏导电层SD2包括转接电极60，转接电极60通过贯穿第一平坦化层PLN1和钝化层PVX的过孔与漏极54电连接。第二源漏导电层SD2的材料参见上文说明，这里不再赘述。
S21f、如图7F所示，在第二源漏导电层SD2远离基板SUB的一侧形成第二平坦化层PLN2。
S21g、如图7G所示，形成多个发光元件中的每个发光元件的第一电极11a。第一电极11a通过第二平坦化层PLN2上的过孔与转接电极60连接。
S21h、如图7H所示，在第二平坦化层PLN2远离基板SUB的一侧形成像素界定层PDL，像素界定层PDL包括与发光元件一一对应的像素开口V。发光元件的第一电极11a位于第二平坦化层PLN2与像素界定层PDL之间，且第一电极11a的一部分被相应的像素开口V暴露出。
S21i、如图7I所示，形成多个发光元件11中的每个发光元件11的发光层11c，发光层11c位于第一电极11a远离基板SUB的一侧，发光层11c位于相应的像素开口中。发光层11c可以采用蒸镀的方式形成。之后，形成多个发光元件11中的每个发光元件11的第二电极11b，多个发光元件11的第二电极11b连接为一体，形成第二电极层。
其中，形成多个发光元件的步骤即为步骤S21g和S21i。
其中，第二源漏导电层SD2、第一电极11a、第二电极11b可以利用磁控溅射等物理气相沉积方法形成。第一平坦化层PLN1、第二平坦化层PLN2和像素界定层PDL可以采用喷墨打印的方式形成。
S22、如图7J所示，在多个发光元件11远离基板SUB的一侧形成封装层EPL。其中，封装层EPL包括第一无机封装层CVD1、第二无机封装层CVD2和位于第一无机封装层CVD1和第二无机封装层CVD2之间的有机封装层IJP。
S23、如图7K所示，在承载板80上依次形成有机胶层21和绝缘间隔层30，该绝缘间隔层30的致密度大于有机胶层21的致密度，且绝缘间隔层30的一部分超出有机胶层21的边界，以使绝缘间隔层30超出有机胶层21边界的部分与承载板80连接。例如，绝缘间隔层包括硅的氮化物层、硅的氧化物层、硅的氮氧化物层中的一者或多者的叠层。
S24、如图7L所示，在绝缘间隔层30远离承载板80的一侧形成触控结构40。具体地，触控结构40参见图2和图4中所示，包括焊盘PAD、触控电极图形(即触控驱动电极TX和触控感应电极RX)、触控信号线TL、触控绝缘层TLD。相应地，步骤S24包括：在绝缘间隔层30远离承载板80的一侧形成焊盘PAD、触控电极图形、触控信号线TL。其中，焊盘PAD位于有机胶层21的与焊盘区PAD对应的位置；多条触控信号线TL中的每条触控信号线TL的一端连接触控电极图形，另一端连接焊盘PAD。进一步具体地，触控电极图形包括多个触控驱动电极TX和多个触控感应电极RX，触控驱动电极TX与触控感应电极RX交叉设置并绝缘间隔。每个触控驱动电极TX和每个触控感应电极RX均对应连接至少一条触控信号线TL。步骤S24还包括：形成图2或图5中的触控绝缘层TLD，触控驱动电极TX与触控感应电极RX交叉处被触控绝缘层TLD绝缘间隔开。
在一些实施例方式中，如图5所示，触控驱动电极TX和触控感应电极RX位于不同层中。
在另一些实施方式中，如图3所示，触控驱动电极TX包括：沿第一方向排列的多个驱动电极单元TX1、以及连接在每相邻两个驱动电极单元TX1之间的桥接部TX2。触控感应电极RX包括：沿第二方向排列的多个感应电极单元RX1、以及连接在每相邻两个感应电极单元RX1之间的连接部RX2。其中，第一方向与第二方向相交叉，驱动电极单元TX1和触控感应电极RX均位于触控绝缘层TLD与封装层EPL之间，连接部RX2位于触控绝缘层TLD与封装层EPL之间，即，驱动电极单元TX1先于桥接部TX2形成。
另外，在一些实施例中，步骤S25还包括：形成第一接地线和第二接地线，形成第一接地线和第二接地线。第一接地线和第二接地线的位置和连接关系如图3和图5中所示，第一接地线GDL1的一端与相应的焊盘PAD连接，另一端延伸至触控电极图形远离焊盘区BA的一侧；第二接地线GDL2的一端与相应的焊盘PAD连接，另一端延伸至触控电极图形远离焊盘区BA的一侧；第一接地线GDL1与第二接地线GDL2形成环绕触控电极图形的半封闭结构，每条触控信号线TL均位于第一接地线GDL1和第二接地线GDL2之间。
另外，步骤S24还可以包括：形成第一防护线Guard1和第二防护线Guard2，第一防护线Guard1和第二防护线Guard2的连接关系已在上文描述，这里不再赘述。其中，第一防护线Guard1和第二防护线Guard2可以与第一接地线GDL1、第二接地线GDL2同步制作。
S25、至少将绝缘间隔层TLD超出有机胶层21边界的部分去除。可选地，如图7L所示，该步骤S25包括：沿预设切割线CL对绝缘间隔层30和有机胶层21切割，其中，预设切割线CL位于有机胶层21边界的靠近所述有机胶层中心的一侧。
S26、将有机胶层21与承载板80分离，并将有机胶层21和触控结构40转移至封装层EPL上；之后，向有机胶层21施加预设催化条件，以使 有机胶层21发生化学反应而形成为转移层20，转移层20与封装层EPL之间的粘结力大于有机胶层21与封装层EPL之间的粘结力，如图7M所示。
之后，形成上覆层OC，当然，上覆层OC也可以在步骤S26之前形成。
本公开实施例还提供一种显示装置，其包括上述任一实施例的显示面板。该显示装置可以为OLED面板、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
可以理解的是，以上实施方式仅仅是为了说明本公开的原理而采用的示例性实施方式，然而本公开并不局限于此。对于本领域内的普通技术人员而言，在不脱离本公开的精神和实质的情况下，可以做出各种变型和改进，这些变型和改进也视为本公开的保护范围。

Claims (19)

  1. 一种显示面板，包括：
    基板；
    设置在所述基板上的多个发光元件和封装层，所述多个发光元件位于所述封装层与所述基板之间；
    设置在所述封装层远离所述基板一侧、且与所述封装层粘结的转移层，所述转移层与所述封装层之间的粘结力大于有机胶层与所述封装层之间的粘结力，所述有机胶层被配置为在预设催化条件下发生化学反应而形成为所述转移层；
    设置在所述转移层远离所述基板一侧的触控结构，所述触控结构被配置为检测触摸动作的发生。
  2. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    设置在所述转移层远离所述基板一侧的绝缘间隔层，所述绝缘间隔层的致密度大于所述转移层的致密度，所述绝缘间隔层在所述基板上的正投影与所述转移层在所述基板上的正投影重合，所述触控结构设置在所述绝缘间隔层远离所述转移层的一侧。
  3. 根据权利要求2所述的显示面板，其中，所述绝缘间隔层包括硅的氮化物层、硅的氧化物层、硅的氮氧化物层中的一者或多者的叠层。
  4. 根据权利要求1至3中任意一项所述的显示面板，其中，所述预设催化条件为紫外光固化条件或湿气固化条件。
  5. 根据权利要求1至3中任意一项所述的显示面板，其中，所述基板 包括显示区和环绕所述显示区的外围区，所述外围区包括位于显示区一侧的焊盘区，所述触控结构包括：
    位于所述焊盘区的焊盘；
    触控电极图形；
    位于所述外围区的触控信号线，所述触控信号线的一端连接所述触控电极图形，另一端连接所述焊盘。
  6. 根据权利要求5所述的显示面板，其中，所述触控结构还包括触控绝缘层，所述触控电极图形包括多个触控驱动电极和多个触控感应电极，
    所述触控驱动电极与触控感应电极交叉设置，所述触控驱动电极与所述触控感应电极交叉处被所述触控绝缘层绝缘间隔开，每个所述触控驱动电极和每个所述触控感应电极均对应连接至少一条所述触控信号线。
  7. 根据权利要求6所述的显示面板，其中，所述触控驱动电极和所述触控感应电极位于不同层中。
  8. 根据权利要求6所述的显示面板，其中，所述触控驱动电极包括：沿第一方向排列的多个驱动电极单元、以及连接在每相邻两个所述驱动电极单元之间的桥接部；
    所述触控感应电极包括：沿第二方向排列的多个感应电极单元、以及连接在每相邻两个所述感应电极单元之间的连接部；
    其中，所述第一方向与所述第二方向相交叉，所述驱动电极单元、所述桥接部和所述感应电极单元均位于所述触控绝缘层远离所述基板的一侧且同层设置，所述连接部位于所述触控绝缘层与所述封装层之间。
  9. 根据权利要求5所述的显示面板，其中，所述触控结构还包括：位 于外围区的第一接地线和第二接地线，
    所述第一接地线的一端与所述焊盘区中相应的焊盘连接，另一端延伸至所述显示区远离所述焊盘区的一侧；
    所述第二接地线的一端与所述焊盘区中相应的焊盘连接，另一端延伸至所述显示区远离所述焊盘区的一侧；
    所述第一接地线与所述第二接地线形成环绕所述显示区的半封闭结构，每条所述触控信号线均位于所述第一接地线和所述第二接地线之间。
  10. 根据权利要求9所述的显示面板，其中，所述第一接地线所连接的焊盘和所述第二接地线所连接的焊盘均被配置为加载接地信号。
  11. 根据权利要求9所述的显示面板，其中，所述第一接地线包括第一接地部，所述第二接地线包括第二接地部，所述第一接地部和所述第二接地部均位于所述显示区远离所述焊盘区的一侧，
    所述第一接地部和所述第二接地部无接触，且所述第一接地部和所述第二接地部在第一方向上存在交叠，所述第一方向为由所述焊盘区指向所述显示区的方向。
  12. 根据权利要求9所述的显示面板，其中，所述触控结构还包括：第一防护线和第二防护线，
    所述第一防护线的一端与所述焊盘区中的相应的焊盘连接，另一端延伸至所述显示区远离所述焊盘区的一侧；
    所述第二防护线的一端与所述焊盘区中的相应的焊盘连接，另一端延伸至所述显示区远离所述焊盘区的一侧；
    所述第一防护线和所述第二防护线形成环绕所述显示区的半封闭结构，所述第一防护线位于最靠近所述第一接地线的触控信号线与所述第一 接地线之间，所述第二防护线位于最靠近所述第二接地线的触控信号线与所述第二接地线之间。
  13. 根据权利要求12所述的显示面板，其中，所述第一防护线所连接的焊盘和所述第二防护线所连接的焊盘均被配置为加载交流电信号。
  14. 根据权利要求12所述的显示面板，其中，所述第一防护线包括第一防护部，所述第二防护线包括第二防护部，所述第一防护部和所述第二防护部均位于所述显示区远离所述焊盘区的一侧，
    所述第一防护部和所述第二防护部无接触，且所述第一防护部和所述第二防护部在第一方向上无交叠，所述第一方向为由所述焊盘区指向所述显示区的方向。
  15. 根据权利要求1至3中任意一项所述的显示面板，其中，所述显示面板还包括：
    缓冲层，设置在所述基板上；
    半导体层，设置在所述缓冲层远离所述基板的一侧；
    第一栅绝缘层，设置在所述半导体层远离所述基板的一侧；
    第一栅电极层，设置在所述第一栅绝缘层远离所述基板的一侧；
    第二栅绝缘层，设置在所述第一栅电极层远离所述基板的一侧；
    第二栅电极层，设置在所述第二栅绝缘层远离所述基板的一侧；
    层间绝缘层，设置在所述第二栅电极层远离所述基板的一侧；
    第一源漏导电层，设置在所述层间绝缘层远离所述基板的一侧；
    钝化层，设置在所述第一源漏导电层远离所述基板的一侧；
    第一平坦化层，设置在所述钝化层远离所述基板的一侧；
    第二源漏导电层，设置在所述第一平坦化层远离所述基板的一侧；
    第二平坦化层，设置在所述第二源漏导电层远离所述基板的一侧；
    像素界定层，设置在所述第二平坦化层远离所述基板的一侧，所述像素界定层包括与所述发光元件一一对应的像素开口；
    其中，所述多个发光元件中的每个发光元件包括：第一电极、发光层和第二电极，所述第一电极位于所述第二平坦化层与所述像素界定层之间，所述发光层位于所述第一电极远离所述基板的一侧，所述发光层设置在相应的像素开口中，所述第二电极位于所述发光层远离所述基板的一侧，所述多个发光元件的第二电极连接为一体，形成第二电极层。
  16. 一种显示面板的制作方法，包括：
    在基板上形成多个发光元件；
    在所述多个发光元件远离所述基板的一侧形成封装层；
    在承载板上形成有机胶层；
    在所述有机胶层远离所述承载板的一侧形成触控结构，所述触控结构被配置为检测触摸动作的发生；
    将所述有机胶层与所述承载板分离，并将所述有机胶层和所述触控结构转移至所述封装层上；
    向所述有机胶层施加预设催化条件，以使所述有机胶层发生化学反应而粘性增强，从而形成为转移层，所述转移层与所述封装层之间的粘结力大于有机胶层与封装层之间的粘结力。
  17. 根据权利要求16所述的制作方法，其中，所述在承载板上形成有机胶层的步骤与所述在所述有机胶层远离所述承载板的一侧形成触控结构的步骤之间还包括：
    形成绝缘间隔层，所述绝缘间隔层的致密度大于所述有机胶层的致密度，且所述绝缘间隔层的一部分超出所述有机胶层的边界，以使所述绝缘 间隔层超出所述有机胶层边界的部分与所述承载板连接；
    所述在有机胶层远离所述承载板的一侧形成触控结构的步骤与所述将有机胶层与所述承载板分离的步骤之间，还包括：
    至少将所述绝缘间隔层超出所述有机胶层边界的部分去除。
  18. 根据权利要求17所述的制作方法，其中，至少将所述绝缘间隔层超出所述有机胶层边界的部分去除的步骤包括：
    沿预设切割线对所述绝缘间隔层和所述有机胶层切割，其中，所述预设切割线位于所述有机胶层边界的靠近所述有机胶层中心的一侧。
  19. 一种显示装置，包括权利要求1至15中任意一项所述的显示面板。
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