WO2021210752A1 - Semiconductor wafer transporting carrier comprising anti-slip pads - Google Patents

Semiconductor wafer transporting carrier comprising anti-slip pads Download PDF

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Publication number
WO2021210752A1
WO2021210752A1 PCT/KR2020/018287 KR2020018287W WO2021210752A1 WO 2021210752 A1 WO2021210752 A1 WO 2021210752A1 KR 2020018287 W KR2020018287 W KR 2020018287W WO 2021210752 A1 WO2021210752 A1 WO 2021210752A1
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Prior art keywords
poly
carrier
holder
wafer
wafers
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PCT/KR2020/018287
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French (fr)
Korean (ko)
Inventor
장동준
이승원
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주식회사 글린트머티리얼즈
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Publication of WO2021210752A1 publication Critical patent/WO2021210752A1/en

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6732Vertical carrier comprising wall type elements whereby the substrates are horizontally supported, e.g. comprising sidewalls
    • H01L21/67323Vertical carrier comprising wall type elements whereby the substrates are horizontally supported, e.g. comprising sidewalls characterized by a material, a roughness, a coating or the like
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B65CONVEYING; PACKING; STORING; HANDLING THIN OR FILAMENTARY MATERIAL
    • B65DCONTAINERS FOR STORAGE OR TRANSPORT OF ARTICLES OR MATERIALS, e.g. BAGS, BARRELS, BOTTLES, BOXES, CANS, CARTONS, CRATES, DRUMS, JARS, TANKS, HOPPERS, FORWARDING CONTAINERS; ACCESSORIES, CLOSURES, OR FITTINGS THEREFOR; PACKAGING ELEMENTS; PACKAGES
    • B65D85/00Containers, packaging elements or packages, specially adapted for particular articles or materials
    • B65D85/30Containers, packaging elements or packages, specially adapted for particular articles or materials for articles particularly sensitive to damage by shock or pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders

Definitions

  • the present invention relates to a carrier for transferring a wafer for solving a problem in which a wafer is detached or damaged during transfer of a semiconductor wafer.
  • a semiconductor device is manufactured by forming a multilayer film according to a desired circuit pattern on a single crystal silicon wafer.
  • a plurality of unit processes such as a deposition process, a photolithography process, an oxidation process, an etching process, an ion implantation process, and a metal wiring process, are repeatedly performed according to the steps.
  • the wafer is moved to the equipment to be subjected to the subsequent process.
  • the wafers may be individually transported, or a plurality of wafers may be loaded and transported in a carrier device called a cassette or FOUP.
  • the carrier on which the wafer is loaded performs rotational movement or vertical movement along sharp corners as well as high-speed linear movement along a preset path of the process line for subsequent processing.
  • the conventional carrier includes a holder capable of supporting and loading wafers by separating the wafers at regular intervals inside a frame constituting the entire body, and the wafer is loaded in a state where it is simply placed on the holder.
  • the holder is generally made of metal, ceramic, or polymer, and has a smooth surface to have a small coefficient of friction with the smooth surface of the silicon wafer.
  • the carrier moves in an irregular path at high speed, the wafer is not fixed on the holder and constantly shakes. In this process, the wafer may be separated and damaged by impacting the inner wall of the carrier, or particles may be generated due to scratches and the like, thereby contaminating the semiconductor manufacturing line.
  • An object of the present invention is to provide a carrier for transporting semiconductor wafers to solve the problem that a wafer loaded in a carrier is separated and damaged during a wafer transport process for a subsequent process during a semiconductor manufacturing process.
  • a semiconductor wafer transport carrier includes an opening, a frame for storing and transporting a plurality of wafers introduced through the opening, and at least one supporting the plurality of wafers to be stacked spaced apart inside the frame It may include a holder, a detachable part for separating the one or more holders to be detached from the inside of the frame, and an anti-slip pad mounted on the holder to support the wafer to prevent detachment.
  • the non-slip pad may include a base part mounted on the upper surface of the holder, and a pattern part formed on the upper surface of the base part and including one or more fine patterns.
  • the one or more fine patterns may be formed in a columnar shape, and the cross-sectional shape of the column is a polygon, a circle, or an ellipse, and the height of the column is 10 nm to 1000 ⁇ m and the diameter of the pillar may be in the range of 10 nm to 1000 ⁇ m.
  • the one or more fine patterns may be formed in a groove shape, and the cross-sectional shape of the groove is a polygon, a circle, or an ellipse, and the depth of the groove is 10 nm to 1000 nm. ⁇ m, and the width of the groove may be 10 nm to 1000 ⁇ m.
  • a mounting force by a Van der Waals force may be generated between the lower surface of the wafer and the upper surface of the pattern part.
  • the base part and the pattern part are flexible elastomers, silicon-based elastomers, fluoroelastomers (FKM, fluoroelastomers), and perfluoroelastomers.
  • FKM fluoroelastomers
  • PTFE polytetrafluoroethylene
  • the pattern part may include a conductive layer part having conductivity so as to be in electrical contact with the wafer on the upper surface.
  • the carrier for transporting semiconductor wafers may further include a conductive part electrically connecting the conductive layer part and the holder.
  • the adhesive layer may have conductivity so as to be electrically connected to the wafer.
  • the thickness of the conductive layer may be 5 nm to 200 ⁇ m.
  • the conducting portion may be formed to surround a side surface of the base portion.
  • the conductive layer portion is graphene, CNT (carbon nano tube), C60, C540, C70, amorphous carbon, graphite, polyacetylene, Polythiophene, polyaniline, polypyrrole, polypphenylene, polyphenylene vinylene, polyparaphenylenesulfide sulphide), poly p phenylene vinylene, poly iso thianaphthene, or poly thienylene vinylene.
  • the conducting part is graphene, carbon nano tube (CNT), C60, C540, C70, amorphous carbon, graphite, polyacetylene, Polythiophene, polyaniline, polypyrrole, polypphenylene, polyphenylene vinylene, polyparaphenylenesulfide sulphide), poly p phenylene vinylene, poly iso thianaphthene, or poly thienylene vinylene.
  • CNT carbon nano tube
  • an anti-skid pad is mounted on the upper surface of the holder of the carrier in contact with the wafer, and a detachable part is included so that the holder can be attached to and detached from the frame, so that the wafer is moved to the carrier even during the rapid acceleration/deceleration of the carrier during the transfer of the wafer.
  • FIG. 1 and 2 are schematic views of a carrier for transferring semiconductor wafers according to an embodiment of the present invention.
  • FIG 3 is a view for explaining the configuration of the holder and the anti-slip pad according to an embodiment of the present invention.
  • FIG. 4 is a view for explaining the configuration of a detachable unit according to an embodiment of the present invention.
  • 5 and 6 are views for explaining the configuration of the anti-slip pad according to the embodiment of the present invention.
  • FIG. 7 is a view for explaining an anti-slip pad including a conductive layer according to an embodiment of the present invention.
  • FIG 8 to 10 are views for explaining an anti-slip pad including a conductive part according to an embodiment of the present invention.
  • FIG. 11 is a view for explaining an anti-slip pad including an adhesive layer according to an embodiment of the present invention.
  • FIG. 1 and 2 are schematic views of a carrier 100 for transferring semiconductor wafers according to an embodiment of the present invention.
  • the carrier 100 for transporting semiconductor wafers includes a frame 110 including an opening, one or more holders 120 mounted inside the frame 110 , and attaching and detaching the holder 120 to the frame 110 . It may include a detachable part 130 that enables this and an anti-skid pad 140 for preventing separation of the wafer.
  • the wafer on which the previous process has been completed is loaded into the robot arm and introduced through the opening of the frame 110 . In this case, the wafer is introduced into the upper surface of any one of the one or more holders, and after reaching an appropriate position, the introduced wafer is unloaded from the robot arm and seated on the holder 120 .
  • An anti-skid pad 140 is positioned between the seated wafer and the holder 120 , and the non-slip pad 140 enables the wafer to be more firmly seated on the holder 120 .
  • the inner width of the frame 110 is formed to be larger than the diameter of the wafer 150 for the inflow and outflow of the wafer 150 into the carrier 100 , and there is a gap therebetween. Due to the rapid acceleration/deceleration of the carrier 100 , the wafer 150 loaded therein may move unstable within the gap, which may cause problems such as breakage. Since the wafer 150 is stably seated on the holder 120 due to the non-slip pad 140 according to the embodiment of the present invention, it is possible to prevent problems such as damage as described above.
  • FIG 3 is a view for explaining the configuration of the holder 120 and the non-slip pad 140 according to an embodiment of the present invention.
  • the holder 120 is shown in the form of 'C' as an example, but if the robot arm and the loading and unloading of the wafer 150 are possible, it can be formed in various shapes such as 'T'. have.
  • the non-slip pad 140 may be mounted at an appropriate position of the holder 120 in consideration of the mounting position of the wafer 150 .
  • 3 illustrates an example in which the anti-slip pad 140 is mounted at three positions on the upper surface of the holder 120 , it may be mounted at various positions depending on the shape of the holder 120 .
  • the planar shape of the non-slip pad 140 may be formed as shown in FIG.
  • FIG. 4 is a view for explaining the configuration of the detachable unit 130 according to an embodiment of the present invention.
  • the anti-skid pad may be worn due to friction. Because the wafer cannot be stably seated in the holder due to abrasion of the non-slip pad and problems such as detachment and breakage may occur, it is necessary to replace the non-slip pad when the wear level of the non-slip pad exceeds the appropriate line.
  • the non-slip pad includes an adhesive layer at the bottom and is mounted on the upper surface of the holder so that it can be easily removed when necessary.
  • the holder and the frame are integrally formed and cannot be separated, it is not easy to replace the non-slip pad mounted inside the holder due to the tight spacing between the holders. If the holder is detached from the frame to enable detachment, the exchange can be easily performed by attaching the holder to the frame after replacing the non-slip pad by detaching the holder.
  • FIG. 4 various forms of the detachable part 130 for attaching and detaching the holder 120 to the frame 110 are illustrated, and it is obvious that the scope of the present invention is not limited thereto.
  • concave-convex shapes are formed in the frame 110 and the holder 120, respectively, the positions may be changed to form the concave-convex shapes in the holder 120 and the frame 110, respectively.
  • the holder 120 may be detachably attached to the frame 110 through a dowel or the like.
  • 5 and 6 are diagrams for explaining the configuration of the anti-slip pad 140 .
  • the anti-slip pad 140 may include a base part 141 and a pattern part 143 .
  • the base part 141 is formed to support the pattern part 143
  • the pattern part 143 may include one or more pillars or protrusions 1431 .
  • One or more pillars or projections 1431 may be formed to extend vertically with respect to the upper surface of the base portion 141, but is not limited thereto and may be formed at a predetermined angle rather than vertical, and each pillar or projection ( The angles 1431 make with the upper surface of the base part 141 may not be the same.
  • one or more pillars or protrusions 1431 are described as an example that they are formed in a straight line, the present invention is not limited thereto and may be formed in a curved shape.
  • One or more pillars or protrusions 1431 are disposed to be spaced apart, and the distance may be the same or different.
  • the one or more pillars or protrusions 1431 may be formed in a cylindrical shape, but are not limited thereto, and may be formed in various cross-sectional shapes such as polygons, such as triangles, quadrilaterals, or pentagons, or ovals, in cross-section.
  • the upper end of the one or more pillars or protrusions 1431 may be flat, but may also be formed in a rounded shape.
  • One or more pillars or protrusions 1431 may be formed to have a height of 10 nm to 1000 ⁇ m, and each of the pillars or protrusions 1431 may be formed to have the same height, but is not limited thereto, and may be formed to have different heights.
  • One or more pillars or protrusions 1431 may be formed with a diameter or thickness of 10 nm to 1000 ⁇ m, and each of the pillars or protrusions 1431 may be formed with the same diameter or thickness, but is not limited thereto, but different diameters or thicknesses. may be formed as
  • the pattern part 143 may include one or more grooves or holes 1433 .
  • One or more grooves or holes 1433 may be formed to vertically extend downwardly toward the upper surface of the base portion 141 , but the present invention is not limited thereto and may be formed at a predetermined angle rather than vertical. The angles 1433 make with the upper surface of the base part 141 may not be the same.
  • grooves or holes 1433 are described as an example in which they are formed in a straight line, the present invention is not limited thereto and may be formed in a curved shape.
  • the one or more grooves or holes 1433 are disposed to be spaced apart, and the spacing distance may be the same or different.
  • the one or more grooves or holes 1433 may be formed in a circular cross-section, but the cross-section is not limited thereto, and the cross-section may be formed in various cross-sectional shapes such as a polygonal shape such as a triangle, a square, or a pentagon, or an oval shape.
  • the bottom of the one or more grooves or holes 1433 may be flat or may be formed in a rounded shape.
  • One or more grooves or holes 1433 may be formed to a depth of 10 nm to 1000 ⁇ m, and each of the grooves or holes 1433 may be formed to have the same depth, but is not limited thereto and may be formed to have different depths.
  • the one or more grooves or holes 1433 may be formed to have a width of 10 nm to 1000 ⁇ m, and each of the grooves or holes 1433 may be formed to have the same width, but is not limited thereto and may be formed to have different widths.
  • the base portion 141 and the pattern portion 143 may be integrally formed at the same time, but is not limited thereto, and may be formed sequentially or separately formed and then combined. When the base part 141 and the pattern part 143 are integrally formed, they may be integrally formed using a pre-fabricated mold. The base part 141 and the pattern part 143 may be formed of the same material. The base portion 141 and the pattern portion 143 may be formed of a polymer material, or may be formed by mixing a polymer material with a carbon-based material such as graphene and carbon nanotubes.
  • the base portion 141 and the pattern portion 143 may include an elastic polymer (elastomer), a silicone-based elastomer (Si based elastomer), a fluoroelastomer (FKM, fluoroelastomer), a perfluoroelastomer (FFKM, perfluoroelastomer), or polytetrafluoro It may be formed including ethylene (PTFE, polytetrafluoroethylene).
  • elastomer elastomer
  • Si based elastomer silicone-based elastomer
  • FKM fluoroelastomer
  • FFKM perfluoroelastomer
  • PTFE polytetrafluoroethylene
  • the pattern part 143 may provide a high frictional force in response to the normal force caused by gravity of the wafer, thereby strengthening the mounting force of the wafer to the holder 120 . Also, an attractive force by a Van der Waals force may be generated between the upper surface of the pattern part 143 and the lower surface of the wafer.
  • FIG. 7 is a view for explaining the non-slip pad 140 including the conductive layer portion 145 .
  • the non-slip pad 140 may include a conductive layer portion 145 having conductivity on a surface portion in contact with the wafer on an upper portion of the pattern portion 143 . Since the conductive layer part 145 has conductivity, it is electrically connected to the lower surface of the wafer seated on the holder 120 .
  • the thickness of the conductive layer portion 145 may be 5 nm to 200 ⁇ m, and may have an overall uniform thickness, but is not limited thereto, and may have an irregular thickness.
  • the thickness of the conductive layer part 145 is smaller than the height of the pillars or protrusions as an example, but the present invention is not limited thereto, and the thickness of the conductive layer part 145 may be greater than the height of the pillars or protrusions.
  • the present invention is not limited thereto, and it is also applicable to the case where the pattern part 143 includes a groove or a hole.
  • the thickness of the conductive layer portion may be smaller than the depth of the groove or hole, but is not limited thereto, and the thickness of the conductive layer portion may be greater than the depth of the groove or hole.
  • the thickness of the conductive layer portion may be uniform as a whole, but is not limited thereto, and may be irregular depending on the shape of the pattern portion.
  • FIG 8 to 10 are views for explaining the non-slip pad 140 including the energizing part 147 .
  • the non-slip pad When the positively or negatively charged wafer due to the previous process is seated on the non-slip pad, if the non-slip pad is formed of an insulator, polarization occurs across the top and bottom. Charges of different polarities from the wafer are aggregated on the upper portion of the anti-skid pad adjacent to the wafer, that is, on the pattern portion, and electrostatic attraction acts between the wafer and the pattern portion due to charges of different polarities. Since the above electrostatic attraction generates an excessive mounting force between the wafer and the non-slip pad, an excessive force is required to separate the wafer from the holder during the unloading process.
  • the non-slip pad may include a conductive part 147 electrically connecting the conductive layer part 145 and the holder 120 .
  • the wafer 150 is electrically connected to the holder 120 through the conductive layer part 145 and the energizing part 147 , and the charge aggregated on the wafer 150 and the top of the non-slip pad. Charges that are aggregated in may be neutralized by being grounded through the holder 120 . Due to this, by removing unnecessary electrostatic attraction generated between the wafer 150 and the non-slip pad 140 , the popping phenomenon that occurs in the process of separating the wafer 150 from the holder 120 can be easily removed. Therefore, process stability can be ensured.
  • the conductive part 147 may be formed to extend along the side surface of the base part 141 to be electrically connected to the holder 120 . Referring to FIG. 10 , the conductive part 147 may be formed to surround the side surface of the base part 141 , but may be formed to surround only some side surfaces of the base part 141 if the grounding is stably made.
  • the conductive layer portion 145 and the conducting portion 147 may be integrally formed, but is not limited thereto, and may be sequentially formed or separately formed and then electrically connected.
  • the conductive layer part 145 and the conductive part 147 may be formed sequentially or integrally by injecting a raw material solution of the conductive layer part 145 or the conductive part 147 into a pre-fabricated mold.
  • the conductive layer portion 145 and the conductive portion 147 may be formed of conductive materials, and may include a carbon-based material or a conductive polymer, or may be formed by mixing them.
  • the carbon-based material may include graphene, carbon nano tube (CNT), C60, C540, C70, amorphous carbon, or graphite.
  • Conductive polymers include polyacetylene, polythiophene, polyaniline, polypyrrole, polypphenylene, and polyphenylenevinylene. , poly p phenylene sulphide, poly p phenylene vinylene, poly iso thianaphthene or poly thienylene vinylene. can
  • 11 is a view for explaining an anti-slip pad including an adhesive layer 160 .
  • the non-slip pad includes an adhesive layer 160 , and may be mounted on the holder 120 through the adhesive layer 160 .
  • the conductive part 147 may be formed to be electrically connected to the conductive layer part 145 and extend to the adhesive layer 160 along the side of the base part, and the conductive part 147 may be formed to be electrically connected to the adhesive layer 160 .
  • an electrical path is formed from the conductive layer part 145 to the holder 120 to neutralize charges through the conductive part 147 and the adhesive layer 160 .
  • the adhesive layer 160 may be formed of conductive materials, and may include a carbon-based material or a conductive polymer in adhesive materials such as polyimide.
  • the carbon-based material forms an electrical path of a network structure in the adhesive material, thereby forming an electrical path from the top to the bottom of the adhesive layer 160 .
  • the charges accumulated on the wafer and the non-slip pad are neutralized by being grounded to the holder 130 through the conductive layer part 145 , the conducting part 147 , and the adhesive layer 160 . have. Accordingly, by removing unnecessary electrostatic attraction between the wafer and the non-slip pad, the popping phenomenon occurring in the process of separating the wafer from the holder can be easily removed, thereby ensuring process stability.

Abstract

A semiconductor wafer transporting carrier, according to one embodiment of the present invention, comprises: a frame which comprises an opening part and stores and transports a plurality of wafers which have been loaded therein through the opening part; one or more holders which provide support so that the plurality of wafers are stacked inside the frame so as to be spaced apart; attachment/detachment parts which enable the one or more holders to be spaced apart and attached/detached to/from the inside of the frame; and anti-slip pads mounted on the holders and providing support so as to prevent the wafers from breaking away, wherein, by disabling the wafers loaded inside from breaking away from the positions where same have been mounted, even during a sudden acceleration/deceleration of the carrier, damage to the wafers may be prevented, and particle generation caused by damage to the wafers may be prevented, and thus process stability may be improved.

Description

미끄럼 방지 패드를 포함한 반도체 웨이퍼 이송용 캐리어Carrier for transporting semiconductor wafers with anti-skid pads
본 발명은 반도체 웨이퍼 이송 중 웨이퍼가 이탈하거나 파손되는 문제를 해결하기 위한 웨이퍼 이송용 캐리어에 관한 것이다. The present invention relates to a carrier for transferring a wafer for solving a problem in which a wafer is detached or damaged during transfer of a semiconductor wafer.
일반적으로 반도체 소자는 단결정의 실리콘 웨이퍼(Silicon wafer) 상에 원하는 회로 패턴에 따라 다층막을 형성하여 제조된다. 이를 위해 증착 공정, 포토리소그래피 공정, 산화 공정, 식각 공정, 이온주입 공정 및 금속배선 공정 등 다수의 단위 공정들이 단계에 따라 반복적으로 수행된다.In general, a semiconductor device is manufactured by forming a multilayer film according to a desired circuit pattern on a single crystal silicon wafer. To this end, a plurality of unit processes, such as a deposition process, a photolithography process, an oxidation process, an etching process, an ion implantation process, and a metal wiring process, are repeatedly performed according to the steps.
이러한 각 단위 공정들이 절차에 따라 진행되기 위해서는 각각의 공정이 완료된 후 후속공정이 행해질 장비로 웨이퍼가 이동된다. 이 때 웨이퍼는 각각 개별적으로 이송되거나, 카셋트 또는 FOUP이라 불리우는 캐리어 장비에 복수 매의 웨이퍼가 적재되어 이송될 수 있다.In order for each of these unit processes to proceed according to the procedure, after each process is completed, the wafer is moved to the equipment to be subjected to the subsequent process. At this time, the wafers may be individually transported, or a plurality of wafers may be loaded and transported in a carrier device called a cassette or FOUP.
웨이퍼가 적재된 캐리어는 후속 공정을 위해 공정 라인의 미리 설정된 경로를 따라 고속의 직선 이동은 물론 급격한 코너를 따라 회전 이동을 하거나 수직 이동을 하게 된다.The carrier on which the wafer is loaded performs rotational movement or vertical movement along sharp corners as well as high-speed linear movement along a preset path of the process line for subsequent processing.
종래의 캐리어는 전체적인 몸체를 이루는 프레임 내부에 웨이퍼들을 일정 간격으로 분리하여 지지, 적재할 수 있는 홀더를 포함하며, 웨이퍼가 홀더 위에 단순히 얹혀진 상태로 적재가 이루어진다. 홀더는 일반적으로 금속, 세라믹 또는 폴리머로 이루어지며, 표면이 매끄러워 실리콘 웨이퍼의 매끄러운 표면과의 사이에 작은 마찰계수를 갖게 된다. 캐리어가 고속으로 불규칙한 경로로 이동하는 경우, 웨이퍼는 홀더 위에 고정되지 못하고 끊임 없이 흔들리게 된다. 이 과정에서, 웨이퍼가 이탈하여 캐리어 내벽을 충격하여 파손되거나, 스크래치 등으로 인해 파티클이 발생하여 반도체 제조 라인을 오염시킬 수 있다.The conventional carrier includes a holder capable of supporting and loading wafers by separating the wafers at regular intervals inside a frame constituting the entire body, and the wafer is loaded in a state where it is simply placed on the holder. The holder is generally made of metal, ceramic, or polymer, and has a smooth surface to have a small coefficient of friction with the smooth surface of the silicon wafer. When the carrier moves in an irregular path at high speed, the wafer is not fixed on the holder and constantly shakes. In this process, the wafer may be separated and damaged by impacting the inner wall of the carrier, or particles may be generated due to scratches and the like, thereby contaminating the semiconductor manufacturing line.
본 발명이 해결하고자 하는 과제는 반도체 제조 공정 중 후속 공정을 위한 웨이퍼 이송 과정에서 캐리어 내에 적재된 웨이퍼가 이탈하여 파손되는 문제점을 해결하기 위한 반도체 웨이퍼 이송용 캐리어를 제공하는 것이다.SUMMARY OF THE INVENTION An object of the present invention is to provide a carrier for transporting semiconductor wafers to solve the problem that a wafer loaded in a carrier is separated and damaged during a wafer transport process for a subsequent process during a semiconductor manufacturing process.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어는 개구부를 포함하며 상기 개구부를 통해 유입된 복수의 웨이퍼를 보관하여 이송하는 프레임, 상기 복수의 웨이퍼를 상기 프레임 내부에 이격되어 쌓이도록 지지하는 하나 이상의 홀더, 상기 하나 이상의 홀더가 이격되어 상기 프레임 내부에 탈착되도록 하는 탈착부 및 상기 홀더 위에 장착되어 상기 웨이퍼의 이탈을 방지하도록 지지하는 미끄럼 방지 패드를 포함할 수 있다.A semiconductor wafer transport carrier according to an embodiment of the present invention includes an opening, a frame for storing and transporting a plurality of wafers introduced through the opening, and at least one supporting the plurality of wafers to be stacked spaced apart inside the frame It may include a holder, a detachable part for separating the one or more holders to be detached from the inside of the frame, and an anti-slip pad mounted on the holder to support the wafer to prevent detachment.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 미끄럼 방지 패드는 상기 홀더의 상면에 장착되는 베이스부 및 상기 베이스부의 상면에 형성되며 하나 이상의 미세패턴을 포함하는 패턴부를 포함할 수 있다.In the carrier for transporting semiconductor wafers according to an embodiment of the present invention, the non-slip pad may include a base part mounted on the upper surface of the holder, and a pattern part formed on the upper surface of the base part and including one or more fine patterns.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 하나 이상의 미세패턴은 기둥 형상으로 형성될 수 있으며, 상기 기둥의 단면 형상은 다각형, 원 또는 타원이며, 상기 기둥의 높이는 10㎚ 내지 1000㎛이고, 상기 기둥의 직경은 10㎚ 내지 1000㎛일 수 있다.In the carrier for semiconductor wafer transport according to an embodiment of the present invention, the one or more fine patterns may be formed in a columnar shape, and the cross-sectional shape of the column is a polygon, a circle, or an ellipse, and the height of the column is 10 nm to 1000 μm and the diameter of the pillar may be in the range of 10 nm to 1000 μm.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 하나 이상의 미세패턴은 홈 형상으로 형성될 수 있으며, 상기 홈의 단면 형상은 다각형, 원 또는 타원이며, 상기 홈의 깊이는 10㎚ 내지 1000㎛이고, 상기 홈의 너비는 10㎚ 내지 1000㎛일 수 있다.In the carrier for transporting semiconductor wafers according to an embodiment of the present invention, the one or more fine patterns may be formed in a groove shape, and the cross-sectional shape of the groove is a polygon, a circle, or an ellipse, and the depth of the groove is 10 nm to 1000 nm. μm, and the width of the groove may be 10 nm to 1000 μm.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 웨이퍼의 하면과 상기 패턴부의 상면 사이에는 반데르발스 힘(Van der Waals)에 의한 장착력이 발생될 수 있다.In the carrier for transporting a semiconductor wafer according to an embodiment of the present invention, a mounting force by a Van der Waals force may be generated between the lower surface of the wafer and the upper surface of the pattern part.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 베이스부 및 상기 패턴부는 신축성이 있는 탄성중합체(elastomer), 실리콘계 탄성중합체(Si based elastomer), 플루오르엘라스토머(FKM, fluoroelastomer), 퍼플루오르엘라스토머(FFKM, perfluoroelastomer) 또는 폴리테트라플루오르에틸렌(PTFE, polytetrafluoroethylene)을 포함하여 형성될 수 있다.In the carrier for transporting semiconductor wafers according to an embodiment of the present invention, the base part and the pattern part are flexible elastomers, silicon-based elastomers, fluoroelastomers (FKM, fluoroelastomers), and perfluoroelastomers. (FFKM, perfluoroelastomer) or polytetrafluoroethylene (PTFE, polytetrafluoroethylene).
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 패턴부는 상부 표면에 상기 웨이퍼와 전기적으로 접촉되도록 전도성을 갖는 전도층부를 포함할 수 있다.In the carrier for transferring a semiconductor wafer according to an embodiment of the present invention, the pattern part may include a conductive layer part having conductivity so as to be in electrical contact with the wafer on the upper surface.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 전도층부와 상기 홀더를 전기적으로 연결하는 통전부를 더 포함할 수 있다.In the carrier for transporting semiconductor wafers according to an embodiment of the present invention, it may further include a conductive part electrically connecting the conductive layer part and the holder.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 베이스부의 하면에 상기 홀더의 상면과의 접착을 위한 접착층 및 상기 전도층부와 상기 접착층을 전기적으로 연결하는 통전부를 더 포함하고, 상기 접착층은 상기 웨이퍼와 전기적으로 연결되도록 전도성을 가질 수 있다.In the carrier for transporting semiconductor wafers according to an embodiment of the present invention, further comprising an adhesive layer for adhesion to the upper surface of the holder on the lower surface of the base part, and a conductive part electrically connecting the conductive layer part and the adhesive layer, the adhesive layer may have conductivity so as to be electrically connected to the wafer.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서 상기 전도층부의 두께는 5㎚ 내지 200㎛ 일 수 있다.In the carrier for transporting semiconductor wafers according to an embodiment of the present invention, the thickness of the conductive layer may be 5 nm to 200 μm.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서 상기 통전부는 상기 베이스부의 측면을 둘러싸도록 형성될 수 있다.In the carrier for transferring a semiconductor wafer according to an embodiment of the present invention, the conducting portion may be formed to surround a side surface of the base portion.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 전도층부는 그래핀, CNT(carbon nano tube), C60, C540, C70, 비정질카본(amorphous carbon), 흑연, 폴리아세틸렌(poly acetylene), 폴리티오펜(poly thiophene), 폴리아닐린(poly aniline), 폴리피롤(poly pyrrole), 폴리파라페닐렌(poly p phenylene), 폴리페닐렌비닐렌(poly phenylene vinylene), 폴리파라페닐렌설파이드(poly p phenylene sulphide), 폴리파라페닐렌비닐렌(poly p phenylene vinylene), 폴리이소티아나프텐(poly iso thianaphthene) 또는 폴리티에닐렌비닐렌(poly thienylene vinylene) 중 하나 이상을 포함할 수 있다.In the carrier for semiconductor wafer transport according to an embodiment of the present invention, the conductive layer portion is graphene, CNT (carbon nano tube), C60, C540, C70, amorphous carbon, graphite, polyacetylene, Polythiophene, polyaniline, polypyrrole, polypphenylene, polyphenylene vinylene, polyparaphenylenesulfide sulphide), poly p phenylene vinylene, poly iso thianaphthene, or poly thienylene vinylene.
본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어에서, 상기 통전부는 그래핀, CNT(carbon nano tube), C60, C540, C70, 비정질카본(amorphous carbon), 흑연, 폴리아세틸렌(poly acetylene), 폴리티오펜(poly thiophene), 폴리아닐린(poly aniline), 폴리피롤(poly pyrrole), 폴리파라페닐렌(poly p phenylene), 폴리페닐렌비닐렌(poly phenylene vinylene), 폴리파라페닐렌설파이드(poly p phenylene sulphide), 폴리파라페닐렌비닐렌(poly p phenylene vinylene), 폴리이소티아나프텐(poly iso thianaphthene) 또는 폴리티에닐렌비닐렌(poly thienylene vinylene) 중 하나 이상을 포함할 수 있다. In the carrier for transporting semiconductor wafers according to an embodiment of the present invention, the conducting part is graphene, carbon nano tube (CNT), C60, C540, C70, amorphous carbon, graphite, polyacetylene, Polythiophene, polyaniline, polypyrrole, polypphenylene, polyphenylene vinylene, polyparaphenylenesulfide sulphide), poly p phenylene vinylene, poly iso thianaphthene, or poly thienylene vinylene.
본 발명의 실시예에 따르면, 웨이퍼와 접촉되는 캐리어의 홀더 상면에 미끄럼 방지 패드를 장착하고, 홀더를 프레임에 탈부착이 가능하도록 탈착부를 포함하여, 웨이퍼의 이송 중 캐리어의 급격한 가감속에도 웨이퍼가 캐리어의 홀더에 안정적으로 안착될 수 있도록 함으로써, 웨이퍼의 이탈에 따른 파손이나 스크레치 등으로 인한 오염을 방지하여 공정 안정성을 향상시킬 수 있도록 한다.According to an embodiment of the present invention, an anti-skid pad is mounted on the upper surface of the holder of the carrier in contact with the wafer, and a detachable part is included so that the holder can be attached to and detached from the frame, so that the wafer is moved to the carrier even during the rapid acceleration/deceleration of the carrier during the transfer of the wafer. By allowing it to be stably seated in the holder, it is possible to prevent contamination due to damage or scratches caused by the separation of the wafer, thereby improving process stability.
도 1및 도 2는 본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어의 개략적인 도면이다.1 and 2 are schematic views of a carrier for transferring semiconductor wafers according to an embodiment of the present invention.
도 3은 본 발명의 실시예에 따른 홀더 및 미끄럼 방지 패드의 구성을 설명하기 위한 도면이다.3 is a view for explaining the configuration of the holder and the anti-slip pad according to an embodiment of the present invention.
도 4는 본 발명의 실시예에 따른 탈착부의 구성을 설명하기 위한 도면이다.4 is a view for explaining the configuration of a detachable unit according to an embodiment of the present invention.
도 5 및 도 6은 본 발명의 실시예에 따른 미끄럼 방지 패드의 구성을 설명하기 위한 도면이다.5 and 6 are views for explaining the configuration of the anti-slip pad according to the embodiment of the present invention.
도 7은 본 발명의 실시예에 따른 전도층부를 포함한 미끄럼 방지 패드를 설명하기 위한 도면이다.7 is a view for explaining an anti-slip pad including a conductive layer according to an embodiment of the present invention.
도 8 내지 도 10은 본 발명의 실시예에 따른 통전부를 포함한 미끄럼 방지 패드를 설명하기 위한 도면이다.8 to 10 are views for explaining an anti-slip pad including a conductive part according to an embodiment of the present invention.
도 11은 본 발명의 실시예에 따른 접착층을 포함한 미끄럼 방지 패드를 설명하기 위한 도면이다.11 is a view for explaining an anti-slip pad including an adhesive layer according to an embodiment of the present invention.
본 발명의 이점 및/또는 특징, 그리고 그것들을 달성하는 방법은 첨부되는 도면과 함께 상세하게 후술되어 있는 실시예들을 참조하면 명확해질 것이다. 그러나, 본 발명은 이하에서 개시되는 실시예들에 한정되는 것이 아니라 서로 다른 다양한 형태로 구현될 것이며, 단지 본 실시예들은 본 발명의 개시가 완전하도록 하며, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 발명의 범주를 완전하게 알려주기 위해 제공되는 것이며, 본 발명은 청구항의 범주에 의해 정의될 뿐이다. 명세서 전체에 걸쳐 동일 참조 부호는 동일 구성요소를 지칭한다.Advantages and/or features of the present invention, and methods of achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various different forms, and only these embodiments allow the disclosure of the present invention to be complete, and common knowledge in the art to which the present invention pertains It is provided to fully inform those who have the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.
이하에서는 첨부된 도면을 참조하여 본 발명의 실시예들을 상세히 설명하기로 한다.Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1및 도 2는 본 발명의 실시예에 따른 반도체 웨이퍼 이송용 캐리어(100)의 개략적인 도면이다.1 and 2 are schematic views of a carrier 100 for transferring semiconductor wafers according to an embodiment of the present invention.
도 1을 참조하면, 반도체 웨이퍼 이송용 캐리어(100)는 개구부를 포함하는 프레임(110), 프레임(110) 내부에 장착되는 하나 이상의 홀더(120), 홀더(120)를 프레임(110)에 탈부착이 가능하도록 하는 탈착부(130) 및 웨이퍼의 이탈 방지를 위한 미끄럼 방지 패드(140)를 포함할 수 있다. 이전 공정이 완료된 웨이퍼는 로봇암에 로딩되어 프레임(110)의 개구부를 통해 유입된다. 이 경우, 하나 이상의 홀더 중 어느 하나의 상면으로 웨이퍼가 유입되고, 적정 위치에 도달 후 유입된 웨이퍼는 로봇암으로부터 언로딩되어 홀더(120)에 안착된다. 안착된 웨이퍼와 홀더(120) 사이에는 미끄럼 방지 패드(140)가 위치하며, 미끄럼 방지 패드(140)는 홀더(120)에 웨이퍼가 더욱 견고하게 안착될 수 있도록 한다.Referring to FIG. 1 , the carrier 100 for transporting semiconductor wafers includes a frame 110 including an opening, one or more holders 120 mounted inside the frame 110 , and attaching and detaching the holder 120 to the frame 110 . It may include a detachable part 130 that enables this and an anti-skid pad 140 for preventing separation of the wafer. The wafer on which the previous process has been completed is loaded into the robot arm and introduced through the opening of the frame 110 . In this case, the wafer is introduced into the upper surface of any one of the one or more holders, and after reaching an appropriate position, the introduced wafer is unloaded from the robot arm and seated on the holder 120 . An anti-skid pad 140 is positioned between the seated wafer and the holder 120 , and the non-slip pad 140 enables the wafer to be more firmly seated on the holder 120 .
도 2를 참조하면, 캐리어(100) 내부에 웨이퍼(150)의 유출입을 위해 프레임(110) 내부 폭은 웨이퍼(150)의 직경보다 크게 형성되어 그 사이에 간격이 존재한다. 캐리어(100)의 급격한 가감속으로 인해 내부에 적재된 웨이퍼(150)는 상기 간격 내에서 불안정하게 움직일 수 있으며, 이로 인해 파손 등의 문제가 발생할 수 있다. 본 발명의 실시예에 따른 미끄럼 방지 패드(140)로 인해 웨이퍼(150)가 홀더(120) 위에 안정적으로 안착됨으로써 상기한 바와 같은 파손 등의 문제를 방지할 수 있다.Referring to FIG. 2 , the inner width of the frame 110 is formed to be larger than the diameter of the wafer 150 for the inflow and outflow of the wafer 150 into the carrier 100 , and there is a gap therebetween. Due to the rapid acceleration/deceleration of the carrier 100 , the wafer 150 loaded therein may move unstable within the gap, which may cause problems such as breakage. Since the wafer 150 is stably seated on the holder 120 due to the non-slip pad 140 according to the embodiment of the present invention, it is possible to prevent problems such as damage as described above.
도 3은 본 발명의 실시예에 따른 홀더(120) 및 미끄럼 방지 패드(140)의 구성을 설명하기 위한 도면이다.3 is a view for explaining the configuration of the holder 120 and the non-slip pad 140 according to an embodiment of the present invention.
도 3을 참조하면, 홀더(120)는 일 예로서 'ㄷ' 형태로 도시되어 있지만, 로봇암의 유출입과 웨이퍼(150)의 로딩 및 언로딩이 가능하다면 'ㅌ' 등 다양한 형태로 형성될 수 있다. 미끄럼 방지 패드(140)는 웨이퍼(150)의 장착 위치를 고려하여 홀더(120)의 적정 위치에 장착될 수 있다. 도 3에서는 미끄럼 방지 패드(140)가 홀더(120) 상면의 세 위치에 장착된 예를 도시하였으나, 홀더(120)의 형태에 따라 다양한 위치에 장착될 수 있다. 미끄럼 방지 패드(140)의 평면 형태는 넓은 접촉 면적을 고려하여 도 3(a)와 같이 형성될 수 있으나, 웨이퍼(150)와 미끄럼 방지 패드(140) 사이의 적정한 장착력, 홀더(120)에의 탈부착 편의성 등을 고려하여 도 3(b)의 원형 등 다양한 평면 형태로 형성될 수 있다.Referring to FIG. 3 , the holder 120 is shown in the form of 'C' as an example, but if the robot arm and the loading and unloading of the wafer 150 are possible, it can be formed in various shapes such as 'T'. have. The non-slip pad 140 may be mounted at an appropriate position of the holder 120 in consideration of the mounting position of the wafer 150 . 3 illustrates an example in which the anti-slip pad 140 is mounted at three positions on the upper surface of the holder 120 , it may be mounted at various positions depending on the shape of the holder 120 . The planar shape of the non-slip pad 140 may be formed as shown in FIG. 3 (a) in consideration of a large contact area, but an appropriate mounting force between the wafer 150 and the non-slip pad 140 and the holder 120 In consideration of the convenience of attachment and detachment, it may be formed in various planar shapes, such as the circle of FIG. 3(b).
도 4는 본 발명의 실시예에 따른 탈착부(130)의 구성을 설명하기 위한 도면이다.4 is a view for explaining the configuration of the detachable unit 130 according to an embodiment of the present invention.
1기의 캐리어에 일반적으로 25매의 웨이퍼가 적재된다. 홀더에 안착되는 웨이퍼들 사이의 수직 간격은 대략 1cm정도로 매우 촘촘하다. In general, 25 wafers are loaded in one carrier. The vertical spacing between the wafers seated in the holder is very tight, about 1 cm.
한편, 캐리어의 반복적인 사용 즉, 웨이퍼의 수많은 접촉으로 미끄럼 방지 패드는 마찰로 인해 마모될 수 있다. 미끄럼 방지 패드의 마모로 인해 웨이퍼가 홀더에 안정적으로 안착되지 못하고 이탈, 파손 등의 문제가 발생할 수 있기 때문에, 미끄럼 방지 패드의 마모 수준이 적정선을 넘어서는 경우 이를 교환할 필요가 있다. 미끄럼 방지 패드는 하부에 접착층을 포함하여 홀더 상면에 장착됨으로써 필요 시 용이하게 제거 가능하도록 할 수 있다.On the other hand, due to repeated use of the carrier, that is, numerous contacts of the wafer, the anti-skid pad may be worn due to friction. Because the wafer cannot be stably seated in the holder due to abrasion of the non-slip pad and problems such as detachment and breakage may occur, it is necessary to replace the non-slip pad when the wear level of the non-slip pad exceeds the appropriate line. The non-slip pad includes an adhesive layer at the bottom and is mounted on the upper surface of the holder so that it can be easily removed when necessary.
홀더와 프레임이 일체로 형성되어 분리가 안되는 경우, 홀더들 사이의 촘촘한 간격으로 인해 홀더 안쪽에 장착되는 미끄럼 방지 패드를 교환하는 것이 용이하지 않다. 홀더를 프레임과 분리하여 탈부착이 가능하도록 하면, 홀더를 탈착하여 미끄럼 방지 패드를 교환 후 프레임에 부착함으로써 교환 작업을 용이하게 수행할 수 있다.When the holder and the frame are integrally formed and cannot be separated, it is not easy to replace the non-slip pad mounted inside the holder due to the tight spacing between the holders. If the holder is detached from the frame to enable detachment, the exchange can be easily performed by attaching the holder to the frame after replacing the non-slip pad by detaching the holder.
도 4를 참조하면, 프레임(110)에 홀더(120)를 탈부착하기 위한 탈착부(130)의 다양한 형태를 도시하였으며, 본 발명의 범위가 이에 한정되는 것이 아님은 자명하다. 프레임(110)과 홀더(120)에 각각 요철 형태를 형성하였으나, 위치를 바꿔 홀더(120)와 프레임(110)에 각각 요철 형태를 형성할 수도 있다. 요철 형태 이외에도 도웰(dowel) 등을 통해 홀더(120)가 프레임(110)에 탈부착될 수 있다. Referring to FIG. 4 , various forms of the detachable part 130 for attaching and detaching the holder 120 to the frame 110 are illustrated, and it is obvious that the scope of the present invention is not limited thereto. Although concave-convex shapes are formed in the frame 110 and the holder 120, respectively, the positions may be changed to form the concave-convex shapes in the holder 120 and the frame 110, respectively. In addition to the concave-convex shape, the holder 120 may be detachably attached to the frame 110 through a dowel or the like.
도 5 및 도 6은 미끄럼 방지 패드(140)의 구성을 설명하기 위한 도면이다.5 and 6 are diagrams for explaining the configuration of the anti-slip pad 140 .
도 5를 참조하면, 미끄럼 방지 패드(140)는 베이스부(141) 및 패턴부(143)를 포함할 수 있다. 베이스부(141)는 패턴부(143)를 지지하도록 형성되며, 패턴부(143)는 하나 이상의 기둥 또는 돌기(1431)를 포함할 수 있다. 하나 이상의 기둥 또는 돌기(1431)는 베이스부(141)의 상면에 대해 수직으로 연장되어 형성될 수 있으나, 이에 한정되지 않고 수직이 아닌 소정의 각도를 이루며 형성될 수도 있으며, 각각의 기둥 또는 돌기(1431)들이 베이스부(141)의 상면과 이루는 각도는 동일하지 않을 수 있다. Referring to FIG. 5 , the anti-slip pad 140 may include a base part 141 and a pattern part 143 . The base part 141 is formed to support the pattern part 143 , and the pattern part 143 may include one or more pillars or protrusions 1431 . One or more pillars or projections 1431 may be formed to extend vertically with respect to the upper surface of the base portion 141, but is not limited thereto and may be formed at a predetermined angle rather than vertical, and each pillar or projection ( The angles 1431 make with the upper surface of the base part 141 may not be the same.
하나 이상의 기둥 또는 돌기(1431)들이 일직선으로 형성되는 것을 예로 들어 설명하지만, 이에 한정되지 않고 휘어진 형태로 형성될 수도 있다.Although one or more pillars or protrusions 1431 are described as an example that they are formed in a straight line, the present invention is not limited thereto and may be formed in a curved shape.
하나 이상의 기둥 또는 돌기(1431)들은 이격되게 배치되며, 이격 거리는 동일할 수도 있고 상이할 수도 있다. 하나 이상의 기둥 또는 돌기(1431)들은 원기둥 형상으로 형성될 수 있으나, 이에 한정되지 않고 단면이 삼각형, 사각형 또는 오각형 등의 다각형이거나 타원형 등 다양한 단면 형상으로 형성될 수도 있다. 하나 이상의 기둥 또는 돌기(1431)들의 상부 끝단은 평평할 수도 있지만, 라운딩 형상으로 형성될 수도 있다.One or more pillars or protrusions 1431 are disposed to be spaced apart, and the distance may be the same or different. The one or more pillars or protrusions 1431 may be formed in a cylindrical shape, but are not limited thereto, and may be formed in various cross-sectional shapes such as polygons, such as triangles, quadrilaterals, or pentagons, or ovals, in cross-section. The upper end of the one or more pillars or protrusions 1431 may be flat, but may also be formed in a rounded shape.
하나 이상의 기둥 또는 돌기(1431)들은 10㎚ 내지 1000㎛의 높이로 형성될 수 있으며, 각각의 기둥 또는 돌기(1431)들은 동일한 높이로 형성될 수 있지만 이에 한정되지 않고 상이한 높이로 형성될 수도 있다. One or more pillars or protrusions 1431 may be formed to have a height of 10 nm to 1000 μm, and each of the pillars or protrusions 1431 may be formed to have the same height, but is not limited thereto, and may be formed to have different heights.
하나 이상의 기둥 또는 돌기(1431)들은 10㎚ 내지 1000㎛의 직경 또는 두께로 형성될 수 있으며, 각각의 기둥 또는 돌기(1431)들은 동일한 직경 또는 두께로 형성될 수 있지만 이에 한정되지 않고 상이한 직경 또는 두께로 형성될 수도 있다.One or more pillars or protrusions 1431 may be formed with a diameter or thickness of 10 nm to 1000 μm, and each of the pillars or protrusions 1431 may be formed with the same diameter or thickness, but is not limited thereto, but different diameters or thicknesses. may be formed as
도 6을 참조하면, 미끄럼 방지 패드에서 패턴부(143)는 하나 이상의 홈 또는 홀(1433)을 포함할 수 있다. 하나 이상의 홈 또는 홀(1433)은 베이스부(141)의 상면을 향해 하방으로 수직 연장되어 형성될 수 있으나, 이에 한정되지 않고 수직이 아닌 소정의 각도를 이루며 형성될 수도 있으며, 각각의 홈 또는 홀(1433)들이 베이스부(141)의 상면과 이루는 각도는 동일하지 않을 수 있다.Referring to FIG. 6 , in the anti-slip pad, the pattern part 143 may include one or more grooves or holes 1433 . One or more grooves or holes 1433 may be formed to vertically extend downwardly toward the upper surface of the base portion 141 , but the present invention is not limited thereto and may be formed at a predetermined angle rather than vertical. The angles 1433 make with the upper surface of the base part 141 may not be the same.
하나 이상의 홈 또는 홀(1433)들이 일직선으로 형성되는 것을 예로 들어 설명하지만, 이에 한정되지 않고 휘어진 형태로 형성될 수도 있다.Although one or more grooves or holes 1433 are described as an example in which they are formed in a straight line, the present invention is not limited thereto and may be formed in a curved shape.
하나 이상의 홈 또는 홀(1433)들은 이격되게 배치되며, 이격 거리는 동일할 수도 있고 상이할 수도 있다. 하나 이상의 홈 또는 홀(1433)들은 단면이 원형의 형상으로 형성될 수 있으나, 이에 한정되지 않고 단면이 삼각형, 사각형 또는 오각형 등의 다각형이거나 타원형 등 다양한 단면 형상으로 형성될 수도 있다. 하나 이상의 홈 또는 홀(1433)들의 바닥은 평평할 수도 있지만, 라운딩 형상으로 형성될 수도 있다.The one or more grooves or holes 1433 are disposed to be spaced apart, and the spacing distance may be the same or different. The one or more grooves or holes 1433 may be formed in a circular cross-section, but the cross-section is not limited thereto, and the cross-section may be formed in various cross-sectional shapes such as a polygonal shape such as a triangle, a square, or a pentagon, or an oval shape. The bottom of the one or more grooves or holes 1433 may be flat or may be formed in a rounded shape.
하나 이상의 홈 또는 홀(1433)들은 10㎚ 내지 1000㎛의 깊이로 형성될 수 있으며, 각각의 홈 또는 홀(1433)들은 동일한 깊이로 형성될 수 있지만 이에 한정되지 않고 상이한 깊이로 형성될 수도 있다. One or more grooves or holes 1433 may be formed to a depth of 10 nm to 1000 μm, and each of the grooves or holes 1433 may be formed to have the same depth, but is not limited thereto and may be formed to have different depths.
하나 이상의 홈 또는 홀(1433)들은 10㎚ 내지 1000㎛의 너비로 형성될 수 있으며, 각각의 홈 또는 홀(1433)들은 동일한 너비로 형성될 수 있지만 이에 한정되지 않고 상이한 너비로 형성될 수도 있다.The one or more grooves or holes 1433 may be formed to have a width of 10 nm to 1000 μm, and each of the grooves or holes 1433 may be formed to have the same width, but is not limited thereto and may be formed to have different widths.
베이스부(141) 및 패턴부(143)는 일체로 동시에 형성될 수 있으나, 이에 한정되지 않고 순차적으로 형성되거나 별도로 형성된 후 결합될 수도 있다. 베이스부(141) 및 패턴부(143)가 일체로 형성되는 경우 미리 제작된 몰드를 이용해 일체로 형성될 수 있다. 베이스부(141) 및 패턴부(143)는 동일한 소재로 형성될 수 있다. 베이스부(141) 및 패턴부(143)는 고분자 소재로 형성될 수 있으며, 그래핀, 탄소나노튜브 등의 탄소계 소재와 고분자 소재를 혼합하여 형성될 수도 있다. 베이스부(141) 및 패턴부(143)는 신축성이 있는 탄성중합체(elastomer), 실리콘계 탄성중합체(Si based elastomer), 플루오르엘라스토머(FKM, fluoroelastomer), 퍼플루오르엘라스토머(FFKM, perfluoroelastomer) 또는 폴리테트라플루오르에틸렌(PTFE, polytetrafluoroethylene)을 포함하여 형성될 수 있다.The base portion 141 and the pattern portion 143 may be integrally formed at the same time, but is not limited thereto, and may be formed sequentially or separately formed and then combined. When the base part 141 and the pattern part 143 are integrally formed, they may be integrally formed using a pre-fabricated mold. The base part 141 and the pattern part 143 may be formed of the same material. The base portion 141 and the pattern portion 143 may be formed of a polymer material, or may be formed by mixing a polymer material with a carbon-based material such as graphene and carbon nanotubes. The base portion 141 and the pattern portion 143 may include an elastic polymer (elastomer), a silicone-based elastomer (Si based elastomer), a fluoroelastomer (FKM, fluoroelastomer), a perfluoroelastomer (FFKM, perfluoroelastomer), or polytetrafluoro It may be formed including ethylene (PTFE, polytetrafluoroethylene).
패턴부(143)는 웨이퍼의 중력에 의한 수직항력에 대응하여 고마찰력을 제공함으로써 웨이퍼가 홀더(120)에 장착되는 장착력을 강화시킬 수 있다. 또한, 패턴부(143)의 상면과 웨이퍼의 하면 사이에는 반데르발스 힘(Van der Waals force)에 의한 인력이 발생될 수 있다.The pattern part 143 may provide a high frictional force in response to the normal force caused by gravity of the wafer, thereby strengthening the mounting force of the wafer to the holder 120 . Also, an attractive force by a Van der Waals force may be generated between the upper surface of the pattern part 143 and the lower surface of the wafer.
도 7은 전도층부(145)를 포함한 미끄럼 방지 패드(140)를 설명하기 위한 도면이다.7 is a view for explaining the non-slip pad 140 including the conductive layer portion 145 .
도 7을 참조하면, 미끄럼 방지 패드(140)는 패턴부(143)의 상부에 웨이퍼와 접촉하는 표면 부분에 전도성을 갖는 전도층부(145)를 포함할 수 있다. 전도층부(145)는 전도성을 갖기 때문에 홀더(120)에 안착되는 웨이퍼의 하면과 전기적으로 연결된다. 전도층부(145)의 두께는 5㎚ 내지 200㎛ 일 수 있으며, 전체적으로 균일한 두께를 가질 수 있지만 이에 한정되지 않고, 불규칙한 두께를 가질 수 있다. 도 7에는 전도층부(145)의 두께가 기둥 또는 돌기의 높이보다 작은 경우를 예로 들어 도시하였지만 이에 한정되지 않고, 전도층부(145)의 두께가 기둥 또는 돌기의 높이보다 클 수도 있다. Referring to FIG. 7 , the non-slip pad 140 may include a conductive layer portion 145 having conductivity on a surface portion in contact with the wafer on an upper portion of the pattern portion 143 . Since the conductive layer part 145 has conductivity, it is electrically connected to the lower surface of the wafer seated on the holder 120 . The thickness of the conductive layer portion 145 may be 5 nm to 200 μm, and may have an overall uniform thickness, but is not limited thereto, and may have an irregular thickness. 7 illustrates a case in which the thickness of the conductive layer part 145 is smaller than the height of the pillars or protrusions as an example, but the present invention is not limited thereto, and the thickness of the conductive layer part 145 may be greater than the height of the pillars or protrusions.
도 7을 통해 패턴부(143)가 기둥 또는 돌기(1431)를 포함하는 경우를 예로 들어 설명하였지만 이에 한정되지 않고, 홈 또는 홀을 포함하는 경우에도 적용 가능하다. 이 경우, 전도층부의 두께가 홈 또는 홀의 깊이보다 작을 수 있지만 이에 한정되지 않고, 전도층부의 두께가 홈 또는 홀의 깊이보다 클 수도 있다. 또한, 전도층부의 두께는 전체적으로 균일할 수 있지만 이에 한정되지 않고, 패턴부의 형상에 따라 불규칙할 수도 있다.Although the case where the pattern part 143 includes the pillars or protrusions 1431 has been described as an example through FIG. 7 , the present invention is not limited thereto, and it is also applicable to the case where the pattern part 143 includes a groove or a hole. In this case, the thickness of the conductive layer portion may be smaller than the depth of the groove or hole, but is not limited thereto, and the thickness of the conductive layer portion may be greater than the depth of the groove or hole. In addition, the thickness of the conductive layer portion may be uniform as a whole, but is not limited thereto, and may be irregular depending on the shape of the pattern portion.
도 8 내지 도 10은 통전부(147)를 포함한 미끄럼 방지 패드(140)를 설명하기 위한 도면이다.8 to 10 are views for explaining the non-slip pad 140 including the energizing part 147 .
이전 공정으로 인해 양전하 또는 음전하로 대전된 웨이퍼가 미끄럼 방지 패드에 안착 시, 미끄럼 방지 패드가 절연체로 형성되었다면 상하부에 걸쳐 분극현상이 일어나게 된다. 웨이퍼와 근접하는 미끄럼 방지 패드의 상부 즉, 패턴부에는 웨이퍼와 다른 극성의 전하가 응집되고, 서로 다른 극성의 전하들로 인해 웨이퍼와 패턴부 사이에는 정전기적 인력이 작용하게 된다. 위와 같은 정전기적 인력은 웨이퍼와 미끄럼 방지 패드 사이에서 과도한 장착력을 발생시키기 때문에, 언로딩 과정에서 웨이퍼를 홀더로부터 분리하기 위해서는 과도한 힘이 필요하게 된다. 이 과정에서 웨이퍼가 홀더에서 갑작스럽게 튀어오르는 파핑(popping) 현상이 발생하게 되고, 과도한 경우 상부 홀더나 측면 프레임에 웨이퍼가 충격하여 스크레치가 발생하거나 파손되는 문제가 발생할 수 있다. 또한, 웨이퍼의 충격 과정에서 파티클이 발생할 수 있으며 이로 인한 오염으로 인해 수율 하락 등의 중대한 문제가 발생할 수도 있다.When the positively or negatively charged wafer due to the previous process is seated on the non-slip pad, if the non-slip pad is formed of an insulator, polarization occurs across the top and bottom. Charges of different polarities from the wafer are aggregated on the upper portion of the anti-skid pad adjacent to the wafer, that is, on the pattern portion, and electrostatic attraction acts between the wafer and the pattern portion due to charges of different polarities. Since the above electrostatic attraction generates an excessive mounting force between the wafer and the non-slip pad, an excessive force is required to separate the wafer from the holder during the unloading process. In this process, a popping phenomenon occurs in which the wafer abruptly jumps out of the holder, and if excessive, the wafer may impact the upper holder or the side frame, causing scratches or damage. In addition, particles may be generated in the process of impacting the wafer, and serious problems such as a decrease in yield may occur due to contamination.
도 8을 참조하면, 미끄럼 방지 패드는 전도층부(145)와 홀더(120)를 전기적으로 연결하는 통전부(147)를 포함할 수 있다. 도 9를 참조하면, 로딩 이후 웨이퍼(150)는 전도층부(145) 및 통전부(147)를 통해 홀더(120)까지 전기적으로 연결되고, 웨이퍼(150)에 응집된 전하 및 미끄럼 방지 패드의 상부에 응집되는 전하들은 홀더(120)를 통해 접지됨으로써 중성화될 수 있다. 이로 인해 웨이퍼(150)와 미끄럼 방지 패드(140) 사이에 발생하는 불필요한 정전기적 인력을 제거함으로써, 웨이퍼(150)를 홀더(120)로부터 분리하는 과정에서 발생하는 파핑 현상을 용이하게 제거할 수 있기 때문에 공정 안정성을 기할 수 있다.Referring to FIG. 8 , the non-slip pad may include a conductive part 147 electrically connecting the conductive layer part 145 and the holder 120 . Referring to FIG. 9 , after loading, the wafer 150 is electrically connected to the holder 120 through the conductive layer part 145 and the energizing part 147 , and the charge aggregated on the wafer 150 and the top of the non-slip pad. Charges that are aggregated in may be neutralized by being grounded through the holder 120 . Due to this, by removing unnecessary electrostatic attraction generated between the wafer 150 and the non-slip pad 140 , the popping phenomenon that occurs in the process of separating the wafer 150 from the holder 120 can be easily removed. Therefore, process stability can be ensured.
통전부(147)는 베이스부(141)의 측면을 따라 연장되어 홀더(120)와 전기적으로 연결되도록 형성될 수 있다. 도 10을 참조하면, 통전부(147)는 베이스부(141)의 측면을 둘러싸도록 형성될 수 있지만, 접지가 안정적으로 이루어진다면 베이스부(141)의 일부 측면만을 둘러싸면서 형성될 수 있다.The conductive part 147 may be formed to extend along the side surface of the base part 141 to be electrically connected to the holder 120 . Referring to FIG. 10 , the conductive part 147 may be formed to surround the side surface of the base part 141 , but may be formed to surround only some side surfaces of the base part 141 if the grounding is stably made.
전도층부(145) 및 통전부(147)는 일체로 형성될 수 있으나 이에 한정되지 않고, 순차적으로 형성되거나 별도로 형성된 후 전기적으로 연결될 수 있다. 미리 제작된 몰드에 전도층부(145) 또는 통전부(147)의 원료 용액을 주입하여 순차적으로 또는 일체로 전도층부(145) 및 통전부(147)를 형성할 수 있다.The conductive layer portion 145 and the conducting portion 147 may be integrally formed, but is not limited thereto, and may be sequentially formed or separately formed and then electrically connected. The conductive layer part 145 and the conductive part 147 may be formed sequentially or integrally by injecting a raw material solution of the conductive layer part 145 or the conductive part 147 into a pre-fabricated mold.
전도층부(145) 및 통전부(147)는 전도성을 갖는 소재들로 형성될 수 있으며, 탄소계 소재 또는 전도성 고분자를 포함하거나 이들을 혼합하여 형성할 수 있다. 탄소계 소재는 그래핀, CNT(carbon nano tube), C60, C540, C70, 비정질카본(amorphous carbon) 또는 흑연을 포함할 수 있다. 전도성 고분자는 폴리아세틸렌(poly acetylene), 폴리티오펜(poly thiophene), 폴리아닐린(poly aniline), 폴리피롤(poly pyrrole), 폴리파라페닐렌(poly p phenylene), 폴리페닐렌비닐렌(poly phenylene vinylene), 폴리파라페닐렌설파이드(poly p phenylene sulphide), 폴리파라페닐렌비닐렌(poly p phenylene vinylene), 폴리이소티아나프텐(poly iso thianaphthene) 또는 폴리티에닐렌비닐렌(poly thienylene vinylene)을 포함할 수 있다.The conductive layer portion 145 and the conductive portion 147 may be formed of conductive materials, and may include a carbon-based material or a conductive polymer, or may be formed by mixing them. The carbon-based material may include graphene, carbon nano tube (CNT), C60, C540, C70, amorphous carbon, or graphite. Conductive polymers include polyacetylene, polythiophene, polyaniline, polypyrrole, polypphenylene, and polyphenylenevinylene. , poly p phenylene sulphide, poly p phenylene vinylene, poly iso thianaphthene or poly thienylene vinylene. can
도 11은 접착층(160)을 포함한 미끄럼 방지 패드를 설명하기 위한 도면이다.11 is a view for explaining an anti-slip pad including an adhesive layer 160 .
도 11을 참조하면, 미끄럼 방지 패드는 접착층(160)을 포함하며, 접착층(160)을 통해 홀더(120)에 장착될 수 있다. 통전부(147)는 전도층부(145)와 전기적으로 연결되어 베이스부 측면을 따라 접착층(160)까지 연장되어 형성될 수 있으며, 통전부(147)는 접착층(160)과 전기적으로 연결되도록 형성될 수 있다. 즉, 미끄럼 방지 패드가 접착층(160)을 통해 블레이드에 장착되는 경우, 전도층부(145)로부터 홀더(120)까지 통전부(147) 및 접착층(160)을 통해 전하들을 중성화시키는 전기적인 통로가 형성될 수 있다. Referring to FIG. 11 , the non-slip pad includes an adhesive layer 160 , and may be mounted on the holder 120 through the adhesive layer 160 . The conductive part 147 may be formed to be electrically connected to the conductive layer part 145 and extend to the adhesive layer 160 along the side of the base part, and the conductive part 147 may be formed to be electrically connected to the adhesive layer 160 . can That is, when the non-slip pad is mounted on the blade through the adhesive layer 160 , an electrical path is formed from the conductive layer part 145 to the holder 120 to neutralize charges through the conductive part 147 and the adhesive layer 160 . can be
접착층(160)은 전도성을 갖는 소재들로 형성될 수 있으며, 폴리이미드(polyimide)와 같은 접착성을 갖는 소재들에 탄소계 소재 또는 전도성 고분자를 포함하여 형성될 수 있다. 탄소계 소재는 접착성 소재 내에서 네트워크 구조의 전기적인 통로를 형성하고, 이로써 접착층(160)의 상부에서 하부까지 전기적인 통로가 형성될 수 있다.The adhesive layer 160 may be formed of conductive materials, and may include a carbon-based material or a conductive polymer in adhesive materials such as polyimide. The carbon-based material forms an electrical path of a network structure in the adhesive material, thereby forming an electrical path from the top to the bottom of the adhesive layer 160 .
웨이퍼가 로딩되면 도 10에 따른 원리와 동일하게 웨이퍼 및 미끄럼 방지 패드에 응집되는 전하들이 전도층부(145), 통전부(147) 및 접착층(160)을 통해 홀더(130)로 접지됨으로써 중성화될 수 있다. 이로 인해 웨이퍼와 미끄럼 방지 패드 사이에 발생하는 불필요한 정전기적 인력을 제거함으로써, 웨이퍼를 홀더로부터 분리하는 과정에서 발생하는 파핑 현상을 용이하게 제거할 수 있기 때문에 공정 안정성을 기할 수 있다.When the wafer is loaded, in the same manner as in the principle according to FIG. 10 , the charges accumulated on the wafer and the non-slip pad are neutralized by being grounded to the holder 130 through the conductive layer part 145 , the conducting part 147 , and the adhesive layer 160 . have. Accordingly, by removing unnecessary electrostatic attraction between the wafer and the non-slip pad, the popping phenomenon occurring in the process of separating the wafer from the holder can be easily removed, thereby ensuring process stability.
지금까지 본 발명에 따른 구체적인 실시예에 설명하였으나, 본 발명의 범위에서 벗어나지 않는 한도 내에서는 여러 가지 변형이 가능함은 물론이다. 그러므로, 본 발명의 범위는 설명된 실시예에 국한되어 정해져서는 안 되며, 후술하는 특허 청구의 범위 뿐만 아니라 이 특허 청구의 범위와 균등한 것들에 의해 정해져야 한다.Although specific embodiments according to the present invention have been described so far, various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims described below as well as the claims and equivalents.
이상과 같이 본 발명은 비록 한정된 실시예와 도면에 의해 설명되었으나, 본 발명은 상기의 실시예에 한정되는 것은 아니며, 이는 본 발명이 속하는 분야에서 통상의 지식을 가진 자라면 이러한 기재로부터 다양한 수정 및 변형이 가능하다. 따라서, 본 발명 사상은 아래에 기재된 특허청구범위에 의해서만 파악되어야 하고, 이의 균등 또는 등가적 변형 모두는 본 발명 사상의 범주에 속한다고 할 것이다.As described above, although the present invention has been described with reference to the limited examples and drawings, the present invention is not limited to the above examples, which are various modifications and Transformation is possible. Accordingly, the spirit of the present invention should be understood only by the claims described below, and all equivalents or equivalent modifications thereof will fall within the scope of the spirit of the present invention.
[부호의 설명][Explanation of code]
100: 캐리어100: carrier
110: 프레임110: frame
120: 홀더120: holder
130: 탈착부130: detachable part
140: 미끄럼 방지 패드140: non-slip pad
141: 베이스부141: base part
143: 패턴부143: pattern part
1431: 기둥 또는 돌기1431: pillar or protuberance
1433: 홈 또는 홀1433: home or hole
145: 전도층부145: conductive layer part
147: 통전부147: current unit
150: 웨이퍼150: wafer
160: 접착층160: adhesive layer

Claims (13)

  1. 반도체 웨이퍼 이송용 캐리어에 있어서,In the carrier for semiconductor wafer transfer,
    개구부를 포함하며 상기 개구부를 통해 유입된 복수의 웨이퍼를 보관하여 이송하는 프레임;a frame including an opening for storing and transferring a plurality of wafers introduced through the opening;
    상기 복수의 웨이퍼를 상기 프레임 내부에 이격되어 쌓이도록 지지하는 하나 이상의 홀더;one or more holders for supporting the plurality of wafers so as to be spaced apart and stacked inside the frame;
    상기 하나 이상의 홀더가 이격되어 상기 프레임 내부에 탈착되도록 하는 탈착부; 및a detachable part configured to separate the one or more holders to be detached from the inside of the frame; and
    상기 홀더 위에 장착되어 상기 웨이퍼의 이탈을 방지하도록 지지하는 미끄럼 방지 패드;를 포함하는 반도체 웨이퍼 이송용 캐리어.and an anti-skid pad mounted on the holder to support the wafer to prevent separation.
  2. 제1항에 있어서,According to claim 1,
    상기 미끄럼 방지 패드는,The anti-slip pad,
    상기 홀더의 상면에 장착되는 베이스부; 및a base part mounted on the upper surface of the holder; and
    상기 베이스부의 상면에 형성되며 하나 이상의 미세패턴을 포함하는 패턴부;를 포함하는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.and a pattern part formed on the upper surface of the base part and including one or more fine patterns.
  3. 제2항에 있어서,3. The method of claim 2,
    상기 하나 이상의 미세패턴은 기둥 형상으로 형성되며,The one or more fine patterns are formed in a columnar shape,
    상기 기둥의 단면 형상은 다각형, 원 또는 타원이며,The cross-sectional shape of the pillar is a polygon, a circle or an ellipse,
    상기 기둥의 높이는 10㎚ 내지 1000㎛이고, The height of the pillar is 10 nm to 1000 μm,
    상기 기둥의 직경은 10㎚ 내지 1000㎛인 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.A carrier for semiconductor wafer transport, characterized in that the pillar has a diameter of 10 nm to 1000 μm.
  4. 제2항에 있어서,3. The method of claim 2,
    상기 하나 이상의 미세패턴은 홈 형상으로 형성되며,The one or more fine patterns are formed in a groove shape,
    상기 홈의 단면 형상은 다각형, 원 또는 타원이며,The cross-sectional shape of the groove is a polygon, a circle or an ellipse,
    상기 홈의 깊이는 10㎚ 내지 1000㎛이고,The depth of the groove is 10 nm to 1000 μm,
    상기 홈의 직경은 10㎚ 내지 1000㎛인 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.A carrier for semiconductor wafer transport, characterized in that the groove has a diameter of 10 nm to 1000 μm.
  5. 제2항에 있어서,3. The method of claim 2,
    상기 웨이퍼의 하면과 상기 패턴부의 상면 사이에는 반데르발스 힘(Van der Waals)에 의한 장착력이 발생되는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.A carrier for transferring semiconductor wafers, characterized in that a mounting force is generated between the lower surface of the wafer and the upper surface of the pattern part by a Van der Waals force.
  6. 제2항에 있어서,3. The method of claim 2,
    상기 베이스부 및 상기 패턴부는 신축성이 있는 탄성중합체(elastomer), 실리콘계 탄성중합체(Si based elastomer), 플루오르엘라스토머(FKM, fluoroelastomer), 퍼플루오르엘라스토머(FFKM, perfluoroelastomer) 또는 폴리테트라플루오르에틸렌(PTFE, polytetrafluoroethylene)을 포함하는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.The base part and the pattern part are elastic polymer (elastomer), silicone-based elastomer (Si based elastomer), fluoroelastomer (FKM, fluoroelastomer), perfluoroelastomer (FFKM, perfluoroelastomer) or polytetrafluoroethylene (PTFE, polytetrafluoroethylene) ) A carrier for transporting semiconductor wafers, characterized in that it comprises.
  7. 제2항에 있어서,3. The method of claim 2,
    상기 패턴부는 상부 표면에 상기 웨이퍼와 전기적으로 접촉되도록 전도성을 갖는 전도층부;를 포함하는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.The carrier for semiconductor wafer transport, characterized in that it comprises a; conductive layer portion having conductivity so as to be in electrical contact with the wafer on the upper surface of the pattern portion.
  8. 제7항에 있어서, 8. The method of claim 7,
    상기 전도층부와 상기 홀더를 전기적으로 연결하는 통전부;를 포함하는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.A carrier for transferring semiconductor wafers comprising a; a conductive part electrically connecting the conductive layer part and the holder.
  9. 제7항에 있어서, 8. The method of claim 7,
    상기 베이스부의 하면에 상기 홀더의 상면과의 접착을 위한 접착층; 및an adhesive layer for adhesion to the upper surface of the holder on the lower surface of the base part; and
    상기 전도층부와 상기 접착층을 전기적으로 연결하는 통전부;를 포함하고,Containing;
    상기 접착층은 상기 웨이퍼와 전기적으로 연결되도록 전도성을 갖는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.The adhesive layer is a carrier for semiconductor wafer transport, characterized in that it has conductivity to be electrically connected to the wafer.
  10. 제7항에 있어서,8. The method of claim 7,
    상기 전도층부의 두께는 5㎚ 내지 200㎛ 인 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.The semiconductor wafer transport carrier, characterized in that the thickness of the conductive layer is 5nm to 200㎛.
  11. 제8항 또는 제9항에 있어서,10. The method according to claim 8 or 9,
    상기 통전부는 상기 베이스부의 측면을 둘러싸는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.The carrier for semiconductor wafer transfer, characterized in that the current-carrying unit surrounds a side surface of the base portion.
  12. 제7항에 있어서,8. The method of claim 7,
    상기 전도층부는 그래핀, CNT(carbon nano tube), C60, C540, C70, 비정질카본(amorphous carbon), 흑연, 폴리아세틸렌(poly acetylene), 폴리티오펜(poly thiophene), 폴리아닐린(poly aniline), 폴리피롤(poly pyrrole), 폴리파라페닐렌(poly p phenylene), 폴리페닐렌비닐렌(poly phenylene vinylene), 폴리파라페닐렌설파이드(poly p phenylene sulphide), 폴리파라페닐렌비닐렌(poly p phenylene vinylene), 폴리이소티아나프텐(poly iso thianaphthene) 또는 폴리티에닐렌비닐렌(poly thienylene vinylene) 중 하나 이상을 포함하는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.The conductive layer portion is graphene, carbon nano tube (CNT), C60, C540, C70, amorphous carbon, graphite, polyacetylene, polythiophene, polyaniline, Poly pyrrole, poly p phenylene, poly phenylene vinylene, poly p phenylene sulphide, poly p phenylene vinylene ), poly iso thianaphthene (poly iso thianaphthene) or poly thienylene vinylene (poly thienylene vinylene), characterized in that it comprises at least one carrier for transporting semiconductor wafers.
  13. 제8항 또는 제9항에 있어서,10. The method according to claim 8 or 9,
    상기 통전부는 그래핀, CNT(carbon nano tube), C60, C540, C70, 비정질카본(amorphous carbon), 흑연, 폴리아세틸렌(poly acetylene), 폴리티오펜(poly thiophene), 폴리아닐린(poly aniline), 폴리피롤(poly pyrrole), 폴리파라페닐렌(poly p phenylene), 폴리페닐렌비닐렌(poly phenylene vinylene), 폴리파라페닐렌설파이드(poly p phenylene sulphide), 폴리파라페닐렌비닐렌(poly p phenylene vinylene), 폴리이소티아나프텐(poly iso thianaphthene) 또는 폴리티에닐렌비닐렌(poly thienylene vinylene) 중 하나 이상을 포함하는 것을 특징으로 하는 반도체 웨이퍼 이송용 캐리어.The conducting part is graphene, carbon nano tube (CNT), C60, C540, C70, amorphous carbon, graphite, polyacetylene, polythiophene, polyaniline, Poly pyrrole, poly p phenylene, poly phenylene vinylene, poly p phenylene sulphide, poly p phenylene vinylene ), poly iso thianaphthene (poly iso thianaphthene) or poly thienylene vinylene (poly thienylene vinylene), characterized in that it comprises at least one carrier for transporting semiconductor wafers.
PCT/KR2020/018287 2020-04-16 2020-12-14 Semiconductor wafer transporting carrier comprising anti-slip pads WO2021210752A1 (en)

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