WO2021208063A1 - 平板探测器基板及其制作方法、平板探测器 - Google Patents

平板探测器基板及其制作方法、平板探测器 Download PDF

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Publication number
WO2021208063A1
WO2021208063A1 PCT/CN2020/085304 CN2020085304W WO2021208063A1 WO 2021208063 A1 WO2021208063 A1 WO 2021208063A1 CN 2020085304 W CN2020085304 W CN 2020085304W WO 2021208063 A1 WO2021208063 A1 WO 2021208063A1
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Prior art keywords
layer
electrode
photoelectric conversion
base substrate
conversion layer
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PCT/CN2020/085304
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English (en)
French (fr)
Inventor
尚建兴
侯学成
张冠
夏会楠
商晓彬
Original Assignee
京东方科技集团股份有限公司
北京京东方传感技术有限公司
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Application filed by 京东方科技集团股份有限公司, 北京京东方传感技术有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US17/264,621 priority Critical patent/US12021092B2/en
Priority to PCT/CN2020/085304 priority patent/WO2021208063A1/zh
Priority to CN202080000568.7A priority patent/CN113811998B/zh
Publication of WO2021208063A1 publication Critical patent/WO2021208063A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H01L27/14658—X-ray, gamma-ray or corpuscular radiation imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/14612—Pixel-elements with integrated switching, control, storage or amplification elements involving a transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
    • H01L27/14692—Thin film technologies, e.g. amorphous, poly, micro- or nanocrystalline silicon

Definitions

  • the present disclosure relates to the technical field of flat-panel detectors, in particular to a flat-panel detector substrate, a manufacturing method, and a flat-panel detector.
  • Digital radiography has become the main direction of digital radiography technology with its significant advantages such as faster imaging speed, more convenient operation, and higher imaging resolution.
  • the technical core of digital X-ray photography is the X-ray flat-panel detector.
  • the X-ray flat-panel detector is a sophisticated and expensive device that plays a decisive role in the quality of imaging.
  • a flat panel detector substrate which includes: a base substrate, a photoelectric conversion layer, a bias signal line, and a conductive structure.
  • the photoelectric conversion layer is located on the base substrate; the photoelectric conversion layer has a first surface close to the base substrate and a second surface away from the base substrate.
  • the bias signal line is located between the photoelectric conversion layer and the base substrate.
  • the conductive structure is located on the base substrate; one end of the conductive structure is coupled to the second surface of the photoelectric conversion layer, the other end is coupled to the bias signal line, and the part between the two ends is located in the The side of the photoelectric conversion layer.
  • the flat panel detector substrate further includes: thin film transistors, gate lines, and data lines.
  • the thin film transistor is located between the photoelectric conversion layer and the base substrate.
  • the thin film transistor includes a gate, an active layer, a source and a drain, and the source is coupled to the first surface of the photoelectric conversion layer. Connect; the orthographic projection of the active layer of the thin film transistor on the base substrate is within the orthographic projection range of the photoelectric conversion layer on the base substrate.
  • the gate line is arranged in the same layer as the gate of the thin film transistor, and the gate is coupled to the gate line; the film layer where the gate and the gate line are located is the gate layer.
  • the data line is arranged in the same layer as the source and drain of the thin film transistor, and the source is coupled to the data line; the film layer where the source, the drain and the data line are located is the source and drain The source and drain layer is located on the side of the gate layer away from the base substrate.
  • the bias signal line is located in the gate layer.
  • the flat panel detector substrate further includes: a first insulating layer and a first connecting electrode.
  • the first insulating layer is located between the gate layer and the source drain layer, and the first insulating layer has a first via hole.
  • the first transfer electrode is located in the source-drain layer, the first transfer electrode is coupled to the bias signal line through the first via hole, and the first transfer electrode is also connected to the photoelectric conversion The second side of the layer is coupled. Wherein, the first transfer electrode forms at least a part of the conductive structure.
  • the orthographic projection of the first transfer electrode on the base substrate overlaps the orthographic projection of the gate line on the base substrate.
  • the flat panel detector substrate further includes a first dielectric pattern. The first dielectric pattern is located in the overlapping area of the first transfer electrode and the gate line, and the first dielectric pattern is located between the gate line and the first transfer electrode; the first The material of the dielectric pattern is at least one of a semiconductor material and an insulating material.
  • the active layer is located between the gate layer and the source and drain layers, and the first insulating layer is located between the gate layer and the active layer;
  • the first dielectric pattern and the active layer are arranged in the same layer.
  • the orthographic projection of the gate line on the base substrate overlaps the orthographic projection of the data line on the base substrate.
  • the flat panel detector substrate further includes a second dielectric pattern. The second dielectric pattern is located in an overlapping area of the gate line and the data line, and the second dielectric pattern is located between the gate line and the data line. Wherein, the first dielectric pattern and the second dielectric pattern are arranged in the same layer.
  • the active layer is located between the gate layer and the base substrate.
  • the flat panel detector substrate further includes a second insulating layer.
  • the second insulating layer is located between the active layer and the gate layer, and the first insulating layer and the second insulating layer have a source contact hole and a drain contact hole passing through the two;
  • the source electrode is in electrical contact with the active layer through the source contact hole, and the drain electrode is in electrical contact with the active layer through the drain contact hole.
  • the first insulating layer further has a second via hole.
  • the flat panel detector substrate further includes binding electrodes.
  • the binding electrode is located in the source and drain layer, and the binding electrode is coupled to the bias signal line through the second via hole.
  • the binding electrode is configured to be bound with a driving chip to receive a bias signal from the driving chip and transmit the bias signal to the bias signal line.
  • the bias signal line is located in the source and drain layer. One end of the bias signal line extends beyond the range covered by the photoelectric conversion layer, and the end of the bias signal line extends from the side of the photoelectric conversion layer to the second side of the photoelectric conversion layer. ⁇ coupled.
  • the flat panel detector substrate further includes: a third insulating layer and a first electrode layer.
  • the third insulating layer is located between the source drain layer and the photoelectric conversion layer, and the third insulating layer has a third via hole.
  • the first electrode layer is located between the third insulating layer and the photoelectric conversion layer; the first electrode layer includes a first electrode in contact with the first surface of the photoelectric conversion layer, and is located on the first electrode On the side second transfer electrode, the first electrode and the second transfer electrode are insulated from each other; the second transfer electrode is coupled to the bias signal line through the third via hole.
  • the second transfer electrode forms at least a part of the conductive structure.
  • the third insulating layer further has electrode contact holes.
  • the first electrode is coupled to the source electrode of the thin film transistor through the electrode contact hole, so that the first surface of the photoelectric conversion layer is coupled to the source electrode.
  • the flat panel detector substrate further includes: a second electrode, a fourth insulating layer, and a third connecting electrode.
  • the second electrode is located on the side of the photoelectric conversion layer away from the base substrate, and the second electrode is in contact with the second surface of the photoelectric conversion layer.
  • the fourth insulating layer is located on a side of the second electrode away from the base substrate, and the fourth insulating layer has a fourth via hole and a fifth via hole.
  • the third transfer electrode is located on the side of the fourth insulating layer away from the base substrate; one end of the third transfer electrode is coupled to the second transfer electrode through the fourth via hole, and the other end is passed through the The five via holes are coupled to the second electrode of the photoelectric conversion layer.
  • the third transfer electrode forms at least a part of the conductive structure.
  • the material of the third transfer electrode is a transparent conductive material.
  • the orthographic projection of the fourth via on the base substrate does not overlap with the orthographic projection of the third via on the base substrate.
  • the orthographic projection of the photoelectric conversion layer on the base substrate and the orthographic projection of the bias signal line on the base substrate at least partially overlap.
  • the flat panel detector substrate further includes: a third insulating layer and a first electrode layer.
  • the third insulating layer is located between the source drain layer and the photoelectric conversion layer.
  • the first electrode layer is located between the third insulating layer and the photoelectric conversion layer, the first electrode layer includes a first electrode in contact with the first surface of the photoelectric conversion layer, and the bias signal line
  • the bias signal line and the first electrode are insulated from each other, and the bias signal line is coupled to the second surface of the photoelectric conversion layer from the side of the photoelectric conversion layer.
  • an orthographic projection of the portion where the source of the thin film transistor and the first surface of the photoelectric conversion layer are coupled is formed on the substrate, and the photoelectric conversion layer is on the substrate.
  • the orthographic projections on the substrate do not overlap.
  • the flat panel detector substrate has a plurality of photosensitive regions; each photosensitive region is provided with the photoelectric conversion layer, the bias signal line and the conductive structure.
  • the plurality of photosensitive regions are arranged in an array; the bias signal line extends in the row direction or the column direction.
  • a flat-panel detector in another aspect, includes: the flat-panel detector substrate according to any one of the foregoing embodiments; and a driving chip coupled to the flat-panel detector substrate.
  • the driving chip is configured to transmit a bias signal to the bias signal line of the flat panel detector substrate.
  • a method for manufacturing a flat panel detector substrate including:
  • a base substrate is provided, and a bias signal line is formed on the base substrate.
  • a photoelectric conversion layer is formed on the side of the base substrate on which the bias signal line is formed; the photoelectric conversion layer has a first surface close to the base substrate and a second surface away from the base substrate.
  • a conductive structure is formed on the base substrate; one end of the conductive structure is coupled to the second surface of the photoelectric conversion layer, the other end is coupled to the bias signal line, and the part between the two ends is located at the second surface of the photoelectric conversion layer.
  • the manufacturing method further includes: before the step of forming the photoelectric conversion layer, forming a thin film transistor; an orthographic projection of the active layer of the thin film transistor on the base substrate It is within the orthographic projection range of the photoelectric conversion layer on the base substrate.
  • the step of forming a thin film transistor includes:
  • a gate layer is formed on the base substrate; the gate layer includes a gate of a thin film transistor, a gate line, and the bias signal line, and the gate is coupled to the gate line.
  • a first insulating layer is formed on the side of the gate layer away from the base substrate; the first insulating layer has a first via hole.
  • a source-drain layer is formed on the side of the first insulating layer away from the base substrate; the source-drain layer includes the source and drain of a thin film transistor, a data line and a first transfer electrode, and the source The electrode is coupled to the data line, and the first transfer electrode is coupled to the bias signal line through the first via hole.
  • the manufacturing method further includes:
  • a third insulating layer is formed; the third insulating layer has a third via hole.
  • a first electrode layer is formed on the side of the third insulating layer away from the base substrate; the first electrode layer includes a first electrode in contact with the first surface of the photoelectric conversion layer, and is located on the first surface of the photoelectric conversion layer.
  • a second transfer electrode beside an electrode, the first electrode and the second transfer electrode are insulated from each other, and the second transfer electrode is coupled to the first transfer electrode through the third via hole catch.
  • the manufacturing method further includes:
  • a second electrode is formed; the second electrode is in contact with the second surface of the photoelectric conversion layer.
  • a fourth insulating layer is formed on the side of the photoelectric conversion layer away from the base substrate; the fourth insulating layer has a fourth via hole and a fifth via hole.
  • a third transfer electrode is formed on the side of the fourth insulating layer away from the base substrate; one end of the third transfer electrode is coupled to the second transfer electrode through a fourth via hole, and the other end It is coupled with the second electrode through the fifth via.
  • first transition electrode, the second transition electrode, and the third transition electrode form at least a part of the conductive structure.
  • Figure 1 is a cross-sectional view of a flat panel detector substrate according to the related art
  • Figure 2A is a top view of a flat panel detector substrate according to some embodiments.
  • Fig. 2B is a partial enlarged view of the flat panel detector substrate shown in Fig. 2A;
  • FIG. 3 is a cross-sectional view along line AA of the flat panel detector substrate according to FIG. 2;
  • FIG. 4 is a cross-sectional view along line BB of the flat panel detector substrate according to FIG. 2;
  • Fig. 5 is a cross-sectional view of the flat panel detector substrate according to Fig. 2 along line CC;
  • 6 to 15 are schematic diagrams of the manufacturing process of the flat panel detector substrate according to some embodiments.
  • Fig. 16 is a flow chart of a method of manufacturing a flat panel detector substrate according to some embodiments.
  • FIG. 17 is another flowchart of a method for manufacturing a flat panel detector substrate according to some embodiments.
  • Fig. 18 is a structural diagram of a flat panel detector according to some embodiments.
  • first and second are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of these features. In the description of the embodiments of the present disclosure, unless otherwise specified, “plurality” means two or more.
  • the expressions “coupled” and “connected” and their extensions may be used.
  • the term “connected” may be used when describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used when describing some embodiments to indicate that two or more components have direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also mean that two or more components are not in direct contact with each other, but still cooperate or interact with each other.
  • the embodiments disclosed herein are not necessarily limited to the content of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, A and B The combination of A and C, the combination of B and C, and the combination of A, B and C.
  • X-ray flat panel detectors can be divided into two types according to the energy conversion method: Indirect Flat Panel X-ray Detector and Direct Flat Panel X-ray Detector.
  • Indirect Flat Panel X-ray Detector Direct Flat Panel X-ray Detector
  • Direct Flat Panel X-ray Detector an indirect conversion X-ray flat-panel detector is taken as an example for illustration.
  • a flat-panel detector substrate 100' includes a base substrate 1', a thin film transistor 3', a photoelectric conversion layer 2', and a bias signal line L'.
  • the bias signal line L' is located above the photoelectric conversion layer 2', and the bias signal line L'is configured to transmit a bias signal to the side of the photoelectric conversion layer 2'away from the base substrate 1', so that the photoelectric conversion layer 2'receives visible light After being irradiated, photocurrent can be generated.
  • the thin film transistor 3' includes a gate 31', an active layer 32', a source 33', a drain 34', and a first insulating layer 35' located between the gate 31' and the active layer 32' .
  • the bias signal line L' Since the bias signal line L'is located above the photoelectric conversion layer 2'and uses a metal material, the bias signal line L'will block the photoelectric conversion layer.
  • the thin film transistor 3'adopts a bottom gate structure it is necessary to provide a light-shielding metal above the active layer 32' to shield the active layer 32'.
  • the bias signal line L'and the light-shielding metal are provided in the same layer.
  • the photoelectric conversion layer 2' will be blocked, affecting the photoelectric conversion layer 2'to receive visible light signals, resulting in a decrease in the filling rate of the flat-panel detector substrate 100', thereby affecting the flat-panel detector The sensitivity and quantum detection efficiency of the substrate 100'.
  • the present disclosure provides a flat panel detector substrate 100.
  • the flat panel detector substrate 100 includes: a base substrate 1, a photoelectric conversion layer 2, a bias The signal line L and the conductive structure 6 are pressed.
  • the photoelectric conversion layer 2 is located on the base substrate 1, and the photoelectric conversion layer 2 has a first surface S1 close to the base substrate 1 and a second surface S2 far away from the base substrate 1.
  • the photoelectric conversion layer includes at least one of a PIN-type photodiode, a NIP-type photodiode, or a PN-type photodiode.
  • the bias signal line L is located between the photoelectric conversion layer 2 and the base substrate 1.
  • the conductive structure 6 is located on the base substrate 1, one end of the conductive structure 6 is coupled to the second surface S2 of the photoelectric conversion layer 2, the other end is coupled to the bias signal line L, and the part between the two ends is located in the photoelectric conversion layer 2.
  • the second surface S2 of the photoelectric conversion layer 2 is coupled to the bias signal line L from the side of the photoelectric conversion layer 2 through the conductive structure 6.
  • the bias signal line L transmits the bias signal to the second surface S2 of the photoelectric conversion layer 2 through the conductive structure 6, and the bias signal line L is located under the photoelectric conversion layer 2, so that the bias signal line L will not interfere with the photoelectric conversion layer 2.
  • the conversion layer 2 causes shielding, which will not affect the photoelectric conversion layer 2 to receive visible light signals, which improves the filling rate of the flat-panel detector substrate 100, and further improves the sensitivity and quantum detection efficiency of the flat-panel detector substrate 100.
  • the thin film transistor 3 is located between the photoelectric conversion layer 2 and the base substrate 1.
  • the thin film transistor 3 includes a gate 31, an active layer 32, a source 33 and a drain 34, and the source 33 is connected to the first surface S1 of the photoelectric conversion layer 2. Coupling.
  • the orthographic projection of the active layer 32 of the thin film transistor 3 on the base substrate 1 is within the range of the orthographic projection of the photoelectric conversion layer 2 on the base substrate 1.
  • the thin film transistor 3 is located between the photoelectric conversion layer 2 and the base substrate 1, and the orthographic projection of the active layer 32 of the thin film transistor 3 on the base substrate 1 is in the photoelectric conversion layer 2 on the base substrate 1. Within the orthographic projection range. In this way, the photoelectric conversion layer 2 can shield the thin film transistor 3 to prevent visible light from irradiating the thin film transistor 3, thereby avoiding the problem of excessive leakage current of the thin film transistor 3 caused thereby.
  • the gate line 4 and the gate electrode 31 of the thin film transistor 3 are arranged in the same layer, and the gate electrode 31 is coupled to the gate line 4; the gate electrode 31 and The film layer where the gate line 4 is located is the gate layer G.
  • the data line 5 is arranged in the same layer as the source 33 and the drain 34 of the thin film transistor 3, and the source 33 is coupled to the data line 5.
  • the film layer where the source electrode 33, the drain electrode 34 and the data line 5 are located is the source drain layer SD, and the source drain layer SD is located on the side of the gate layer G away from the base substrate 1.
  • the thin film transistor 3 has a bottom gate structure or a top gate structure, which is not limited in the embodiment of the present disclosure.
  • the thin film transistor 3 has a bottom gate structure.
  • the active layer 32 is located between the gate layer G and the base substrate 1.
  • the flat panel detector substrate further includes a first insulating layer 35, the first insulating layer 35 is located between the gate layer G and the active layer 32, and the active layer 32 is located between the gate layer G and the source drain layer SD.
  • the thin film transistor 3 has a top gate structure.
  • the flat panel detector substrate further includes a first insulating layer 35 and a second insulating layer.
  • the second insulating layer is located between the active layer 32 and the gate layer G, and the first insulating layer 35 and the second insulating layer have source contact holes and drain contact holes penetrating the two.
  • the source electrode 33 is in electrical contact with the active layer 32 through the source contact hole
  • the drain electrode 34 is in electrical contact with the active layer 32 through the drain contact hole.
  • the thin film transistor 3 has a bottom gate structure as an example for illustration.
  • the bias signal line L may be located on the gate layer G.
  • the first insulating layer 35 has a first via 351 therein.
  • the flat panel detector substrate 100 further includes a first transfer electrode 61.
  • the first transfer electrode 61 is located in the source and drain layer SD, the first transfer electrode 61 is coupled to the bias signal line L through the first via 351, and the first transfer electrode 61 is also connected to the second surface of the photoelectric conversion layer 2 S2 is coupled. Wherein, the first transfer electrode 61 forms at least a part of the conductive structure 6.
  • the coupling between the first transfer electrode 61 and the second surface S2 of the photoelectric conversion layer 2 may be an indirect coupling, that is, the coupling between the two is realized through some structures, and subsequent implementations Some implementation methods will be given in the example.
  • the orthographic projection of the first transfer electrode 61 on the base substrate 1 and the orthographic projection of the gate line 4 on the base substrate 1 overlap.
  • the flat panel detector substrate 100 further includes: a first dielectric pattern 321 located in the overlapping area of the first transfer electrode 61 and the gate line 4, and the first dielectric pattern 321 is located Between the gate line 4 and the first transfer electrode 61.
  • the orthographic projection area of the first dielectric pattern 321 on the base substrate 1 is greater than or equal to the orthographic projection area of the overlap area of the gate line 4 and the first transfer electrode 61 on the base substrate 1.
  • the material of the first dielectric pattern 321 is at least one of a semiconductor material and an insulating material.
  • the first dielectric pattern 321 increases the dielectric constant of the dielectric material between the first transfer electrode 61 and the gate line 4, so that the first dielectric pattern 321 can reduce the gate line 4 and the first transfer electrode. Parasitic capacitance between 61.
  • the material of the first dielectric pattern 321 is a semiconductor material
  • the first insulating layer 35 is located between the gate layer G and the source-drain layer SD.
  • the first dielectric pattern 321 can be arranged in the same layer as the active layer 32. In this way, the first dielectric pattern 321 can be formed in the same manufacturing process as the active layer 32, which simplifies the manufacturing process.
  • the flat panel detector substrate 100 further includes a second dielectric pattern 322 located in the overlapping area of the gate line 4 and the data line 5, and the second dielectric pattern 322 is located between the gate line 4 and the data line 5.
  • the material of the second dielectric pattern 322 is at least one of a semiconductor material and an insulating material. In this way, the second dielectric pattern 322 can reduce the parasitic capacitance between the gate line 4 and the data line 5.
  • the orthographic projection area of the second dielectric pattern 322 on the base substrate 1 is greater than or equal to the orthographic projection area of the overlap area of the gate line 4 and the data line 5 on the base substrate 1.
  • the first dielectric pattern 321 and the second dielectric pattern 322 may be arranged in the same layer, or the first dielectric pattern 321, the second dielectric pattern 322, and the active layer 32 may be arranged in the same layer, which can simplify Production process.
  • the first insulating layer 35 further has a second via 352.
  • the flat panel detector substrate 100 further includes a binding electrode 60, the binding electrode 60 may be located in the source and drain layer SD, and the binding electrode 60 is coupled to the bias signal line L through the second via 352.
  • the binding electrode 60 is configured to be bound with an external driving chip to receive a bias signal from the driving chip and transmit the bias signal to the bias signal line L.
  • the flat-panel detector substrate 100 has a plurality of photosensitive regions GG.
  • a photoelectric conversion layer 2, a bias signal line L, and a conductive structure 6 are provided in each photosensitive region GG.
  • the multiple photosensitive regions GG are arranged in an array, and the bias signal line L extends in the row direction or the column direction.
  • the external driving chip transmits the bias signal to the binding electrode 60 in each photosensitive area GG column by column through the connecting line, and the binding electrode 60 transmits the bias signal to its corresponding photosensitive area through the second via 352
  • the bias signal line L inside, thereby realizing the reception and transmission of the bias signal by the binding electrode 60.
  • the bias signal line L may also be located in the source-drain layer SD. One end of the bias signal line L extends beyond the range covered by the photoelectric conversion layer 2, and this end of the bias signal line L is coupled to the second surface S2 of the photoelectric conversion layer 2 from the side of the photoelectric conversion layer 2.
  • the first via hole 351 and the second via hole 352 may not be provided in the first insulating layer 35.
  • the source and drain layers SD may or may not be provided with a binding electrode 60, which is not limited in the embodiment of the present disclosure.
  • the bias signal line L is directly coupled to the driving chip, and the bias signal line L directly receives the bias signal from the driving chip.
  • the flat-panel detector substrate 100 further includes a third insulating layer 7 and a first electrode layer 8.
  • the third insulating layer 7 is located between the source and drain layer SD and the photoelectric conversion layer 2, and the third insulating layer 7 has a third via 71.
  • the first electrode layer 8 is located between the third insulating layer 7 and the photoelectric conversion layer 2.
  • the first electrode layer 8 includes a first electrode 81 and a second transfer electrode 62.
  • the first electrode 81 is in contact with the first surface S1 of the photoelectric conversion layer 2, the second transfer electrode 62 is located beside the first electrode 81, the first electrode 81 and the second transfer electrode 62 are insulated from each other, and the second transfer electrode 62
  • the third via 71 is coupled to the bias signal line L.
  • the second transfer electrode 62 forms at least a part of the conductive structure 6.
  • the coupling between the second transfer electrode 62 and the bias signal line L may be an indirect coupling.
  • the second transfer electrode 62 passes through the third The via 71, the first transfer electrode 61, and the first via 351 are coupled to the bias signal line L.
  • the second transfer electrode 62 is also coupled to the second surface S2 of the photoelectric conversion layer 2.
  • the coupling between the second transfer electrode 62 and the second surface S2 of the photoelectric conversion layer 2 is an indirect coupling, and the coupling between the two is achieved through some structures, and some implementation manners will be given in subsequent embodiments.
  • first electrode 81 and the second transfer electrode 62 are arranged in the same layer and insulated from each other, which can prevent the bias signal line L coupled to the second transfer electrode 62 from being coupled to the first electrode 81, thereby It is ensured that the bias signal in the bias signal line L will not be transmitted to the first surface S1 of the photoelectric conversion layer 2.
  • the third insulating layer 7 further has an electrode contact hole 72.
  • the first electrode 81 is coupled to the source 33 of the thin film transistor 3 through the electrode contact hole 72 so that the first surface S1 of the photoelectric conversion layer 2 is coupled to the source 33.
  • the material of the first electrode 81 includes a metal or alloy; the material of the first electrode 81 may also include a metal oxide conductive material, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc gallium oxide At least one of materials such as GZO or aluminum-doped zinc oxide (AZO); the material of the first electrode 81 may also include metal nitride conductive materials, such as titanium nitride (TiN), titanium oxynitride (TiON), At least one of tantalum nitride (TaN) or tantalum oxynitride (TaON). The embodiments of the present disclosure do not limit this.
  • a metal oxide conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc gallium oxide At least one of materials such as GZO or aluminum-doped zinc oxide (AZO)
  • the material of the first electrode 81 may also include metal nitride conductive materials, such as titanium nit
  • the material of the third insulating layer 7 may include at least one of insulating materials such as resin, silicon oxide, and silicon nitride.
  • the source 33 of the thin film transistor 3 and the first surface S1 of the photoelectric conversion layer 2 form an orthographic projection on the base substrate 1, and the photoelectric conversion layer 2 is on the base substrate 1.
  • the orthographic projections do not overlap.
  • the photoelectric conversion layer 2 is not provided above the portion where the source electrode 33 and the first surface S1 of the photoelectric conversion layer 2 are coupled.
  • the part where the source electrode 33 is coupled to the first surface S1 of the photoelectric conversion layer 2 has a certain height, and the photoelectric conversion layer 2 is arranged above the area of the coupling part, which will cause the photoelectric conversion layer 2 to be uneven. This affects the characteristics of the photoelectric conversion layer 2. Therefore, the photoelectric conversion layer 2 is not provided above the area where the source 33 and the first surface S1 of the photoelectric conversion layer 2 form a coupling part, which avoids the adverse effects caused by unevenness of the photoelectric conversion layer 2 and improves the photoelectricity. Conversion layer 2 characteristics.
  • the part of the source 33 of the thin film transistor 3 that is coupled to the first surface S1 of the photoelectric conversion layer 2 is an orthographic projection on the base substrate 1, and it may also be on the substrate 1 with the photoelectric conversion layer 2
  • the orthographic projections on the substrate 1 overlap, which is not limited in the embodiment of the present disclosure.
  • the photoelectric conversion layer 2 is provided above the portion where the source electrode 33 is coupled to the first surface S1 of the photoelectric conversion layer 2. In this way, the laying area of the photoelectric conversion layer 2 can be increased, thereby increasing the filling rate of the flat panel detector substrate 100.
  • the flat panel detector substrate 100 further includes: a fourth insulating layer 9, a second electrode 10 and a third connecting electrode 63.
  • the second electrode 10 is located on the side of the photoelectric conversion layer 2 away from the base substrate 1, and the second electrode 10 is in contact with the second surface S2 of the photoelectric conversion layer 2.
  • the fourth insulating layer 9 is located on a side of the second electrode 10 away from the base substrate 1, and the fourth insulating layer 9 has a fourth via 91 and a fifth via 92.
  • the third transfer electrode 63 is located on the side of the fourth insulating layer 9 away from the base substrate 1, one end of the third transfer electrode 63 is coupled to the second transfer electrode 62 through the fourth via 91, and the third transfer electrode 63 The other end of the photoelectric conversion layer 2 is coupled to the second electrode 10 on the side away from the base substrate 1 through the fifth via hole 92.
  • the third connecting electrode 63 also forms at least a part of the conductive structure 6.
  • the distance between the fourth via 91 and the fifth via 92 in the fourth insulating layer 9 is very close.
  • the distance between the center of the fourth via hole 91 and the center of the fifth via hole 92 is less than or equal to 70 microns. This reduces the length of the third transfer electrode 63 spanning between the fourth via 91 and the fifth via 92, thereby increasing the signal transmission rate of the third transfer electrode 63.
  • the materials of the third connecting electrode 63 and the second electrode 10 are transparent conductive materials. In this way, the third switching electrode 63 and the second electrode 10 are prevented from blocking the photoelectric conversion layer 2.
  • the material of the third transfer electrode 63 is a transparent conductive material.
  • the material of the third via electrode 63 is the same as or different from the material of the second electrode 10.
  • the material of the third transfer electrode 63 includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc gallium oxide (GZO), or aluminum-doped zinc oxide (AZO).
  • the material of the fourth insulating layer 9 may be a transparent insulating material, such as a resin material.
  • the orthographic projection of the fourth via 91 for connecting the second transfer electrode 62 and the third transfer electrode 63 on the base substrate 1 and the third via 71 are on the base substrate 1
  • the orthographic projections do not overlap.
  • the orthographic projection of the fourth via 91 for connecting the second transfer electrode 62 and the third transfer electrode 63 on the base substrate 1 and the third via 71 on the substrate do not overlap.
  • the orthographic projection of the fourth via 91 for connecting the second transfer electrode 62 and the third transfer electrode 63 on the base substrate 1, and the third via 71 on the base substrate 1 The orthographic projection on at least partially overlaps, which is not limited in the embodiment of the present disclosure.
  • the orthographic projection of the photoelectric conversion layer 2 on the base substrate 1 and the orthographic projection of the bias signal line L on the base substrate 1 at least partially overlap.
  • the orthographic projection of the bias signal line L on the base substrate 1 It at least partially overlaps with the orthographic projection of the photoelectric conversion layer 2 on the base substrate 1.
  • the orthographic projection of the photoelectric conversion layer 2 on the base substrate 1 covers the main part of the orthographic projection of the bias signal line L on the base substrate 1, and only the end of the projection of the bias signal line L is exposed.
  • the bias signal line L may also be located on the first electrode layer 8.
  • the bias signal line L is coupled to the second surface S2 of the photoelectric conversion layer 2 from the side of the photoelectric conversion layer 2.
  • the bias signal line L is located outside the range covered by the photoelectric conversion layer 2, so that it is convenient for the bias signal line L to be coupled to the second surface S2 of the photoelectric conversion layer 2 from the side.
  • the first electrode 81 of the first electrode layer 8 is in contact with the first surface S1 of the photoelectric conversion layer 2, the bias signal line L is located beside the first electrode 81, and the first electrode 81 and the bias signal line L are mutually connected. insulation.
  • the bias signal line L is located on the first electrode layer 8
  • the first electrode layer 8 may not be provided with the second transfer electrode 62.
  • the bias signal line L is directly coupled to the third transfer electrode 63 through the fourth via 91 in the fourth insulating layer 9.
  • the third switching electrode 63 is used to realize the coupling with the second surface S2 of the photoelectric conversion layer 2, so that the bias signal line L transmits the bias signal to the second surface S2 of the photoelectric conversion layer 2.
  • the flat panel detector substrate 100 further includes a conductive layer.
  • the conductive layer may be located between the source and drain layer SD and the first electrode layer 8.
  • the bias signal line L may also be located in the conductive layer.
  • the orthographic projection of the bias signal line L on the base substrate 1 and the orthographic projection of the thin film transistor 3 on the base substrate 1 do not overlap, thus avoiding the mutual influence of the bias signal line L and the thin film transistor 3 during signal transmission .
  • the third insulating layer 7 is located between the conductive layer and the first electrode layer 8, and the third insulating layer 7 has a third via 71 therein.
  • the first electrode layer 8 includes a first electrode 81 and a second transfer electrode 62.
  • the first electrode 81 is in contact with the first surface S1 of the photoelectric conversion layer 2, the second transfer electrode 62 is located beside the first electrode 81, the first electrode 81 and the second transfer electrode 62 are insulated from each other, and the second transfer electrode 62
  • the third via 71 is coupled to the bias signal line L located in the conductive layer.
  • the second transfer electrode 62 is also coupled to the second surface S2 of the photoelectric conversion layer 2.
  • the coupling between the second transfer electrode 62 and the second surface S2 of the photoelectric conversion layer 2 is an indirect coupling, for example, through the third transfer electrode 63 and the second electrode 10, the second transfer electrode 62 and the photoelectric conversion layer
  • the second surface S2 of the conversion layer 2 is indirectly coupled, so that the bias signal line L transmits the bias signal to the second surface S2 of the photoelectric conversion layer 2.
  • the flat-panel detector substrate 100 further includes: a protective layer 11 on the side of the photoelectric conversion layer 2 and the conductive structure 6 away from the base substrate 1.
  • the protective layer 11 can protect each layer structure on the base substrate 1 and improve the stability of the flat panel detector substrate 100.
  • the material of the protective layer 11 may be a transparent insulating material, for example, the material of the protective layer 11 is a resin material.
  • the flat-panel detector substrate 100 further includes: a light conversion layer 12 on the side of the protective layer 11 away from the base substrate 1.
  • the light conversion layer 12 is configured to convert X-ray photons into visible light photons.
  • the material of the light conversion layer 12 is cesium iodide (CsI) or gadolinium oxysulfide (GOS).
  • the “same layer arrangement” mentioned in the present disclosure refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a patterning process.
  • a patterning process may include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights. Or have different thicknesses.
  • the source 33 and the drain 34 in the thin film transistor 3 are generally symmetrical in structure, there is no difference in structure between the source 33 and the drain 34. of.
  • one of the electrodes is called the source 33 and the other is called the drain 34.
  • the connection relationship between the two can also be interchanged. This is an equivalent transformation of the above-mentioned embodiment of the present disclosure. .
  • an embodiment of the present disclosure also provides a method for manufacturing a flat panel detector substrate.
  • the manufacturing method includes: S100 to S300.
  • a base substrate 1 is provided, and a bias signal line L is formed on the base substrate 1.
  • the bias signal line L can be arranged in the same layer as other film layer structures, or the bias signal line L can also be arranged in a separate layer.
  • the embodiments of the present disclosure do not limit this.
  • the photoelectric conversion layer 2 has a first surface S1 close to the base substrate 1 and a second surface S2 away from the base substrate 1.
  • S300 forming a conductive structure 6 on the base substrate 1.
  • One end of the conductive structure 6 is coupled to the second surface S2 of the photoelectric conversion layer 2, and the other end is coupled to the bias signal line L.
  • the part between the two ends is located beside the photoelectric conversion layer 2, so that the photoelectric conversion layer 2
  • the second surface S2 is coupled to the bias signal line L from the side of the photoelectric conversion layer 2 through the conductive structure 6.
  • the method for manufacturing the flat panel detector substrate 100 further includes: forming the thin film transistor 3 before the step of forming the photoelectric conversion layer 2.
  • the orthographic projection of the active layer 32 of the thin film transistor 3 on the base substrate 1 is within the range of the orthographic projection of the photoelectric conversion layer 2 on the base substrate 1.
  • the manufacturing process of the flat panel detector substrate 100 depends on its specific structure.
  • the following takes the bias signal line L in the gate layer G and the thin film transistor 3 as the bottom gate structure as an example to illustrate the manufacturing method. .
  • the step of forming the thin film transistor 3 includes: S101 to S103.
  • the gate layer G includes the gate 31 of the thin film transistor 3, the gate line 4 and the bias signal line L, and the gate 31 is coupled to the gate line 4.
  • the bias signal line L is located on the gate layer G.
  • the gate electrode 31, the gate line 4 and the bias signal line L can be fabricated through a patterning process to form the gate layer G.
  • the patterning process includes procedures such as glue coating, exposure, development, and etching.
  • the patterning process may include multiple exposure, development, or etching processes, and the specific patterns in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.
  • the gate 31, the gate line 4 and the bias signal line L can be fabricated at the same time, thereby simplifying the fabrication process.
  • the first insulating layer 35 is deposited on the side of the gate layer G away from the base substrate 1.
  • the first insulating layer 35 has a first via hole 351; or, the first insulating layer 35 has a first via hole 351 and a second via hole 352.
  • the orthographic projection of the first via 351 and the second via 352 on the sunken bottom substrate 1 and the orthographic projection of the bias signal line L on the sunken bottom substrate 1 at least partially overlap.
  • the active layer 32 may be fabricated.
  • the flat panel detector substrate 100 further includes at least one of the first dielectric pattern 321 and the second dielectric pattern 322, the first dielectric pattern 321 and the second dielectric pattern 322 may be the same as the active layer 32 same layer production.
  • the source and drain layer SD includes the source 33 and the drain 34 of the thin film transistor 3, the data line 5 and the first switching electrode 61.
  • the source electrode 33 is coupled to the data line 5
  • the first transfer electrode 61 is coupled to the bias signal line L through the first via 351.
  • the source electrode 33 and the drain electrode 34, the data line 5 and the first transfer electrode 61 can be fabricated in the same patterning process to form the source and drain layer SD.
  • the binding electrode 60 can also be produced when the source and drain layers SD are produced.
  • the manufacturing method of the flat panel detector substrate 100 further includes:
  • the third insulating layer 7 is formed.
  • the third insulating layer 7 has a third via 71 and an electrode contact hole 72, as shown in FIG. 10.
  • the first electrode layer 8 includes a first electrode 81 in contact with the first surface S1 of the photoelectric conversion layer 2, and a second transfer electrode 62 located beside the first electrode 81, the first electrode 81 and the second transfer electrode 62 Insulated from each other, the second transfer electrode 62 is coupled to the first transfer electrode 61 through the third via 71, as shown in FIG. 11.
  • the manufacturing method of the flat panel detector substrate 100 further includes:
  • the fourth insulating layer 9 has a fourth via 91 and a fifth via 92, as shown in FIG. 14.
  • the first switching electrode 61, the second switching electrode 62 and the third switching electrode 63 form at least a part of the conductive structure 6.
  • An embodiment of the present disclosure also provides a flat-panel detector 200.
  • the flat-panel detector 200 includes the flat-panel detector substrate 100 and the driving chip 202 described in any of the foregoing embodiments.
  • the flat panel detector substrate 100 has a plurality of photosensitive regions GG, and each photosensitive region GG is provided with a photoelectric conversion layer, a bias signal line and a thin film transistor.
  • the thin film transistor is coupled to the first side of the photoelectric conversion layer, and the bias signal line is coupled to the second side of the photoelectric conversion layer.
  • the driving chip 202 is coupled to the flat panel detector substrate 100.
  • the driving chip 202 is coupled to the flat panel detector substrate 100 through a flexible printed circuit (FPC) 201.
  • FPC flexible printed circuit
  • the driving chip 201 is configured to transmit a bias signal to the bias signal line L of the flat panel detector substrate 100, so that the bias signal can be transmitted to the second surface of the photoelectric conversion layer through the bias signal line.
  • the driving chip 201 is also configured to control the thin film transistor in the flat panel detector substrate 100 to turn on, and transmit a voltage signal to the first surface of the photoelectric conversion layer coupled with the thin film transistor.
  • the photoelectric conversion layer can be driven to sense and collect light, such as collecting X-rays passing through the human body, and outputting corresponding electrical signals.
  • the beneficial effects achieved by the flat-panel detector 200 provided in the embodiments of the present disclosure are the same as the beneficial effects of the flat-panel detector substrate 100 described above, and will not be repeated here.

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Abstract

一种平板探测器基板，包括：衬底基板、光电转换层、偏压信号线和导电结构。光电转换层位于所述衬底基板上；所述光电转换层具有靠近所述衬底基板的第一面和远离所述衬底基板的第二面。偏压信号线位于所述光电转换层与所述衬底基板之间。导电结构位于所述衬底基板上；所述导电结构的一端与所述光电转换层的第二面耦接，另一端与所述偏压信号线耦接，两端之间的部分位于所述光电转换层的旁侧。

Description

平板探测器基板及其制作方法、平板探测器 技术领域
本公开涉及平板探测器技术领域，尤其涉及一种平板探测器基板及制作方法、平板探测器。
背景技术
数字化X射线摄影(Digital Radiography，DR)，以其更快的成像速度、更便捷的操作、更高的成像分辨率等显著优点，成为数字X射线摄影技术的主要方向。数字化X射线摄影的技术核心是X射线平板探测器，X射线平板探测器是一种精密和贵重的设备，对成像质量起着决定性的作用。
发明内容
一方面，提供一种平板探测器基板，包括：衬底基板、光电转换层、偏压信号线和导电结构。光电转换层位于所述衬底基板上；所述光电转换层具有靠近所述衬底基板的第一面和远离所述衬底基板的第二面。偏压信号线位于所述光电转换层与所述衬底基板之间。导电结构位于所述衬底基板上；所述导电结构的一端与所述光电转换层的第二面耦接，另一端与所述偏压信号线耦接，两端之间的部分位于所述光电转换层的旁侧。
在一些实施例中，平板探测器基板，还包括：薄膜晶体管、栅线和数据线。薄膜晶体管位于所述光电转换层与所述衬底基板之间，所述薄膜晶体管包括栅极、有源层、源极和漏极，所述源极与所述光电转换层的第一面耦接；所述薄膜晶体管的有源层在所述衬底基板上的正投影处于所述光电转换层在所述衬底基板上的正投影范围之内。栅线与所述薄膜晶体管的栅极同层设置，所述栅极与所述栅线耦接；所述栅极和所述栅线所在膜层为栅极层。数据线与所述薄膜晶体管的源极和漏极同层设置，所述源极与所述数据线耦接；所述源极、所述漏极和所述数据线所在膜层为源漏极层，所述源漏极层位于所述栅极层远离所述衬底基板的一侧。
在一些实施例中，所述偏压信号线位于所述栅极层。所述平板探测器基板还包括：第一绝缘层和第一转接电极。第一绝缘层位于所述栅极层和所述源漏极层之间，所述第一绝缘层中具有第一过孔。第一 转接电极位于所述源漏极层，所述第一转接电极通过所述第一过孔与所述偏压信号线耦接，所述第一转接电极还与所述光电转换层的第二面耦接。其中，所述第一转接电极形成所述导电结构的至少一部分。
在一些实施例中，所述第一转接电极在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影相交叠。所述平板探测器基板还包括第一介电图案。第一介电图案位于所述第一转接电极与所述栅线的交叠区域，所述第一介电图案位于所述栅线与所述第一转接电极之间；所述第一介电图案的材料为半导体材料和绝缘材料中的至少一种。
在一些实施例中，所述有源层位于所述栅极层与所述源漏极层之间，所述第一绝缘层位于所述栅极层与所述有源层之间；所述第一介电图案与所述有源层同层设置。
在一些实施例中，所述栅线在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影相交叠。所述平板探测器基板还包括第二介电图案。第二介电图案位于所述栅线与所述数据线的交叠区域，所述第二介电图案位于所述栅线与所述数据线之间。其中，所述第一介电图案与所述第二介电图案同层设置。
在一些实施例中，所述有源层位于所述栅极层与所述衬底基板之间。所述平板探测器基板还包括第二绝缘层。第二绝缘层位于所述有源层和所述栅极层之间，所述第一绝缘层和所述第二绝缘层中具有贯通二者的源极接触孔和漏极接触孔；所述源极通过所述源极接触孔与所述有源层形成电接触，所述漏极通过所述漏极接触孔与所述有源层形成电接触。
在一些实施例中，所述第一绝缘层中还具有第二过孔。所述平板探测器基板还包括绑定电极。绑定电极位于所述源漏极层，所述绑定电极通过所述第二过孔与所述偏压信号线耦接。所述绑定电极被配置为，与驱动芯片绑定，以接收来自所述驱动芯片的偏置信号，并将所述偏置信号传输至所述偏压信号线。
在一些实施例中，所述偏压信号线位于所述源漏极层。所述偏压信号线的一端延伸至所述光电转换层所覆盖的范围之外，且所述偏压信号线的该端从所述光电转换层的旁侧与所述光电转换层的第二面 耦接。
在一些实施例中，平板探测器基板还包括：第三绝缘层和第一电极层。第三绝缘层位于所述源漏极层与所述光电转换层之间，所述第三绝缘层中具有第三过孔。第一电极层位于所述第三绝缘层与所述光电转换层之间；所述第一电极层包括与所述光电转换层的第一面接触的第一电极，及位于所述第一电极旁侧的第二转接电极，所述第一电极与所述第二转接电极相互绝缘；所述第二转接电极通过所述第三过孔与所述偏压信号线耦接。其中，所述第二转接电极形成所述导电结构的至少一部分。
在一些实施例中，所述第三绝缘层中还具有电极接触孔。所述第一电极通过所述电极接触孔与所述薄膜晶体管的源极耦接，以使所述光电转换层的第一面与所述源极耦接。
在一些实施例中，平板探测器基板，还包括：第二电极、第四绝缘层和第三转接电极。第二电极位于所述光电转换层远离所述衬底基板一侧，所述第二电极与所述光电转换层的第二面接触。第四绝缘层位于所述第二电极远离所述衬底基板一侧，所述第四绝缘层中具有第四过孔和第五过孔。第三转接电极位于所述第四绝缘层远离所述衬底基板一侧；所述第三转接电极的一端通过第四过孔与所述第二转接电极耦接，另一端通过第五过孔与所述光电转换层的第二电极耦接。其中，所述第三转接电极形成所述导电结构的至少一部分。
在一些实施例中，述第三转接电极的材料为透明导电材料。
在一些实施例中，所述第四过孔在所述衬底基板上的正投影，与所述第三过孔在所述衬底基板上的正投影不重叠。
在一些实施例中，所述光电转换层在所述衬底基板上的正投影与所述偏压信号线在所述衬底基板上的正投影至少部分重叠。
在一些实施例中，所述平板探测器基板还包括：第三绝缘层和第一电极层。第三绝缘层位于所述源漏极层与所述光电转换层之间。第一电极层位于所述第三绝缘层与所述光电转换层之间，所述第一电极层包括与所述光电转换层的第一面接触的第一电极，及所述偏压信号线；所述偏压信号线与所述第一电极相互绝缘，所述偏压信号线从所述光电转换层的旁侧与所述光电转换层的第二面耦接。
在一些实施例中，所述薄膜晶体管的源极与所述光电转换层的第一面形成耦接的部分在所述衬底基板上的正投影，与所述光电转换层在所述衬底基板上的正投影不重叠。
在一些实施例中，所述平板探测器基板具有多个感光区域；每个感光区域内设置有所述光电转换层、所述偏压信号线和所述导电结构。所述多个感光区域呈阵列式排布；所述偏压信号线沿行方向或列方向延伸。
另一方面，提供一种平板探测器，所述平板探测器包括：上述任一实施例所述的平板探测器基板；以及，与所述平板探测器基板耦接的驱动芯片。所述驱动芯片被配置为，向所述平板探测器基板的偏压信号线传输偏压信号。
又一方面，提供一种平板探测器基板的制作方法，包括：
提供衬底基板，在所述衬底基板上形成偏压信号线。
在形成有所述偏压信号线的衬底基板的一侧形成光电转换层；所述光电转换层具有靠近所述衬底基板的第一面和远离所述衬底基板的第二面。
在所述衬底基板上形成导电结构；所述导电结构的一端与所述光电转换层的第二面耦接，另一端与所述偏压信号线耦接，两端之间的部分位于所述光电转换层的旁侧，以使所述光电转换层的第二面通过所述导电结构从所述光电转换层的旁侧与所述偏压信号线耦接。
在一些实施例中，所述的制作方法，还包括：在所述形成所述光电转换层的步骤之前，形成薄膜晶体管；所述薄膜晶体管的有源层在所述衬底基板上的正投影处于所述光电转换层在所述衬底基板上的正投影范围之内。
所述形成薄膜晶体管的步骤，包括：
在所述衬底基板上形成栅极层；所述栅极层包括薄膜晶体管的栅极、栅线和所述偏压信号线，所述栅极与所述栅线耦接。
在所述栅极层远离所述衬底基板的一侧形成第一绝缘层；所述第一绝缘层中具有第一过孔。
在所述第一绝缘层远离所述衬底基板的一侧形成源漏极层；所述源漏极层包括薄膜晶体管的源极和漏极、数据线和第一转接电极，所 述源极与所述数据线耦接，所述第一转接电极通过所述第一过孔与所述偏压信号线耦接。
在一些实施例中，所述的制作方法，还包括：
在所述形成薄膜晶体管的步骤与所述形成光电转换层的步骤之间，形成第三绝缘层；所述第三绝缘层中具有第三过孔。
在所述第三绝缘层远离所述衬底基板的一侧形成第一电极层；所述第一电极层包括与所述光电转换层的第一面接触的第一电极，及位于所述第一电极旁侧的第二转接电极，所述第一电极与所述第二转接电极相互绝缘，所述第二转接电极通过所述第三过孔与所述第一转接电极耦接。
在一些实施例中，所述的制作方法，还包括：
在形成所述光电转换层的步骤之后，形成第二电极；所述第二电极与所述光电转换层的第二面接触。
在所述光电转换层远离所述衬底基板的一侧形成第四绝缘层；所述第四绝缘层中具有第四过孔和第五过孔。
在所述第四绝缘层远离所述衬底基板的一侧形成第三转接电极；所述第三转接电极的一端通过第四过孔与所述第二转接电极耦接，另一端通过第五过孔与所述第二电极耦接。
其中，所述第一转接电极、所述第二转接电极和所述第三转接电极形成所述导电结构的至少一部分。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程等的限制。
图1为根据相关技术的平板探测器基板的剖视图；
图2A为根据一些实施例的平板探测器基板的俯视图；
图2B为图2A所示的平板探测器基板的局部放大图；
图3为根据图2的平板探测器基板的沿AA线的剖视图；
图4为根据图2的平板探测器基板的沿BB线的剖视图；
图5为根据图2的平板探测器基板的沿CC线的剖视图；
图6～图15为根据一些实施例的平板探测器基板的制作过程示意图；
图16为根据一些实施例的平板探测器基板的制作方法的一种流程图；
图17为根据一些实施例的平板探测器基板的制作方法的另一种流程图；
图18为根据一些实施例的平板探测器的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
X射线平板探测器按照能量转换的方式可以分为两种：间接转换X射线平板探测器(Indirect Flat Panel X-ray Detector)和直接转换X射线平板探测器(Direct Flat Panel X-ray Detector)。以下，以间接转换X射线平板探测器为例进行示意。
相关技术中，如图1所示，平板探测器基板100’包括衬底基板1’、薄膜晶体管3’、光电转换层2’以及偏压信号线L’。偏压信号线L’位于光电转换层2’上方，偏压信号线L’被配置为向光电转换层2’远离衬底基板1’的一面传输偏压信号，使得光电转换层2’接收可见光的照射后，可以产生光电流。
示例性地，薄膜晶体管3’包括栅极31’、有源层32’、源极33’、漏极34’以及位于栅极31’和有源层32’之间的第一绝缘层35’。
由于偏压信号线L’位于光电转换层2’上方，且使用金属材料，因此偏压信号线L’会对光电转换层造成遮挡。此外，在薄膜晶体管3’采用底栅结构的情况下，需要在有源层32’的上方设置遮光金属遮挡有源层32’。示例性地，偏压信号线L’与遮光金属同层设置。通过设置遮光金属可以避免有源层32’受到光照，造成薄膜晶体管3’因产生光生电流而漏电流增大。上述遮光金属位于光电转换层2’上方，同样会对光电转换层2’造成遮挡。
由于偏压信号线L’及遮光金属的存在，会对光电转换层2’造成遮挡，影响光电转换层2’接收可见光信号，导致平板探测器基板 100’的填充率下降，从而影响平板探测器基板100’的灵敏度及量子检出效率。
基于此，本公开提供一种平板探测器基板100，如图2A、图2B、图3、图4和图5所示，平板探测器基板100包括：衬底基板1、光电转换层2、偏压信号线L以及导电结构6。
光电转换层2位于衬底基板1上，光电转换层2具有靠近衬底基板1的第一面S1和远离衬底基板1的第二面S2。
示例性地，光电转换层包括PIN型光电二极管、NIP型光电二极管或者PN型光电二极管中的至少一种。
偏压信号线L位于光电转换层2与衬底基板1之间。
导电结构6位于衬底基板1上，导电结构6的一端与光电转换层2的第二面S2耦接，另一端与偏压信号线L耦接，两端之间的部分位于光电转换层2的旁侧，以使光电转换层2的第二面S2通过导电结构6从光电转换层2的旁侧与偏压信号线L耦接。
这样，偏压信号线L通过导电结构6实现向光电转换层2的第二面S2传输偏压信号，并且偏压信号线L位于光电转换层2下方，使得偏压信号线L不会对光电转换层2造成遮挡，从而不会影响光电转换层2接收可见光信号，提高了平板探测器基板100的填充率，进而提高了平板探测器基板100的灵敏度及量子检出效率。
此外，由于不需要在光电转换层2上方设置具有偏压信号线L’(如图1所示)的金属膜层以及与其共生的钝化层4’(如图1所示)，从而减少了制作平板探测器基板的阵列(Array)工序。
在一些实施例中，如图2B、图3、图4和图5所示，平板探测器基板100还包括：薄膜晶体管3、栅线4以及数据线5。薄膜晶体管3位于光电转换层2与衬底基板1之间，薄膜晶体管3包括栅极31、有源层32、源极33和漏极34，源极33与光电转换层2的第一面S1耦接。薄膜晶体管3的有源层32在衬底基板1上的正投影处于光电转换层2在衬底基板1上的正投影范围之内。
示例性地，薄膜晶体管3位于光电转换层2与衬底基板1之间，并且，薄膜晶体管3的有源层32在衬底基板1上的正投影处于光电转换层2在衬底基板1上的正投影范围之内。这样，光电转换层2可 以对薄膜晶体管3形成遮挡，避免可见光照射薄膜晶体管3，从而避免了由此产生的薄膜晶体管3漏电流过大的问题。
在一些实施例中，如图2B、图3、图4和图6所示，栅线4与薄膜晶体管3的栅极31同层设置，栅极31与栅线4耦接；栅极31和栅线4所在膜层为栅极层G。如图2B、图3、图4和图9所示，数据线5与薄膜晶体管3的源极33和漏极34同层设置，源极33与数据线5耦接。源极33、漏极34和数据线5所在膜层为源漏极层SD，源漏极层SD位于栅极层G远离衬底基板1的一侧。
在一些实施例中，薄膜晶体管3为底栅结构或者顶栅结构，本公开实施例对此不做限定。
在一些实施例中，薄膜晶体管3为底栅结构。有源层32位于栅极层G与衬底基板1之间。平板探测器基板还包括第一绝缘层35，第一绝缘层35位于栅极层G与有源层32之间，有源层32位于栅极层G与源漏极层SD之间。
在一些实施例中，薄膜晶体管3为顶栅结构。平板探测器基板还包括第一绝缘层35和第二绝缘层。第二绝缘层位于有源层32和栅极层G之间，第一绝缘层35和第二绝缘层中具有贯通二者的源极接触孔和漏极接触孔。源极33通过源极接触孔与有源层32形成电接触，漏极34通过漏极接触孔与有源层32形成电接触。
以下，均以薄膜晶体管3为底栅结构为例进行示意。
在一些实施例中，如图2B、图4和图6所示，偏压信号线L可以位于栅极层G。如图2B、图4和图7所示，第一绝缘层35中具有第一过孔351。如图2、图4、图5和图9所示，平板探测器基板100还包括第一转接电极61。第一转接电极61位于源漏极层SD，第一转接电极61通过第一过孔351与偏压信号线L耦接，第一转接电极61还与光电转换层2的第二面S2耦接。其中，第一转接电极61形成导电结构6的至少一部分。
需要说明的是，此处，第一转接电极61与光电转换层2的第二面S2之间的耦接可以是间接耦接，即，二者之间通过一些结构实现耦接，后续实施例中会给出一些实现方式。
在一些实施例中，如图2B和图9所示，第一转接电极61在衬 底基板1上的正投影与栅线4在衬底基板1上的正投影相交叠。如图2B、图8和图9所示，平板探测器基板100还包括：位于第一转接电极61与栅线4的交叠区域的第一介电图案321，第一介电图案321位于栅线4与第一转接电极61之间。
示例性地，第一介电图案321在衬底基板1上的正投影的面积大于或等于栅线4与第一转接电极61的交叠区域在衬底基板1上的正投影面积。
示例性地，第一介电图案321的材料为半导体材料和绝缘材料中的至少一种。这样，第一介电图案321增大了第一转接电极61与栅线4之间介电材料的介电常数，从而第一介电图案321可以减小栅线4与第一转接电极61之间的寄生电容。
在第一介电图案321的材料为半导体材料的情况下，示例性地，由于有源层32位于栅极层G与源漏极层SD之间，第一绝缘层35位于栅极层G与有源层32之间，因此第一介电图案321可以与有源层32同层设置。这样，第一介电图案321可以与有源层32在同一制作工艺中形成，简化了制作流程。
在一些实施例中，如图2B、图8和图9所示，栅线4在衬底基板1上的正投影与数据线5在衬底基板1上的正投影相交叠。平板探测器基板100还包括第二介电图案322，第二介电图案322位于栅线4与数据线5的交叠区域，第二介电图案322位于栅线4与数据线5之间。第二介电图案322的材料为半导体材料和绝缘材料中的至少一种。这样，第二介电图案322可以减小栅线4与数据线5之间的寄生电容。
示例性地，第二介电图案322在衬底基板1上的正投影的面积大于或等于栅线4与数据线5的交叠区域在衬底基板1上的正投影面积。
示例性地，第一介电图案321可以与第二介电图案322同层设置，或者，第一介电图案321、第二介电图案322和有源层32可以同层设置，这样可以简化制作流程。
在一些实施例中，如图2B、图7、图8和图9所示，第一绝缘层35中还具有第二过孔352。平板探测器基板100还包括绑定电极60，绑定电极60可以位于源漏极层SD，绑定电极60通过第二过孔 352与偏压信号线L耦接。绑定电极60被配置为，与外部的驱动芯片绑定，以接收来自驱动芯片的偏置信号，并将偏置信号传输至偏压信号线L。
在一些实施例中，如图2A所示，平板探测器基板100具有多个感光区域GG。如图2B所示，每个感光区域GG内设置有光电转换层2、偏压信号线L和导电结构6。多个感光区域GG呈阵列式排布，偏压信号线L沿行方向或列方向延伸。
示例性地，外部的驱动芯片通过连接线逐列向每个感光区域GG内的绑定电极60传输偏压信号，绑定电极60通过第二过孔352将偏压信号传输至其对应感光区域内的偏压信号线L，从而实现绑定电极60对偏压信号的接收和传输。
在一些实施例中，偏压信号线L也可以位于源漏极层SD。偏压信号线L的一端延伸至光电转换层2所覆盖的范围之外，且偏压信号线L的这一端从光电转换层2的旁侧与光电转换层2的第二面S2耦接。在此情况下，第一绝缘层35中可以不设置第一过孔351、第二过孔352。在源漏极层SD可以设置绑定电极60，也可以不设置绑定电极60，本公开实施例对此不做限定。
示例性地，在源漏极层不设置绑定电极60的情况下，偏压信号线L直接与驱动芯片耦接，偏压信号线L直接接收来自驱动芯片的偏压信号。
在一些实施例中，如图2B、图3、图4、图5和图11所示，平板探测器基板100还包括第三绝缘层7和第一电极层8。第三绝缘层7位于源漏极层SD与光电转换层2之间，第三绝缘层7中具有第三过孔71。第一电极层8位于第三绝缘层7与光电转换层2之间。
第一电极层8包括第一电极81和第二转接电极62。第一电极81与光电转换层2的第一面S1接触，第二转接电极62位于第一电极81旁侧，第一电极81与第二转接电极62相互绝缘，第二转接电极62通过第三过孔71与偏压信号线L耦接。其中，第二转接电极62形成导电结构6的至少一部分。
此处，第二转接电极62与偏压信号线L的耦接可以为间接耦接，例如，在偏压信号线L位于栅极层G的情况下，第二转接电极62通 过第三过孔71、第一转接电极61、第一过孔351与偏压信号线L实现耦接。
第二转接电极62还与光电转换层2的第二面S2耦接。
此处，第二转接电极62与光电转换层2的第二面S2的耦接为间接耦接，二者之间通过一些结构实现耦接，后续实施例中会给出一些实现方式。
需要说明的是，第一电极81与第二转接电极62同层设置且相互绝缘，这样可以避免与第二转接电极62耦接的偏压信号线L和第一电极81耦接，从而确保了偏压信号线L中的偏压信号不会传输至光电转换层2的第一面S1。
在一些实施例中，如图2B、图11所示，第三绝缘层7中还具有电极接触孔72。第一电极81通过电极接触孔72与薄膜晶体管3的源极33耦接，以使光电转换层2的第一面S1与源极33耦接。
示例性地，第一电极81的材料包括金属或者合金；第一电极81的材料也可以包括金属氧化物导电材料，例如铟锡氧化物(ITO)、铟锌氧化物(IZO)、锌镓氧化物(GZO)或者掺铝氧化锌(AZO)等材料中的至少一种；第一电极81的材料也可以包括金属氮化物导电材料，例如氮化钛(TiN)、氮氧化钛(TiON)、氮化钽(TaN)或者氮氧化钽(TaON)等材料中的至少一种。本公开实施例对此不做限定。
示例性地，第三绝缘层7的材料可以包括树脂、氧化硅、氮化硅等绝缘材料中的至少一种。
在一些实施例中，薄膜晶体管3的源极33与光电转换层2的第一面S1形成耦接的部分在衬底基板1上的正投影，与光电转换层2在衬底基板1上的正投影不重叠。
示例性地，在源极33与光电转换层2的第一面S1形成耦接的部分上方，不设置光电转换层2。
需要指出的是，源极33与光电转换层2的第一面S1形成耦接的部分具有一定高度，在上述耦接部分的区域上方设置光电转换层2，会造成光电转换层2不平整，从而影响光电转换层2的特性。因此，在源极33与光电转换层2的第一面S1形成耦接部分的区域上方，不 设置光电转换层2，避免了由于对光电转换层2不平整所造成的不良影响，提高了光电转换层2的特性。
在另一些实施例中，薄膜晶体管3的源极33中与光电转换层2的第一面S1形成耦接的部分在衬底基板1上的正投影，也可以与光电转换层2在衬底基板1上的正投影重叠，本公开实施例对此不做限定。
示例性地，在源极33与光电转换层2的第一面S1形成耦接的部分上方，设置光电转换层2。这样，可以增大光电转换层2的铺设面积，从而提高了平板探测器基板100的填充率。
在一些实施例中，如图2B、图3、图4、图5和图15所示，平板探测器基板100还包括：第四绝缘层9、第二电极10和第三转接电极63。第二电极10位于光电转换层2远离衬底基板1一侧，第二电极10与光电转换层2的第二面S2接触。第四绝缘层9位于第二电极10远离衬底基板1的一侧，第四绝缘层9中具有第四过孔91和第五过孔92。
第三转接电极63位于第四绝缘层9远离衬底基板1一侧，第三转接电极63的一端通过第四过孔91与第二转接电极62耦接，第三转接电极63的另一端通过第五过孔92与光电转换层2远离衬底基板1一侧的第二电极10耦接。其中，第三转接电极63也形成导电结构6的至少一部分。
这样，通过第二转接电极62、第三转接电极63以及第二电极10，实现了偏压信号线L与光电转换层2的第二面S2的耦接。
示例性地，第四绝缘层9中的第四过孔91和第五过孔92之间的距离很近。例如，第四过孔91的中心和第五过孔92的中心之间的距离小于或者等于70微米。这样使得跨越第四过孔91和第五过孔92之间第三转接电极63的长度减小，从而提高了第三转接电极63的信号传输速率。
在一些实施例中，第三转接电极63和第二电极10的材料为透明导电材料。这样，避免了第三转接电极63和第二电极10对光电转换层2造成遮挡。
示例性地，第三转接电极63的材料为透明导电材料。第三转接 电极63的材料与第二电极10的材料相同或者不相同。例如，第三转接电极63的材料包括铟锡氧化物(ITO)、铟锌氧化物(IZO)、锌镓氧化物(GZO)或者掺铝氧化锌(AZO)等材料中的至少一种。
示例性地，第四绝缘层9的材料可以为透明绝缘材料，例如树脂材料。
在一些实施例中，用于连接第二转接电极62与第三转接电极63的第四过孔91在衬底基板1上的正投影，与第三过孔71在衬底基板1上的正投影不重叠。
示例性地，如图14所示，用于连接第二转接电极62与第三转接电极63的第四过孔91在衬底基板1上的正投影与第三过孔71在衬底基板1上的正投影不重叠。
在另一些实施例中，用于连接第二转接电极62与第三转接电极63的第四过孔91在衬底基板1上的正投影，与第三过孔71在衬底基板1上的正投影至少部分重叠，本公开实施例对此不做限定。
在一些实施例中，光电转换层2在衬底基板1上的正投影与偏压信号线L在衬底基板1上的正投影至少部分重叠。例如，在偏压信号线L位于栅极层G(如图2B、图6、图9所示)或者位于源漏层SD的情况下，偏压信号线L在衬底基板1上的正投影与光电转换层2在衬底基板1上的正投影至少部分重叠。例如，光电转换层2在衬底基板1上的正投影覆盖偏压信号线L在衬底基板1上的正投影的主体部分，仅露出偏压信号线L的投影的端部。
在一些实施例中，偏压信号线L也可以位于第一电极层8。偏压信号线L从光电转换层2的旁侧与光电转换层2的第二面S2耦接。例如，偏压信号线L位于光电转换层2所覆盖的范围之外，这样，便于偏压信号线L从旁侧与光电转换层2的第二面S2耦接。
示例性地，第一电极层8的第一电极81与光电转换层2的第一面S1接触，偏压信号线L位于第一电极81旁侧，第一电极81与偏压信号线L相互绝缘。例如，偏压信号线L位于第一电极层8的情况下，偏压信号线L在衬底基板1上的正投影与栅线4在衬底基板1上的正投影重合或者至少部分重合。
在此情况下，第一电极层8可以不设置第二转接电极62。例如， 在第一电极层8中不设置第二转接电极62的情况下，偏压信号线L直接通过第四绝缘层9中的第四过孔91与第三转接电极63耦接，并通过第三转接电极63实现与光电转换层2的第二面S2进行耦接，从而实现偏压信号线L向光电转换层2的第二面S2传输偏压信号。
在一些实施例中，平板探测器基板100还包括导电层。导电层可以位于源漏极层SD和第一电极层8之间，在此情况下，偏压信号线L也可以位于导电层。偏压信号线L在衬底基板1上的正投影与薄膜晶体管3在衬底基板1上的正投影没有重叠，这样，避免了偏压信号线L和薄膜晶体管3在传输信号时的相互影响。
在此情况下，示例性地，第三绝缘层7位于导电层与第一电极层8之间，第三绝缘层7中具有第三过孔71。第一电极层8包括第一电极81和第二转接电极62。第一电极81与光电转换层2的第一面S1接触，第二转接电极62位于第一电极81旁侧，第一电极81与第二转接电极62相互绝缘，第二转接电极62通过第三过孔71与位于导电层的偏压信号线L耦接。
并且，第二转接电极62还与光电转换层2的第二面S2耦接。
此处，第二转接电极62与光电转换层2的第二面S2的耦接为间接耦接，例如通过第三转接电极63及第二电极10，实现第二转接电极62与光电转换层2的第二面S2的间接耦接，从而实现偏压信号线L向光电转换层2的第二面S2传输偏压信号。
在一些实施例中，如图3、图4和图5所示，平板探测器基板100还包括：位于光电转换层2和导电结构6远离衬底基板1一侧的保护层11。这样，保护层11可以对位于衬底基板1上的各膜层结构起到保护作用，提高了平板探测器基板100的稳定性。
示例性地，保护层11的材料可以为透明绝缘材料，例如，保护层11的材料为树脂材料。
在一些实施例中，如图3、图4和图5所示，平板探测器基板100还包括：位于保护层11远离衬底基板1一侧的光转换层12。光转换层12被配置为将X射线光子转化为可见光光子。
示例性地，光转换层12的材料为碘化铯(CsI)或者硫氧化钆(GOS)。
需要说明的是，本公开中所提及的“同层设置”，指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。
此外，本公开实施例中所涉及的薄膜晶体管3，由于薄膜晶体管3中的源极33、漏极34在结构上通常是对称的，所以其源极33、漏极34在结构上是没有区别的。在本公开实施例中，为区分薄膜晶体管3除栅极31之外的两极，将其中一极称为源极33，另一极称为漏极34。然而本领域的技术人员应当明白，由于所述薄膜晶体管的源极和漏极在结构上的可互换性，两者的连接关系也可以互换，这属于本公开的上述实施例的等同变换。
此外，本公开实施例还提供一种平板探测器基板的制作方法，参考图2B～图16所示，制作方法包括：S100～S300。
S100：提供衬底基板1，在衬底基板1上形成偏压信号线L。
示例性地，偏压信号线L可以与其他膜层结构同层设置，或者，偏压信号线L也可以单独一层设置。本公开实施例对此不做限定。
S200：在形成有偏压信号线L的衬底基板1的一侧形成光电转换层2。光电转换层2具有靠近衬底基板1的第一面S1和远离衬底基板1的第二面S2。
S300：在衬底基板1上形成导电结构6。导电结构6的一端与光电转换层2的第二面S2耦接，另一端与偏压信号线L耦接，两端之间的部分位于光电转换层2的旁侧，以使光电转换层2的第二面S2通过导电结构6从光电转换层2的旁侧与偏压信号线L耦接。
在一些实施例中，平板探测器基板100的制作方法，还包括：在形成光电转换层2的步骤之前，形成薄膜晶体管3。薄膜晶体管3有源层32在衬底基板1上的正投影处于光电转换层2在衬底基板1上的正投影范围之内。
需要指出的是，平板探测器基板100的制作过程根据其具体结构而定，下面以偏压信号线L位于栅极层G、薄膜晶体管3为底栅结构 为例，对制作方法进行示例性介绍。
如图17所示，在一些实施例中，形成薄膜晶体管3的步骤包括：S101～S103。
S101：在衬底基板1上形成栅极层G。其中，栅极层G包括薄膜晶体管3的栅极31、栅线4和偏压信号线L，栅极31与栅线4耦接。
示例性地，如图6所示，偏压信号线L位于栅极层G，例如可以通过一道构图工艺制作栅极31、栅线4和偏压信号线L，形成栅极层G。
此处，构图工艺包括涂胶、曝光、显影、刻蚀等工序。构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形，可以是连续的也可以是不连续的，这些特定图形还可能处于不同的高度或者具有不同的厚度。这样一来，可以同时制作栅极31、栅线4和偏压信号线L，从而简化了制作工艺。
S102：在栅极层G远离衬底基板1的一侧形成第一绝缘层35。其中，第一绝缘层35中具有第一过孔351。
示例性地，如图7所示，在栅极层G远离衬底基板1的一侧沉积第一绝缘层35。第一绝缘层35中具有第一过孔351；或者，第一绝缘层35中具有第一过孔351和第二过孔352。第一过孔351和第二过孔352在沉底基板1上的正投影与偏压信号线L在在沉底基板1上的正投影至少部分重叠。
示例性地，如图8所示，形成第一绝缘层35后，可以制作有源层32。此外，在平板探测器基板100还包括第一介电图案321和第二介电图案322中的至少一者的情况下，第一介电图案321和第二介电图案322可以与有源层32同层制作。
S103：在第一绝缘层35远离衬底基板1的一侧形成源漏极层SD。源漏极层SD包括薄膜晶体管3的源极33和漏极34、数据线5和第一转接电极61。其中，源极33与数据线5耦接，第一转接电极61通过第一过孔351与偏压信号线L耦接。
示例性地，如图9所示，源极33和漏极34、数据线5和第一转接电极61可以在同一道构图工艺中制作完成，以形成源漏极层SD。 此外，在平板探测器基板100还包括绑定电极60的情况下，绑定电极60也可以在制作源漏极层SD时进行制作。
在一些实施例中，平板探测器基板100的制作方法还包括：
S104：在形成薄膜晶体管3的步骤与形成光电转换层2的步骤之间，形成第三绝缘层7。第三绝缘层7中具有第三过孔71和电极接触孔72，如图10所示。
S105：在第三绝缘层7远离衬底基板1的一侧形成第一电极层8。第一电极层8包括与光电转换层2的第一面S1接触的第一电极81，及位于第一电极81旁侧的第二转接电极62，第一电极81与第二转接电极62相互绝缘，第二转接电极62通过第三过孔71与第一转接电极61耦接，如图11所示。
在一些实施例中，平板探测器基板100的制作方法还包括：
S301：在形成光电转换层2的步骤之后，形成第二电极10，第二电极10与光电转换层2的第二面S2接触，如图12和图13所示。
S302：在光电转换层2远离衬底基板1的一侧形成第四绝缘层9。第四绝缘层9中具有第四过孔91和第五过孔92，如图14所示。
S303：在第四绝缘层9远离衬底基板1的一侧形成第三转接电极63。第三转接电极63的一端通过第四过孔91与第二转接电极62耦接，另一端通过第五过孔92与第二电极10耦接，如图15所示。
其中，第一转接电极61、第二转接电极62和第三转接电极63形成导电结构6的至少一部分。
本公开实施例还提供一种平板探测器200，如图18所示，平板探测器200包括如上述任一实施例所述的平板探测器基板100和驱动芯片202。
平板探测器基板100具有多个感光区域GG，每个感光区域GG内设置有光电转换层、偏压信号线和薄膜晶体管。薄膜晶体管与光电转换层的第一面耦接，偏压信号线与光电转换层的第二耦接。
驱动芯片202与平板探测器基板100耦接。例如，驱动芯片202通过柔性线路板201(Flexible Printed Circuit，FPC)与平板探测器基板100耦接。
驱动芯片201被配置为向平板探测器基板100的偏压信号线L 传输偏压信号，这样可通过偏压信号线向光电转换层的第二面传输偏压信号。
此外，驱动芯片201还被配置为控制平板探测器基板100中的薄膜晶体管打开，向与薄膜晶体管耦接的光电转换层的第一面传输电压信号。这样，就能够驱动光电转换层进行光线的感应和采集，例如采集透过人体的X射线，并输出相应的电信号。
本公开实施例中提供的平板探测器200所达到的有益效果与上述平板探测器基板100的有益效果相同，在此不再赘述。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种平板探测器基板，包括：
    衬底基板；
    位于所述衬底基板上的光电转换层，所述光电转换层具有靠近所述衬底基板的第一面和远离所述衬底基板的第二面；
    位于所述光电转换层与所述衬底基板之间的偏压信号线；
    位于所述衬底基板上的导电结构；所述导电结构的一端与所述光电转换层的第二面耦接，另一端与所述偏压信号线耦接，两端之间的部分位于所述光电转换层的旁侧。
  2. 根据权利要求1所述的平板探测器基板，还包括：
    位于所述光电转换层与所述衬底基板之间的薄膜晶体管，所述薄膜晶体管包括栅极、有源层、源极和漏极，所述源极与所述光电转换层的第一面耦接；所述薄膜晶体管的有源层在所述衬底基板上的正投影处于所述光电转换层在所述衬底基板上的正投影范围之内；
    与所述薄膜晶体管的栅极同层设置的栅线，所述栅极与所述栅线耦接；所述栅极和所述栅线所在膜层为栅极层；
    与所述薄膜晶体管的源极和漏极同层设置的数据线，所述源极与所述数据线耦接；所述源极、所述漏极和所述数据线所在膜层为源漏极层，所述源漏极层位于所述栅极层远离所述衬底基板的一侧。
  3. 根据权利要求2所述的平板探测器基板，其中，所述偏压信号线位于所述栅极层；
    所述平板探测器基板还包括：
    位于所述栅极层和所述源漏极层之间的第一绝缘层，所述第一绝缘层中具有第一过孔；
    位于所述源漏极层的第一转接电极，所述第一转接电极通过所述第一过孔与所述偏压信号线耦接，所述第一转接电极还与所述光电转换层的第二面耦接；
    其中，所述第一转接电极形成所述导电结构的至少一部分。
  4. 根据权利要求3所述的平板探测器基板，其中，所述第一转接电极在所述衬底基板上的正投影与所述栅线在所述衬底基板上的正投影相交叠；
    所述平板探测器基板还包括：
    位于所述第一转接电极与所述栅线的交叠区域的第一介电图案，所述第一介电图案位于所述栅线与所述第一转接电极之间；所述第一介电图案的材料为半导体材料和绝缘材料中的至少一种。
  5. 根据权利要求4所述的平板探测器基板，其中，所述有源层位于所述栅极层与所述源漏极层之间，所述第一绝缘层位于所述栅极层与所述有源层之间；
    所述第一介电图案与所述有源层同层设置。
  6. 根据权利要求4或5所述的平板探测器基板，其中，所述栅线在所述衬底基板上的正投影与所述数据线在所述衬底基板上的正投影相交叠；
    所述平板探测器基板还包括：
    位于所述栅线与所述数据线的交叠区域的第二介电图案，所述第二介电图案位于所述栅线与所述数据线之间；
    其中，所述第一介电图案与所述第二介电图案同层设置。
  7. 根据权利要求3所述的平板探测器基板，其中，所述有源层位于所述栅极层与所述衬底基板之间；
    所述平板探测器基板还包括：
    位于所述有源层和所述栅极层之间的第二绝缘层，所述第一绝缘层和所述第二绝缘层中具有贯通二者的源极接触孔和漏极接触孔；所述源极通过所述源极接触孔与所述有源层形成电接触，所述漏极通过所述漏极接触孔与所述有源层形成电接触。
  8. 根据权利要求3～7任一项所述的平板探测器基板，其中，所述第一绝缘层中还具有第二过孔；
    所述平板探测器基板还包括：
    位于所述源漏极层的绑定电极，所述绑定电极通过所述第二过孔与所述偏压信号线耦接；
    所述绑定电极被配置为，与驱动芯片绑定，以接收来自所述驱动芯片的偏置信号，并将所述偏置信号传输至所述偏压信号线。
  9. 根据权利要求2所述的平板探测器基板，其中，所述偏压信号线位于所述源漏极层；
    所述偏压信号线的一端延伸至所述光电转换层所覆盖的范围之 外，且所述偏压信号线的该端从所述光电转换层的旁侧与所述光电转换层的第二面耦接。
  10. 根据权利要求2～9中任一项所述的平板探测器基板，还包括：
    位于所述源漏极层与所述光电转换层之间的第三绝缘层，所述第三绝缘层中具有第三过孔；
    位于所述第三绝缘层与所述光电转换层之间的第一电极层；所述第一电极层包括与所述光电转换层的第一面接触的第一电极，及位于所述第一电极旁侧的第二转接电极，所述第一电极与所述第二转接电极相互绝缘；所述第二转接电极通过所述第三过孔与所述偏压信号线耦接；
    其中，所述第二转接电极形成所述导电结构的至少一部分。
  11. 根据权利要求10所述的平板探测器基板，其中，所述第三绝缘层中还具有电极接触孔；
    所述第一电极通过所述电极接触孔与所述薄膜晶体管的源极耦接，以使所述光电转换层的第一面与所述源极耦接。
  12. 根据权利要求10或11所述的平板探测器基板，还包括：
    位于所述光电转换层远离所述衬底基板一侧的第二电极，所述第二电极与所述光电转换层的第二面接触；
    位于所述第二电极远离所述衬底基板一侧的第四绝缘层，所述第四绝缘层中具有第四过孔和第五过孔；位于所述第四绝缘层远离所述衬底基板一侧的第三转接电极；所述第三转接电极的一端通过所述第四过孔与所述第二转接电极耦接，另一端通过所述第五过孔与所述第二电极耦接；
    其中，所述第三转接电极形成所述导电结构的至少一部分。
  13. 根据权利要求12所述的平板探测器基板，其中，所述第三转接电极的材料为透明导电材料。
  14. 根据权利要求12所述的平板探测器基板，其中，所述第四过孔在所述衬底基板上的正投影，与所述第三过孔在所述衬底基板上的正投影不完全重叠。
  15. 根据权利要求2～14中任一项所述的平板探测器基板，其中，所述光电转换层在所述衬底基板上的正投影与所述偏压信号线在所 述衬底基板上的正投影至少部分重叠。
  16. 根据权利要求2所述的平板探测器基板，还包括：
    位于所述源漏极层与所述光电转换层之间的第三绝缘层；
    位于所述第三绝缘层与所述光电转换层之间的第一电极层，所述第一电极层包括与所述光电转换层的第一面接触的第一电极，及所述偏压信号线；所述偏压信号线与所述第一电极相互绝缘。
  17. 根据权利要求2～16中任一项所述的平板探测器基板，其中，所述薄膜晶体管的源极与所述光电转换层的第一面形成耦接的部分在所述衬底基板上的正投影，与所述光电转换层在所述衬底基板上的正投影不重叠。
  18. 根据权利要求1～17中任一项所述的平板探测器基板，其中，所述平板探测器基板具有多个感光区域；每个感光区域内设置有所述光电转换层、所述偏压信号线和所述导电结构；
    所述多个感光区域呈阵列式排布；所述偏压信号线沿行方向或列方向延伸。
  19. 一种平板探测器，包括：
    如权利要求1～18中任一项所述平板探测器基板；
    与所述平板探测器基板耦接的驱动芯片，所述驱动芯片被配置为，向所述平板探测器基板的偏压信号线传输偏压信号。
  20. 一种平板探测器基板的制作方法，包括：
    提供衬底基板，在所述衬底基板上形成偏压信号线；
    在形成有所述偏压信号线的衬底基板的一侧形成光电转换层；所述光电转换层具有靠近所述衬底基板的第一面和远离所述衬底基板的第二面；
    在所述衬底基板上形成导电结构；所述导电结构的一端与所述光电转换层的第二面耦接，另一端与所述偏压信号线耦接，两端之间的部分位于所述光电转换层的旁侧。
  21. 根据权利要求20所述的制作方法，还包括：在所述形成所述光电转换层的步骤之前，形成薄膜晶体管；所述薄膜晶体管的有源层在所述衬底基板上的正投影处于所述光电转换层在所述衬底基板上的正投影范围之内；
    所述形成薄膜晶体管的步骤，包括：
    在所述衬底基板上形成栅极层；所述栅极层包括薄膜晶体管的栅极、栅线和所述偏压信号线，所述栅极与所述栅线耦接；
    在所述栅极层远离所述衬底基板的一侧形成第一绝缘层；所述第一绝缘层中具有第一过孔；
    在所述第一绝缘层远离所述衬底基板的一侧形成源漏极层；所述源漏极层包括薄膜晶体管的源极和漏极、数据线和第一转接电极，所述源极与所述数据线耦接，所述第一转接电极通过所述第一过孔与所述偏压信号线耦接。
  22. 根据权利要求21所述的制作方法，还包括：
    在所述形成薄膜晶体管的步骤与所述形成光电转换层的步骤之间，形成第三绝缘层；所述第三绝缘层中具有第三过孔；
    在所述第三绝缘层远离所述衬底基板的一侧形成第一电极层；所述第一电极层包括与所述光电转换层的第一面接触的第一电极，及位于所述第一电极旁侧的第二转接电极，所述第一电极与所述第二转接电极相互绝缘，所述第二转接电极通过所述第三过孔与所述第一转接电极耦接。
  23. 根据权利要求21所述的制作方法，还包括：
    在形成所述光电转换层的步骤之后，形成第二电极；所述第二电极与所述光电转换层的第二面接触；
    在所述光电转换层远离所述衬底基板的一侧形成第四绝缘层；所述第四绝缘层中具有第四过孔和第五过孔；
    在所述第四绝缘层远离所述衬底基板的一侧形成第三转接电极；所述第三转接电极的一端通过第四过孔与所述第二转接电极耦接，另一端通过第五过孔与所述第二电极耦接；
    其中，所述第一转接电极、所述第二转接电极和所述第三转接电极形成所述导电结构的至少一部分。
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CN107851667A (zh) * 2015-06-04 2018-03-27 夏普株式会社 有源矩阵基板
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CN109979948A (zh) * 2017-12-27 2019-07-05 乐金显示有限公司 数字x射线检测器用阵列基板及包括其的x射线检测器
CN110660816A (zh) * 2018-06-29 2020-01-07 京东方科技集团股份有限公司 一种平板探测器
CN109727968A (zh) * 2019-02-26 2019-05-07 京东方科技集团股份有限公司 平板探测器及制作方法

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