WO2021197104A1 - 用于数据通信的编码方法及装置 - Google Patents

用于数据通信的编码方法及装置 Download PDF

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WO2021197104A1
WO2021197104A1 PCT/CN2021/081940 CN2021081940W WO2021197104A1 WO 2021197104 A1 WO2021197104 A1 WO 2021197104A1 CN 2021081940 W CN2021081940 W CN 2021081940W WO 2021197104 A1 WO2021197104 A1 WO 2021197104A1
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bits
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codeword
col
frame
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PCT/CN2021/081940
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French (fr)
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马会肖
梁伟光
黄沁辉
黄科超
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华为技术有限公司
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Priority to EP21782019.0A priority Critical patent/EP4120572A4/en
Priority to JP2022559489A priority patent/JP2023519407A/ja
Publication of WO2021197104A1 publication Critical patent/WO2021197104A1/zh
Priority to US17/954,160 priority patent/US20230021167A1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0046—Code rate detection or code type detection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
    • H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
    • H03M13/2927—Decoding strategies
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/3746—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35 with iterative decoding
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0041—Arrangements at the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0064—Concatenated codes
    • H04L1/0066—Parallel concatenated codes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0071—Use of interleaving
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/20—Arrangements for detecting or preventing errors in the information received using signal quality detector
    • H04L1/201—Frame classification, e.g. bad, good or erased
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/152—Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/19—Single error correction without using particular properties of the cyclic codes, e.g. Hamming codes, extended or generalised Hamming codes

Definitions

  • This application relates to an encoding technology, and in particular to an encoding technology and device for data communication with low latency.
  • the communication system usually sends data at the transmitting end and transmits it to the receiving end through a communication channel, thereby realizing a large amount of information transmission.
  • communication channels include fiber optic transmission, wireless, cable and so on.
  • the noise in the channel or the noise of the transceiver device will be superimposed, thereby causing errors in the receiving end of the signal.
  • FEC Forward Error Correction
  • FEC uses the information bits to be transmitted to generate a check bit of a certain length according to a certain coding relationship, and then combines the check bit and the information bit to send, and uses the check bit and the known coding relationship at the receiving end to correct the transmission. Bit errors caused by the process.
  • AI artificial intelligence
  • the present application provides an encoding method and device for data communication, which solves the problem that high encoding gain and low delay cannot be guaranteed at the same time in the prior art.
  • an encoding method for data communication includes: forming a first codeword.
  • the first codeword includes 2n bits and is formed by k encoded bits.
  • the n bits come from m codewords formed before the first codeword, and the other n bits in the first codeword include kn information bits and 2n-k parity bits, where n, m , K are all positive integers, 2n>k>n>m; the other n bits in the first codeword are sent out.
  • the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between codewords at different times is not the same, so
  • the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can increase the decoding speed of the decoder and reduce the delay.
  • the method further includes: storing the other n bits for use when encoding codewords after the first codeword.
  • the first codeword is derived from the m first codewords
  • the number of bits of each codeword in the previously formed codeword is the same, where n is an integer multiple of m.
  • the first codeword shares the same number of bits from each of the m codewords previously formed, and the number of shared bits is more than one. If the number of bits shared between two codewords is large, it needs to be shared. The number of codewords is reduced, and the data collection and decoding process can be completed quickly at the receiving end, thereby reducing the time delay.
  • the number of bits of the first codeword from the second codeword is a, and Among the m codewords formed before the first codeword, at least one codeword provides the first codeword with a different number of bits than a, where a is a positive integer, and the second codeword is Any one of the m codewords formed before the first codeword.
  • the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords converge faster , And then drive the bits protected by fewer codewords to converge, thereby increasing the decoding speed of the decoder and reducing the delay.
  • said forming the first codeword specifically includes: The n bits of the previously formed codeword and the kn information bits to be transmitted are encoded to obtain 2n-k check bits to form the first codeword.
  • the n bits sent in the first codeword are the same as those in the first codeword. Some codewords formed afterwards are shared. Further, the n bits sent in the first codeword are shared with m codewords formed after the first codeword. Half of the bits in each codeword are shared with the codeword formed before, and the other half of the bits are shared with the codeword formed later, ensuring that each bit is protected by a different codeword, and better coding gain can be obtained.
  • each bit in the first codeword is adopted by at least two codewords.
  • a seventh possible implementation manner of the first aspect in the first codeword, among the bits from m previously formed codewords, at least Some bits are check bits in the previous codeword.
  • n 360 and k is 700. It should be understood that this is a specific codeword given in this application, and the first codeword can also be other bit numbers, which is not limited in this application.
  • the m codewords formed before the first codeword are divided into b groups, Divide the n bits in the first codeword shared with the previous codeword into b groups, and each group in the first codeword corresponds to the m codewords formed before the first codeword A group in where b is a positive integer, and both n and m are integer multiples of b.
  • the codewords are divided into 4 groups, each group of 64 codewords; the 360 bits shared with the previous codeword in the first codeword are divided into 4 groups, each group of 90 bits, where each group of 90 bits comes from Corresponding to a set of 64 code words.
  • an encoding device for data communication includes an encoding unit and a sending unit.
  • the encoding unit is configured to form a first codeword, and the first codeword includes 2n bits, It is formed by k coded bits, and the n bits of the first codeword come from m codewords formed before the first codeword, and the other n bits in the first codeword include kn information bits and 2n-k check bits, sending the other n bits to the sending unit, where n, m, and k are all positive integers, and 2n>k>n>m; the sending unit is also used for Sending the other n bits in the first codeword.
  • the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between the codewords at different times is different. All the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can increase the decoding speed of the decoder and reduce the delay.
  • the encoding device further includes a storage unit configured to store the other n bits in the first codeword for the encoding The unit is used when encoding codewords after the first codeword.
  • the first codeword is derived from the m first codewords
  • the number of bits of each codeword in the previously formed codeword is the same, where n is an integer multiple of m.
  • the first codeword shares the same number of bits from each of the m codewords previously formed, and the number of shared bits is more than one. If the number of bits shared between two codewords is large, it needs to be shared. The number of codewords is reduced, and the data collection and decoding process can be completed quickly at the receiving end, thereby reducing the time delay.
  • the number of bits of the first codeword from the second codeword is a, and Among the m codewords formed before the first codeword, at least one codeword provides the first codeword with a different number of bits than a, where a is a positive integer, and the second codeword is Any one of the m codewords formed before the first codeword.
  • the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords converge faster , And then drive the bits protected by fewer codewords to converge, thereby increasing the decoding speed of the decoder and reducing the delay.
  • the encoding device is specifically configured to: The n bits of the codeword and the kn information bits to be transmitted are encoded to obtain 2n-k check bits to form the first codeword.
  • the n bits sent in the first codeword are the same as those in the first codeword. Some codewords formed afterwards are shared. Further, the n bits sent in the first codeword are shared with m codewords formed after the first codeword. Half of the bits in each codeword are shared with the codeword formed before, and the other half of the bits are shared with the codeword formed later, ensuring that each bit is protected by a different codeword, and better coding gain can be obtained.
  • each bit in the first codeword is adopted by at least two codewords.
  • a seventh possible implementation manner of the first aspect in the first codeword, among the bits from m previously formed codewords, at least Some bits are check bits in the previous codeword.
  • n 360 and k is 700. It should be understood that this is a specific codeword given in this application, and the first codeword can also be other bit numbers, which is not limited in this application.
  • the m codewords formed before the first codeword are divided into b groups, Divide the n bits in the first codeword shared with the previous codeword into b groups, and each group in the first codeword corresponds to the m codewords formed before the first codeword A group in where b is a positive integer, and both n and m are integer multiples of b.
  • the codewords are divided into 4 groups, each group of 64 codewords; the 360 bits shared with the previous codeword in the first codeword are divided into 4 groups, each group of 90 bits, where each group of 90 bits comes from Corresponding to a set of 64 code words.
  • a decoding method for data communication includes: recovering a first codeword, where the first codeword includes 2n bits and is formed by k coded bits, and the first codeword The n bits of the word come from m codewords decoded before the first codeword, and the other n bits in the first codeword include kn information bits and 2n-k parity bits, where n, m , K are all positive integers, 2n>k>n>m; decode the first codeword to obtain decoded bits.
  • the number of bits shared between different codewords is different. There are multiple codewords sharing more than one bit. The more shared bits, the number of codewords that need to be associated will be reduced. If the waiting time is too long, it can be decoded, thereby reducing the system delay.
  • the first codeword is derived from each of the m codewords decoded before the first codeword
  • the number of bits is the same, where n is an integer multiple of m.
  • the first codeword shares the same number of bits from each of the m codewords previously decoded, and the number of shared bits is more than one. If the number of bits shared between two codewords is large, it is necessary The number of shared codewords is reduced, and the data collection and decoding process can be completed quickly, thereby reducing time delay.
  • the number of bits of the first codeword from the second codeword is a, and the m bits are before the first codeword Among the decoded codewords, at least one codeword provides the first codeword with a different number of bits than a, where a is a positive integer, and the second codeword is the m number of bits in the first codeword. Any one of the previously decoded codewords.
  • the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords converge faster , And then drive the bits protected by fewer codewords to converge, thereby increasing the decoding speed of the decoder and reducing the delay.
  • n 360 and k is 700. It should be understood that this is a specific codeword given in this application, and the first codeword can also be other bit numbers, which is not limited in this application.
  • a decoding device for data communication including a decoding unit and a storage unit, wherein the decoding unit is used to receive the transmitted codeword, recover the first codeword, and compare the first codeword to the first codeword. Words are decoded, where the first codeword includes 2n bits, and the n bits of the first codeword come from m codewords decoded before the first codeword, and n and m are both positive integers , N>m; the storage unit is used to store the codeword from the transmission, and receive decoding information from the decoding unit, update the stored codeword, and update the codeword in the subsequent decoding process The words are sent back to the decoding unit.
  • the information bits obtained by previous decoding are used, and the information bits are protected by different codewords, and the decoding performance is stronger.
  • the number of bits shared between two codewords is larger, and the number of codewords that need to be associated will be reduced, and decoding can be performed without excessive waiting time, thereby reducing system delay.
  • the first codeword is derived from each of the m codewords decoded before the first codeword
  • the number of bits is the same, where n is an integer multiple of m.
  • the first codeword shares the same number of bits from each of the m codewords previously decoded, and the number of shared bits is more than one. If the number of bits shared between two codewords is large, it is necessary The number of shared codewords is reduced, and the data collection and decoding process can be completed quickly, thereby reducing time delay.
  • the number of bits of the first codeword from the second codeword is a, and the m bits are before the first codeword Among the decoded codewords, at least one codeword provides the first codeword with a different number of bits than a, where a is a positive integer, and the second codeword is the m number of bits in the first codeword. Any one of the previously decoded codewords.
  • the number of bits shared between codewords at different times is not the same, so that the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords converge faster , And then drive the bits protected by fewer codewords to converge, thereby increasing the decoding speed of the decoder and reducing the delay.
  • n 360 and k is 700. It should be understood that this is a specific codeword given in this application, and the first codeword can also be other bit numbers, which is not limited in this application.
  • a concatenated encoding method based on data communication includes: receiving data bits, performing KP4 encoding on the data bits to obtain a KP4 codeword; interleaving the KP4 codeword to obtain an interleaved Codeword; the interleaved codeword is coded according to the first aspect or any one of the possible implementation manners of the first aspect, wherein the interleaved codeword is performed as in the first aspect or Before encoding described in any possible implementation manner of the first aspect, no decoding is performed. In this embodiment, the interleaved KP4 codeword does not need to be decoded, and the next step of concatenated coding is directly performed, which can reduce power consumption.
  • a concatenated encoding device based on data communication.
  • the concatenated encoding device includes: a first encoding unit, an interleaving unit, and a second encoding unit; Bits undergo KP4 coding, and the obtained KP4 codeword is sent to the interleaving unit; the interleaving unit is used to interleave the KP4 codeword and send the interleaved codeword to the second coding unit; the second coding unit is used for The interleaved codeword is coded according to the coding method described in the first aspect or any one of the possible implementation manners of the first aspect, wherein the second coding unit does not decode the interleaved codeword.
  • the interleaved KP4 codeword does not need to be decoded, and the next step of concatenated coding is directly performed, which can reduce power consumption.
  • an encoding method for data communication includes: forming a first codeword, where the first codeword includes n mirror bits and n bits to be transmitted, and the n mirror images The bits are selected from the bits to be transmitted of m source code words, where the source code word is a code word formed before the first code word, n and m are both positive integers, and n>m; The n bits to be transmitted of the codeword are sent out.
  • the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between codewords at different times is not the same, so
  • the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can increase the decoding speed of the decoder and reduce the delay.
  • the n bits to be transmitted include p check bits and np information bits, wherein the p check bits are determined by the n mirror bits and the np information bits are encoded, and p is a positive integer smaller than n.
  • the n mirroring bits include mirroring check bits and mirroring information bits, wherein the mirroring check The bits are selected from the check bits of the m source words, and the mirror information bits are selected from the m information bits of the source words.
  • the number of the mirror check bits and the number of the check bits are the same.
  • a fourth possible implementation manner of the seventh aspect among the m source code words, different source code words are provided to the first code word The maximum value of the difference in the number of bits is greater than one bit. At this time, the error correction performance can be further improved while maintaining a low delay.
  • the code length of the first codeword is not greater than 2048, and the number of error correction bits is not greater than 5.
  • the first codeword can still have better performance under the premise of ensuring low latency.
  • a sixth possible implementation manner of the seventh aspect among the m source code words, at least one source code word is provided to the first code word The number of bits of is different from the number of bits provided to the first codeword by other source code words; or each source word is provided to the first codeword q bits, where q is an integer greater than 1, and n is m Integer multiples of.
  • each bit is protected by a different codeword, and the number of bits provided by one codeword to the first codeword may be more than one. Under the condition of ensuring the coding gain, the decoding speed is faster.
  • p_words of the first codewords constitute a first frame, and the codewords in the first frame
  • the mirroring bits of is derived from the to-be-transmitted bits of the codewords in the h second frames generated before the first frame, where h and p_word are both positive integers greater than 1.
  • the frame coordinates, row coordinates, and column coordinates of the bits in the h second frames pass through ⁇ f(),
  • the three functions ⁇ r() and ⁇ c() are calculated:
  • the column coordinate Col_str set of the mirror check bit of the codeword in the first frame is as follows:
  • the column coordinate Col_str set of the mirror check bit of the codeword in the first frame is as follows:
  • Col_str_vec(i,:) ⁇ [68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359] ⁇ .
  • the frame coordinates Frame', the row coordinates Row_str', and the column coordinates of the bits in the h second frames Col_str' is obtained by the following formula:
  • Frame’ Frame+1+frm_map(Col_str%h);
  • Col_str’ (h–1–Col_str%h)*ceiling(n/h)+floor(Col_str/h)– ⁇ ;
  • Col_str’ (4–Col_str%5)*72+floor(Col_str/5);
  • frm_map(i) i,i ⁇ [0,4].
  • the method further includes: storing the n bits to be transmitted for encoding the first Used when the code word after the code word.
  • the n bits sent in the first codeword are different from those after the first codeword. Some code words formed are shared.
  • each bit in the first codeword is adopted by at least two codewords.
  • the first codeword is a BCH (720, 700) code.
  • an encoding device in an eighth aspect, includes an encoding unit and a sending unit.
  • the encoding unit is configured to form a first codeword.
  • the first codeword includes n mirror bits and n to-be-transmitted bits. Bits, and the n mirror bits are selected from the bits to be transmitted of m source words, where the source word is a code word formed before the first code word, n and m are both positive integers, and n >m; the sending unit is configured to send the n bits to be transmitted in the first codeword.
  • the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between the codewords at different times is not the same, so
  • the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can increase the decoding speed of the decoder and reduce the delay.
  • the n bits to be transmitted include p check bits and np information bits, wherein the p check bits are determined by the n mirror bits and the np information bits are encoded, and p is a positive integer smaller than n.
  • the n mirroring bits include mirroring check bits and mirroring information bits, wherein the mirroring check The bits are selected from the check bits of the m source words, and the mirror information bits are selected from the m information bits of the source words.
  • the number of the mirror check bits and the number of the check bits are the same.
  • the number of bits provided by different source code words to the first code word The maximum value of the difference is greater than one bit.
  • the code length of the first codeword is not greater than 2048, and the number of error correction bits is not greater than 5.
  • At least one source code word is provided to the bit of the first code word The number is different from the number of bits provided by other source code words to the first code word;
  • Each source code word is provided with q bits of the first code word, where q is an integer greater than 1, and n is an integer multiple of m.
  • p_words of the first codewords constitute a first frame
  • the codewords in the first frame are mirror images
  • the bits come from the to-be-transmitted bits of the codewords in the h second frames generated before the first frame, where h and p_word are both positive integers greater than 1.
  • the frame coordinates, row coordinates, and column coordinates of the bits in the h second frames pass through ⁇ f(),
  • the three functions ⁇ r() and ⁇ c() are calculated:
  • the set of column coordinates Col_str of the mirror check bit of the codeword in the first frame is as follows:
  • the column coordinate Col_str set of the mirror check bit of the codeword in the first frame is as follows:
  • Col_str_vec(i,:) ⁇ [68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359] ⁇ .
  • the frame coordinates Frame', the row coordinates Row_str', and the column coordinates of the bits in the h second frames Col_str' is obtained by the following formula:
  • Frame’ Frame+1+frm_map(Col_str%h);
  • Col_str’ (h–1–Col_str%h)*ceiling(n/h)+floor(Col_str/h)– ⁇ ;
  • Col_str’ (4–Col_str%5)*72+floor(Col_str/5);
  • frm_map(i) i,i ⁇ [0,4].
  • the method further includes: storing the n bits to be transmitted for encoding the first Used when the code word after the code word.
  • the n bits sent in the first codeword are different from those after the first codeword. Some code words formed are shared.
  • each bit in the first codeword is adopted by at least two codewords.
  • the first codeword is a BCH (720, 700) code.
  • a computer-readable storage medium stores instructions.
  • the terminal device executes any one of the first aspect or the first aspect.
  • a computer program product containing instructions which when running on a terminal device, causes the terminal device to execute the method described in the first aspect or any one of the possible implementation manners of the first aspect; or causes the The terminal device executes the method described in the third aspect or any one of the possible implementation manners of the third aspect; or causes the terminal device to execute the method described in any one of the possible implementation manners of the seventh aspect or the seventh aspect method.
  • the terminal device may be a chip, a processor, etc., which is not limited in this application.
  • a concatenated encoding method based on data communication includes: receiving data bits, performing KP4 encoding on the data bits to obtain KP4 codewords; interleaving the KP4 codewords to obtain the interleaved Codeword; the interleaved codeword is coded according to the coding method of the seventh aspect or any one of the possible implementation manners of the seventh aspect, wherein the interleaved codeword is performed as in the seventh aspect Or before the encoding described in any possible implementation manner of the seventh aspect, no decoding is performed.
  • the interleaved KP4 codeword does not need to be decoded, and the next step of concatenated coding is directly performed, which can reduce power consumption.
  • a concatenated coding device based on data communication.
  • the concatenated coding device includes: a first coding unit, an interleaving unit, and a second coding unit; the first coding unit is used to receive data bits, The data bits are KP4 encoded, and the obtained KP4 codeword is sent to the interleaving unit; the interleaving unit is used to interleave the KP4 codeword, and send the interleaved codeword to the second coding unit; the second coding unit uses When the interleaved codeword is coded according to the coding method of the seventh aspect or any one of the possible implementation manners of the seventh aspect, the second coding unit does not decode the interleaved codeword. In this embodiment, the interleaved KP4 codeword does not need to be decoded, and the next step of concatenated coding is directly performed, which can reduce power consumption.
  • the bits in the first codeword are protected by multiple codewords generated at different times, and the coding gain effect is better; moreover, the number of bits shared between codewords at different times is not the same.
  • the bits in the codeword are protected by different numbers of codewords, and the bits protected by a larger number of codewords have a faster convergence speed, which can increase the decoding speed of the decoder and reduce the delay.
  • Figure 1 is a block diagram of the structure of the communication system
  • FIG. 2 is a flowchart of the encoding method provided by this application.
  • FIG. 3 is a schematic diagram of a codeword sharing rule provided by an embodiment of this application.
  • FIG. 4 is a schematic diagram of a codeword sharing rule provided by another embodiment of this application.
  • FIG. 5 is a schematic diagram of a codeword sharing rule provided by another embodiment of this application.
  • FIG. 6 is a schematic diagram of a storage mode of an FEC frame provided by another embodiment of the application.
  • FIG. 7 is a diagram of a construction manner of supplementary bits in an FEC frame provided by another embodiment of the application.
  • FIG. 8 is a diagram of a sharing rule of a column of bits that needs to be supplemented in an FEC frame provided by another embodiment of the application;
  • FIG. 9 is a flowchart of a decoding method provided by another embodiment of this application.
  • FIG. 10 is a diagram of an encoding device provided by another embodiment of the present application.
  • FIG. 11 is a diagram of a decoding device provided by another embodiment of the present application.
  • Figure 12 is a diagram of an encoding device provided by another embodiment of the present application.
  • FIG. 13 is a diagram of a decoding device provided by another embodiment of the present application.
  • FIG. 14 is a structural diagram of a high-speed transmission system provided by another embodiment of this application.
  • 15 is a structural diagram of an 800G transmission system provided by another embodiment of this application.
  • FIG. 16 is a simulation result diagram of the coding scheme provided by this application applied to an 800G transmission system
  • FIG. 17(a) is a schematic diagram of a codeword structure provided by another embodiment of this application.
  • FIG. 17(b) is a schematic diagram of the FEC frame structure provided by another embodiment of this application.
  • FIG. 18 is a schematic diagram of a codeword sharing rule provided by another embodiment of this application.
  • FIG. 19 is a schematic diagram of an interleaving solution provided by another embodiment of this application.
  • FIG. 20 is a schematic diagram of a specific FEC frame interleaving solution provided by another embodiment of this application.
  • FIG. 21 is a schematic diagram of a specific FEC frame interleaving solution provided by another embodiment of this application.
  • FIG. 22 is a schematic diagram of a specific FEC frame interleaving solution provided by another embodiment of this application.
  • FIG. 23 is a diagram of an FEC frame encoding architecture provided by another embodiment of this application.
  • FIG. 24 is a schematic diagram of using the coding architecture shown in FIG. 23 to generate the mirror bit of the current frame
  • FIG. 25 is a schematic diagram of a specific FEC frame interleaving solution provided by another embodiment of this application.
  • FIG. 26 is a schematic diagram of a specific FEC frame interleaving solution provided by another embodiment of this application.
  • FIG. 27 is a schematic diagram of a specific FEC frame interleaving solution provided by another embodiment of this application.
  • Figure 1 shows the structural block diagram of the communication system.
  • the source provides the data stream to be sent; the encoder receives the data stream and encodes it, and the codeword information obtained by encoding the check bit and the information bit is combined.
  • Sending, through channel transmission, arrives at the receiving end; after the receiving end receives the codeword information that is erroneous due to noise or other damage in the channel, it is decoded by a decoder to restore the original data and send it to the sink.
  • the encoding method provided in this application is applied to the encoder shown in FIG. 1 and is a very important part of the communication system.
  • the data sent from the source is passed through the encoder using this coding scheme, and a plurality of code words composed of data bits and check bits are continuously formed to form a code word stream.
  • the generated code word will be the same as before or after this.
  • the generated codewords share bits, so that the bits in the codeword are protected by multiple codewords generated at different times, and a better coding gain can be obtained.
  • This application provides an encoding method for data communication, as shown in FIG. 2, including:
  • a first codeword is formed, the first codeword includes 2n bits and is formed by k coded bits, and the n bits of the first codeword come from m codewords formed before the first codeword,
  • the other n bits in the first codeword include kn information bits and 2n-k check bits, where n, m, and k are all positive integers, and 2n>k>n>m;
  • the first codeword before the first codeword is formed, at least m codewords have been generated; half of the bits in the first codeword are derived from the previously formed m codewords, that is, this Half of the bits are composed of several bits from each codeword of the m codewords, which are shared with the previous m codewords; and the remaining kn bits are the information bits at the current moment.
  • the n bits shared among the formed m codewords and the kn information bits at the current moment are encoded to obtain 2n-k check bits, thereby forming the first codeword. Since there are n bits in the first codeword that have been sent in the previously formed codeword, there is no need to send it again. Therefore, the other n bits in the first codeword are sent out, that is, the remaining kn information bits and the newly generated
  • the 2n-k check bits constitute the codeword to be transmitted, and the codeword to be transmitted is sent out.
  • the first codeword shares bits with previously formed codewords and subsequently formed codewords; in the first codeword, each bit is located in at least one previously formed or subsequently formed codeword.
  • at least some of the k encoded bits of the first codeword are data bits of other codewords, and at least some of the k encoded bits are check bits of other codewords.
  • the bits participating in the coding of the codeword are coded bits, and the bits to be transmitted received at the current moment are information bits.
  • the k coded bits there are n bits that are shared with the previous codeword, and the remaining The kn bits are the information bits to be transmitted at the current moment.
  • the initial part of the codeword needs to include padding bits, for example, a sequence of all 0 bits is filled, until a sufficient number of codewords are formed, which can provide sufficient shared bits for subsequent codewords.
  • the codeword includes 2n bits, half of which are shared with the bits of the previously formed m codewords, that is, the bits in the previous codeword will be used as the coded bits of the current codeword. ; At this time, in the initial m codewords, since there are no m prior codewords, enough coding bits cannot be obtained from the previous codewords.
  • padding bits need to be added to the codewords to encode
  • the number of bits is complete to generate check bits to form the first codeword. It should be understood that in the initial m codewords, except for the first codeword, other codewords can share some bits from the previous codewords, and then fill the remaining part of the bits; it may not be the same as the previous codewords. Shared, the missing coded bits are all replaced by padding bits, which is not limited in this application.
  • n bits need to be stored and used when encoding the codeword after the first codeword.
  • the n bits of the first codeword are shared with m codewords formed before the first codeword, and since n is greater than m, there will always be codes in the m codewords.
  • the word shares multiple bits with the first code word.
  • n is an integer multiple of m, and each of the m codewords shares the same number of bits with the first codeword.
  • Figure 3 is a schematic diagram of a specific codeword sharing rule provided by this solution.
  • each codeword has a length of 16 bits, including 14 coded bits (D in the figure) and 2 check bits (P in the figure).
  • D coded bits
  • P check bits
  • 8 bits half the length of the codeword
  • each codeword takes 2 bits.
  • the codeword surrounded by a solid line in Figure 3 is codeword X, of which 2 bits are derived from codeword X-1, 2 bits are derived from codeword X-2, and 2 bits are derived from codeword X-3.
  • the 6 bits are the information bits in the previous codeword, and the other 2 bits are derived from X-4, these 2 bits are the check bits in the previous codeword; the remaining 6 information bits in the codeword X are the current time
  • the 8 bits from the previous codeword and the 6 bits from the current moment are encoded to obtain 2 check bits, thereby forming a codeword X with a length of 16 bits.
  • codeword X+1 includes 16 bits, of which 2 bits are derived from codeword X, and 2 bits are derived from Codeword X-1, 2 bits are derived from X-2, these 6 bits are also the information bits of the previous codeword, and the remaining 2 bits are derived from X-3, which are the check bits of the previous codeword; the remaining 6 bits are the check bits of the previous codeword.
  • the bits are the information bits to be transmitted at the current moment.
  • the 8 bits from the previous codeword and the 6 bits from the current moment are encoded to obtain 2 check bits to form a codeword X+1 with a length of 16 bits.
  • each codeword has half the bit and the previous codeword. Sharing, half of the bits are shared with subsequent codewords, so that the bits in the codeword are protected by multiple codewords generated at different times, and a better coding gain can be obtained; and the number of bits shared by each codeword with other codewords is equal If the number of bits shared between two codewords increases, the number of codewords that need to be shared decreases, and the data collection and decoding process can be quickly completed at the receiving end, thereby reducing the time delay. Of course, the number of shared bits can be further increased, which is not limited in this application.
  • Figure 4 is a schematic diagram of a specific codeword sharing rule provided according to this solution.
  • the length of each codeword is also 16 bits, including 14 coded bits (D in the figure) and 2 checksums. Bit (P in the figure).
  • D coded bits
  • P checksums.
  • 8 bits 8 bits (half the length of the codeword) come from the 6 codewords previously formed.
  • the number of bits obtained from each codeword is shown in Figure 4, for example, it is shown in Figure 4.
  • the code word X surrounded by lines, of which 2 bits are derived from code word X-1, 1 bit is derived from code word X-2, 1 bit is derived from code word X-3, and 2 bits are derived from code word X- 4.
  • These 6 bits are the information bits in the previous codeword; the remaining 2 bits are the check bits in the previous codeword, one of which is derived from codeword X-5, and the other bit is derived from codeword X -6; The remaining 6 bits in the code word X are the information bits to be transmitted at the current moment.
  • the 8 bits from the previous code word and the 6 bits at the current moment are encoded to obtain 2 check bits, thus forming A code word X with a length of 16 bits.
  • the subsequent codeword X+1 of the codeword X is similar to the codeword X, and will not be repeated in this application.
  • n is an integer multiple of m
  • n 8
  • Figure 5 is a schematic diagram of another specific codeword sharing rule provided according to this solution.
  • the length of each codeword is also 16 bits, including 14 coded bits (D in the figure) and 2 corrections. Check the bit (P in the figure).
  • the 14 coded bits 8 bits (half the length of the codeword) come from the 4 codewords previously formed.
  • the number of bits obtained from each codeword is shown in Figure 5, for example, as shown in Figure 4.
  • the code word X surrounded by lines, of which 3 bits are derived from code word X-1, 1 bit is derived from code word X-2, 3 bits are derived from code word X-3, and 1 bit is derived from code word X- 4.
  • These 8 bits include the information bits in the 6 previous code words and the check bits in the 2 previous code words; the remaining 6 bits in the code word X are the information bits to be transmitted at the current moment, which will come from the previous code
  • the 8 bits of the word and the 6 bits of the current moment are encoded to obtain 2 check bits, thereby forming a code word X with a length of 16 bits.
  • the subsequent codeword X+1 of the codeword X is similar to the codeword X, and will not be repeated in this application.
  • FIG. 4 and FIG. 5 only show two different bit sharing methods, and there are other sharing methods, which are not limited in this application.
  • the maximum value of the difference in the number of bits provided by different codewords to the first codeword is greater than one bit, which can further improve error while maintaining low latency. Wrong performance.
  • the number of bits is 720 as an example, of which 360 bits come from the previously formed codeword, 340
  • the bits are the information bits in the current codeword.
  • a total of 700 coded bits are coded according to the generator polynomial corresponding to BCH(720,700), and 20 check bits can be obtained; among them, 360 bits are derived from the previously formed codeword.
  • One bit does not participate in data transmission.
  • the 340 current information bits and 20 check bits together form a 360-bit BCH codeword to be transmitted.
  • BCH (720, 700) is obtained by shortening BCH (1023, 1003) by 303 bits.
  • the specific shortening method can be to remove the high 303 bits, or remove the low 303 bits, or other methods.
  • the application is not limited.
  • Another embodiment of the present application also provides an FEC frame encoding method, where the FEC frame includes Num codewords to be transmitted as described in the previous embodiment, which can be stored in the memory with reference to the method shown in FIG. 6 , Each column is a codeword to be transmitted, and Num is a positive integer greater than 1.
  • the codeword to be transmitted includes n bits
  • n additional bits need to be supplemented, and the n bits are from the previous
  • this embodiment records the supplemented bits as Info_Pad. Therefore, to generate an FEC frame, n rows and Num column Info_Pad need to be supplemented. Assuming that Info_Pad comes from T FEC frames formed before, the bits of Info_Pad can be represented by (Row_Inf, Col_Inf), and Row_Inf is the row number of Info_Pad, which is 0, 1, 2. . .
  • n-1; Col_Inf is the column number of Info_Pad, which is 0, 1, 2. . . Any value in Num-1.
  • the bits of the previously formed T FEC frames are represented by (Frame, Row_str, Col_str), and Frame is the number of the FEC frame, which is 0, 1, 2. . . Any value in T-1, the 0th frame is the FEC frame generated at the previous moment, the 1st frame is the FEC frame generated at the previous moment, and so on; Row_str is the row number of the FEC frame, which is 0, 1 ,2. . . Any value in n-1; Col_str is the column number of the FEC frame, which is any value among 0, 1, 2...Num-1.
  • the correspondence between each bit in Info_Pad and the bits of the FEC frame formed before can be calculated according to the following formula:
  • Row_str (Intial_Row+Row_skip*Row_Inf+floor(Row_skip*Row_Inf/n))%n(2)
  • Intial_Row represents the row number of the first row of bits shared with Info_Pad in T FEC frames
  • Row_skip represents how many rows in T FEC frames, how many rows to select a row of bits to share with Info_Pad; it should be noted that, Intial_Row is an integer not less than 0, Row_skip is a positive integer, and Intial_Row+Row_skip*(n-1) cannot exceed the value of n*(T-1).
  • the T FEC frames formed before the current time mentioned here may be T FEC frames at any time before.
  • FEC frames at T consecutive times before the current time can also be taken after a fixed time interval between the current time and T FEC frames, or FEC frames at any T discontinuous time before the current time. This application does not Make a limit.
  • the following takes the codeword to be transmitted as BCH (360, 340), and the FEC frame includes 64 codewords to be transmitted as an example, and describes a specific form of Info_Pad, in which an additional 360 lines are required to generate the FEC frame , 64-column Info_Pad.
  • the structure of Info_Pad is shown in Figure 7. At this time, the row number Row_Inf of Info_Pad is 0, 1, and 2. . . For any value in 359, the column number Col_Inf of Info_Pad is 0, 1, 2. . .
  • the number Frame of the FEC frame is any one of 0, 1, 2, and 3, and the row number Row_str of the FEC frame is 0, 1, 2. . .
  • the column number Col_str of the FEC frame is 0, 1, and 2. . . Any value in 63.
  • Row_str (4*Row_Inf+floor(Row_Inf/90)%360(5)
  • Col_str (Col_Inf+Row_Inf)%64 (6)
  • the 90th line of Info_Pad corresponds to the first line of the first frame of the 4 FEC frames formed before.
  • formula (6) gives the interleaving relationship between each row of Info_Pad and the corresponding row in the previous FEC frame, and the period of row interleaving is 64, and the interleaving relationship will be repeated once every 64 rows pass.
  • the interleaving relationship between each row and the corresponding row of the previous FEC frame is different, but starting from row 64, the interleaving relationship begins to repeat.
  • row 0 and row of Info_Pad The interleaving relationship of 64 rows is the same, the interleaving relationship of the first row and the 65th row is the same, and so on. It should be understood that other row interleaving relationships may also be used, for example, the interleaving calculation is performed according to the Galois Field (Galois Field, GF).
  • Galois Field Galois Field
  • FIG. 8 shows the sharing relationship between the 90 bits included in the first column of Info_Pad and the bits in the corresponding FEC frame.
  • the solid blocks in Figure 8 represent the bit positions shared with the first column of Info_Pad in the FEC frame.
  • the sharing relationship satisfies the conditions of formulas (5) and (6). For example, Info_Pad(0,0) shares with the bits in the solid block (0,0) in Fig. 8, and Info_Pad(1,0) is the same as the solid block in Fig.
  • the first column of bits in the to-be-transmitted FEC frame (the first column of bits is recorded as the first to-be-transmitted codeword) is taken as an example.
  • the generation of the codeword to be transmitted is related to the first column of Info_Pad bits and the received 340 current information bits, that is, according to the generator polynomial corresponding to BCH (720, 700), the 360 bits included in the first column of Info_Pad are related to the received 340 current information bits.
  • the 340 current information bits and the generated 20 check bits constitute the first codeword to be transmitted;
  • the codewords are transmitted to form the currently encoded FEC frame.
  • the number of information bits to be transmitted is 340;
  • 360 bits are obtained from the previously formed 256 codewords
  • the received 340 bits and the generated 20 bits The check bits constitute the first codeword to be transmitted, and the 64 first codewords to be transmitted constitute an FEC frame;
  • one encoder can perform encoding, or multiple encoders can perform encoding in parallel.
  • 8 encoders can encode in parallel to obtain 8 codewords to be transmitted. After parallel-serial conversion, a bit stream is formed. , Send it out.
  • the codeword to be transmitted as BCH (360, 340) is only a possible embodiment, and it can also be of other lengths, for example, BCH (510, 490), BCH (256, 238), etc., and can also be used such as Chinese Different encoding rules such as plain code and Reed-Solomon (Reed-Solomon, RS) code are not limited in this application.
  • the bits in the to-be-transmitted codewords included in each FEC frame are protected by the to-be-transmitted codewords included in multiple FEC frames generated at different times, and a better coding gain can be obtained.
  • the number of bits shared between different codewords is different, and the codewords with more bits shared between each other have faster convergence speed, and then can drive the convergence of the remaining codewords, thereby improving the decoder
  • the convergence speed of plays a role in reducing the delay.
  • This application provides a decoding method for data communication, as shown in FIG. 9, including:
  • the first codeword is restored; where the first codeword includes 2n bits and is formed by k coded bits, and the n bits of the first codeword come from m decoded bits before the first codeword.
  • Codeword, the other n bits in the first codeword include kn information bits and 2n-k check bits, where n, m, and k are all positive integers, and 2n>k>n>m;
  • the first codeword before the first codeword is recovered, at least m codewords have been decoded; half of the bits in the first codeword are derived from the m codewords previously decoded. The other n bits are the bit stream received at the current moment.
  • the first codeword shares bits with previously decoded codewords and subsequently decoded codewords; in the first codeword, each bit is located in at least one previously decoded or subsequently decoded codeword.
  • at least some of the k encoded bits of the first codeword are data bits of other codewords, and at least some of the k encoded bits are check bits of other codewords.
  • the initial part of the codeword needs to contain padding bits, for example, a sequence of all 0 bits is filled, until a sufficient number of codewords are decoded.
  • padding bits for example, a sequence of all 0 bits is filled, until a sufficient number of codewords are decoded.
  • some of the erroneous bits in the previously decoded codeword have been corrected.
  • the number of erroneous bits in the composed codeword is reduced. It can increase the probability of correct decoding.
  • the remaining errors in the previous codewords can also be corrected to improve the error correction capability.
  • the number of bits shared between different codewords is different. There are multiple codewords sharing more than one bit. The more bits are shared, the number of codewords that need to be associated will be reduced, and there is no need to wait too long, that is Can be decoded, thereby reducing system delay.
  • FIG. 10 Another embodiment of the present application provides an encoding device for data communication. As shown in FIG. 10, it includes an encoding unit 1001 and a sending unit 1002.
  • the encoding unit 1001 receives information bits to be transmitted and encodes them to form The codeword to be transmitted sends the formed codeword to the sending unit 1002; the sending unit 1002 is used to send the received codeword.
  • the encoding device further includes a storage unit 1003 for storing the codeword to be transmitted and sending it back to the encoding unit 1001. During the encoding process, the encoding unit 1001 will use the bits in the previously formed codeword to encode and generate a new codeword to be transmitted.
  • a first codeword is formed.
  • the first codeword includes 2n bits and is formed by k coded bits, and the n bits of the first codeword come from m formed before the first codeword Codeword, the other n bits in the first codeword include kn information bits and 2n-k check bits, where n, m, and k are all positive integers, 2n>k>n>m; when sending, The bits from the previous m codewords do not participate in data transmission, and the other n bits in the first codeword (that is, the codeword to be transmitted) will be sent out.
  • the specific encoding process is as described in the previous embodiment, which is not repeated in this embodiment.
  • FIG. 11 Another embodiment of the present application provides a decoding device for data communication. As shown in FIG. 11, it includes a decoding unit 1101 and a storage unit 1102.
  • the decoding unit 1101 is used to receive the transmitted codeword and restore The first codeword is output, and the first codeword is decoded;
  • the storage unit 1102 is used to store the transmitted codeword, and receive the decoding information from the decoding unit 1101, and update the stored codeword, And in the subsequent decoding process, the updated codeword is sent back to the decoding unit 1101.
  • the decoding unit 1101 uses the information bits obtained by previous decoding during the decoding process. The information bits are protected by different codewords, and the decoding performance is stronger.
  • a first codeword is formed, the first codeword includes 2n bits, and the n bits of the first codeword come from m codewords decoded before the first codeword, where, Both n and m are positive integers, and n>m.
  • these n bits have been decoded in the previous decoding process, so the number of error bits will be reduced, thereby increasing the decoding success rate of the first codeword.
  • the code word x-1 contains y errors before decoding.
  • the error bits in the code word x-1 are partially corrected; because some errors are corrected in the code word x-1 Therefore, other previously uncorrectable codewords sharing bits with codeword x-1 can now have a sufficient number of correct bits so that the previously uncorrectable codeword becomes correctable.
  • the codeword can be decoded repeatedly.
  • FIG. 12 Another embodiment of the present application provides an encoding device for data communication. As shown in FIG. 12, it includes: an input interface 1201, an encoder 1202, a memory 1203, and an output interface 1204; an encoder 1202 is used to pass the input interface 1201 Receive information data and send the generated codewords through the output interface 1204; the memory 1203 is used to store the codewords sent by the encoder 1202, and send it back to the encoder 1202 in the subsequent encoding process; the encoder 1202 is in the encoding process It will use the bits in the previously formed codeword to encode and generate a new codeword. The specific encoding process is as described in the previous embodiment, and will not be repeated here.
  • the memory shown in FIG. 12 is a device independent of the encoder. In actual situations, the storage function can also be implemented in the encoder, that is, there is no need for a separate memory.
  • the memory 1203 may also receive information data from the input interface 1201 and check data from the encoder 1202, which is not limited by this application.
  • another embodiment of the present application also provides a decoding device for data communication, as shown in FIG. 13, including an input interface 1301, a decoder 1302, a memory 1303, and an output interface 1304; the decoder 1302 is used for Receive the sent codeword through the input interface 1301 and decode it; the memory 1303 is used to store the codeword from the input interface 1301, and receive the decoding information from the decoder 1302 to update the stored codeword, And in the subsequent decoding process, the updated codeword is sent back to the decoder 1302; the memory 1303 can also send the updated codeword through the output interface 1304.
  • the decoder 1302 uses the information bits obtained by previous decoding during the decoding process to improve the decoding capability.
  • the storage function can also be implemented in the decoder, that is, a separate memory may not exist.
  • the embodiment of the present application provides a computer-readable storage medium or computer program product for storing a computer program, and the computer program is used to execute the encoding or decoding method involved in the method embodiment of the present application.
  • FIG. 12 only shows a simplified design of the encoding device.
  • the encoding device may include any number of interfaces, encoders, etc., and all terminals that can implement the embodiments of the present application are within the protection scope of the embodiments of the present application.
  • the decoding device can also contain any number of interfaces and decoders to realize parallel decoding and improve decoding efficiency.
  • the encoder or decoder involved in the embodiments of the present application may be a central processing unit (Central Processing Unit, referred to as "CPU"), or may also be other general-purpose processors, digital signal processors ( DSP), application specific integrated circuit (ASIC), off-the-shelf programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
  • the general-purpose processor may be a microprocessor or the processor may also be any conventional processor or the like.
  • the coding scheme disclosed in this application can be used in a high-speed transmission system, for example, an 800G transmission system. Its structure is shown in FIG. 14.
  • the transmitting end includes a first coding unit 1401, an interleaving unit 1402 and a second coding unit 1403;
  • the encoding unit 1401 is used to receive the data bit stream, perform KP4 encoding on the received data bit stream, and send the encoded bit stream to the interleaving unit 1402;
  • the interleaving unit 1402 is used to interleave the received bit stream, and after interleaving Send the bitstream of the code to the second coding unit 1403;
  • the second coding unit 1403 is used to perform the coding method disclosed in the previous embodiment on the interleaved bitstream, and send the generated codewords.
  • the specific coding method will not be described here. Go into details.
  • the KP4 codeword is RS(544,514,15,10), that is, the KP4 codeword includes 544 symbols, of which 514 symbols are information symbols, and one decoding can correct up to 15 symbol errors.
  • Each symbol includes 10 bits; the interleaving unit can process the received bit stream in a row-column interleaving manner, that is, bits are written in rows and read in columns to achieve the interleaving function. This is a relatively easy
  • the implemented interleaving method may of course also be other interleaving methods, which is not limited in this application.
  • the receiving end of the high-speed transmission system includes a first decoding unit 1404, a de-interleaving unit 1405, and a second decoding unit 1406;
  • the first decoding unit 1404 is used for the codeword sent by the transmitting end, and the received The codeword is decoded as disclosed in the previous embodiment, and the decoded bit stream is sent to the de-interleaving unit 1405;
  • the de-interleaving unit 1405 is used to de-interleave the received bit stream, and the de-interleaved bit stream Sent to the second decoding unit 1406;
  • the second decoding unit 1406 is used to perform KP4 decoding on the de-interleaved bit stream to obtain the original data bits.
  • the high-speed transmission system provided in this embodiment uses KP4 coding and the coding method provided in the previous embodiment to perform cascaded coding, which can enhance coding performance and meet the ever-increasing coding performance requirements as the optical transmission rate increases.
  • KP4 encoding and the encoding method disclosed in this application are implemented in different chips.
  • KP4 is encoded in the first chip 1501.
  • the encoding method of this application is implemented in the second chip 1502
  • the decoding method disclosed in this application is implemented in the third chip 1503
  • the KP4 decoding is implemented in the fourth chip 1504; the two first chips jointly output 8 channels 100G signal realizes the transmission function of 800G signal.
  • the 800G transmission system may also include only one first chip to implement KP4 encoding, and the 800G signal is sent to the second chip through one first chip, which is not limited in this application.
  • the second chip 1502 receives the KP4 codeword transmitted from the first chip 1501, does not perform KP4 decoding, and directly encodes the KP4 code with check bits according to the encoding method provided in the previous embodiment. Since the interconnection of the first chip 1501 and the second chip 1502 has circuit noise, which will cause correlation bit errors, the transceiver needs to perform interleaving and de-interleaving to break up the correlation, that is, at the transmitting end, the KP4 codeword is interleaved and sent to In the same way, the second chip 1502 de-interleaves the codeword decoded by the third chip 1503 at the receiving end, and then sends it to the fourth chip 1504.
  • first chip and the fourth chip can be integrated together, and the second chip and the third chip can be integrated together to realize the transceiver function.
  • interleaving function may be implemented in the first chip 1501 or the second chip 1502
  • de-interleaving function may be implemented in the third chip 1503 or the fourth chip 1504, which is not limited in this application.
  • the data distribution and interleaving functions of the output port of the first chip can be integrated, that is, when the KP4 data is distributed, the data transmission order is disrupted to achieve the interleaving function; the same way, the decoding side can also be used Do a similar treatment.
  • the simulation result of the encoding performance is as follows As shown in Figure 16, when the Bit Error Ratio (BER) of the input signal is 2.5E-3 and below, it can be ensured that the BER of the decoded signal is below 1E-15; In the case of low latency, coding performance can also be guaranteed.
  • BER Bit Error Ratio
  • the coding performance is improved by cascading two different codewords, and there is no need to decode KP4 at the transmitting end, and the KP4 codeword is directly encoded to realize the transparent transmission of the KP4 codeword. Further reduce system power consumption.
  • FIG. 17(a) Another codeword structure of the code is also given.
  • the coded interleaving depth as m.
  • the mirror information bit if it comes from the information bit at the previous time, it is called the mirror information bit; if it comes from the check bit at the previous time, it is called the mirror check bit.
  • the entire codeword can be called a component code.
  • the BCH code or shortened BCH code is used as the component code, and the number of error correction bits is t.
  • FEC frame Multiple component codes can form an FEC frame.
  • the structure of the FEC frame is shown in Figure 17(b).
  • Each frame contains p_word component code words, and p_word is an integer greater than 1. It should be understood that in this embodiment, p_word has the same meaning as NUM in the previous embodiment.
  • These component codes are encoded at the same time, and then the information bits and check bits of all the component codes are combined and sent, a total of n*p_word bits. The n*p_word mirror bits will not be transmitted on the channel.
  • the FEC frame may be a spatially coupled code.
  • the FEC frame described in this solution can be described by a matrix of n columns and infinite rows.
  • each row represents a component code word
  • consecutive p_word rows represent a frame as shown in Figure 17(b); the bits corresponding to each column have the same bit number.
  • the information bits and check bits are generated at the current moment, while the mirror bits (bits marked by slashes) of the current frame are changed from the previous
  • the information bits of the h frames (frame-h - frame-1) and check bits (bits marked by squares) are obtained by interleaving and mapping.
  • FIG. 19 is a schematic diagram of an interleaving scheme, which describes a corresponding relationship between an interleaving source and an interleaving target.
  • frm_map represents a bijective function whose input domain and output domain are both ⁇ 0,1,...,h-1 ⁇ .
  • frm_map(i) h-1-i,i ⁇ [0,h-1];
  • the interleaving mapping function ⁇ () is bijective. For the determined number of interleaving-related frames h, the number of codewords per frame p_word, code length 2n, and frm_map function, the interleaving mapping function ⁇ () exists and is uniquely determined. h, p_word and 2n are independent of each other and do not restrict each other. Therefore, even if p_word and 2n have been determined, h can still be adjusted to weigh the decoding performance and the decoding delay.
  • the h FEC frames formed before the current time mentioned here may be h FEC frames at any time before.
  • the FEC frames at h consecutive times before the current time can also be h FEC frames at a fixed time interval from the current time, or h FEC frames at any discontinuous time before the current time. This is not limited.
  • each frame in the interleaving source provides b_frm bits for each codeword of the interleaving target; otherwise, (ceiling(b_frm)-b_frm)*h frames in the interleaving source
  • the frame provides floor(b_frm) bits for each codeword of the interleaving target, and the remaining (b_frm-floor(b_frm))*h frames provide ceiling(b_frm) bits for each codeword of the interleaving target.
  • Each codeword provides ceiling(b_word) bits. It can be seen that the number of bits obtained by the interleaving target from each codeword is basically the same, and the codewords obtained from each frame are also basically the same. performance. In the example shown in Figure 19, b_frm is an integer. It can be seen that each frame in the interleaving source provides p_word*b_frm bits to the interleaving target.
  • the embodiment of the present application also describes the position of the mirror check bit.
  • interleaving scheme in order to distinguish different types of interleaving schemes, we give the following definitions: if b_word is an integer, the association relationship is a regular pattern, and the interleaving scheme is defined as a complete regular interleaving scheme; if b_word is not an integer, but b_frm is an integer , Define the interleaving scheme as a partial regular interleaving scheme; if both b_word and b_frm are not integers, define the interleaving scheme as an irregular interleaving scheme. Specific examples of different types of interleaving schemes are given below.
  • the corresponding interleaving mapping function ⁇ () can be expressed as:
  • the 360 mirror bits of each codeword come from a total of 5*64 codewords in the previous 5 frames.
  • the interleaving scheme in this embodiment is a partial regular interleaving scheme.
  • the difference in the number of bits that the interleaving target obtains from each codeword is very small, indicating that the interleaving method proposed in this scheme fully breaks up the interleaving sources, thereby effectively improving the decoding performance.
  • i_base([0,1,2,3,4]) [71,143,215,287,359];
  • the corresponding interleaving mapping function ⁇ () can be expressed as:
  • the 360 mirror bits of each codeword come from a total of 7*64 codewords in the previous 7 frames.
  • there are 3 frames in the interleaving source and each frame provides 52 bits for each codeword of the interleaving target, and each frame of the remaining 4 frames provides each codeword of the interleaving target.
  • the interleaving scheme in this embodiment is an irregular interleaving scheme.
  • the number of bits obtained by the interleaving target from each of the 360 codewords is the same, and the number of bits obtained from each frame is also very small, indicating that the interleaving method proposed by this scheme will interleave the source Fully break up, thereby effectively improving decoding performance.
  • i_base([0,1,2,3,4,5,6]) [50,101,152,203,255,307,359];
  • Another embodiment of the present application also provides an interleaving scheme for FEC frames.
  • the code included in the FEC frame is the extended BCH (256, 239) code.
  • the corresponding interleaving mapping function ⁇ () can be expressed as:
  • the interleaving scheme in this embodiment is a completely regular interleaving scheme.
  • the number of bits obtained by the interleaving target from each codeword in the interleaving source is the same, and the number of bits obtained from each frame is also the same. Effectively improve decoding performance.
  • i_base([0,1,2,3,4,5,6,7]) [15,31,47,63,79,95,111,127],
  • the FEC frame described in the foregoing embodiment may be a spatially coupled code, and its coding architecture is shown in FIG. 23.
  • the convolutional interleaver stores the information and check bits of h frames before the current time, and it stores a total of h*n*p_word bits for generating n*p_word mirror bits at the current time.
  • the input of the encoder is (k-n)*p_word information bits, which will be allocated to p_word component code encoders.
  • the input of each component code encoder is (k-n) information bits and n mirror bits, and the output is (k-n) information bits and p check bits.
  • the mirror bit from the convolutional interleaver only participates in the component code encoding. Will be transmitted. It should be understood that the meanings of h, n, and p_word are the same as those in the previous embodiment, and will not be repeated in this embodiment.
  • Fig. 24 shows a method of generating the mirror bit of the current frame by using the coding architecture shown in Fig. 23.
  • the upper part of Figure 24 is a matrix of h*p_word rows and n columns.
  • consecutive p_word rows represent a frame as shown in Figure 17(b), so a total of h frames (frame-h - frame-1) are stored in the convolutional interleaver at the current moment.
  • the mirrored bits of the current frame (frame 0) are interleaved by the bits in the interleaver.
  • the coordinate of a specific bit we mark the coordinate of a specific bit as [Frame, Row_str, Col_str]. Among them, the frame coordinates Frame ⁇ (- ⁇ ,+ ⁇ ), the row coordinates Row_str ⁇ [0,p_word-1], and the column coordinates Col_str ⁇ [0,n-1].
  • the interleaving relationship in the convolutional interleaver is divided into two layers, namely inter-frame interleaving and inter-code interleaving. Assuming that the coordinates of the mirror bit after interleaving are [Frame’, Row_str’, Col_str’], the convolutional interleaver describes the interleaving mapping relationship from [Frame, Row_str, Col_str] to [Frame’, Row_str’, Col_str’]. The following describes the specific scheme of each layer of interleaving.
  • the symbol corresponding to the mirror bit of the current frame (frame 0) corresponds to a symbol in the interleaver, and the corresponding coordinate relationship is as follows:
  • Col_str’ (h–1–Col_str%h)*ceiling(b_frm)+floor(Col_str/h)– ⁇ .
  • the ceiling() and floor() functions round the input up and down respectively, and% means modulo;
  • frm_map represents a bijective function whose input domain and output domain are both ⁇ 0,1,...,h-1 ⁇ .
  • frm_map(i) i,i ⁇ [0,h-1];
  • inter-frame interleaving does not involve the transformation of row coordinates, so the order of bits in each symbol is the same as the order of bits in the interleaver.
  • inter-code interleaving For each symbol that has undergone inter-frame interleaving, inter-code interleaving is further performed to make the bits of the same codeword come from different frames as much as possible after interleaving.
  • the specific mapping relationship between codes is shown in the following row coordinate transformation formula:
  • the input bits and output bits of the interleaver correspond one-to-one.
  • the interleaving mode exists and is uniquely determined.
  • h, p_word and 2n are independent of each other and do not restrict each other. Therefore, even if p_word and 2n have been determined, h can still be adjusted to weigh the decoding performance and the decoding delay.
  • each frame in the interleaver provides b_frm bits for each codeword of the current frame; otherwise, (ceiling(b_frm)-b_frm)*h frames in the interleaver
  • the frame provides floor(b_frm) bits for each codeword of the current frame, and the remaining (b_frm-floor(b_frm))*h frames provide ceiling(b_frm) bits for each codeword of the current frame.
  • each codeword in the interleaver provides b_word bits for each codeword in the current frame; otherwise, the interleaver includes (ceiling(b_word)-b_word)*(h*p_word) codewords
  • Each codeword in the current frame provides floor(b_word) bits for each codeword in the current frame, and among the remaining (b_word-floor(b_word))*(h*p_word) codewords, each codeword is each codeword in the current frame.
  • Each codeword provides ceiling(b_word) bits.
  • the number of bits obtained from each codeword in the current frame is basically the same, and the codewords obtained from each frame are also basically the same, indicating that the interleaving method proposed in this scheme can also fully break up the bits in the interleaver , Thereby effectively improving decoding performance.
  • the embodiment of the present application also describes the position of the mirror check bit.
  • interleaving scheme in order to distinguish different types of interleaving schemes, we give the following definitions: if b_word is an integer, the association relationship is a regular pattern, and the interleaving scheme is defined as a complete regular interleaving scheme; if b_word is not an integer, but b_frm is an integer , Define the interleaving scheme as a partial regular interleaving scheme; if both b_word and b_frm are not integers, define the interleaving scheme as an irregular interleaving scheme. Based on the coding architecture shown in FIG. 23, different types of interleaving schemes are described in detail below.
  • the convolutional interleaver stores information and parity bits of 5 frames before the current moment, and it stores 115200 bits in total. , Used to generate 23040 mirror bits at the current moment.
  • the input of the encoder is 21760 information bits, which will be allocated to 64 component code encoders.
  • the input of each component code encoder is 340 information bits and 360 mirror bits, and the output is 340 information bits and 20 parity bits.
  • the overall output of the encoder is a total of 23040 information and check bits from 64 component code encoders.
  • the mirrored bits from the convolutional interleaver only participate in component code encoding and will not be transmitted.
  • the symbol corresponding to the mirror bit of the current frame corresponds to a symbol in the interleaver, and the corresponding coordinate relationship is as follows:
  • Col_str' (4–Col_str%5)*72+floor(Col_str/5).
  • inter-frame interleaving is performed.
  • the inter-code interleaving is performed according to the following correspondence relationship.
  • the specific inter-code interleaving is The mapping relationship is shown in the following row coordinate transformation formula:
  • each codeword come from a total of 5*64 codewords in the previous 5 frames.
  • the specific number of bits obtained from each frame and each codeword is as shown in Figure 20.
  • the embodiment shown is the same; moreover, the column coordinate set of the 20 mirror check bits included in each component code is also the same as the embodiment shown in FIG. 20, and the details are not repeated in the embodiment of the present application.
  • the convolutional interleaver stores information and parity bits of 7 frames before the current moment, and it stores a total of 161280 bits. , Used to generate 23040 mirror bits at the current moment.
  • the input of the encoder is 21760 information bits, which will be allocated to 64 component code encoders.
  • the input of each component code encoder is 340 information bits and 360 mirror bits, and the output is 340 information bits and 20 parity bits.
  • the overall output of the encoder is a total of 23040 information and check bits from 64 component code encoders.
  • the mirrored bits from the convolutional interleaver only participate in component code encoding and will not be transmitted.
  • the symbol corresponding to the mirror bit of the current frame corresponds to a symbol in the interleaver, and the corresponding coordinate relationship is as follows:
  • Col_str' (6-Col_str%7)*52+floor(Col_str/7)- ⁇ .
  • inter-frame interleaving is performed.
  • the inter-code interleaving is performed according to the following correspondence relationship.
  • the specific inter-code interleaving is The mapping relationship is shown in the following row coordinate transformation formula:
  • each codeword come from a total of 7*64 codewords in the previous 7 frames.
  • the specific number of bits obtained from each frame and each codeword is as shown in Figure 21.
  • the illustrated embodiment is the same; moreover, the column coordinate set of the 20 mirror check bits included in each component code is also the same as the embodiment shown in FIG. 21, and the details are not repeated in the embodiment of this application.
  • the component code is a spatial coupling code of extended BCH (256, 239).
  • the convolutional interleaver stores information and parity bits of 8 frames before the current moment, and it stores a total of 16384 bits. , Used to generate 2048 mirror bits at the current moment.
  • the input of the encoder is 1776 information bits, which will be distributed to 16 component code encoders.
  • the input of each component code encoder is 111 information bits and 128 mirror bits, and the output is 111 information bits and 17 parity bits.
  • the overall output of the encoder is a total of 2048 information and check bits from 16 component code encoders.
  • the mirrored bits from the convolutional interleaver only participate in component code encoding and will not be transmitted.
  • the symbol corresponding to the mirror bit of the current frame corresponds to a symbol in the interleaver, and the corresponding coordinate relationship is as follows:
  • Col_str' (7-Col_str%8)*16+floor(Col_str/8).
  • inter-frame interleaving is performed.
  • the inter-code interleaving is performed according to the following correspondence relationship.
  • the specific inter-code interleaving is The mapping relationship is shown in the following row coordinate transformation formula:
  • each codeword come from a total of 5*64 codewords in the previous 5 frames.
  • the specific number of bits obtained from each frame and each codeword is as shown in Figure 22.
  • the embodiment shown is the same; moreover, the column coordinate set of the 20 mirror check bits included in each component code is also the same as the embodiment shown in FIG. 22, which is not repeated in the embodiment of the present application.
  • the h FEC frames formed before the current time mentioned here may be h FEC frames at any time before.
  • the FEC frames at h consecutive times before the current time can also be h FEC frames at a fixed time interval from the current time, or h FEC frames at any discontinuous time before the current time. This is not limited.
  • this application may also include the following situations:
  • All the codewords constructed above can still have good performance under the premise of ensuring low delay.
  • the foregoing multiple embodiments provide a variety of different interleaving schemes. Any encoding method that satisfies the foregoing interleaving scheme is either the same as the formula provided by the foregoing interleaving scheme, or is just equivalent to the formula provided by the foregoing interleaving scheme. Or simple variants, all fall within the scope of protection of this application.
  • one embodiment or “an embodiment” mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present invention. Therefore, the appearances of "in one embodiment” or “in an embodiment” in various places throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner.
  • the size of the sequence number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute the implementation process of the embodiment of the present invention. Any restrictions.
  • the disclosed device and method may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division, and there may be other divisions in actual implementation, for example, multiple units or components may be combined or It can be integrated into another system, or some features can be ignored or not implemented.
  • the displayed or discussed mutual coupling or direct coupling or communication connection may be indirect coupling or communication connection through some interfaces, devices or units, and may also be electrical or other forms of connection.
  • the functional units in the various embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit.

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Abstract

一种用于数据通信的编码方法，可应用于城域、骨干网、数据中心互连等多个场景，所述方法包括：形成第一码字，所述第一码字包括n个镜像比特和n个待传输比特，且所述n个镜像比特从m个源码字的待传输比特中挑选，其中，所述源码字为在所述第一码字之前形成的码字，n和m均为正整数，n＞m；将所述第一码字的所述n个待传输比特发送出去。其中，第一码字中的比特被多个不同时刻产生的码字保护，编码增益效果更好；而且，码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特具备更快的收敛速度，可以提升译码器的译码速度，降低时延。

Description

用于数据通信的编码方法及装置
本申请要求于2020年3月31日提交中国国家知识产权局、申请号为202010245565.1、申请名称为“用于纠错的编码技术及装置”的中国专利申请的优先权，以及要求于2020年8月27日提交中国国家知识产权局、申请号为202010881014.4、申请名称为“用于数据通信的编码方法及装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及一种编码技术，尤其涉及一种用于数据通信、低时延的编码技术及装置。
背景技术
通信系统通常在发射端发送数据，经过通信信道传输到接收端，从而实现大量的信息传输。例如，通信信道包括光纤传输，无线，电缆等。然而发送信号经过通信信道时，会叠加信道中的噪声或者收发器件的噪声，从而造成接收端接收信号的错误。为了能够在错误接收的信号中恢复出发送端发送的原始信号，采用前项纠错编码(Forward Error Correction，FEC)是一种普遍的做法。
FEC是根据某种编码关系利用要传输的信息比特来产生一定长度的校验比特，再将校验比特和信息比特合并发送，在接收端利用校验比特和已知的编码关系去纠正因为传输过程导致的比特错误。现阶段，由于人工智能(Artificial Intelligence，AI)等新技术应用出现，对超低时延、高可靠性的互联需求日益突出，提高编码增益和降低时延变得越来越重要。
发明内容
本申请提供一种用于数据通信的编码方法及装置，解决了现有技术中无法同时保证高编码增益和低时延的问题。
第一方面，提供一种用于数据通信的编码方法，所述方法包括：形成第一码字，所述第一码字包括2n个比特，由k个编码比特形成，且第一码字的n个比特来自于m个在所述第一码字之前形成的码字，所述第一码字中另外n个比特包括k-n个信息比特和2n-k个校验比特，其中，n、m、k均为正整数，2n＞k＞n＞m；将所述第一码字中的所述另外n个比特发送出去。
在本申请实施例中，第一码字中的比特被多个不同时刻产生的码字保护，编码增益效果更好；而且，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特具备更快的收敛速度，可以提升译码器的译码速度，起到降低时延的作用。
结合第一方面，在第一方面的第一种可能的实现方式中，所述方法还包括：将所述另外n个比特存储起来，供编码所述第一码字之后的码字时使用。
结合第一方面或第一方面的第一种可能的实现方式，在第一方面的第二种可能的实现方式中，所述第一码字来自于所述m个在所述第一码字之前形成的码字中每个码字的比特数相 同，其中，n为m的整数倍。本实施中第一码字从m个之前形成的码字中的每一个码字共享相同数目的比特，且共享比特数不止一个，两个码字之间共享的比特个数多，则需要共享的码字个数降低，在接收端可以快速完成数据的收集以及译码过程，从而降低时延。
结合第一方面或第一方面的第一种可能的实现方式，在第一方面的第三种可能的实现方式中，所述第一码字来自于第二码字的比特数为a，在所述m个在所述第一码字之前形成的码字中，至少有一个码字提供给所述第一码字的比特数与a不同，其中，a为正整数，第二码字为所述m个在所述第一码字之前形成的码字中的任意一个。
在本实施例中，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特较快收敛，然后带动被更少码字保护的比特收敛，从而提升译码器的译码速度，降低时延。
结合第一方面或以上任一种可能的实现方式，在第一方面的第四种可能的实现方式中，所述形成第一码字具体包括：对来自于m个在所述第一码字之前形成的码字的n个比特和k-n个待传输的信息比特进行编码，得到2n-k个校验比特，形成所述第一码字。
结合第一方面或以上任一种可能的实现方式，在第一方面的第五种可能的实现方式中，所述第一码字中发送出去的n个比特，与在所述第一码字之后形成的一些码字共享。进一步地，所述第一码字中发送出去的n个比特，与在所述第一码字之后形成的m个码字共享。每个码字中的一半比特与之前形成的码字共享，另一半比特与之后形成的码字共享，保证每个比特均被不同的码字保护，可以得到更好的编码增益。
结合第一方面或以上任一种可能的实现方式，在第一方面的第六种可能的实现方式中，所述第一码字中的每个比特被至少两个码字采用。
结合第一方面或以上任一种可能的实现方式，在第一方面的第七种可能的实现方式中，在所述第一码字中来自于m个之前形成的码字的比特中，至少一些比特为之前码字中的校验比特。
结合第一方面或以上任一种可能的实现方式，在第一方面的第八种可能的实现方式中，n为360，k为700。应理解，这是本申请给出的一个具体的码字，第一码字还可以为其他比特数量，本申请并不做限定。
结合第一方面或以上任一种可能的实现方式，在第一方面的第九种可能的实现方式中，将所述m个在所述第一码字之前形成的码字分为b组，将所述第一码字中与之前码字共享的n个比特分为b组，所述第一码字中的每一组对应所述m个在所述第一码字之前形成的码字中的一组，其中，b为正整数，n和m均为b的整数倍。
结合第一方面的第九种可能的实现方式，在第一方面的第十种可能的实现方式中，n为360，m为256；将所述256个在所述第一码字之前形成的码字分为4组，每组64个码字；将所述第一码字中与之前码字共享的360个比特分为4组，每组90个比特，其中，每组90个比特来自于对应的一组64个码字。
第二方面，提供一种用于数据通信的编码装置，所述编码装置包括编码单元和发送单元，所述编码单元，用于形成第一码字，所述第一码字包括2n个比特，由k个编码比特形成，且第一码字的n个比特来自于m个在所述第一码字之前形成的码字，所述第一码字中另外n个比特包括k-n个信息比特和2n-k个校验比特，将所述另外n个比特发送给所述发送单元，其 中，n、m、k均为正整数，2n＞k＞n＞m；所述发送单元，还用于将所述第一码字中的所述另外n个比特发送出去。
在本申请实施例提供的编码装置中，第一码字中的比特被多个不同时刻产生的码字保护，编码增益效果更好；而且，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特具备更快的收敛速度，可以提升译码器的译码速度，起到降低时延的作用。
结合第二方面，在第二方面的第一种可能的实现方式中，所述编码装置还包括存储单元，用于存储所述第一码字中的所述另外n个比特，供所述编码单元在编码所述第一码字之后的码字时使用。
结合第二方面或第二方面的第一种可能的实现方式，在第二方面的第二种可能的实现方式中，所述第一码字来自于所述m个在所述第一码字之前形成的码字中每个码字的比特数相同，其中，n为m的整数倍。本实施中第一码字从m个之前形成的码字中的每一个码字共享相同数目的比特，且共享比特数不止一个，两个码字之间共享的比特个数多，则需要共享的码字个数降低，在接收端可以快速完成数据的收集以及译码过程，从而降低时延。
结合第二方面或第二方面的第一种可能的实现方式，在第二方面的第三种可能的实现方式中，所述第一码字来自于第二码字的比特数为a，在所述m个在所述第一码字之前形成的码字中，至少有一个码字提供给所述第一码字的比特数与a不同，其中，a为正整数，第二码字为所述m个在所述第一码字之前形成的码字中的任意一个。在本实施例中，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特较快收敛，然后带动被更少码字保护的比特收敛，从而提升译码器的译码速度，降低时延。
结合第二方面或以上任一种可能的实现方式，在第二方面的第四种可能的实现方式中，所述编码装置具体用于：对来自于m个在所述第一码字之前形成的码字的n个比特和k-n个待传输的信息比特进行编码，得到2n-k个校验比特，形成所述第一码字。
结合第二方面或以上任一种可能的实现方式，在第二方面的第五种可能的实现方式中，所述第一码字中发送出去的n个比特，与在所述第一码字之后形成的一些码字共享。进一步地，所述第一码字中发送出去的n个比特，与在所述第一码字之后形成的m个码字共享。每个码字中的一半比特与之前形成的码字共享，另一半比特与之后形成的码字共享，保证每个比特均被不同的码字保护，可以得到更好的编码增益。
结合第二方面或以上任一种可能的实现方式，在第二方面的第六种可能的实现方式中，所述第一码字中的每个比特被至少两个码字采用。
结合第一方面或以上任一种可能的实现方式，在第一方面的第七种可能的实现方式中，在所述第一码字中来自于m个之前形成的码字的比特中，至少一些比特为之前码字中的校验比特。
结合第二方面或以上任一种可能的实现方式，在第二方面的第八种可能的实现方式中，n为360，k为700。应理解，这是本申请给出的一个具体的码字，第一码字还可以为其他比特数量，本申请并不做限定。
结合第二方面或以上任一种可能的实现方式，在第二方面的第九种可能的实现方式中，将所述m个在所述第一码字之前形成的码字分为b组，将所述第一码字中与之前码字共享的 n个比特分为b组，所述第一码字中的每一组对应所述m个在所述第一码字之前形成的码字中的一组，其中，b为正整数，n和m均为b的整数倍。
结合第二方面的第九种可能的实现方式，在第二方面的第十种可能的实现方式中，n为360，m为256；将所述256个在所述第一码字之前形成的码字分为4组，每组64个码字；将所述第一码字中与之前码字共享的360个比特分为4组，每组90个比特，其中，每组90个比特来自于对应的一组64个码字。
第三方面，提供一种用于数据通信的译码方法，所述方法包括：恢复出第一码字，其中，第一码字包括2n个比特，由k个编码比特形成，且第一码字的n个比特来自于m个在该第一码字之前译码的码字，第一码字中另外n个比特包括k-n个信息比特和2n-k个校验比特，其中，n、m、k均为正整数，2n＞k＞n＞m；对第一码字进行译码，得到译码后的比特。
应理解，在本实施例中，恢复出第一码字之前，至少已经有m个码字进行过译码了；第一码字中的一半比特是来自于之前译码的m个码字，另外n个比特是当前时刻接收到的比特流。此外，在本实施例中，不同的码字之间共享的比特个数不同，存在多个码字共享不止一个比特，共享的比特数越多，需要关联的码字数量会有所降低，无需等待时间过长，即可译码，从而降低系统时延。
结合第三方面，在第三方面的第一种可能的实现方式中，所述第一码字来自于所述m个在所述第一码字之前译码的码字中每个码字的比特数相同，其中，n为m的整数倍。本实施中第一码字从m个之前译码的码字中的每一个码字共享相同数目的比特，且共享比特数不止一个，两个码字之间共享的比特个数多，则需要共享的码字个数降低，可以快速完成数据的收集以及译码过程，从而降低时延。
结合第三方面，在第三方面的第二种可能的实现方式中，所述第一码字来自于第二码字的比特数为a，在所述m个在所述第一码字之前译码的码字中，至少有一个码字提供给所述第一码字的比特数与a不同，其中，a为正整数，第二码字为所述m个在所述第一码字之前译码的码字中的任意一个。在本实施例中，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特较快收敛，然后带动被更少码字保护的比特收敛，从而提升译码器的译码速度，降低时延。
结合第三方面或以上任一种可能的实现方式，在第三方面的第三种可能的实现方式中，n为360，k为700。应理解，这是本申请给出的一个具体的码字，第一码字还可以为其他比特数量，本申请并不做限定。
第四方面，提供一种用于数据通信的译码装置，包括译码单元和存储单元，其中，译码单元用于接收传输过来的码字，恢复出第一码字，并对第一码字进行译码，其中，该第一码字包括2n个比特，且第一码字的n个比特来自于m个在该第一码字之前译码的码字，n、m均为正整数，n＞m；存储单元用于存储来自于所述传输过来的码字，并从译码单元接收译码信息，对存储的码字进行更新，并在后续译码过程中将更新后的码字发回给译码单元。本实施例在译码过程中，会使用之前译码得到的信息比特，信息比特被不同的码字保护，译码性能更强。且两个码字之间共享的比特数更多，需要关联的码字数量会有所降低，无需等待时间过长，即可译码，从而降低系统时延。
结合第四方面，在第四方面的第一种可能的实现方式中，所述第一码字来自于所述m个在所述第一码字之前译码的码字中每个码字的比特数相同，其中，n为m的整数倍。本实施中第一码字从m个之前译码的码字中的每一个码字共享相同数目的比特，且共享比特数不止一个，两个码字之间共享的比特个数多，则需要共享的码字个数降低，可以快速完成数据的收集以及译码过程，从而降低时延。
结合第四方面，在第四方面的第二种可能的实现方式中，所述第一码字来自于第二码字的比特数为a，在所述m个在所述第一码字之前译码的码字中，至少有一个码字提供给所述第一码字的比特数与a不同，其中，a为正整数，第二码字为所述m个在所述第一码字之前译码的码字中的任意一个。在本实施例中，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特较快收敛，然后带动被更少码字保护的比特收敛，从而提升译码器的译码速度，降低时延。
结合第四方面或以上任一种可能的实现方式，在第四方面的第三种可能的实现方式中，n为360，k为700。应理解，这是本申请给出的一个具体的码字，第一码字还可以为其他比特数量，本申请并不做限定。
第五方面，提供一种基于数据通信的级联编码方法，所述方法包括：接收数据比特，对数据比特进行KP4编码，得到KP4码字；将所述KP4码字进行交织，得到交织后的码字；将所述交织后的码字按照第一方面或第一方面任一种可能的实现方式所述的编码方法进行编码，其中，所述交织后的码字在进行如第一方面或第一方面任一种可能的实现方式所述的编码之前，不进行译码。本实施例中，经交织的KP4码字无需译码，直接进行下一步的级联编码，可以降低功耗。
第六方面，提供一种基于数据通信的级联编码装置，所述级联编码装置包括：第一编码单元，交织单元和第二编码单元；第一编码单元，用于接收数据比特，对数据比特进行KP4编码，将得到的KP4码字发送给交织单元；交织单元，用于将所述KP4码字进行交织，将交织后的码字发送给第二编码单元；第二编码单元，用于将所述交织后的码字按照第一方面或第一方面任一种可能的实现方式所述的编码方法进行编码，其中，第二编码单元不对所述交织后的码字进行译码。本实施例中，经交织的KP4码字无需译码，直接进行下一步的级联编码，可以降低功耗。
第七方面、提供一种用于数据通信的编码方法，所述方法包括：形成第一码字，所述第一码字包括n个镜像比特和n个待传输比特，且所述n个镜像比特从m个源码字的待传输比特中挑选，其中，所述源码字为在所述第一码字之前形成的码字，n和m均为正整数，n＞m；将所述第一码字的所述n个待传输比特发送出去。
在本申请实施例中，第一码字中的比特被多个不同时刻产生的码字保护，编码增益效果更好；而且，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特具备更快的收敛速度，可以提升译码器的译码速度，起到降低时延的作用。
结合第七方面，在第七方面的第一种可能的实现方式中，所述n个待传输比特包括p个校验比特和n-p个信息比特，其中，所述p个校验比特由所述n个镜像比特和所述n-p个信息比特编码得到，p为小于n的正整数。
结合第七方面的第一种可能的实现方式，在第七方面的第二种可能的实现方式中，所述 n个镜像比特包括镜像校验比特和镜像信息比特，其中，所述镜像校验比特为从m个所述源码字的校验比特中挑选，所述镜像信息比特从m个所述源码字的信息比特中挑选。
结合第七方面的第二种可能的实现方式，在第七方面的第三种可能的实现方式中，所述镜像校验比特和所述校验比特的个数相同。
结合第七方面或第七方面的上述可能的实现方式，在第七方面的第四种可能的实现方式中，在所述m个源码字中，不同源码字提供给所述第一码字的比特数目差的最大值大于一个比特，此时，在保持低时延的前提下可以进一步提升纠错性能。
结合第七方面或第七方面的上述可能的实现方式，在第七方面的第五种可能的实现方式中，所述第一码字的码长不大于2048，纠错比特数不大于5。在本实施例中，所述第一码字能在保证低时延的前提下依旧具有较好的性能。
结合第七方面或第七方面的上述可能的实现方式，在第七方面的第六种可能的实现方式中，在所述m个源码字中，至少一个源码字提供给所述第一码字的比特数目与其他源码字提供给所述第一码字的比特数目不相同；或每个源码字提供给所述第一码字q个比特，其中，q为大于1的整数，n为m的整数倍。本实施例中，每个比特均被不同的码字保护，且一个码字提供给所述第一码字的比特数可以不止一个，在保证编码增益的情况下，译码的速度更快。
结合第七方面或第七方面的上述可能的实现方式，在第七方面的第七种可能的实现方式中，p_word个所述第一码字构成第一帧，所述第一帧中码字的镜像比特来自于在所述第一帧之前生成的h个第二帧中码字的待传输比特，其中，h和p_word均为大于1的正整数。
结合第七方面的第七种可能的实现方式，在第七方面的第八种可能的实现方式中，所述h个第二帧中比特的帧坐标，行坐标和列坐标通过Φf()，Φr()和Φc()三个函数计算得到：
Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str+Δ)/ceiling(n/h)))；
Figure PCTCN2021081940-appb-000001
Φc([Frame,Row_str,Col_str])＝n+h*((Col_str+Δ)％ceiling(n/h))+(h-1-floor((Col_str+Δ)/ceiling(n/h)))。
其中，所述第一帧中码字的镜像比特的帧坐标Frame、行坐标Row_str和列坐标Col_str均为整数，且Frame∈(-∞,+∞)，Row_str∈[0，p_word-1]，Col_str∈[0，2n-1]；frm_map(i)＝h-1-i,i∈[0,h-1]；
如果n/h为整数，Δ＝0；否则，如果Col_str/floor(n/h)<ceiling(n/h)*h-n，Δ＝floor(Col_str/floor(n/h))；如果Col_str/floor(n/h)>＝ceiling(n/h)*h-n，Δ＝ceiling(n/h)*h-n。
结合第七方面的第八种可能的实现方式，在第七方面的第九种可能的实现方式中，所述第一帧中码字的镜像校验比特的列坐标Col_str集合如下所示：
Col_str_vec(i,:)＝[i_base(i)-Range(i)+1:i_base(i)]，0<＝i<＝h-1；
其中，如果i<ceiling(n/h)*h-n，i_base(i)＝(i+1)*ceiling(n/h)-i-2；如果i>＝ceiling(n/h)*h-n，i_base(i)＝(i+1)*ceiling(n/h)-ceiling(n/h)*h-n-1；Range(i)＝ceiling((p-i)/h)ROR(ceiling(n/h)*h-n)，ROR为数组循环右移。
结合第七方面的第八种或第九种可能的实现方式，在第七方面的第十种可能的实现方式中，第一码字为BCH(720，700)码，h＝5，p_word＝64，则Φf()，Φr()和Φc()三个函数表 达式如下所示：
Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str)/72))，
Figure PCTCN2021081940-appb-000002
Φc([Frame,Row_str,Col_str])＝360+5*((Col_str)％72)+(4–floor((Col_str)/72))，其中，frm_map(i)＝4-i,i∈[0,4]，且i为整数。
结合第七方面的第十种可能的实现方式，在第七方面的第十一种可能的实现方式中，所述第一帧中码字的镜像校验比特的列坐标Col_str集合如下所示：
Col_str_vec(i,:)＝{[68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359]}。
结合第七方面的第七种可能的实现方式，在第七方面的第十二种可能的实现方式中，所述h个第二帧中比特的帧坐标Frame’，行坐标Row_str’和列坐标Col_str’由如下公式得到：
Frame’＝Frame+1+frm_map(Col_str％h)；
Col_str’＝(h–1–Col_str％h)*ceiling(n/h)+floor(Col_str/h)–Δ；
Figure PCTCN2021081940-appb-000003
其中，所述第一帧中码字的镜像比特的帧坐标Frame、行坐标Row_str和列坐标Col_str均为整数，且Frame∈(-∞,+∞)，Row_str∈[0，p_word-1]，Col_str∈[0，2n-1]；frm_map(i)＝i,i∈[0,h-1]，且i为整数；
如果n/h为整数，Δ＝0；否则，如果Col_str/floor(n/h)<ceiling(n/h)*h-n，Δ＝floor(Col_str/floor(n/h))；如果Col_str/floor(n/h)>＝ceiling(n/h)*h-n，Δ＝ceiling(n/h)*h-n。
结合第七方面的第十二种可能的实现方式，在第七方面的第十三种可能的实现方式中，第一码字为BCH(720，700)码，h＝5，p_word＝64，则：Frame’＝Frame+1+frm_map(Col_str％5)；
Col_str’＝(4–Col_str％5)*72+floor(Col_str/5)；
Figure PCTCN2021081940-appb-000004
其中，frm_map(i)＝i,i∈[0,4]。
结合第七方面任一种可能的实现方式，在第七方面的第十四种可能的实现方式中，所述方法还包括：将所述n个待传输比特存储起来，供编码所述第一码字之后的码字时使用。
结合第七方面任一种可能的实现方式，在第七方面的第十五种可能的实现方式中，所述第一码字中发送出去的n个比特，与在所述第一码字之后形成的一些码字共享。
结合第七方面任一种可能的实现方式，在第七方面的第十六种可能的实现方式中，所述第一码字中的每个比特被至少两个码字采用。
结合第七方面任一种可能的实现方式，在第七方面的第十七种可能的实现方式中，所述第一码字为BCH(720，700)码。
第八方面，提供一种编码装置，所述编码装置包括编码单元和发送单元，所述编码单元，用于形成第一码字，所述第一码字包括n个镜像比特和n个待传输比特，且所述n个镜像比特从m个源码字的待传输比特中挑选，其中，所述源码字为在所述第一码字之前形成的码字，n和m均为正整数，n＞m；所述发送单元，用于将所述第一码字中的所述n个待传输比特发送出去。
在本申请实施例中，第一码字中的比特被多个不同时刻产生的码字保护，编码增益效果更好；而且，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特具备更快的收敛速度，可以提升译码器的译码速度，起到降低时延的作用。
结合第八方面，在第八方面的第一种可能的实现方式中，所述n个待传输比特包括p个校验比特和n-p个信息比特，其中，所述p个校验比特由所述n个镜像比特和所述n-p个信息比特编码得到，p为小于n的正整数。
结合第八方面的第一种可能的实现方式，在第八方面的第二种可能的实现方式中，所述n个镜像比特包括镜像校验比特和镜像信息比特，其中，所述镜像校验比特为从m个所述源码字的校验比特中挑选，所述镜像信息比特从m个所述源码字的信息比特中挑选。
结合第八方面的第二种可能的实现方式，在第八方面的第三种可能的实现方式中，所述镜像校验比特和所述校验比特的个数相同。
结合第八方面的任一种可能的实现方式，在第八方面的第四种可能的实现方式中，在所述m个源码字中，不同源码字提供给所述第一码字的比特数目差的最大值大于一个比特。
结合第八方面的任一种可能的实现方式，在第八方面的第五种可能的实现方式中，所述第一码字的码长不大于2048，纠错比特数不大于5。
结合第八方面的任一种可能的实现方式，在第八方面的第六种可能的实现方式中，在所述m个源码字中，至少一个源码字提供给所述第一码字的比特数目与其他源码字提供给所述第一码字的比特数目不相同；或
每个源码字提供给所述第一码字q个比特，其中，q为大于1的整数，n为m的整数倍。
结合第八方面的任一种可能的实现方式，在第八方面的第七种可能的实现方式中，p_word个所述第一码字构成第一帧，所述第一帧中码字的镜像比特来自于在所述第一帧之前生成的h个第二帧中码字的待传输比特，其中，h和p_word均为大于1的正整数。
结合第八方面的第七种可能的实现方式，在第八方面的第八种可能的实现方式中，所述h个第二帧中比特的帧坐标，行坐标和列坐标通过Φf()，Φr()和Φc()三个函数计算得到：
Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str+Δ)/ceiling(n/h)))；
Figure PCTCN2021081940-appb-000005
Φc([Frame,Row_str,Col_str])＝n+h*((Col_str+Δ)％ceiling(n/h))+(h-1-floor((Col_str+Δ)/ceiling(n/h)))。
其中，所述第一帧中码字的镜像比特的帧坐标Frame、行坐标Row_str和列坐标Col_str均为整数，且Frame∈(-∞,+∞)，Row_str∈[0，p_word-1]，Col_str∈[0，2n-1]；frm_map(i)＝h-1-i,i∈[0,h-1]；如果n/h为整数，Δ＝0；否则，如果Col_str/floor(n/h)<ceiling(n/h)*h-n，Δ＝floor(Col_str/floor(n/h))；如果Col_str/floor(n/h)>＝ceiling(n/h)*h-n，Δ＝ceiling(n/h)*h-n。
结合第八方面的第八种可能的实现方式，在第八方面的第九种可能的实现方式中，所述第一帧中码字的镜像校验比特的列坐标Col_str集合如下所示：
Col_str_vec(i,:)＝[i_base(i)-Range(i)+1:i_base(i)]，0<＝i<＝h-1；
其中，如果i<ceiling(n/h)*h-n，i_base(i)＝(i+1)*ceiling(n/h)-i-2；如果i>＝ ceiling(n/h)*h-n，i_base(i)＝(i+1)*ceiling(n/h)-ceiling(n/h)*h-n-1；Range(i)＝ceiling((p-i)/h)ROR(ceiling(n/h)*h-n)，ROR为数组循环右移。
结合第八方面的第八种或第九种可能的实现方式，在第八方面的第十种可能的实现方式中，第一码字为BCH(720，700)码，h＝5，p_word＝64，则Φf()，Φr()和Φc()三个函数表达式如下所示：
Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str)/72))，
Figure PCTCN2021081940-appb-000006
Φc([Frame,Row_str,Col_str])＝360+5*((Col_str)％72)+(4–floor((Col_str)/72))，其中，frm_map(i)＝4-i,i∈[0,4]，且i为整数。
结合第八方面的第十种可能的实现方式，在第八方面的第十一种可能的实现方式中，所述第一帧中码字的镜像校验比特的列坐标Col_str集合如下所示：
Col_str_vec(i,:)＝{[68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359]}。
结合第八方面的第七种可能的实现方式，在第八方面的第十二种可能的实现方式中，所述h个第二帧中比特的帧坐标Frame’，行坐标Row_str’和列坐标Col_str’由如下公式得到：
Frame’＝Frame+1+frm_map(Col_str％h)；
Col_str’＝(h–1–Col_str％h)*ceiling(n/h)+floor(Col_str/h)–Δ；
Figure PCTCN2021081940-appb-000007
其中，所述第一帧中码字的镜像比特的帧坐标Frame、行坐标Row_str和列坐标Col_str均为整数，且Frame∈(-∞,+∞)，Row_str∈[0，p_word-1]，Col_str∈[0，2n-1]；frm_map(i)＝i,i∈[0,h-1]，且i为整数；
如果n/h为整数，Δ＝0；否则，如果Col_str/floor(n/h)<ceiling(n/h)*h-n，Δ＝floor(Col_str/floor(n/h))；如果Col_str/floor(n/h)>＝ceiling(n/h)*h-n，Δ＝ceiling(n/h)*h-n。
结合第八方面的第十二种可能的实现方式，在第八方面的第十三种可能的实现方式中，第一码字为BCH(720，700)码，h＝5，p_word＝64，则：Frame’＝Frame+1+frm_map(Col_str％5)；
Col_str’＝(4–Col_str％5)*72+floor(Col_str/5)；
Figure PCTCN2021081940-appb-000008
其中，frm_map(i)＝i,i∈[0,4]。
结合第八方面任一种可能的实现方式，在第八方面的第十四种可能的实现方式中，所述方法还包括：将所述n个待传输比特存储起来，供编码所述第一码字之后的码字时使用。
结合第八方面任一种可能的实现方式，在第八方面的第十五种可能的实现方式中，所述第一码字中发送出去的n个比特，与在所述第一码字之后形成的一些码字共享。
结合第八方面任一种可能的实现方式，在第八方面的第十六种可能的实现方式中，所述第一码字中的每个比特被至少两个码字采用。
结合第八方面的任一种可能的实现方式，在第八方面的第十七种可能的实现方式中，所述第一码字为BCH(720，700)码。
第九方面，提供一种计算机可读存储介质，所述计算机可读存储介质存储指令，当所述 指令在终端设备上运行时，使得所述终端设备执行如第一方面或第一方面任一种可能的实现方式所述的方法；或使得所述终端设备执行如第三方面或第三方面中任一种可能的实现方式所述的方法；或使得所述终端设备执行如第七方面或第七方面中任一种可能的实现方式所述的方法。
第十方面，提供一种包含指令的计算机程序产品，当在终端设备上运行时，使得终端设备执行如第一方面或第一方面任一种可能的实现方式所述的方法；或使得所述终端设备执行如第三方面或第三方面中任一种可能的实现方式所述的方法；或使得所述终端设备执行如第七方面或第七方面中任一种可能的实现方式所述的方法。应理解，终端设备可以为芯片、处理器等等，本申请并不做限定。
第十一方面，提供一种基于数据通信的级联编码方法，所述方法包括：接收数据比特，对数据比特进行KP4编码，得到KP4码字；将所述KP4码字进行交织，得到交织后的码字；将所述交织后的码字按照第七方面或第七方面任一种可能的实现方式所述的编码方法进行编码，其中，所述交织后的码字在进行如第七方面或第七方面任一种可能的实现方式所述的编码之前，不进行译码。本实施例中，经交织的KP4码字无需译码，直接进行下一步的级联编码，可以降低功耗。
第十二方面，提供一种基于数据通信的级联编码装置，所述级联编码装置包括：第一编码单元，交织单元和第二编码单元；第一编码单元，用于接收数据比特，对数据比特进行KP4编码，将得到的KP4码字发送给交织单元；交织单元，用于将所述KP4码字进行交织，将交织后的码字发送给第二编码单元；第二编码单元，用于将所述交织后的码字按照第七方面或第七方面任一种可能的实现方式所述的编码方法进行编码，其中，第二编码单元不对所述交织后的码字进行译码。本实施例中，经交织的KP4码字无需译码，直接进行下一步的级联编码，可以降低功耗。
在本申请上述实施例中，第一码字中的比特被多个不同时刻产生的码字保护，编码增益效果更好；而且，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特具备更快的收敛速度，可以提升译码器的译码速度，起到降低时延的作用。
附图说明
图1为通信系统的结构框图；
图2为本申请提供的编码方法流程图；
图3为本申请一实施例提供的一种码字共享规则示意图；
图4为本申请另一实施例提供的一种码字共享规则示意图；
图5为本申请另一实施例提供的一种码字共享规则示意图；
图6为本申请另一实施例提供的FEC帧的存储方式示意图；
图7为本申请另一实施例提供的FEC帧中需补充比特的构成方式图；
图8为本申请另一实施例提供的FEC帧中需补充的一列比特的共享规则图；
图9为本申请另一实施例提供的译码方法流程图；
图10本申请另一实施例提供的编码装置图；
图11本申请另一实施例提供的译码装置图；
图12本申请另一实施例提供的编码装置图；
图13本申请另一实施例提供的译码装置图；
图14为本申请另一实施例提供的高速传输系统结构图；
图15为本申请另一实施例提供的800G传输系统结构图；
图16为本申请提供的编码方案应用于800G传输系统中的仿真结果图；
图17(a)为本申请另一实施例提供的码字结构示意图；
图17(b)为本申请另一实施例提供的FEC帧结构示意图；
图18为本申请另一实施例提供一种码字共享规则示意图；
图19为本申请另一实施例提供的一种交织方案示意图；
图20为本申请另一实施例提供的一种具体的FEC帧交织方案示意图；
图21为本申请另一实施例提供的一种具体的FEC帧交织方案示意图；
图22为本申请另一实施例提供的一种具体的FEC帧交织方案示意图；
图23为本申请另一实施例提供的FEC帧的编码架构图；
图24为利用如图23所示的编码架构生成当前帧的镜像比特的示意图；
图25为本申请另一实施例提供的一种具体的FEC帧交织方案示意图；
图26为本申请另一实施例提供的一种具体的FEC帧交织方案示意图；
图27为本申请另一实施例提供的一种具体的FEC帧交织方案示意图。
具体实施方式
在对本申请实施例进行详细地解释说明之前，先对本申请实施例的应用场景予以说明。图1示出通信系统的结构框图，在发送端，信源提供待发送的数据流；编码器接收该数据流，并对其进行编码，编码获得校验比特和信息比特合并的码字信息进行发送，经过信道传输，到达接收端；接收端接收到因为信道中的噪声或者其他损伤产生错误的码字信息后，通过译码器进行译码，恢复出原有数据，发给信宿。其中，本申请提供的编码方法应用于图1所示的编码器中，是通信系统中非常重要的一环。
信源中发出的数据经过采用本编码方案的编码器，会连续形成多个由数据比特和校验比特组成的码字，构成码字流，其中，生成的码字会与在此之前或之后生成的码字共享比特，使得码字中的比特被多个不同时刻产生的码字保护，可以获得更好的编码增益。
本申请提供一种用于数据通信的编码方法，如图2所示，包括：
201、形成第一码字，该第一码字包括2n个比特，由k个编码比特形成，且第一码字的n个比特来自于m个在该第一码字之前形成的码字，第一码字中另外n个比特包括k-n个信息比特和2n-k个校验比特，其中，n、m、k均为正整数，2n＞k＞n＞m；
202、将所述第一码字中的所述另外n个比特发送出去。
应理解，在本实施例中，形成第一码字之前，至少已经产生m个码字了；第一码字中的一半比特是来自于之前形成的m个码字的，也就是说，这一半比特是从该m个码字的每个码字中各拿几个比特组成的，是与之前的m个码字共享的；而剩余的k-n个比特为当前时刻的信息比特，根据从之前形成的m个码字中共享的n个比特和当前时刻的k-n个信息比特，经过编码，得到2n-k个校验比特，从而形成第一码字。由于第一码字中有n个比特已经在之前 形成的码字发送过了，无需再次发送，因此，将第一码字中另外n个比特发送出去，即剩余的k-n个信息比特和新生成的2n-k个校验比特构成待传输码字，将所述待传输码字发送出去。
大体来说，第一码字与先前形成的码字及后续形成的码字共享比特；在第一码字中，每一个比特位于至少一个先前形成或后续形成的码字中。此外，在一些实施例中，第一码字的k个编码比特中的至少一些比特为其它码字的数据比特，且k个编码比特中的至少一些比特为其它码字的校验比特。在本申请实施例中，参与码字编码的比特为编码比特，当前时刻收到的待传输比特为信息比特，在k个编码比特中，存在n个比特是与之前码字共享的，剩余的k-n个比特为当前时刻待传输的信息比特。
通常情况下，在生成的码字流中，初始的部分码字需要包含填充比特，例如填充全0比特序列，直到形成足够数量的码字，可以为后续码字提供足够的共享比特。例如，如本申请实施例所述，码字包括2n个比特，其中一半比特与在先形成的m个码字的比特进行共享，即在先码字中的比特会作为当前码字的编码比特；此时，在初始的m个码字中，由于不存在m个在先码字，无法从在先码字中获得足够的编码比特，因此，需要在码字中增加一些填充比特，将编码比特的数量补充完整，以便生成校验比特，形成第一码字。应理解，在初始的m个码字中，除了第一个码字之外，其他码字可以从之前的码字中共享一部分比特，再填充剩余部分的比特；也可以不与在先码字共享，缺少的编码比特全部由填充比特替换，本申请在此不做限定。
进一步地，还需要将所述另外n个比特存储起来，在对第一码字之后的码字进行编码时使用。
在本申请实施例中，第一码字的n个比特是与m个在该第一码字之前形成的码字共享的，且由于n是大于m的，m个码字中总会有码字与第一码字共享多个比特，具体的共享规则有多种，描述如下：
(1)n是m的整数倍，m个码字中每个码字与第一码字共享的比特数目相同。图3是根据本方案提供的一种具体的码字共享规则示意图，在图3中，每个码字的长度为16比特，包括14个编码比特(图中的D)和2个校验比特(图中的P)。在14个编码比特中，有8个比特(码字长度的一半)来自于之前形成的4个码字，每个码字各取2个比特。例如图3中被实线包围的码字，为码字X，其中2个比特来源于码字X-1，2个比特来源于码字X-2，2个比特来源于X-3，这6个比特均为之前码字中的信息比特，还有2个比特来源于X-4，这2个比特为之前码字中的检验比特；码字X中剩余的6个信息比特为当前时刻待传输的信息比特，将来自于之前码字的8个比特和当前时刻的6个比特经过编码，得到2个校验比特，从而构成长度为16比特的码字X。
同理，码字X的下一个码字X+1，如图3中被虚线包围的部分，码字X+1包括16个比特，其中2个比特来源于码字X，2个比特来源于码字X-1，2个比特来源于X-2，这6个比特也为之前码字的信息比特，剩余2个比特来源于X-3，为之前码字的校验比特；剩余的6个比特为当前时刻待传输的信息比特，将来自于之前码字的8个比特和当前时刻的6个比特经过编码，得到2个校验比特，构成长度为16比特的码字X+1。
在本实施例公开的码字流中，除去初始的4个比特以及结尾的4个比特(m＝4)，中间的所有码字中，每个码字均有一半比特与在先的码字共享，一半比特与后续的码字共享，使得 码字中的比特被多个不同时刻产生的码字保护，可以获得更好的编码增益；且每个码字与其他码字共享的比特数均为2，两个码字之间共享的比特个数增多，则需要共享的码字个数降低，在接收端可以快速完成数据的收集以及译码过程，从而降低时延。当然共享的比特个数还可以进一步增大，本申请并不做限定。
(2)在m个之前形成的码字中，至少存在一个码字与第一码字共享的比特数目，与其他码字与第一码字共享的比特数目不同。例如，假设n＝9，m＝4，有一个码字与第一码字共享3个比特，剩余三个码字均与第一码字共享2个比特；或者，一个码字与第一码字共享1个比特，另一个码字与第一码字共享2个比特，剩余两个码字均与第一码字共享3个比特。
图4为根据本方案提供的一种具体的码字共享规则示意图，在图4中，每个码字的长度也为16比特，包括14个编码比特(图中的D)和2个校验比特(图中的P)。在14个编码比特中，有8个比特(码字长度的一半)来自于之前形成的6个码字，从每个码字获取的比特个数如图4所示，例如图4中被实线包围的码字X，其中2个比特来源于码字X-1，1个比特来源于码字X-2，1个比特来源于码字X-3，2个比特来源于码字X-4，这6个比特均为之前码字中的信息比特；剩余的2个比特均为之前码字中的检验比特，其中一个比特来源于码字X-5，另一个比特来源于码字X-6；码字X中剩余的6个比特为当前时刻待传输的信息比特，将来自于之前码字的8个比特和当前时刻的6个比特经过编码，得到2个校验比特，从而构成长度为16比特的码字X。同理，码字X的后续码字X+1，如图4中虚线包围的部分所示，与码字X类似，本申请不再赘述。
此外，在n为m的整数倍的情况下，也可能存在至少一个码字与第一码字共享的比特数目，与其他码字和第一码字共享的比特数不同的情况；例如，n＝8，m＝4，一个码字与第一码字共享5个比特，其余码字各共享1个比特，或者，两个码字与第一码字共享3个比特，另两个码字与第一码字共享1个比特。
图5为根据本方案提供的另一种具体的码字共享规则示意图，在图5中，每个码字的长度同样为16比特，包括14个编码比特(图中的D)和2个校验比特(图中的P)。在14个编码比特中，有8个比特(码字长度的一半)来自于之前形成的4个码字，从每个码字获取的比特个数如图5所示，例如图4中被实线包围的码字X，其中3个比特来源于码字X-1，1个比特来源于码字X-2，3个比特来源于码字X-3，1个比特来源于码字X-4，这8个比特包括6个之前码字中的信息比特和2个之前码字中的检验比特；码字X中剩余的6个比特为当前时刻待传输的信息比特，将来自于之前码字的8个比特和当前时刻的6个比特经过编码，得到2个校验比特，从而构成长度为16比特的码字X。同理，码字X的后续码字X+1，如图4中虚线包围的部分所示，与码字X类似，本申请不再赘述。
在本实施例公开的码字流中，除去初始的m个比特以及结尾的m个比特(图4中m＝6，图5中m＝4)，中间的所有码字中，每个码字均有一半比特与在先的码字共享，一半比特与后续的码字共享，使得码字中的比特被多个不同时刻产生的码字保护，可以获得更好的编码增益。此外，不同时刻的码字之间共享的比特个数不尽相同，使得码字中的比特被不同个数的码字保护，被更多数量的码字保护的比特较快收敛，然后带动被更少码字保护的比特收敛，从而提升译码器的收敛速度，起到降低时延的作用。应理解，图4和图5只是给出了两种不同的比特共享方式，还存在其他的共享方式，本申请对此不做限定。
可选地，在所述m个之前形成的码字中，不同码字提供给所述第一码字的比特数目差的 最大值大于一个比特，在保持低时延的前提下可以进一步提升纠错性能。
从上述两个不同的实施例中可以看出，除去初始和结尾的部分码字，中间的所有码字均有一半比特来自于在先形成的码字，这一半比特的作用是与当前时刻的信息比特共同参与校验比特的生成，且这一半比特本身是不参与当前码字的传输的。当前时刻的信息比特以及编码生成的校验比特构成码字的另一半比特，这另一半比特是待传输的比特，且与后续形成的码字共享。
以第一码字为博斯-查德胡里-霍昆格姆(Bose-Chaudhuri-Hocquenghem，BCH)码，其比特数为720为例，其中360个比特来自于之前形成的码字，340个比特为当前码字中的信息比特，总共700个编码比特根据BCH(720，700)对应的生成多项式进行编码，即可得到20个校验比特；其中，来自于之前形成的码字的360个比特不参与数据传输，由340个当前信息比特和20个校验比特一起组成360个比特的待传输的BCH码字。应理解，BCH(720，700)是通过BCH(1023，1003)缩短303个比特得到的，具体的缩短方式可以为去掉高位的303个比特，或去掉低位的303个比特，或者其他方式，本申请对此不做限定。
本申请另一实施例还提供了一种FEC帧的编码方式，其中，该FEC帧包括Num个如之前实施例所述的待传输码字，其可参照图6所示的方式存入内存中，每一列为一个待传输码字，Num为大于1的正整数。
在某一时刻编码生成FEC帧时，根据之前的实施例所述，生成每一个待传输码字(待传输码字包括n个比特)，需要额外补充n个比特，该n个比特来自于之前形成的一些码字，本实施例将补充的比特记为Info_Pad，因此，生成FEC帧需要额外补充n行，Num列Info_Pad。假设Info_Pad来自于之前形成的T个FEC帧，Info_Pad的比特可以用(Row_Inf，Col_Inf)来表示，Row_Inf为Info_Pad的行号，为0、1、2。。。n-1中任意一个值；Col_Inf为Info_Pad的列号，为0、1、2。。。Num-1中任意一个值。之前形成的T个FEC帧的比特用(Frame，Row_str，Col_str)表示，Frame为FEC帧的编号，为0、1、2。。。T-1中任意一个值，第0帧为在上一个时刻生成的FEC帧，第1帧为再往前一个时刻生成的FEC帧，依次类推；Row_str为FEC帧的行号，为0、1、2。。。n-1中任意一个值；Col_str为FEC帧的列号，为0、1、2…Num-1中任意一个值。此时，Info_Pad中每一个比特与之前形成的FEC帧的比特之间的对应关系，可以根据如下公式计算：
Frame＝floor((Intial_Row+Row_skip*Row_Inf)/n)(1)
Row_str＝(Intial_Row+Row_skip*Row_Inf+floor(Row_skip*Row_Inf/n))％n(2)
Col_str＝(Col_Inf+Row_Inf)％Num    (3)
其中，Intial_Row表示的是在T个FEC帧中，与Info_Pad共享的第一行比特的行号，Row_skip表示的是在T个FEC帧中，每隔多少行选取一行比特与Info_Pad共享；应注意，Intial_Row为不小于0的整数，Row_skip为正整数，且Intial_Row+Row_skip*(n-1)不能超过n*(T-1)的值。
此处提到的在当前时刻之前形成的T个FEC帧，可以为之前任意时刻的T个FEC帧。例如当前时刻之前T个连续时刻的FEC帧，也可以为当前时刻间隔某个固定时刻后，再连续取 T个FEC帧，也可以当前时刻之前任意T个不连续时刻的FEC帧，本申请不做限定。
具体地，下面以待传输码字为BCH(360，340)，FEC帧包括64个待传输码字为例，描述了一种具体的Info_Pad的构成方式，其中，生成FEC帧需要额外补充360行、64列的Info_Pad。假设Info_Pad来自于之前形成的4个FEC帧，共256个码字，则Info_Pad的构成方式如图7所示，此时，Info_Pad的行号Row_Inf为0、1、2。。。359中任意一个值，Info_Pad的列号Col_Inf为0、1、2。。。63中任意一个值；FEC帧的编号Frame为0、1、2、3中任意一个值，FEC帧的行号Row_str为0、1、2。。。359中任意一个值，FEC帧的列号Col_str为0、1、2。。。63中任意一个值。
在图7所示的构成方式中，初始行号为0，每隔4行选取一行比特与Info_Pad共享，即Intial_Row＝0，Row_skip＝4，则Info_Pad中每一个比特与之前形成的FEC帧的比特之间的对应关系的公式可以简化如下：
Frame＝floor(Row_Inf/90)(4)
Row_str＝(4*Row_Inf+floor(Row_Inf/90)％360(5)
Col_str＝(Col_Inf+Row_Inf)％64     (6)
结合上述公式(4)和(5)，以及图7可以看出，当Row_Inf＝0时，则Frame＝0，Row_str＝0，也就是说，Info_Pad的第0行是与之前形成的4个FEC帧中第0帧的第0行对应的；当Row_Inf＝89时，则Frame＝0，Row_str＝356，即Info_Pad的第89行是与之前形成的4个FEC帧中第0帧的第356行对应的；当Row_Inf＝90时，则Frame＝1，Row_str＝1，也就是说，
Info_Pad的第90行是与之前形成的4个FEC帧中第1帧的第1行对应的。
根据公式(4)和(5)确定出Info_Pad中每一行分别对应哪个帧中的哪一行后，再根据公式(6)，可确定Info_Pad的某一行中任一比特与对应的FEC帧的对应行中的哪个比特共享。例如，当Row_Inf＝0时，则Col_str＝Col_Inf，即在Info_Pad的第0行中，第0个比特与对应行的第0个比特共享，第1个比特与对应行的第1个比特共享，以此类推；当Row_Inf＝1时，则Col_str＝Col_Inf+1，即在Info_Pad的第1行中，第0个比特与对应行的第1个比特共享，第1个比特与对应行的第2个比特共享，以此类推；当Row_Inf＝64时，则Col_str＝Col_Inf，即在Info_Pad的第64行中，第0个比特与对应的那一行的第0个比特共享，第1个比特与对应的那一行的第1个比特共享，其中，Info_Pad第64行的共享关系与Info_Pad第0行的共享关系是一致的。
综上所述，公式(6)给出了Info_Pad的每一行与之前FEC帧中对应行之间的交织关系，且行交织的周期为64，每经过64行，交织关系会重复一次。例如，Info_Pad的第0-63行中，每一行与之前FEC帧的对应行之间的交织关系都不相同，但从第64行开始，交织关系开始重复，例如，Info_Pad的第0行与第64行的交织关系相同，第1行与第65行的交织关系相同等等。应理解，还可以采用其他的行交织关系，例如，按照伽罗华域(Galois Field，GF)进行交织计算。
在本实施例中，Info_Pad的每5760个比特(90行×64列)来源于一个之前形成的FEC帧，而行交织的周期为64，因此，在这90行比特中，有26行比特只能重复采用其他行用过的交织关系。图8给出了Info_Pad第一列中包括的90个比特与对应的FEC帧中的比特之间 的共享关系，图8中的实心块表示该FEC帧中与Info_Pad第一列共享的比特位置，该共享关系满足公式(5)和(6)的条件，例如，Info_Pad(0，0)与图8中实心块(0，0)位置的比特共享，Info_Pad(1，0)与图8中实心块(4，1)位置的比特共享，Info_Pad(2，0)与图8中实心块(8，2)位置的比特共享，Info_Pad(64，0)与图8中实心块(256，0)位置的比特共享，Info_Pad(89，0)与图8中实心块(356，25)位置的比特共享，其中，(a，b)表示第a行，第b列。
从图8中可以看出，在FEC帧中，第0-25列均与Info_Pad的第0列共享两个比特，第26-63列均与Info_Pad的第0列共享一个比特。同理可以推出，Info_Pad的每一列包括的90个比特与26个之前形成的待传输码字各共享两个比特，与另外38个之前形成的待传输码字各共享1个比特。由于Info_Pad的每一列包括360个比特，且每90行对应一个之前形成的FEC帧，则Info_Pad的每一列与104个(26×4＝104)之前形成的待传输码字各共享两个比特，与另外152个(38×4＝152)之前形成的待传输码字各共享1个比特。
综上所述，在编码生成待传输的FEC帧的过程中，以生成待传输的FEC帧中的第一列比特(第一列比特记为第一待传输码字)为例，该第一待传输码字的生成与Info_Pad的第一列比特以及接收到的340个当前信息比特相关，即根据BCH(720，700)对应的生成多项式，Info_Pad的第一列包括的360个比特与接收到的340个当前信息比特一起编码，生成20个校验比特，其中，340个当前信息比特和生成的20个校验比特构成了第一待传输码字；以此类推，可以编码得到64个待传输码字，共同组成当前编码的FEC帧。
简而言之，FEC帧的编码过程如下：
首先，接收待传输的信息比特，在本实施例中待传输的信息比特的数量为340；
其次，通过本实施例提供的方式，从之前形成的256个码字中获得360个比特；
再次，将该360个比特与接收的340个比特一起编码，生成20个校验比特，将接收的340个比特和生成的20个比特发送出去，其中，接收的340个比特和生成的20个校验比特构成了第一待传输码字，64个第一待传输码字构成了FEC帧；
实际的编码过程中，可以是一个编码器执行编码，也可以由多个编码器并行编码，例如，8个编码器并行编码，得到8个待传输码字，在经过并串转换形成一个比特流，发送出去。
应理解，待传输码字为BCH(360，340)只是一种可能的实施例，还可以是其他长度，例如，BCH(510，490)、BCH(256，238)等，也可以采用如汉明码、里德-所罗门(Reed-solomon，RS)码等不同的编码规则，本申请对此不做限定。
采用本实施例公开的编码方法，每个FEC帧包括的待传输码字中的比特会被多个不同时刻产生的FEC帧包括的待传输码字保护，可以获得更好的编码增益。而且，不同的码字之间共享的比特个数不同，彼此之间共享比特个数更多的码字，具有更快的收敛速度，然后，可以带动其余码字的收敛，从而提升译码器的收敛速度，起到降低时延的作用。
本申请提供一种用于数据通信的译码方法，如图9所示，包括：
901、恢复出第一码字；其中，第一码字包括2n个比特，由k个编码比特形成，且第一码字的n个比特来自于m个在该第一码字之前译码的码字，第一码字中另外n个比特包括k-n个信息比特和2n-k个校验比特，其中，n、m、k均为正整数，2n＞k＞n＞m；
902、对第一码字进行译码，得到译码后的比特。
应理解，在本实施例中，恢复出第一码字之前，至少已经有m个码字进行过译码了；第一码字中的一半比特是来自于之前译码的m个码字，另外n个比特是当前时刻接收到的比特流。大体来说，第一码字与先前译码的码字及后续译码的码字共享比特；在第一码字中，每一个比特位于至少一个先前译码或后续译码的码字中。此外，在一些实施例中，第一码字的k个编码比特中的至少一些比特为其它码字的数据比特，且k个编码比特中的至少一些比特为其它码字的校验比特。
通常情况下，在接收的码字流中，初始的部分码字需要包含填充比特，例如填充全0比特序列，直到译码了足够数量的码字。例如，如本申请实施例所述，在接收到初始的m个码字时，由于不存在m个在先译码的码字，无法从在先译码的码字中获得足够的编码比特，因此，需要在码字中增加一些填充比特，将编码比特的数量补充完整，以便译码。应理解，在接收的初始m个码字中，除了第一个码字之外，其他码字可以从之前译码的码字中共享一部分比特，再填充剩余部分的比特；也可以不与在先译码的码字共享，缺少的编码比特全部由填充比特替换，本申请在此不做限定。此外，关于填充比特采用全0比特序列还是其他形式的比特序列，译码端应与编码端保持一致，以便于正确译码。
在本申请实施例中，之前译码过的码字中的部分错误比特已经被纠正，在与当前时刻接收到的比特组成码字后，相当于组成的码字中的错误比特数目减少了，可增大译码正确的概率。进而，在经过本次译码，除了纠正当前时刻新接收的比特错误，还可以纠正之前码字中剩余的错误，提高纠错能力。此外，不同的码字之间共享的比特个数不同，存在多个码字共享不止一个比特，共享的比特数越多，需要关联的码字数量会有所降低，无需等待时间过长，即可译码，从而降低系统时延。
本申请另一实施例提供一种用于数据通信的编码装置，如图10所示，包括编码单元1001和发送单元1002，其中，编码单元1001接收待传输的信息比特，并对其进行编码形成待传输的码字，将形成的码字发送给发送单元1002；发送单元1002，用于将接收到的码字发送出去。进一步地，编码装置还包括存储单元1003，用于存储待传输的码字，并将其发回给编码单元1001。编码单元1001在编码过程中会使用之前形成的码字中的比特，去编码生成新的待传输码字。
在编码过程中会形成第一码字，该第一码字包括2n个比特，由k个编码比特形成，且第一码字的n个比特来自于m个在该第一码字之前形成的码字，第一码字中另外n个比特包括k-n个信息比特和2n-k个校验比特，其中，n、m、k均为正整数，2n＞k＞n＞m；发送的时候，来自于之前m个码字的比特不参与数据传输，第一码字中的另外n个比特(即待传输的码字)将会发送出去。其中，具体的编码过程如之前实施例所述，本实施例不在赘述。
本申请另一实施例提供一种用于数据通信的译码装置，如图11所示，包括译码单元1101和存储单元1102，其中，译码单元1101用于接收传输过来的码字，恢复出第一码字，对第一码字进行译码；存储单元1102用于存储来自于所述传输过来的码字，并从译码单元1101接收译码信息，对存储的码字进行更新，并在后续译码过程中将更新后的码字发回给译码单元1101。译码单元1101在译码过程中会使用之前译码得到的信息比特，信息比特被不同的码字保护，译码性能更强。
在译码过程中会形成第一码字，该第一码字包括2n个比特，且第一码字的n个比特来自于m个在该第一码字之前译码的码字，其中，n、m均为正整数，n＞m。此时，这n个比特已 经在之前的译码过程中译码过，因此错误比特数将会降低，从而提高第一码字的译码成功率。举例来说，码字x-1在译码之前含有y个错误，在经过译码之后，码字x-1中的错误比特被纠正了一部分；由于在码字x-1中纠正了部分错误，因此与码字x-1共享比特的其它先前无法纠正的码字现在可具有充分数目个正确比特，使得先前无法纠正的码字变得可纠正。以此类推，可反复地译码码字。
本申请另一实施例提供一种用于数据通信的编码装置，如图12所示，包括：输入接口1201、编码器1202、存储器1203和输出接口1204；编码器1202，用于通过输入接口1201接收信息数据，通过输出接口1204将生成的码字发送出去；存储器1203用于存储编码器1202发出的码字，并在后续编码过程中将其发回给编码器1202；编码器1202在编码过程中会使用之前形成的码字中的比特，去编码生成新的码字。具体的编码过程如之前实施例所述，此处不再赘述。
进一步地，图12中所示的存储器是一个独立于编码器的器件，实际情况中，存储功能也可以在编码器内实现，即不需要存在单独的存储器。此外，存储器1203也可以从输入接口1201接收信息数据，从编码器1202接收校验数据，本申请并不限定。
此外，本申请另一实施例还提供一种用于数据通信的译码装置，如图13所示，包括输入接口1301、译码器1302、存储器1303和输出接口1304；译码器1302用于通过输入接口1301接收发送过来的码字，并对其译码；存储器1303用于存储来自于输入接口1301的码字，并从译码器1302接收译码信息，对存储的码字进行更新，并在后续译码过程中将更新的码字发回给译码器1302；存储器1303还可以通过输出接口1304发送更新后的码字。译码器1302在译码过程中会使用之前译码得到的信息比特，提高译码能力。同理，在译码装置中，存储功能也可以在译码器内实现，即单独的存储器可以不存在。
本申请提实施例供了一种计算机可读存储介质或者计算机程序产品，用于存储计算机程序，该计算机程序用于执行本申请方法实施例中涉及的编码或译码方法。
可以理解的是，图12仅仅示出了编码装置的简化设计。在实际应用中，编码装置可以包含任意数量的接口和编码器等，而所有可以实现本申请实施例的终端都在本申请实施例的保护范围之内。同理，译码装置也可以含任意数量的接口和译码器等，实现并行译码，提高译码效率。
进一步可以理解的是，在本申请实施例中涉及的编码器或译码器可以是中央处理单元(Central Processing Unit，简称为“CPU”)，还可以是其他通用处理器、数字信号处理器(DSP)、专用集成电路(ASIC)、现成可编程门阵列(FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者该处理器也可以是任何常规的处理器等。
本申请公开的编码方案可以用于高速传输系统，例如，800G传输系统，其结构如图14所示，发送端包括第一编码单元1401，交织单元1402和第二编码单元1403；其中，第一编码单元1401用于接收数据比特流，对收到的数据比特流进行KP4编码，将编码得到的比特流发送给交织单元1402；交织单元1402用于对收到的比特流进行交织，将交织后的比特流发送给第二编码单元1403；第二编码单元1403用于对交织后的比特流执行如之前实施例公开的编码方法，将生成的码字发送出去，具体的编码方式在此不再赘述。
需要说明的是，KP4码字为RS(544，514，15，10)，即KP4码字包括544个符号，其中，有514个符号是信息符号，一次译码最多可以纠正15个符号的错误，每个符号包括10个比 特；交织单元可以采用行列交织的方式处理接收的比特流，即将比特以行的形式写入，以列的形式读出，起到交织功能，这是一种较易实现的交织方法，当然也可以采用其他的交织方法，本申请不做限定。
进一步地，该高速传输系统的接收端包括第一译码单元1404，解交织单元1405和第二译码单元1406；第一译码单元1404用于发送端发过来的码字，对收到的码字进行如之前实施例公开的译码方法，将译码得到的比特流发送给解交织单元1405；解交织单元1405用于对收到的比特流进行解交织，将解交织后的比特流发送给第二译码单元1406；第二译码单元1406用于对解交织后的比特流进行KP4译码，得到原始的数据比特。本实施例提供的高速传输系统，利用KP4编码和如之前实施例提供的编码方法进行级联编码，可以增强编码性能，满足随着光传输速率提高，而日益提高的编码性能要求。
此外，在实际的高速传输系统中，KP4编码和本申请公开的编码方法在不同的芯片中实现，以800G传输系统为例，其基本结构如图15所示，KP4编码在第一芯片1501中实现，本申请的编码方法在第二芯片1502中实现，本申请公开的译码方法在第三芯片1503中实现，KP4译码在第四芯片1504中实现；两个第一芯片共同输出8路100G的信号，实现800G信号的传输功能。应理解，800G传输系统也可以只包括一个第一芯片来实现KP4编码，通过一个第一芯片发送800G信号给第二芯片，本申请不做限定。
具体地，第二芯片1502接收到第一芯片1501传输过来的KP4码字，不进行KP4译码，将带有校验比特的KP4码直接按照之前实施例提供的编码方法进行编码。由于第一芯片1501和第二芯片1502的互联存在电路噪声，将造成相关性比特错误，因此收发端需要进行交织和解交织将相关性打散，即在发送端，将KP4码字交织之后发给第二芯片1502，同理，在接收端，将经过第三芯片1503译码之后的码字进行解交织，再发给第四芯片1504。需要说明的是，第一芯片和第四芯片可集成在一起，第二芯片和第三芯片可集成在一起，实现收发功能。此外，交织功能可以在第一芯片1501或第二芯片1502中实现，解交织功能可以在第三芯片1503或第四芯片1504中实现，本申请不做限定。
为了进一步降低时延和功耗，可将第一芯片输出端口的数据分配和交织功能相融合，即在KP4数据分发时，打乱数据发送顺序，实现交织功能；同理，译码端也可以做类似处理。
进一步地，以KP4级联如本申请之前实施例公开的FEC帧为例，且在译码时延(编码时延较小，在此忽略)仅为170ns的情况下，编码性能的仿真结果如图16所示，在输入信号的误码率(Bit Error Ratio，BER)在2.5E-3及以下情况下，即可保证译码后信号的BER在1E-15以下；也就是说，在较低时延的情况下，编码性能也可以得到保证。
在本申请实施例中，通过级联两种不同的码字，提升了编码性能，而且，在发送端无需对KP4进行译码，直接对KP4码字进行编码，实现KP4码字的透传，进一步降低系统功耗。
在本申请实施例中，还给出另外一种码的码字结构，具体结构如图17(a)所示，其中，每个码字的码长为2n，每个码字的编码比特长度为k，校验比特长度为p＝2n-k。定义编码的交织深度为m，每个码字中的前n个比特来源于前面的m个时刻的数据，称为镜像比特；后n个比特中，k-n个比特是当前时刻的信息比特，其余p＝2n-k个比特称为校验比特，其中，n、m、k均为正整数，2n＞k＞n＞m。对于镜像比特，如果其来自之前时刻的信息比特，则称其为镜像信息比特；如果其来自之前时刻的校验比特，则称其为镜像校验比特。整个码字可以称为分量码。本实施例使用BCH码或缩短BCH码作为分量码，其纠错比特数为t。
多个分量码可以构成一个FEC帧，该FEC帧的结构如图17(b)所示，每个帧包含p_word 个分量码码字，p_word为大于1的整数，应理解，本实施例中的p_word和之前实施例中的NUM含义相同。这些分量码同时被编码，然后所有分量码的信息比特和校验比特被合并后进行发送，一共n*p_word个比特。n*p_word个镜像比特不会在信道上传输。此外，该FEC帧可以为空间耦合码。
如图18所示，本方案中描述的FEC帧可以被一个n列，无穷行的矩阵来描述。在该矩阵中，每一行表示一个分量码码字，而连续的p_word行表示如图17(b)所示的一帧；每一列所对应的比特有相同的比特序号。假设当前时刻的帧为帧0，根据图17(b)中给出的帧结构，其信息比特和校验比特在当前时刻产生，而当前帧的镜像比特(被斜线标记的比特)由之前的h个帧(帧-h -帧-1)的信息比特和校验比特(被方格标记的比特)交织映射而获得。我们称当前帧的镜像比特为交织目标，称之前h个帧的信息比特和校验比特称为交织源，应理解，本实施例中的h和之前实施例中的T含义相同。
我们将一个特定比特的坐标记为(Frame，Row_str，Col_str)，其中，帧标识Frame∈(-∞,+∞)，行标识Row_str∈[0，p_word-1]，列标识Col_str∈[0，2n-1]。我们用函数Φ([Frame，Row_str，Col_str])表示从交织目标到交织源的交织映射关系。因此，Φ()函数的输入和输出均为矩阵中的一个坐标。Φ-1()为Φ()的反函数，表示从交织源到交织目标的映射关系。
具体地，图19是一种交织方案的示意图，其描述了一种交织源与交织目标的对应关系。为了方便表示，我们将交织目标中p_word个列坐标相同的比特表达成为{[0,:,Col_str]}＝{[0,0,Col_str],[0,1,Col_str],…,[0,p_word-1,Col_str]}。它们对应到交织源中的p_word个比特，其对应坐标在图19中被表示为Φ({[0,:,Col_str]})。
具体的交织方案描述如下：
Φ()函数的具体表达式：Φ([Frame,Row_str,Col_str])＝[Φf([Frame,Row_str,Col_str])，Φr([Frame,Row_str,Col_str]),Φc([Frame,Row_str,Col_str])]。
为了方便表示，我们用三个子函数Φf()，Φr()和Φc()分别表示由交织目标中比特的坐标计算交织源中比特的帧坐标，行坐标和列坐标。它们的具体表达式如下所示：
Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str+Δ)/ceiling(b_frm)))；
Figure PCTCN2021081940-appb-000009
Φc([Frame,Row_str,Col_str])＝n+h*((Col_str+Δ)％ceiling(b_frm))+(h-1-floor((Col_str+Δ)/ceiling(b_frm)))。
其中：
ceiling()和floor()函数分别将输入向上和向下取整，
Figure PCTCN2021081940-appb-000010
表示按位异或，％表示取模；
frm_map表示一个输入域输出域均为{0,1,…,h-1}的双射函数。在图19的交织方案中，对应的frm_map(i)＝h-1-i,i∈[0,h-1]；
b_frm＝n/h表示交织目标中的每个码字平均从交织源的每个帧获取的比特个数；
Δ是一个调整项。如果b_frm为整数，Δ＝0；如果b_frm不为整数，Δ取值如下：
如果Col_str/floor(b_frm)<N_ext，Δ＝floor(Col_str/floor(b_frm))；
如果Col_str/floor(b_frm)>＝N_ext，Δ＝N_ext。其中，N_ext＝ceiling(b_frm)*h-n。由于交织源和交织目标中的比特是一一对应的，交织映射函数Φ()是双射的。对于确定的交 织关联帧数h、每帧码字数p_word、码长2n和frm_map函数，交织映射函数Φ()存在且唯一确定。h、p_word和2n三者相互独立，不互相约束。因此，即使p_word和2n已经确定，h仍旧可以被调节来权衡解码性能和解码时延。
进一步地，对于本申请中的码字，码长2n<＝2048，BCH分量码纠错比特数t<＝5，交织源包括的帧的个数h>1，则构造的码字能在保证低时延的前提下依旧具有较好的性能。应理解，此处提到的当前时刻之前形成的h个FEC帧，可以为之前任意时刻的h个FEC帧。例如当前时刻之前h个连续时刻的FEC帧，也可以为当前时刻间隔某个固定时刻后，再连续取h个FEC帧，也可以当前时刻之前任意h个不连续时刻的FEC帧，本申请对此不做限定。
根据上述的交织方案，如果b_frm为整数，则交织源中的每帧为交织目标的每个码字提供b_frm个比特；否则，交织源中的(ceiling(b_frm)-b_frm)*h个帧每帧为交织目标的每个码字提供floor(b_frm)个比特，其余(b_frm-floor(b_frm))*h个帧每帧为交织目标的每个码字提供ceiling(b_frm)个比特。另外，定义b_word＝n/(h*p_word)表示交织目标中的每个码字平均从交织源的每个码字获取的比特个数。如果b_word为整数，则交织源中的每个码字为交织目标的每个码字提供b_word个比特；否则，交织源包括的(ceiling(b_word)-b_word)*(h*p_word)个码字中每个码字为交织目标的每个码字提供floor(b_word)个比特，其余(b_word-floor(b_word))*(h*p_word)个码字中，每个码字为交织目标的每个码字提供ceiling(b_word)个比特。可以看到交织目标从每个码字中得的比特数量基本一致，从每个帧中获得的码字也是基本一致的，说明本方案提出的交织方式将交织源充分打散，从而有效提升解码性能。在图19所示的例子中，b_frm为整数，可以看到交织源中的每帧给交织目标提供p_word*b_frm个比特。
进一步地，本申请实施例还对镜像校验比特的位置进行描述，对于如图19所示的一组参数h、p_word和码长2n确定的FEC帧，其一共p*p_word个镜像校验比特的位置也是确定的。镜像校验比特的Frame＝0，Row_str∈[0,p_word-1]。所有p个Col_str的坐标分为h组，以下主要定义p个对应镜像校验比特的Col_str。
首先，定义如下一组共h个i_base坐标，每个i_base坐标表示来自于一个帧的镜像校验比特在镜像比特中列坐标Col_str的最大值，如果i<N_ext，i_base(i)＝(i+1)*ceiling(b_frm)-i-2；如果i>＝N_ext，i_base(i)＝(i+1)*ceiling(b_frm)-N_ext-1，其中，0<＝i<＝h-1。
其次，定义如下数组，表示对应每个i_base的坐标数量。Range(i)＝ceiling((p-i)/h)，Range＝Range ROR N_ext，其中，ROR为数组循环右移。那么，包含所有Col_str坐标的集合为Col_str_vec(i,:)＝[i_base(i)-Range(i)+1:i_base(i)]。
需要说明的是，为了区分不同的交织方案类型，我们给出以下定义：如果b_word为整数，则关联关系为规则图案，定义交织方案为完全规则交织方案；如果b_word不为整数，但b_frm为整数，定义交织方案为部分规则交织方案；如果b_word与b_frm均不为整数，定义交织方案为不规则交织方案。下面给出不同类型的交织方案的具体例子。
结合图20，本申请给出一种具体的FEC帧交织方案，其中，交织源包括的帧的个数h＝5，每个帧包括的码字数p_word＝64，FEC帧包括的码为BCH(720，700)码，其中，BCH(720，700)码可由伽罗华域GF(2^10)上的BCH(1023，1003)码缩短303个比特得到的缩短BCH码，其纠错比特数t＝2。
对应的交织映射函数Φ()可以表达为：
Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str)/72))，
Figure PCTCN2021081940-appb-000011
Φc([Frame,Row_str,Col_str])＝360+5*((Col_str)％72)+(4–floor((Col_str)/72))，其中，frm_map(i)＝4-i,i∈[0,4]。
在本交织方案中，每个码字的360个镜像比特来自之前5帧的共5*64个码字。具体地，b_frm＝360/5＝72，即交织源中的每帧为交织目标的每个码字提供72个比特；b_word＝360/(5*64)＝1.125，即交织源中的(ceiling(1.125)-1.125)*(5*64)＝280个码字每个为交织目标的每个码字提供floor(1.125)＝1个比特，其余(1.125-floor(1.125))*(5*64)＝40个码字每个为交织目标的每个码字提供ceiling(1.125)＝2个比特。因此，本实施例中的交织方案为部分规则交织方案。在本交织方案中，交织目标从每个码字中得的比特数量相差很小，说明本方案提出的交织方式将交织源充分打散，从而有效提升解码性能。
进一步地，本申请实施例提供的FEC帧中，每个分量码(即交织目标中的码字)包括20个镜像校验比特，其中，20个镜像校验比特被分为5组，由于N_ext＝ceiling(b_frm)*h-n＝ceiling(360/5)*5-360＝0，i>＝N_ext，根据公式i_base(i)＝(i+1)*ceiling(b_frm)-N_ext-1，对应的Col_str的取值计算如下：
i_base([0,1,2,3,4])＝[71,143,215,287,359]；
进一步地，由于Range(i)＝ceiling((p-i)/h)，0<＝i<＝h-1，且Range＝Range ROR N_ext，故Range([0,1,2,3,4])＝[4,4,4,4,4]。因此，交织目标的每个码字包括的20个镜像校验比特的列坐标集合Col_str_vec＝{[68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359]}。需要说明的是，在本申请实施例中，交织目标中每个码字的镜像校验比特的列坐标集合相同。本申请另一实施例给出了另外一种FEC帧的交织方案，其交织方案示意图如图21所示，其中，交织源包括的帧的个数h＝7，每个帧包括的码字数p_word＝64，FEC帧包括的码为BCH(720，700)码，该BCH(720，700)码为由伽罗华域GF(2^10)上的BCH(1023，1003)码缩短303个比特得到的缩短BCH码，其纠错比特数t＝2。
对应的交织映射函数Φ()可以表达为：
Φf([Frame,Row_str,Col_str])＝Frame–1–frm_map(floor((Col_str+Δ)/52))，
Figure PCTCN2021081940-appb-000012
Φc([Frame,Row_str,Col_str])＝360+7*((Col_str+Δ)％52)+(6–floor((Col_str+Δ)/52))，其中，frm_map(i)＝i,i∈[0,6]。在Col_str/51<4时，Δ＝floor(Col_str/51)；在Col_str/51>＝4时，Δ＝4。
在本交织方案中，每个码字的360个镜像比特来自之前7帧的共7*64个码字。具体地，b_frm＝360/7＝51.42，此时，交织源中存在3帧，每帧为交织目标的每个码字提供52个比特，其余4帧每帧为交织目标的每个码字提供51个比特。b_word＝360/(7*64)＝0.803，则交织源中存在88个码字不为交织目标中的码字提供比特，其余360个码字中的每个码字为交织目标的每个码字提供1个比特。因此，本实施例中的交织方案为不规则交织方案。在本交织方案中，交织目标从其中360个码字中的每个码字得到的比特数量相同，从每个帧中获得的比特数也相差很小，说明本方案提出的交织方式将交织源充分打散，从而有效提升解码性能。
在本交织方案中，交织目标的每个码字包括的20个镜像校验比特被分为7组，由于N_ext＝ceiling(b_frm)*h-n＝ceiling(360/7)*7-360＝4，且0<＝i<＝6，可以得出，在0<＝i<4时，i_base(i)＝(i+1)*ceiling(b_frm)-i+2；在4<＝i<＝6时，i_base(i)＝(i+1)*ceiling(b_frm)-N_ext-1。因此，对应的Col_str的取值计算如下：
i_base([0,1,2,3,4,5,6])＝[50,101,152,203,255,307,359]；
进一步地，由于Range(i)＝ceiling((p-i)/h)，0<＝i<＝h-1，且Range＝Range ROR N_ext，故Range([0,1,2,3,4,5,6])＝[3,3,3,2,3,3,3]。因此，交织目标的每个码字中包括的20个镜像校验比特的列坐标集合Col_str_vec＝{[48,49,50],[99,100,101],[150,151,152],[202,203],[253,254,255],[305,306,307],[357,358,359]}。需要说明的是，在本申请实施例中，交织目标中每个码字的镜像校验比特的列坐标集合相同。
本申请另一实施例还给出一种FEC帧的交织方案，其交织方案示意图如图22所示，其中，交织源包括的帧的个数h＝8，每个帧包括的码字数p_word＝16，FEC帧包括的码为extended BCH(256,239)码。对应的交织映射函数Φ()可以表达为：
Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str)/16))，
Figure PCTCN2021081940-appb-000013
Φc([Frame,Row_str,Col_str])＝128+8*((Col_str)％16)+(7–floor((Col_str)/16))，其中，frm_map(i)＝7-i,i∈[0,7]。
在本交织方案中，每个码字的128个镜像比特来自之前8帧的共8*16个码字。b_frm＝128/8＝16，即交织源中的每帧为交织目标的每个码字提供16个比特；b_word＝128/(8*16)＝1，即交织源中的每个码字为交织目标的每个码字提供1个比特。因此，本实施例中的交织方案为完全规则交织方案。在本交织方案中，交织目标从交织源中的每个码字得到的比特数量相同，从每个帧中获得的比特数量也相同，说明本方案提出的交织方式将交织源充分打散，从而有效提升解码性能。
在本交织方案中，交织目标的每个码字包括的17个镜像校验比特被分为8组，由于N_ext＝ceiling(b_frm)*h-n＝ceiling(128/8)*8-128＝0，且0<＝i<＝7，可以得出，i_base(i)＝(i+1)*ceiling(b_frm)-N_ext-1。因此，对应的Col_str的取值计算如下：
i_base([0,1,2,3,4,5,6,7])＝[15,31,47,63,79,95,111,127]，
进一步地，由于Range(i)＝ceiling((p-i)/h)，且Range＝Range ROR N_ext，故Range([0,1,2,3,4,5,6,7])＝[3,2,2,2,2,2,2,2]。因此，交织目标的每个码字包括的17个镜像校验比特的列坐标集合Col_str_vec＝{[13,14,15],[30,31],[46,47],[62,63],[78,79],[94,95],[110,111],[126,127]}。需要说明的是，在本申请实施例中，交织目标中每个码字的镜像校验比特的列坐标集合相同。
进一步地，上述实施例描述的FEC帧可以为空间耦合码，其编码架构如图23所示，在此框图中，共有p_word个分量码编码器和一个卷积交织器。其中，卷积交织器存储当前时刻之前h帧的信息和校验比特，其总共存储h*n*p_word个比特，用于产生当前时刻的n*p_word个镜像比特。
编码器的输入为(k-n)*p_word个信息比特，它们将被分配到p_word个分量码编码器。每个分量码编码器的输入为(k-n)个信息比特和n个镜像比特，输出为(k-n)个信息比特和p 个校验比特。整个编码器的输出为来自p_word个分量码编码器的总共(k-n+p)*p_word＝n*p_word个信息和校验比特，来自卷积交织器的镜像比特仅参与分量码编码而不会被传输。应理解，h、n、p_word的含义与之前实施例相同，本实施例不再赘述。
图24给出了利用如图23所示的编码架构生成当前帧的镜像比特的方法。图24的上半部分是一个h*p_word行，n列的矩阵。在该矩阵中，连续的p_word行表示如图17(b)所示的一帧，所以当前时刻卷积交织器中一共存储h帧(帧-h -帧-1)。当前帧(帧0)的镜像比特由交织器中的比特交织而来。为了方便表示，我们将一个特定比特的坐标记为[Frame,Row_str,Col_str]。其中，帧坐标Frame∈(-∞,+∞)，行坐标Row_str∈[0,p_word-1]，列坐标Col_str∈[0,n-1]。
卷积交织器中的交织关系分为两层，即帧间交织和码间交织。假设交织后的镜像比特的坐标为[Frame’,Row_str’,Col_str’]，则卷积交织器描述了[Frame,Row_str,Col_str]到[Frame’,Row_str’,Col_str’]的交织映射关系。下面介绍每一层交织的具体方案。
帧间交织：为了方便描述，我们将交织器中p_word个具有相同帧坐标和列坐标的比特称为一个符号，并表达成为{[Frame,:,Col_str]}＝{[Frame,0,Col_str],[Frame,1,Col_str],…,[Frame,p_word-1,Col_str]}。如图24所示，当前帧(帧0)的镜像比特对应的符号对应交织器中的一个符号，对应的坐标关系如下所示：
Frame’＝Frame+1+frm_map(Col_str％h)，
Col_str’＝(h–1–Col_str％h)*ceiling(b_frm)+floor(Col_str/h)–Δ。
其中：
ceiling()和floor()函数分别将输入向上和向下取整，％表示取模；
frm_map表示一个输入域和输出域均为{0,1,…,h-1}的双射函数。在图24所示的交织方案中，对应的frm_map(i)＝i,i∈[0,h-1]；
b_frm＝n/h表示当前帧的每个码字平均从交织器的每个帧获取的比特个数；
Δ是一个调整项。如果b_frm为整数，Δ＝0；如果b_frm不为整数，在Col_str/floor(b_frm)<N_ext时，Δ＝floor(Col_str/floor(b_frm))；在Col_str/floor(b_frm)>＝N_ext时，Δ＝N_ext，其中，N_ext＝ceiling(b_frm)*h-n。
从公式中可以看到，帧间交织不涉及行坐标的变换，因此每个符号中比特的顺序与交织器中的比特顺序是相同的。
对于每个进行过帧间交织的符号，进一步对其进行码间交织，使交织后同一个码字的比特尽量来自不同的帧。具体的码间映射关系如下面的行坐标变换公式所示：
Figure PCTCN2021081940-appb-000014
其中，
Figure PCTCN2021081940-appb-000015
表示按位异或。可以看到，根据Col_str的不同，码间交织共有p_word种不同的方案。
交织器的输入比特和输出比特一一对应。对于确定的交织关联帧数h、每帧码字数p_word、码长2n和frm_map函数，交织方式存在且唯一确定。h、p_word和2n三者相互独立，不互相约束。因此，即使p_word和2n已经确定，h仍旧可以被调节来权衡解码性能和解码时延。
根据上述的交织方案，如果b_frm为整数，则交织器中的每帧为当前帧的每个码字提供b_frm个比特；否则，交织器中的(ceiling(b_frm)-b_frm)*h个帧每帧为当前帧的每个码字 提供floor(b_frm)个比特，其余(b_frm-floor(b_frm))*h个帧每帧为当前帧的每个码字提供ceiling(b_frm)个比特。另外，定义b_word＝n/(h*p_word)表示当前帧中的每个码字平均从交织器的每个码字获取的比特个数。如果b_word为整数，则交织器中的每个码字为当前帧的每个码字提供b_word个比特；否则，交织器包括的(ceiling(b_word)-b_word)*(h*p_word)个码字中每个码字为当前帧的每个码字提供floor(b_word)个比特，其余(b_word-floor(b_word))*(h*p_word)个码字中，每个码字为当前帧的每个码字提供ceiling(b_word)个比特。可以看到当前帧从每个码字中获得的比特数量基本一致，从每个帧中获得的码字也是基本一致的，说明本方案提出的交织方式也可以将交织器中的比特充分打散，从而有效提升解码性能。
进一步地，本申请实施例还对镜像校验比特的位置进行描述，对于如图24所示的一组参数h、p_word和码长2n确定的FEC帧，其一共p*p_word个镜像校验比特的位置也是确定的。镜像校验比特的Frame＝0，Row_str∈[0,p_word-1]。所有p个Col_str的坐标分为h组，以下主要定义p个对应镜像校验比特的Col_str。
首先，定义如下一组共h个i_base坐标，每个i_base坐标表示来自于一个帧的镜像校验比特在镜像比特中的最大Col_str值，如果i<N_ext，i_base(i)＝(i+1)*ceiling(b_frm)-i-2；如果i>＝N_ext，i_base(i)＝(i+1)*ceiling(b_frm)-N_ext-1，其中，0<＝i<＝h-1。
其次，定义如下数组，表示对应每个i_base的坐标数量。Range(i)＝ceiling((p-i)/h)，Range＝Range ROR N_ext，其中，ROR为数组循环右移。那么，包含所有Col_str坐标的集合为Col_str_vec(i,:)＝[i_base(i)-Range(i)+1:i_base(i)]。
需要说明的是，为了区分不同的交织方案类型，我们给出以下定义：如果b_word为整数，则关联关系为规则图案，定义交织方案为完全规则交织方案；如果b_word不为整数，但b_frm为整数，定义交织方案为部分规则交织方案；如果b_word与b_frm均不为整数，定义交织方案为不规则交织方案。下面基于图23所示的编码架构，对不同类型的交织方案进行具体描述。
本实例描述h＝5，p_word＝64，分量码为BCH(720，700)的空间耦合码。BCH(720，700)分量码为由伽罗华域GF(2^10)上的BCH(1023，1003)码缩短303个比特得到的缩短BCH码，其纠错比特数t＝2。
在本实例的空间耦合码的编码架构中，共有64个分量码编码器和一个卷积交织器，其中，卷积交织器存储当前时刻之前5帧的信息和校验比特，其总共存储115200比特，用于产生当前时刻的23040个镜像比特。
编码器的输入为21760个信息比特，它们将被分配到64个分量码编码器。每个分量码编码器的输入为340个信息比特和360个镜像比特，输出为340个信息比特和20个校验比特。编码器的总体输出为来自64个分量码编码器的总共23040个信息和校验比特。来自卷积交织器的镜像比特仅参与分量码编码而不会被传输。
如图25所示，当前帧的镜像比特对应的符号对应交织器中的一个符号，对应的坐标关系如下所示：
Frame’＝Frame+1+frm_map(Col_str％5)，
Col_str’＝(4–Col_str％5)*72+floor(Col_str/5)。
frm_map(i)＝i,i∈[0,4]，其中，b_frm＝72，Δ＝0。
依据上述公式，可以知道当前帧的镜像比特对应的符号来自于在先的哪一帧的哪一个符 号，即进行了帧间交织，下面根据下面的对应关系，进行码间交织，具体的码间映射关系如下面的行坐标变换公式所示：
Figure PCTCN2021081940-appb-000016
需要说明的是，在本交织方案中，每个码字的360个镜像比特来自之前5帧的共5*64个码字，具体从每个帧以及每个码字获取的比特数与图20所示实施例相同；而且，每个分量码包括的20个镜像校验比特的列坐标集合也与图20所示实施例相同，本申请实施例不再赘述。
本实例描述h＝7，p_word＝64，分量码为BCH(720，700)的空间耦合码。BCH(720，700)分量码为由伽罗华域GF(2^10)上的BCH(1023，1003)码缩短303个比特得到的缩短BCH码，其纠错比特数t＝2。
在本实例的空间耦合码的编码架构中，共有64个分量码编码器和一个卷积交织器，其中，卷积交织器存储当前时刻之前7帧的信息和校验比特，其总共存储161280比特，用于产生当前时刻的23040个镜像比特。
编码器的输入为21760个信息比特，它们将被分配到64个分量码编码器。每个分量码编码器的输入为340个信息比特和360个镜像比特，输出为340个信息比特和20个校验比特。编码器的总体输出为来自64个分量码编码器的总共23040个信息和校验比特。来自卷积交织器的镜像比特仅参与分量码编码而不会被传输。
如图26所示，当前帧的镜像比特对应的符号对应交织器中的一个符号，对应的坐标关系如下所示：
Frame’＝Frame+1+frm_map(Col_str％7)，
Col_str’＝(6–Col_str％7)*52+floor(Col_str/7)-Δ。
frm_map(i)＝6-i,i∈[0,6]，其中，在Col_str/51<4时，Δ＝ceiling(Col_str/51)；在Col_str/51>＝4时，Δ＝4；b_frm＝51.42。
依据上述公式，可以知道当前帧的镜像比特对应的符号来自于在先的哪一帧的哪一个符号，即进行了帧间交织，下面根据下面的对应关系，进行码间交织，具体的码间映射关系如下面的行坐标变换公式所示：
Figure PCTCN2021081940-appb-000017
需要说明的是，在本交织方案中，每个码字的360个镜像比特来自之前7帧的共7*64个码字，具体从每个帧以及每个码字获取的比特数与图21所示实施例相同；而且，每个分量码包括的20个镜像校验比特的列坐标集合也与图21所示实施例相同，本申请实施例不再赘述。
本实例描述h＝8，p_word＝16，分量码为extended BCH(256，239)的空间耦合码。在本实例的空间耦合码的编码架构中，共有16个分量码编码器和一个卷积交织器，其中，卷积交织器存储当前时刻之前8帧的信息和校验比特，其总共存储16384比特，用于产生当前时刻的2048个镜像比特。
编码器的输入为1776个信息比特，它们将被分配到16个分量码编码器。每个分量码编码器的输入为111个信息比特和128个镜像比特，输出为111个信息比特和17个校验比特。编码器的总体输出为来自16个分量码编码器的总共2048个信息和校验比特。来自卷积交织器的镜像比特仅参与分量码编码而不会被传输。
如图27所示，当前帧的镜像比特对应的符号对应交织器中的一个符号，对应的坐标关系如下所示：
Frame’＝Frame+1+frm_map(Col_str％8)，
Col_str’＝(7–Col_str％8)*16+floor(Col_str/8)。
frm_map(i)＝i,i∈[0,7]，其中，b_frm＝16，Δ＝0。
依据上述公式，可以知道当前帧的镜像比特对应的符号来自于在先的哪一帧的哪一个符号，即进行了帧间交织，下面根据下面的对应关系，进行码间交织，具体的码间映射关系如下面的行坐标变换公式所示：
Figure PCTCN2021081940-appb-000018
需要说明的是，在本交织方案中，每个码字的360个镜像比特来自之前5帧的共5*64个码字，具体从每个帧以及每个码字获取的比特数与图22所示实施例相同；而且，每个分量码包括的20个镜像校验比特的列坐标集合也与图22所示实施例相同，本申请实施例不再赘述。
进一步地，对于本申请中的码字，码长2n<＝2048，BCH分量码纠错比特数t<＝5，交织源包括的帧的个数h>1，则构造的码字能在保证低时延的前提下依旧具有较好的性能。应理解，此处提到的当前时刻之前形成的h个FEC帧，可以为之前任意时刻的h个FEC帧。例如当前时刻之前h个连续时刻的FEC帧，也可以为当前时刻间隔某个固定时刻后，再连续取h个FEC帧，也可以当前时刻之前任意h个不连续时刻的FEC帧，本申请对此不做限定。
此外，除之前提到的实施例之外，本申请还可以包括如下情况：
码长2n＝720，纠错比特数t＝2，交织关联帧数h＝4；
码长2n＝720，纠错比特数t＝2，交织关联帧数h＝5；
码长2n＝804，纠错比特数t＝2，交织关联帧数h＝4；
码长2n＝1206，纠错比特数t＝3，交织关联帧数h＝4；
码长2n＝868，纠错比特数t＝2，交织关联帧数h＝4；
码长2n＝1302，纠错比特数t＝3，交织关联帧数h＝4。
上述构造的码字均能在保证低时延的前提下，依旧具有较好的性能。此外，上述多个实施例中给出多种不同的交织方案，任何满足上述交织方案的编码方式，或者与上述交织方案提供的公式相同，或者只是在上述交织方案提供的公式基础上做等价或简单的变型，均在本申请的保护范围之内。
应理解，说明书通篇提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本发明的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。在本发明的各种实施例中，上述各过程的序号大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本发明实施例的实施过程构成任何限定。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置和方法，可以通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口、装置或单元的间接耦合或通信连接，也可以是电的或其它的形式连接。
另外，在本发明各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以是两个或两个以上单元集成在一个单元中。
总之，以上所述仅为本发明技术方案的较佳实施例而已，并非用于限定本发明的保护范围。凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (33)

  1. 一种用于数据通信的编码方法，其特征在于，所述方法包括：
    形成第一码字，所述第一码字包括n个镜像比特和n个待传输比特，且所述n个镜像比特从m个源码字的待传输比特中挑选，其中，所述源码字为在所述第一码字之前形成的码字，n和m均为正整数，n＞m；
    将所述第一码字的所述n个待传输比特发送出去。
  2. 根据权利要求1所述的编码方法，其特征在于，所述n个待传输比特包括p个校验比特和n-p个信息比特，其中，所述p个校验比特由所述n个镜像比特和所述n-p个信息比特编码得到，p为小于n的正整数。
  3. 根据权利要求2所述的编码方法，其特征在于，所述n个镜像比特包括镜像校验比特和镜像信息比特，其中，所述镜像校验比特为从m个所述源码字的校验比特中挑选，所述镜像信息比特从m个所述源码字的信息比特中挑选。
  4. 根据权利要求3所述的编码方法，其特征在于，所述镜像校验比特和所述校验比特的个数相同。
  5. 根据权利要求1-4中任一项所述的编码方法，其特征在于，在所述m个源码字中，不同源码字提供给所述第一码字的比特数目差的最大值大于一个比特。
  6. 根据权利要求1-4中任一项所述的编码方法，其特征在于，所述第一码字的码长不大于2048，纠错比特数不大于5。
  7. 根据权利要求1-4中任一项所述的编码方法，其特征在于，在所述m个源码字中，至少一个源码字提供给所述第一码字的比特数目与其他源码字提供给所述第一码字的比特数目不相同；或
    每个源码字提供给所述第一码字q个比特，其中，q为大于1的整数，n为m的整数倍。
  8. 根据权利要求1-7中任一项所述的编码方法，其特征在于，p_word个所述第一码字构成第一帧，所述第一帧中码字的镜像比特来自于在所述第一帧之前生成的h个第二帧中码字的待传输比特，其中，h和p_word均为大于1的正整数。
  9. 根据权利要求8所述的编码方法，其特征在于，所述h个第二帧中比特的帧坐标，行坐标和列坐标通过Φf()，Φr()和Φc()三个函数计算得到：
    Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str+Δ)/ceiling(n/h)))；
    Figure PCTCN2021081940-appb-100001
    Φc([Frame,Row_str,Col_str])＝n+h*((Col_str+Δ)％ceiling(n/h))+(h-1-floor((Col_str+Δ)/ceiling(n/h)))。
    其中，所述第一帧中码字的镜像比特的帧坐标Frame、行坐标Row_str和列坐标Col_str均为整数，且Frame∈(-∞,+∞)，Row_str∈[0，p_word-1]，Col_str∈[0，2n-1]；frm_map(i)＝h-1-i,i∈[0,h-1]；
    如果n/h为整数，Δ＝0；否则，如果Col_str/floor(n/h)<ceiling(n/h)*h-n，Δ＝floor(Col_str/floor(n/h))；如果Col_str/floor(n/h)>＝ceiling(n/h)*h-n，Δ＝ceiling(n/h)*h-n。
  10. 根据权利要求9所述的编码方法，其特征在于，所述第一帧中码字的镜像校验比特的列坐标Col_str集合如下所示：
    Col_str_vec(i,:)＝[i_base(i)-Range(i)+1:i_base(i)]，0<＝i<＝h-1；
    其中，如果i<ceiling(n/h)*h-n，i_base(i)＝(i+1)*ceiling(n/h)-i-2；如果i>＝ceiling(n/h)*h-n，i_base(i)＝(i+1)*ceiling(n/h)-ceiling(n/h)*h-n-1；Range(i)＝ceiling((p-i)/h)ROR(ceiling(n/h)*h-n)，ROR为数组循环右移。
  11. 根据权利要求9或10所述的编码方法，其特征在于，第一码字为BCH(720，700)码，h＝5，p_word＝64，则Φf()，Φr()和Φc()三个函数表达式如下所示：
    Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str)/72))，
    Figure PCTCN2021081940-appb-100002
    Φc([Frame,Row_str,Col_str])＝360+5*((Col_str)％72)+(4–floor((Col_str)/72))，其中，frm_map(i)＝4-i,i∈[0,4]，且i为整数。
  12. 根据权利要求11所述的编码方法，其特征在于，所述第一帧中码字的镜像校验比特的列坐标Col_str集合如下所示：
    Col_str_vec(i,:)＝{[68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359]}。
  13. 根据权利要求8所述的编码方法，其特征在于，所述h个第二帧中比特的帧坐标Frame’，行坐标Row_str’和列坐标Col_str’由如下公式得到：
    Frame’＝Frame+1+frm_map(Col_str％h)；
    Col_str’＝(h–1–Col_str％h)*ceiling(n/h)+floor(Col_str/h)–Δ；
    Figure PCTCN2021081940-appb-100003
    其中，所述第一帧中码字的镜像比特的帧坐标Frame、行坐标Row_str和列坐标Col_str均为整数，且Frame∈(-∞,+∞)，Row_str∈[0，p_word-1]，Col_str∈[0，2n-1]；frm_map(i)＝i,i∈[0,h-1]，且i为整数；
    如果n/h为整数，Δ＝0；否则，如果Col_str/floor(n/h)<ceiling(n/h)*h-n，Δ＝floor(Col_str/floor(n/h))；如果Col_str/floor(n/h)>＝ceiling(n/h)*h-n，Δ＝ceiling(n/h)*h-n。
  14. 根据权利要求13所述的编码方法，其特征在于，第一码字为BCH(720，700)码，h＝5，p_word＝64，则：Frame’＝Frame+1+frm_map(Col_str％5)；
    Col_str’＝(4–Col_str％5)*72+floor(Col_str/5)；
    Figure PCTCN2021081940-appb-100004
    其中，frm_map(i)＝i,i∈[0,4]。
  15. 根据权利要求1-14中任一项所述的编码方法，其特征在于，所述第一码字为BCH(720，700)码。
  16. 一种用于数据通信的编码装置，其特征在于，所述编码装置包括编码单元和发送单元，
    所述编码单元，用于形成第一码字，所述第一码字包括n个镜像比特和n个待传输比特，且所述n个镜像比特从m个源码字的待传输比特中挑选，其中，所述源码字为在所述第一码字之前形成的码字，n和m均为正整数，n＞m；
    所述发送单元，用于将所述第一码字中的所述n个待传输比特发送出去。
  17. 根据权利要求16所述的编码装置，其特征在于，所述n个待传输比特包括p个校验比特和n-p个信息比特，其中，所述p个校验比特由所述n个镜像比特和所述n-p个信息比特编码得到，p为小于n的正整数。
  18. 根据权利要求17所述的编码装置，其特征在于，所述n个镜像比特包括镜像校验比特和镜像信息比特，其中，所述镜像校验比特为从m个所述源码字的校验比特中挑选，所述镜像信息比特从m个所述源码字的信息比特中挑选。
  19. 根据权利要求18所述的编码装置，其特征在于，所述镜像校验比特和所述校验比特的个数相同。
  20. 根据权利要求16-19中任一项所述的编码装置，其特征在于，在所述m个源码字中，不同源码字提供给所述第一码字的比特数目差的最大值大于一个比特。
  21. 根据权利要求16-19中任一项所述的编码装置，其特征在于，所述第一码字的码长不大于2048，纠错比特数不大于5。
  22. 根据权利要求16-19中任一项所述的编码装置，其特征在于，在所述m个源码字中，至少一个源码字提供给所述第一码字的比特数目与其他源码字提供给所述第一码字的比特数目不相同；或
    每个源码字提供给所述第一码字q个比特，其中，q为大于1的整数，n为m的整数倍。
  23. 根据权利要求16-22中任一项所述的编码装置，其特征在于，p_word个所述第一码字构成第一帧，所述第一帧中码字的镜像比特来自于在所述第一帧之前生成的h个第二帧中码字的待传输比特，其中，h和p_word均为大于1的正整数。
  24. 根据权利要求23所述的编码装置，其特征在于，所述h个第二帧中比特的帧坐标，行坐标和列坐标通过Φf()，Φr()和Φc()三个函数计算得到：
    Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str+Δ)/ceiling(n/h)))；
    Figure PCTCN2021081940-appb-100005
    Φc([Frame,Row_str,Col_str])＝n+h*((Col_str+Δ)％ceiling(n/h))+(h-1-floor((Col_str+Δ)/ceiling(n/h)))。
    其中，所述第一帧中码字的镜像比特的帧坐标Frame、行坐标Row_str和列坐标Col_str均为整数，且Frame∈(-∞,+∞)，Row_str∈[0，p_word-1]，Col_str∈[0，2n-1]；frm_map(i)＝h-1-i,i∈[0,h-1]；
    如果n/h为整数，Δ＝0；否则，如果Col_str/floor(n/h)<ceiling(n/h)*h-n，Δ＝floor(Col_str/floor(n/h))；如果Col_str/floor(n/h)>＝ceiling(n/h)*h-n，Δ＝ceiling(n/h)*h-n。
  25. 根据权利要求24所述的编码装置，其特征在于，所述第一帧中码字的镜像校验比特的列坐标Col_str集合如下所示：
    Col_str_vec(i,:)＝[i_base(i)-Range(i)+1:i_base(i)]，0<＝i<＝h-1；
    其中，如果i<ceiling(n/h)*h-n，i_base(i)＝(i+1)*ceiling(n/h)-i-2；如果i>＝ceiling(n/h)*h-n，i_base(i)＝(i+1)*ceiling(n/h)-ceiling(n/h)*h-n-1；Range(i)＝ceiling((p-i)/h)ROR(ceiling(n/h)*h-n)，ROR为数组循环右移。
  26. 根据权利要求24或25所述的编码装置，其特征在于，第一码字为BCH(720，700)码，h＝5，p_word＝64，则Φf()，Φr()和Φc()三个函数表达式如下所示：
    Φf([Frame,Row_str,Col_str])＝Frame-1-frm_map(floor((Col_str)/72))，
    Figure PCTCN2021081940-appb-100006
    Φc([Frame,Row_str,Col_str])＝360+5*((Col_str)％72)+(4–floor((Col_str)/72))，其中，frm_map(i)＝4-i,i∈[0,4]，且i为整数。
  27. 根据权利要求26所述的编码装置，其特征在于，所述第一帧中码字的镜像校验比特的列坐标Col_str集合如下所示：
    Col_str_vec(i,:)＝{[68,69,70,71],[140,141,142,143],[212,213,214,215],[284,285,286,287],[356,357,358,359]}。
  28. 根据权利要求23所述的编码装置，其特征在于，所述h个第二帧中比特的帧坐标Frame’，行坐标Row_str’和列坐标Col_str’由如下公式得到：
    Frame’＝Frame+1+frm_map(Col_str％h)；
    Col_str’＝(h–1–Col_str％h)*ceiling(n/h)+floor(Col_str/h)–Δ；
    Figure PCTCN2021081940-appb-100007
    其中，所述第一帧中码字的镜像比特的帧坐标Frame、行坐标Row_str和列坐标Col_str均为整数，且Frame∈(-∞,+∞)，Row_str∈[0，p_word-1]，Col_str∈[0，2n-1]；frm_map(i)＝i,i∈[0,h-1]，且i为整数；
    如果n/h为整数，Δ＝0；否则，如果Col_str/floor(n/h)<ceiling(n/h)*h-n，Δ＝floor(Col_str/floor(n/h))；如果Col_str/floor(n/h)>＝ceiling(n/h)*h-n，Δ＝ceiling(n/h)*h-n。
  29. 根据权利要求28所述的编码装置，其特征在于，第一码字为BCH(720，700)码，h＝5，p_word＝64，则：Frame’＝Frame+1+frm_map(Col_str％5)；
    Col_str’＝(4–Col_str％5)*72+floor(Col_str/5)；
    Figure PCTCN2021081940-appb-100008
    其中，frm_map(i)＝i,i∈[0,4]。
  30. 根据权利要求16-29中任一项所述的编码装置，其特征在于，所述第一码字为BCH(720，700)码。
  31. 一种基于数据通信的级联编码方法，其特征在于，所述方法包括：
    接收数据比特，对数据比特进行KP4编码，得到KP4码字；
    将所述KP4码字进行交织，得到交织后的码字；
    将所述交织后的码字按照权1-15中任一项所述的编码方式进行编码，其中，所述交织后的码字在进行如权1-15中任一项所述的编码之前，不进行译码。
  32. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储指令，当所述指令在终端设备上运行时，使得所述终端设备执行如权利要求1-15中任一项所述的方法。
  33. 一种包含指令的计算机程序产品，其特征在于，当在终端设备上运行时，使得终端设备执行如权利要求1-15中任一项所述的方法。
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